RegisterContext_powerpc.h

Go to the documentation of this file.

//===-- RegisterContext_powerpc.h --------------------------------*- C++
//-*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
 
#ifndef LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_POWERPC_H
#define LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_POWERPC_H
 
// eh_frame and DWARF Register numbers (eRegisterKindEHFrame &
// eRegisterKindDWARF)
enum {
  dwarf_r0_powerpc = 0,
  dwarf_r1_powerpc,
  dwarf_r2_powerpc,
  dwarf_r3_powerpc,
  dwarf_r4_powerpc,
  dwarf_r5_powerpc,
  dwarf_r6_powerpc,
  dwarf_r7_powerpc,
  dwarf_r8_powerpc,
  dwarf_r9_powerpc,
  dwarf_r10_powerpc,
  dwarf_r11_powerpc,
  dwarf_r12_powerpc,
  dwarf_r13_powerpc,
  dwarf_r14_powerpc,
  dwarf_r15_powerpc,
  dwarf_r16_powerpc,
  dwarf_r17_powerpc,
  dwarf_r18_powerpc,
  dwarf_r19_powerpc,
  dwarf_r20_powerpc,
  dwarf_r21_powerpc,
  dwarf_r22_powerpc,
  dwarf_r23_powerpc,
  dwarf_r24_powerpc,
  dwarf_r25_powerpc,
  dwarf_r26_powerpc,
  dwarf_r27_powerpc,
  dwarf_r28_powerpc,
  dwarf_r29_powerpc,
  dwarf_r30_powerpc,
  dwarf_r31_powerpc,
  dwarf_f0_powerpc,
  dwarf_f1_powerpc,
  dwarf_f2_powerpc,
  dwarf_f3_powerpc,
  dwarf_f4_powerpc,
  dwarf_f5_powerpc,
  dwarf_f6_powerpc,
  dwarf_f7_powerpc,
  dwarf_f8_powerpc,
  dwarf_f9_powerpc,
  dwarf_f10_powerpc,
  dwarf_f11_powerpc,
  dwarf_f12_powerpc,
  dwarf_f13_powerpc,
  dwarf_f14_powerpc,
  dwarf_f15_powerpc,
  dwarf_f16_powerpc,
  dwarf_f17_powerpc,
  dwarf_f18_powerpc,
  dwarf_f19_powerpc,
  dwarf_f20_powerpc,
  dwarf_f21_powerpc,
  dwarf_f22_powerpc,
  dwarf_f23_powerpc,
  dwarf_f24_powerpc,
  dwarf_f25_powerpc,
  dwarf_f26_powerpc,
  dwarf_f27_powerpc,
  dwarf_f28_powerpc,
  dwarf_f29_powerpc,
  dwarf_f30_powerpc,
  dwarf_f31_powerpc,
  dwarf_cr_powerpc,
  dwarf_fpscr_powerpc,
  dwarf_msr_powerpc,
  dwarf_vscr_powerpc,
  dwarf_xer_powerpc = 101,
  dwarf_lr_powerpc = 108,
  dwarf_ctr_powerpc,
  dwarf_pc_powerpc,
  dwarf_vrsave_powerpc = 356,
  dwarf_v0_powerpc = 1124,
  dwarf_v1_powerpc,
  dwarf_v2_powerpc,
  dwarf_v3_powerpc,
  dwarf_v4_powerpc,
  dwarf_v5_powerpc,
  dwarf_v6_powerpc,
  dwarf_v7_powerpc,
  dwarf_v8_powerpc,
  dwarf_v9_powerpc,
  dwarf_v10_powerpc,
  dwarf_v11_powerpc,
  dwarf_v12_powerpc,
  dwarf_v13_powerpc,
  dwarf_v14_powerpc,
  dwarf_v15_powerpc,
  dwarf_v16_powerpc,
  dwarf_v17_powerpc,
  dwarf_v18_powerpc,
  dwarf_v19_powerpc,
  dwarf_v20_powerpc,
  dwarf_v21_powerpc,
  dwarf_v22_powerpc,
  dwarf_v23_powerpc,
  dwarf_v24_powerpc,
  dwarf_v25_powerpc,
  dwarf_v26_powerpc,
  dwarf_v27_powerpc,
  dwarf_v28_powerpc,
  dwarf_v29_powerpc,
  dwarf_v30_powerpc,
  dwarf_v31_powerpc,
};
 
// Internal codes for all powerpc registers.
enum {
  k_first_gpr_powerpc,
  gpr_r0_powerpc = k_first_gpr_powerpc,
  gpr_r1_powerpc,
  gpr_r2_powerpc,
  gpr_r3_powerpc,
  gpr_r4_powerpc,
  gpr_r5_powerpc,
  gpr_r6_powerpc,
  gpr_r7_powerpc,
  gpr_r8_powerpc,
  gpr_r9_powerpc,
  gpr_r10_powerpc,
  gpr_r11_powerpc,
  gpr_r12_powerpc,
  gpr_r13_powerpc,
  gpr_r14_powerpc,
  gpr_r15_powerpc,
  gpr_r16_powerpc,
  gpr_r17_powerpc,
  gpr_r18_powerpc,
  gpr_r19_powerpc,
  gpr_r20_powerpc,
  gpr_r21_powerpc,
  gpr_r22_powerpc,
  gpr_r23_powerpc,
  gpr_r24_powerpc,
  gpr_r25_powerpc,
  gpr_r26_powerpc,
  gpr_r27_powerpc,
  gpr_r28_powerpc,
  gpr_r29_powerpc,
  gpr_r30_powerpc,
  gpr_r31_powerpc,
  gpr_lr_powerpc,
  gpr_cr_powerpc,
  gpr_xer_powerpc,
  gpr_ctr_powerpc,
  gpr_pc_powerpc,
  k_last_gpr_powerpc = gpr_pc_powerpc,
 
  k_first_fpr,
  fpr_f0_powerpc = k_first_fpr,
  fpr_f1_powerpc,
  fpr_f2_powerpc,
  fpr_f3_powerpc,
  fpr_f4_powerpc,
  fpr_f5_powerpc,
  fpr_f6_powerpc,
  fpr_f7_powerpc,
  fpr_f8_powerpc,
  fpr_f9_powerpc,
  fpr_f10_powerpc,
  fpr_f11_powerpc,
  fpr_f12_powerpc,
  fpr_f13_powerpc,
  fpr_f14_powerpc,
  fpr_f15_powerpc,
  fpr_f16_powerpc,
  fpr_f17_powerpc,
  fpr_f18_powerpc,
  fpr_f19_powerpc,
  fpr_f20_powerpc,
  fpr_f21_powerpc,
  fpr_f22_powerpc,
  fpr_f23_powerpc,
  fpr_f24_powerpc,
  fpr_f25_powerpc,
  fpr_f26_powerpc,
  fpr_f27_powerpc,
  fpr_f28_powerpc,
  fpr_f29_powerpc,
  fpr_f30_powerpc,
  fpr_f31_powerpc,
  fpr_fpscr_powerpc,
  k_last_fpr = fpr_fpscr_powerpc,
 
  k_first_vmx,
  vmx_v0_powerpc = k_first_vmx,
  vmx_v1_powerpc,
  vmx_v2_powerpc,
  vmx_v3_powerpc,
  vmx_v4_powerpc,
  vmx_v5_powerpc,
  vmx_v6_powerpc,
  vmx_v7_powerpc,
  vmx_v8_powerpc,
  vmx_v9_powerpc,
  vmx_v10_powerpc,
  vmx_v11_powerpc,
  vmx_v12_powerpc,
  vmx_v13_powerpc,
  vmx_v14_powerpc,
  vmx_v15_powerpc,
  vmx_v16_powerpc,
  vmx_v17_powerpc,
  vmx_v18_powerpc,
  vmx_v19_powerpc,
  vmx_v20_powerpc,
  vmx_v21_powerpc,
  vmx_v22_powerpc,
  vmx_v23_powerpc,
  vmx_v24_powerpc,
  vmx_v25_powerpc,
  vmx_v26_powerpc,
  vmx_v27_powerpc,
  vmx_v28_powerpc,
  vmx_v29_powerpc,
  vmx_v30_powerpc,
  vmx_v31_powerpc,
  vmx_vrsave_powerpc,
  vmx_vscr_powerpc,
  k_last_vmx = vmx_vscr_powerpc,
 
  k_num_registers_powerpc,
  k_num_gpr_registers_powerpc = k_last_gpr_powerpc - k_first_gpr_powerpc + 1,
  k_num_fpr_registers_powerpc = k_last_fpr - k_first_fpr + 1,
  k_num_vmx_registers_powerpc = k_last_vmx - k_first_vmx + 1,
};
 
#endif // LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_POWERPC_H