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RegisterInfos_arm64_sve.h
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1 //===-- RegisterInfos_arm64_sve.h -------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
10 
11 enum {
12  sve_vg = exc_far,
13 
14  sve_z0,
15  sve_z1,
16  sve_z2,
17  sve_z3,
18  sve_z4,
19  sve_z5,
20  sve_z6,
21  sve_z7,
22  sve_z8,
23  sve_z9,
24  sve_z10,
25  sve_z11,
26  sve_z12,
27  sve_z13,
28  sve_z14,
29  sve_z15,
30  sve_z16,
31  sve_z17,
32  sve_z18,
33  sve_z19,
34  sve_z20,
35  sve_z21,
36  sve_z22,
37  sve_z23,
38  sve_z24,
39  sve_z25,
40  sve_z26,
41  sve_z27,
42  sve_z28,
43  sve_z29,
44  sve_z30,
45  sve_z31,
46 
47  sve_p0,
48  sve_p1,
49  sve_p2,
50  sve_p3,
51  sve_p4,
52  sve_p5,
53  sve_p6,
54  sve_p7,
55  sve_p8,
56  sve_p9,
57  sve_p10,
58  sve_p11,
59  sve_p12,
60  sve_p13,
61  sve_p14,
62  sve_p15,
63 
64  sve_ffr,
65 };
66 
67 #ifndef SVE_OFFSET_VG
68 #error SVE_OFFSET_VG must be defined before including this header file
69 #endif
70 
71 static uint32_t g_sve_s0_invalidates[] = {sve_z0, fpu_v0, fpu_d0,
73 static uint32_t g_sve_s1_invalidates[] = {sve_z1, fpu_v1, fpu_d1,
75 static uint32_t g_sve_s2_invalidates[] = {sve_z2, fpu_v2, fpu_d2,
77 static uint32_t g_sve_s3_invalidates[] = {sve_z3, fpu_v3, fpu_d3,
79 static uint32_t g_sve_s4_invalidates[] = {sve_z4, fpu_v4, fpu_d4,
81 static uint32_t g_sve_s5_invalidates[] = {sve_z5, fpu_v5, fpu_d5,
83 static uint32_t g_sve_s6_invalidates[] = {sve_z6, fpu_v6, fpu_d6,
85 static uint32_t g_sve_s7_invalidates[] = {sve_z7, fpu_v7, fpu_d7,
87 static uint32_t g_sve_s8_invalidates[] = {sve_z8, fpu_v8, fpu_d8,
89 static uint32_t g_sve_s9_invalidates[] = {sve_z9, fpu_v9, fpu_d9,
91 static uint32_t g_sve_s10_invalidates[] = {sve_z10, fpu_v10, fpu_d10,
93 static uint32_t g_sve_s11_invalidates[] = {sve_z11, fpu_v11, fpu_d11,
95 static uint32_t g_sve_s12_invalidates[] = {sve_z12, fpu_v12, fpu_d12,
97 static uint32_t g_sve_s13_invalidates[] = {sve_z13, fpu_v13, fpu_d13,
99 static uint32_t g_sve_s14_invalidates[] = {sve_z14, fpu_v14, fpu_d14,
101 static uint32_t g_sve_s15_invalidates[] = {sve_z15, fpu_v15, fpu_d15,
103 static uint32_t g_sve_s16_invalidates[] = {sve_z16, fpu_v16, fpu_d16,
105 static uint32_t g_sve_s17_invalidates[] = {sve_z17, fpu_v17, fpu_d17,
107 static uint32_t g_sve_s18_invalidates[] = {sve_z18, fpu_v18, fpu_d18,
109 static uint32_t g_sve_s19_invalidates[] = {sve_z19, fpu_v19, fpu_d19,
111 static uint32_t g_sve_s20_invalidates[] = {sve_z20, fpu_v20, fpu_d20,
113 static uint32_t g_sve_s21_invalidates[] = {sve_z21, fpu_v21, fpu_d21,
115 static uint32_t g_sve_s22_invalidates[] = {sve_z22, fpu_v22, fpu_d22,
117 static uint32_t g_sve_s23_invalidates[] = {sve_z23, fpu_v23, fpu_d23,
119 static uint32_t g_sve_s24_invalidates[] = {sve_z24, fpu_v24, fpu_d24,
121 static uint32_t g_sve_s25_invalidates[] = {sve_z25, fpu_v25, fpu_d25,
123 static uint32_t g_sve_s26_invalidates[] = {sve_z26, fpu_v26, fpu_d26,
125 static uint32_t g_sve_s27_invalidates[] = {sve_z27, fpu_v27, fpu_d27,
127 static uint32_t g_sve_s28_invalidates[] = {sve_z28, fpu_v28, fpu_d28,
129 static uint32_t g_sve_s29_invalidates[] = {sve_z29, fpu_v29, fpu_d29,
131 static uint32_t g_sve_s30_invalidates[] = {sve_z30, fpu_v30, fpu_d30,
133 static uint32_t g_sve_s31_invalidates[] = {sve_z31, fpu_v31, fpu_d31,
135 
136 static uint32_t g_sve_d0_invalidates[] = {sve_z0, fpu_v0, fpu_s0,
138 static uint32_t g_sve_d1_invalidates[] = {sve_z1, fpu_v1, fpu_s1,
140 static uint32_t g_sve_d2_invalidates[] = {sve_z2, fpu_v2, fpu_s2,
142 static uint32_t g_sve_d3_invalidates[] = {sve_z3, fpu_v3, fpu_s3,
144 static uint32_t g_sve_d4_invalidates[] = {sve_z4, fpu_v4, fpu_s4,
146 static uint32_t g_sve_d5_invalidates[] = {sve_z5, fpu_v5, fpu_s5,
148 static uint32_t g_sve_d6_invalidates[] = {sve_z6, fpu_v6, fpu_s6,
150 static uint32_t g_sve_d7_invalidates[] = {sve_z7, fpu_v7, fpu_s7,
152 static uint32_t g_sve_d8_invalidates[] = {sve_z8, fpu_v8, fpu_s8,
154 static uint32_t g_sve_d9_invalidates[] = {sve_z9, fpu_v9, fpu_s9,
156 static uint32_t g_sve_d10_invalidates[] = {sve_z10, fpu_v10, fpu_s10,
158 static uint32_t g_sve_d11_invalidates[] = {sve_z11, fpu_v11, fpu_s11,
160 static uint32_t g_sve_d12_invalidates[] = {sve_z12, fpu_v12, fpu_s12,
162 static uint32_t g_sve_d13_invalidates[] = {sve_z13, fpu_v13, fpu_s13,
164 static uint32_t g_sve_d14_invalidates[] = {sve_z14, fpu_v14, fpu_s14,
166 static uint32_t g_sve_d15_invalidates[] = {sve_z15, fpu_v15, fpu_s15,
168 static uint32_t g_sve_d16_invalidates[] = {sve_z16, fpu_v16, fpu_s16,
170 static uint32_t g_sve_d17_invalidates[] = {sve_z17, fpu_v17, fpu_s17,
172 static uint32_t g_sve_d18_invalidates[] = {sve_z18, fpu_v18, fpu_s18,
174 static uint32_t g_sve_d19_invalidates[] = {sve_z19, fpu_v19, fpu_s19,
176 static uint32_t g_sve_d20_invalidates[] = {sve_z20, fpu_v20, fpu_s20,
178 static uint32_t g_sve_d21_invalidates[] = {sve_z21, fpu_v21, fpu_s21,
180 static uint32_t g_sve_d22_invalidates[] = {sve_z22, fpu_v22, fpu_s22,
182 static uint32_t g_sve_d23_invalidates[] = {sve_z23, fpu_v23, fpu_s23,
184 static uint32_t g_sve_d24_invalidates[] = {sve_z24, fpu_v24, fpu_s24,
186 static uint32_t g_sve_d25_invalidates[] = {sve_z25, fpu_v25, fpu_s25,
188 static uint32_t g_sve_d26_invalidates[] = {sve_z26, fpu_v26, fpu_s26,
190 static uint32_t g_sve_d27_invalidates[] = {sve_z27, fpu_v27, fpu_s27,
192 static uint32_t g_sve_d28_invalidates[] = {sve_z28, fpu_v28, fpu_s28,
194 static uint32_t g_sve_d29_invalidates[] = {sve_z29, fpu_v29, fpu_s29,
196 static uint32_t g_sve_d30_invalidates[] = {sve_z30, fpu_v30, fpu_s30,
198 static uint32_t g_sve_d31_invalidates[] = {sve_z31, fpu_v31, fpu_s31,
200 
201 static uint32_t g_sve_v0_invalidates[] = {sve_z0, fpu_d0, fpu_s0,
203 static uint32_t g_sve_v1_invalidates[] = {sve_z1, fpu_d1, fpu_s1,
205 static uint32_t g_sve_v2_invalidates[] = {sve_z2, fpu_d2, fpu_s2,
207 static uint32_t g_sve_v3_invalidates[] = {sve_z3, fpu_d3, fpu_s3,
209 static uint32_t g_sve_v4_invalidates[] = {sve_z4, fpu_d4, fpu_s4,
211 static uint32_t g_sve_v5_invalidates[] = {sve_z5, fpu_d5, fpu_s5,
213 static uint32_t g_sve_v6_invalidates[] = {sve_z6, fpu_d6, fpu_s6,
215 static uint32_t g_sve_v7_invalidates[] = {sve_z7, fpu_d7, fpu_s7,
217 static uint32_t g_sve_v8_invalidates[] = {sve_z8, fpu_d8, fpu_s8,
219 static uint32_t g_sve_v9_invalidates[] = {sve_z9, fpu_d9, fpu_s9,
221 static uint32_t g_sve_v10_invalidates[] = {sve_z10, fpu_d10, fpu_s10,
223 static uint32_t g_sve_v11_invalidates[] = {sve_z11, fpu_d11, fpu_s11,
225 static uint32_t g_sve_v12_invalidates[] = {sve_z12, fpu_d12, fpu_s12,
227 static uint32_t g_sve_v13_invalidates[] = {sve_z13, fpu_d13, fpu_s13,
229 static uint32_t g_sve_v14_invalidates[] = {sve_z14, fpu_d14, fpu_s14,
231 static uint32_t g_sve_v15_invalidates[] = {sve_z15, fpu_d15, fpu_s15,
233 static uint32_t g_sve_v16_invalidates[] = {sve_z16, fpu_d16, fpu_s16,
235 static uint32_t g_sve_v17_invalidates[] = {sve_z17, fpu_d17, fpu_s17,
237 static uint32_t g_sve_v18_invalidates[] = {sve_z18, fpu_d18, fpu_s18,
239 static uint32_t g_sve_v19_invalidates[] = {sve_z19, fpu_d19, fpu_s19,
241 static uint32_t g_sve_v20_invalidates[] = {sve_z20, fpu_d20, fpu_s20,
243 static uint32_t g_sve_v21_invalidates[] = {sve_z21, fpu_d21, fpu_s21,
245 static uint32_t g_sve_v22_invalidates[] = {sve_z22, fpu_d22, fpu_s22,
247 static uint32_t g_sve_v23_invalidates[] = {sve_z23, fpu_d23, fpu_s23,
249 static uint32_t g_sve_v24_invalidates[] = {sve_z24, fpu_d24, fpu_s24,
251 static uint32_t g_sve_v25_invalidates[] = {sve_z25, fpu_d25, fpu_s25,
253 static uint32_t g_sve_v26_invalidates[] = {sve_z26, fpu_d26, fpu_s26,
255 static uint32_t g_sve_v27_invalidates[] = {sve_z27, fpu_d27, fpu_s27,
257 static uint32_t g_sve_v28_invalidates[] = {sve_z28, fpu_d28, fpu_s28,
259 static uint32_t g_sve_v29_invalidates[] = {sve_z29, fpu_d29, fpu_s29,
261 static uint32_t g_sve_v30_invalidates[] = {sve_z30, fpu_d30, fpu_s30,
263 static uint32_t g_sve_v31_invalidates[] = {sve_z31, fpu_d31, fpu_s31,
265 
266 static uint32_t g_contained_z0[] = {sve_z0, LLDB_INVALID_REGNUM};
267 static uint32_t g_contained_z1[] = {sve_z1, LLDB_INVALID_REGNUM};
268 static uint32_t g_contained_z2[] = {sve_z2, LLDB_INVALID_REGNUM};
269 static uint32_t g_contained_z3[] = {sve_z3, LLDB_INVALID_REGNUM};
270 static uint32_t g_contained_z4[] = {sve_z4, LLDB_INVALID_REGNUM};
271 static uint32_t g_contained_z5[] = {sve_z5, LLDB_INVALID_REGNUM};
272 static uint32_t g_contained_z6[] = {sve_z6, LLDB_INVALID_REGNUM};
273 static uint32_t g_contained_z7[] = {sve_z7, LLDB_INVALID_REGNUM};
274 static uint32_t g_contained_z8[] = {sve_z8, LLDB_INVALID_REGNUM};
275 static uint32_t g_contained_z9[] = {sve_z9, LLDB_INVALID_REGNUM};
276 static uint32_t g_contained_z10[] = {sve_z10, LLDB_INVALID_REGNUM};
277 static uint32_t g_contained_z11[] = {sve_z11, LLDB_INVALID_REGNUM};
278 static uint32_t g_contained_z12[] = {sve_z12, LLDB_INVALID_REGNUM};
279 static uint32_t g_contained_z13[] = {sve_z13, LLDB_INVALID_REGNUM};
280 static uint32_t g_contained_z14[] = {sve_z14, LLDB_INVALID_REGNUM};
281 static uint32_t g_contained_z15[] = {sve_z15, LLDB_INVALID_REGNUM};
282 static uint32_t g_contained_z16[] = {sve_z16, LLDB_INVALID_REGNUM};
283 static uint32_t g_contained_z17[] = {sve_z17, LLDB_INVALID_REGNUM};
284 static uint32_t g_contained_z18[] = {sve_z18, LLDB_INVALID_REGNUM};
285 static uint32_t g_contained_z19[] = {sve_z19, LLDB_INVALID_REGNUM};
286 static uint32_t g_contained_z20[] = {sve_z20, LLDB_INVALID_REGNUM};
287 static uint32_t g_contained_z21[] = {sve_z21, LLDB_INVALID_REGNUM};
288 static uint32_t g_contained_z22[] = {sve_z22, LLDB_INVALID_REGNUM};
289 static uint32_t g_contained_z23[] = {sve_z23, LLDB_INVALID_REGNUM};
290 static uint32_t g_contained_z24[] = {sve_z24, LLDB_INVALID_REGNUM};
291 static uint32_t g_contained_z25[] = {sve_z25, LLDB_INVALID_REGNUM};
292 static uint32_t g_contained_z26[] = {sve_z26, LLDB_INVALID_REGNUM};
293 static uint32_t g_contained_z27[] = {sve_z27, LLDB_INVALID_REGNUM};
294 static uint32_t g_contained_z28[] = {sve_z28, LLDB_INVALID_REGNUM};
295 static uint32_t g_contained_z29[] = {sve_z29, LLDB_INVALID_REGNUM};
296 static uint32_t g_contained_z30[] = {sve_z30, LLDB_INVALID_REGNUM};
297 static uint32_t g_contained_z31[] = {sve_z31, LLDB_INVALID_REGNUM};
298 
299 #define VG_OFFSET_NAME(reg) SVE_OFFSET_VG
300 
301 #define SVE_REG_KIND(reg) MISC_KIND(reg, sve, LLDB_INVALID_REGNUM)
302 #define MISC_VG_KIND(lldb_kind) MISC_KIND(vg, sve, LLDB_INVALID_REGNUM)
303 
304 // Default offset SVE Z registers and all corresponding pseudo registers
305 // ( S, D and V registers) is zero and will be configured during execution.
306 
307 // Defines sve pseudo vector (V) register with 16-byte size
308 #define DEFINE_VREG_SVE(vreg, zreg) \
309  { \
310  #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
311  VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \
312  }
313 
314 // Defines S and D pseudo registers mapping over corresponding vector register
315 #define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg) \
316  { \
317  #reg, nullptr, size, 0, lldb::eEncodingIEEE754, lldb::eFormatFloat, \
318  LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates, \
319  }
320 
321 // Defines a Z vector register with 16-byte default size
322 #define DEFINE_ZREG(reg) \
323  { \
324  #reg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
325  SVE_REG_KIND(reg), nullptr, nullptr, \
326  }
327 
328 // Defines a P vector register with 2-byte default size
329 #define DEFINE_PREG(reg) \
330  { \
331  #reg, nullptr, 2, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
332  SVE_REG_KIND(reg), nullptr, nullptr, \
333  }
334 
335 static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
336  // clang-format off
337  // DEFINE_GPR64(name, GENERIC KIND)
338  DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
339  DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2),
340  DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3),
341  DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4),
342  DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5),
343  DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6),
344  DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7),
345  DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8),
346  DEFINE_GPR64(x8, LLDB_INVALID_REGNUM),
347  DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
348  DEFINE_GPR64(x10, LLDB_INVALID_REGNUM),
349  DEFINE_GPR64(x11, LLDB_INVALID_REGNUM),
350  DEFINE_GPR64(x12, LLDB_INVALID_REGNUM),
351  DEFINE_GPR64(x13, LLDB_INVALID_REGNUM),
352  DEFINE_GPR64(x14, LLDB_INVALID_REGNUM),
353  DEFINE_GPR64(x15, LLDB_INVALID_REGNUM),
354  DEFINE_GPR64(x16, LLDB_INVALID_REGNUM),
355  DEFINE_GPR64(x17, LLDB_INVALID_REGNUM),
356  DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
357  DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
358  DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
359  DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
360  DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
361  DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
362  DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
363  DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
364  DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
365  DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
366  DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
367  // DEFINE_GPR64(name, GENERIC KIND)
368  DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP),
369  DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA),
370  DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
371  DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
372 
373  // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
374  DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
375 
376  // DEFINE_GPR32(name, parent name)
377  DEFINE_GPR32(w0, x0),
378  DEFINE_GPR32(w1, x1),
379  DEFINE_GPR32(w2, x2),
380  DEFINE_GPR32(w3, x3),
381  DEFINE_GPR32(w4, x4),
382  DEFINE_GPR32(w5, x5),
383  DEFINE_GPR32(w6, x6),
384  DEFINE_GPR32(w7, x7),
385  DEFINE_GPR32(w8, x8),
386  DEFINE_GPR32(w9, x9),
387  DEFINE_GPR32(w10, x10),
388  DEFINE_GPR32(w11, x11),
389  DEFINE_GPR32(w12, x12),
390  DEFINE_GPR32(w13, x13),
391  DEFINE_GPR32(w14, x14),
392  DEFINE_GPR32(w15, x15),
393  DEFINE_GPR32(w16, x16),
394  DEFINE_GPR32(w17, x17),
395  DEFINE_GPR32(w18, x18),
396  DEFINE_GPR32(w19, x19),
397  DEFINE_GPR32(w20, x20),
398  DEFINE_GPR32(w21, x21),
399  DEFINE_GPR32(w22, x22),
400  DEFINE_GPR32(w23, x23),
401  DEFINE_GPR32(w24, x24),
402  DEFINE_GPR32(w25, x25),
403  DEFINE_GPR32(w26, x26),
404  DEFINE_GPR32(w27, x27),
405  DEFINE_GPR32(w28, x28),
406 
407  // DEFINE_VREG_SVE(v register, z register)
408  DEFINE_VREG_SVE(v0, z0),
409  DEFINE_VREG_SVE(v1, z1),
410  DEFINE_VREG_SVE(v2, z2),
411  DEFINE_VREG_SVE(v3, z3),
412  DEFINE_VREG_SVE(v4, z4),
413  DEFINE_VREG_SVE(v5, z5),
414  DEFINE_VREG_SVE(v6, z6),
415  DEFINE_VREG_SVE(v7, z7),
416  DEFINE_VREG_SVE(v8, z8),
417  DEFINE_VREG_SVE(v9, z9),
418  DEFINE_VREG_SVE(v10, z10),
419  DEFINE_VREG_SVE(v11, z11),
420  DEFINE_VREG_SVE(v12, z12),
421  DEFINE_VREG_SVE(v13, z13),
422  DEFINE_VREG_SVE(v14, z14),
423  DEFINE_VREG_SVE(v15, z15),
424  DEFINE_VREG_SVE(v16, z16),
425  DEFINE_VREG_SVE(v17, z17),
426  DEFINE_VREG_SVE(v18, z18),
427  DEFINE_VREG_SVE(v19, z19),
428  DEFINE_VREG_SVE(v20, z20),
429  DEFINE_VREG_SVE(v21, z21),
430  DEFINE_VREG_SVE(v22, z22),
431  DEFINE_VREG_SVE(v23, z23),
432  DEFINE_VREG_SVE(v24, z24),
433  DEFINE_VREG_SVE(v25, z25),
434  DEFINE_VREG_SVE(v26, z26),
435  DEFINE_VREG_SVE(v27, z27),
436  DEFINE_VREG_SVE(v28, z28),
437  DEFINE_VREG_SVE(v29, z29),
438  DEFINE_VREG_SVE(v30, z30),
439  DEFINE_VREG_SVE(v31, z31),
440 
441  // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register)
442  DEFINE_FPU_PSEUDO_SVE(s0, 4, z0),
443  DEFINE_FPU_PSEUDO_SVE(s1, 4, z1),
444  DEFINE_FPU_PSEUDO_SVE(s2, 4, z2),
445  DEFINE_FPU_PSEUDO_SVE(s3, 4, z3),
446  DEFINE_FPU_PSEUDO_SVE(s4, 4, z4),
447  DEFINE_FPU_PSEUDO_SVE(s5, 4, z5),
448  DEFINE_FPU_PSEUDO_SVE(s6, 4, z6),
449  DEFINE_FPU_PSEUDO_SVE(s7, 4, z7),
450  DEFINE_FPU_PSEUDO_SVE(s8, 4, z8),
451  DEFINE_FPU_PSEUDO_SVE(s9, 4, z9),
452  DEFINE_FPU_PSEUDO_SVE(s10, 4, z10),
453  DEFINE_FPU_PSEUDO_SVE(s11, 4, z11),
454  DEFINE_FPU_PSEUDO_SVE(s12, 4, z12),
455  DEFINE_FPU_PSEUDO_SVE(s13, 4, z13),
456  DEFINE_FPU_PSEUDO_SVE(s14, 4, z14),
457  DEFINE_FPU_PSEUDO_SVE(s15, 4, z15),
458  DEFINE_FPU_PSEUDO_SVE(s16, 4, z16),
459  DEFINE_FPU_PSEUDO_SVE(s17, 4, z17),
460  DEFINE_FPU_PSEUDO_SVE(s18, 4, z18),
461  DEFINE_FPU_PSEUDO_SVE(s19, 4, z19),
462  DEFINE_FPU_PSEUDO_SVE(s20, 4, z20),
463  DEFINE_FPU_PSEUDO_SVE(s21, 4, z21),
464  DEFINE_FPU_PSEUDO_SVE(s22, 4, z22),
465  DEFINE_FPU_PSEUDO_SVE(s23, 4, z23),
466  DEFINE_FPU_PSEUDO_SVE(s24, 4, z24),
467  DEFINE_FPU_PSEUDO_SVE(s25, 4, z25),
468  DEFINE_FPU_PSEUDO_SVE(s26, 4, z26),
469  DEFINE_FPU_PSEUDO_SVE(s27, 4, z27),
470  DEFINE_FPU_PSEUDO_SVE(s28, 4, z28),
471  DEFINE_FPU_PSEUDO_SVE(s29, 4, z29),
472  DEFINE_FPU_PSEUDO_SVE(s30, 4, z30),
473  DEFINE_FPU_PSEUDO_SVE(s31, 4, z31),
474 
475  DEFINE_FPU_PSEUDO_SVE(d0, 8, z0),
476  DEFINE_FPU_PSEUDO_SVE(d1, 8, z1),
477  DEFINE_FPU_PSEUDO_SVE(d2, 8, z2),
478  DEFINE_FPU_PSEUDO_SVE(d3, 8, z3),
479  DEFINE_FPU_PSEUDO_SVE(d4, 8, z4),
480  DEFINE_FPU_PSEUDO_SVE(d5, 8, z5),
481  DEFINE_FPU_PSEUDO_SVE(d6, 8, z6),
482  DEFINE_FPU_PSEUDO_SVE(d7, 8, z7),
483  DEFINE_FPU_PSEUDO_SVE(d8, 8, z8),
484  DEFINE_FPU_PSEUDO_SVE(d9, 8, z9),
485  DEFINE_FPU_PSEUDO_SVE(d10, 8, z10),
486  DEFINE_FPU_PSEUDO_SVE(d11, 8, z11),
487  DEFINE_FPU_PSEUDO_SVE(d12, 8, z12),
488  DEFINE_FPU_PSEUDO_SVE(d13, 8, z13),
489  DEFINE_FPU_PSEUDO_SVE(d14, 8, z14),
490  DEFINE_FPU_PSEUDO_SVE(d15, 8, z15),
491  DEFINE_FPU_PSEUDO_SVE(d16, 8, z16),
492  DEFINE_FPU_PSEUDO_SVE(d17, 8, z17),
493  DEFINE_FPU_PSEUDO_SVE(d18, 8, z18),
494  DEFINE_FPU_PSEUDO_SVE(d19, 8, z19),
495  DEFINE_FPU_PSEUDO_SVE(d20, 8, z20),
496  DEFINE_FPU_PSEUDO_SVE(d21, 8, z21),
497  DEFINE_FPU_PSEUDO_SVE(d22, 8, z22),
498  DEFINE_FPU_PSEUDO_SVE(d23, 8, z23),
499  DEFINE_FPU_PSEUDO_SVE(d24, 8, z24),
500  DEFINE_FPU_PSEUDO_SVE(d25, 8, z25),
501  DEFINE_FPU_PSEUDO_SVE(d26, 8, z26),
502  DEFINE_FPU_PSEUDO_SVE(d27, 8, z27),
503  DEFINE_FPU_PSEUDO_SVE(d28, 8, z28),
504  DEFINE_FPU_PSEUDO_SVE(d29, 8, z29),
505  DEFINE_FPU_PSEUDO_SVE(d30, 8, z30),
506  DEFINE_FPU_PSEUDO_SVE(d31, 8, z31),
507 
508  // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
509  DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
510  DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
511 
512  DEFINE_MISC_REGS(vg, 8, VG, sve_vg),
513  // DEFINE_ZREG(name)
514  DEFINE_ZREG(z0),
515  DEFINE_ZREG(z1),
516  DEFINE_ZREG(z2),
517  DEFINE_ZREG(z3),
518  DEFINE_ZREG(z4),
519  DEFINE_ZREG(z5),
520  DEFINE_ZREG(z6),
521  DEFINE_ZREG(z7),
522  DEFINE_ZREG(z8),
523  DEFINE_ZREG(z9),
524  DEFINE_ZREG(z10),
525  DEFINE_ZREG(z11),
526  DEFINE_ZREG(z12),
527  DEFINE_ZREG(z13),
528  DEFINE_ZREG(z14),
529  DEFINE_ZREG(z15),
530  DEFINE_ZREG(z16),
531  DEFINE_ZREG(z17),
532  DEFINE_ZREG(z18),
533  DEFINE_ZREG(z19),
534  DEFINE_ZREG(z20),
535  DEFINE_ZREG(z21),
536  DEFINE_ZREG(z22),
537  DEFINE_ZREG(z23),
538  DEFINE_ZREG(z24),
539  DEFINE_ZREG(z25),
540  DEFINE_ZREG(z26),
541  DEFINE_ZREG(z27),
542  DEFINE_ZREG(z28),
543  DEFINE_ZREG(z29),
544  DEFINE_ZREG(z30),
545  DEFINE_ZREG(z31),
546 
547  // DEFINE_PREG(name)
548  DEFINE_PREG(p0),
549  DEFINE_PREG(p1),
550  DEFINE_PREG(p2),
551  DEFINE_PREG(p3),
552  DEFINE_PREG(p4),
553  DEFINE_PREG(p5),
554  DEFINE_PREG(p6),
555  DEFINE_PREG(p7),
556  DEFINE_PREG(p8),
557  DEFINE_PREG(p9),
558  DEFINE_PREG(p10),
559  DEFINE_PREG(p11),
560  DEFINE_PREG(p12),
561  DEFINE_PREG(p13),
562  DEFINE_PREG(p14),
563  DEFINE_PREG(p15),
564 
565  // DEFINE FFR
566  DEFINE_PREG(ffr)
567  // clang-format on
568 };
569 
570 #endif // DECLARE_REGISTER_INFOS_ARM64_SVE_STRUCT
arm64_dwarf::x18
@ x18
Definition: ARM64_DWARF_Registers.h:35
arm64_dwarf::p11
@ p11
Definition: ARM64_DWARF_Registers.h:74
LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_ARG2
Definition: lldb-defines.h:70
fpu_s24
@ fpu_s24
Definition: RegisterContextDarwin_arm.cpp:78
LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG3
Definition: lldb-defines.h:72
x27
@ x27
Definition: CompactUnwindInfo.cpp:1244
v12
@ v12
Definition: CompactUnwindInfo.cpp:1261
LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG1
Definition: lldb-defines.h:68
arm64_dwarf::z16
@ z16
Definition: ARM64_DWARF_Registers.h:131
x20
@ x20
Definition: CompactUnwindInfo.cpp:1237
arm64_dwarf::x10
@ x10
Definition: ARM64_DWARF_Registers.h:27
fpu_s19
@ fpu_s19
Definition: RegisterContextDarwin_arm.cpp:73
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:91
v10
@ v10
Definition: CompactUnwindInfo.cpp:1259
arm64_dwarf::p3
@ p3
Definition: ARM64_DWARF_Registers.h:66
arm64_dwarf::v31
@ v31
Definition: ARM64_DWARF_Registers.h:112
fpu_s12
@ fpu_s12
Definition: RegisterContextDarwin_arm.cpp:66
arm64_dwarf::v1
@ v1
Definition: ARM64_DWARF_Registers.h:82
fpu_s5
@ fpu_s5
Definition: RegisterContextDarwin_arm.cpp:59
arm64_dwarf::x2
@ x2
Definition: ARM64_DWARF_Registers.h:19
fpu_s2
@ fpu_s2
Definition: RegisterContextDarwin_arm.cpp:56
LLDB_REGNUM_GENERIC_ARG5
#define LLDB_REGNUM_GENERIC_ARG5
Definition: lldb-defines.h:76
arm64_dwarf::p6
@ p6
Definition: ARM64_DWARF_Registers.h:69
x19
@ x19
Definition: CompactUnwindInfo.cpp:1236
fpu_s23
@ fpu_s23
Definition: RegisterContextDarwin_arm.cpp:77
fpu_s17
@ fpu_s17
Definition: RegisterContextDarwin_arm.cpp:71
fpu_s22
@ fpu_s22
Definition: RegisterContextDarwin_arm.cpp:76
arm64_dwarf::v22
@ v22
Definition: ARM64_DWARF_Registers.h:103
arm64_dwarf::x15
@ x15
Definition: ARM64_DWARF_Registers.h:32
arm64_dwarf::p9
@ p9
Definition: ARM64_DWARF_Registers.h:72
arm64_dwarf::z6
@ z6
Definition: ARM64_DWARF_Registers.h:121
arm64_dwarf::cpsr
@ cpsr
Definition: ARM64_DWARF_Registers.h:53
arm64_dwarf::x12
@ x12
Definition: ARM64_DWARF_Registers.h:29
arm64_dwarf::v29
@ v29
Definition: ARM64_DWARF_Registers.h:110
arm64_dwarf::x13
@ x13
Definition: ARM64_DWARF_Registers.h:30
gpr_cpsr
@ gpr_cpsr
Definition: RegisterContextDarwin_arm.cpp:52
arm64_dwarf::v20
@ v20
Definition: ARM64_DWARF_Registers.h:101
fpu_s6
@ fpu_s6
Definition: RegisterContextDarwin_arm.cpp:60
arm64_dwarf::v27
@ v27
Definition: ARM64_DWARF_Registers.h:108
v9
@ v9
Definition: CompactUnwindInfo.cpp:1258
arm64_dwarf::z25
@ z25
Definition: ARM64_DWARF_Registers.h:140
arm64_dwarf::v24
@ v24
Definition: ARM64_DWARF_Registers.h:105
fpu_s0
@ fpu_s0
Definition: RegisterContextDarwin_arm.cpp:54
pc
@ pc
Definition: CompactUnwindInfo.cpp:1250
arm64_dwarf::x3
@ x3
Definition: ARM64_DWARF_Registers.h:20
arm64_dwarf::z3
@ z3
Definition: ARM64_DWARF_Registers.h:118
arm64_dwarf::p12
@ p12
Definition: ARM64_DWARF_Registers.h:75
arm64_dwarf::x17
@ x17
Definition: ARM64_DWARF_Registers.h:34
arm64_dwarf::p5
@ p5
Definition: ARM64_DWARF_Registers.h:68
arm64_dwarf::z24
@ z24
Definition: ARM64_DWARF_Registers.h:139
arm64_dwarf::x6
@ x6
Definition: ARM64_DWARF_Registers.h:23
arm64_dwarf::z14
@ z14
Definition: ARM64_DWARF_Registers.h:129
LLDB_REGNUM_GENERIC_ARG6
#define LLDB_REGNUM_GENERIC_ARG6
Definition: lldb-defines.h:78
arm64_dwarf::z19
@ z19
Definition: ARM64_DWARF_Registers.h:134
fpu_s26
@ fpu_s26
Definition: RegisterContextDarwin_arm.cpp:80
arm64_dwarf::z30
@ z30
Definition: ARM64_DWARF_Registers.h:145
arm64_dwarf::p4
@ p4
Definition: ARM64_DWARF_Registers.h:67
x26
@ x26
Definition: CompactUnwindInfo.cpp:1243
arm64_dwarf::v7
@ v7
Definition: ARM64_DWARF_Registers.h:88
arm64_dwarf::x11
@ x11
Definition: ARM64_DWARF_Registers.h:28
arm64_dwarf::z27
@ z27
Definition: ARM64_DWARF_Registers.h:142
v13
@ v13
Definition: CompactUnwindInfo.cpp:1262
arm64_dwarf::p15
@ p15
Definition: ARM64_DWARF_Registers.h:78
x24
@ x24
Definition: CompactUnwindInfo.cpp:1241
fpu_s3
@ fpu_s3
Definition: RegisterContextDarwin_arm.cpp:57
arm64_dwarf::v21
@ v21
Definition: ARM64_DWARF_Registers.h:102
fpu_s10
@ fpu_s10
Definition: RegisterContextDarwin_arm.cpp:64
fpu_s29
@ fpu_s29
Definition: RegisterContextDarwin_arm.cpp:83
arm64_dwarf::z7
@ z7
Definition: ARM64_DWARF_Registers.h:122
arm64_dwarf::z0
@ z0
Definition: ARM64_DWARF_Registers.h:115
arm64_dwarf::z10
@ z10
Definition: ARM64_DWARF_Registers.h:125
fpu_s31
@ fpu_s31
Definition: RegisterContextDarwin_arm.cpp:85
arm64_dwarf::z20
@ z20
Definition: ARM64_DWARF_Registers.h:135
fpu_s15
@ fpu_s15
Definition: RegisterContextDarwin_arm.cpp:69
arm64_dwarf::z31
@ z31
Definition: ARM64_DWARF_Registers.h:146
arm64_dwarf::p7
@ p7
Definition: ARM64_DWARF_Registers.h:70
arm64_dwarf::z11
@ z11
Definition: ARM64_DWARF_Registers.h:126
fpu_s18
@ fpu_s18
Definition: RegisterContextDarwin_arm.cpp:72
arm64_dwarf::x1
@ x1
Definition: ARM64_DWARF_Registers.h:18
exc_far
@ exc_far
Definition: RegisterContextDarwin_arm.cpp:90
arm64_dwarf::p0
@ p0
Definition: ARM64_DWARF_Registers.h:63
fpu_s20
@ fpu_s20
Definition: RegisterContextDarwin_arm.cpp:74
fpu_s16
@ fpu_s16
Definition: RegisterContextDarwin_arm.cpp:70
sp
@ sp
Definition: CompactUnwindInfo.cpp:1249
arm64_dwarf::z5
@ z5
Definition: ARM64_DWARF_Registers.h:120
arm64_dwarf::v0
@ v0
Definition: ARM64_DWARF_Registers.h:81
v15
@ v15
Definition: CompactUnwindInfo.cpp:1264
fpu_s7
@ fpu_s7
Definition: RegisterContextDarwin_arm.cpp:61
arm64_dwarf::z23
@ z23
Definition: ARM64_DWARF_Registers.h:138
arm64_dwarf::v17
@ v17
Definition: ARM64_DWARF_Registers.h:98
x22
@ x22
Definition: CompactUnwindInfo.cpp:1239
arm64_dwarf::x4
@ x4
Definition: ARM64_DWARF_Registers.h:21
arm64_dwarf::z4
@ z4
Definition: ARM64_DWARF_Registers.h:119
arm64_dwarf::z18
@ z18
Definition: ARM64_DWARF_Registers.h:133
v8
@ v8
Definition: CompactUnwindInfo.cpp:1257
fpu_s25
@ fpu_s25
Definition: RegisterContextDarwin_arm.cpp:79
arm64_dwarf::z29
@ z29
Definition: ARM64_DWARF_Registers.h:144
arm64_dwarf::x14
@ x14
Definition: ARM64_DWARF_Registers.h:31
x23
@ x23
Definition: CompactUnwindInfo.cpp:1240
arm64_dwarf::v28
@ v28
Definition: ARM64_DWARF_Registers.h:109
fpu_s13
@ fpu_s13
Definition: RegisterContextDarwin_arm.cpp:67
v11
@ v11
Definition: CompactUnwindInfo.cpp:1260
GPR
Definition: RegisterContextFreeBSD_i386.cpp:16
arm64_dwarf::v2
@ v2
Definition: ARM64_DWARF_Registers.h:83
arm64_dwarf::v3
@ v3
Definition: ARM64_DWARF_Registers.h:84
fpu_s4
@ fpu_s4
Definition: RegisterContextDarwin_arm.cpp:58
arm64_dwarf::v4
@ v4
Definition: ARM64_DWARF_Registers.h:85
uint32_t
arm64_dwarf::z13
@ z13
Definition: ARM64_DWARF_Registers.h:128
arm64_dwarf::v25
@ v25
Definition: ARM64_DWARF_Registers.h:106
x28
@ x28
Definition: CompactUnwindInfo.cpp:1245
LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:64
arm64_dwarf::z9
@ z9
Definition: ARM64_DWARF_Registers.h:124
arm64_dwarf::z2
@ z2
Definition: ARM64_DWARF_Registers.h:117
arm64_dwarf::p14
@ p14
Definition: ARM64_DWARF_Registers.h:77
arm64_dwarf::x7
@ x7
Definition: ARM64_DWARF_Registers.h:24
fpu_s9
@ fpu_s9
Definition: RegisterContextDarwin_arm.cpp:63
arm64_dwarf::x16
@ x16
Definition: ARM64_DWARF_Registers.h:33
arm64_dwarf::z17
@ z17
Definition: ARM64_DWARF_Registers.h:132
fpu_s11
@ fpu_s11
Definition: RegisterContextDarwin_arm.cpp:65
fpu_s21
@ fpu_s21
Definition: RegisterContextDarwin_arm.cpp:75
arm64_dwarf::x8
@ x8
Definition: ARM64_DWARF_Registers.h:25
arm64_dwarf::p10
@ p10
Definition: ARM64_DWARF_Registers.h:73
x25
@ x25
Definition: CompactUnwindInfo.cpp:1242
arm64_dwarf::v18
@ v18
Definition: ARM64_DWARF_Registers.h:99
LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG4
Definition: lldb-defines.h:74
arm64_dwarf::x31
@ x31
Definition: ARM64_DWARF_Registers.h:50
arm64_dwarf::p2
@ p2
Definition: ARM64_DWARF_Registers.h:65
arm64_dwarf::vg
@ vg
Definition: ARM64_DWARF_Registers.h:57
arm64_dwarf::z21
@ z21
Definition: ARM64_DWARF_Registers.h:136
LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:65
fpu_s30
@ fpu_s30
Definition: RegisterContextDarwin_arm.cpp:84
arm64_dwarf::z12
@ z12
Definition: ARM64_DWARF_Registers.h:127
arm64_dwarf::ffr
@ ffr
Definition: ARM64_DWARF_Registers.h:60
arm64_dwarf::x29
@ x29
Definition: ARM64_DWARF_Registers.h:46
LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:63
fpu_s1
@ fpu_s1
Definition: RegisterContextDarwin_arm.cpp:55
arm64_dwarf::x9
@ x9
Definition: ARM64_DWARF_Registers.h:26
arm64_dwarf::x0
@ x0
Definition: ARM64_DWARF_Registers.h:17
arm64_dwarf::z1
@ z1
Definition: ARM64_DWARF_Registers.h:116
arm64_dwarf::p8
@ p8
Definition: ARM64_DWARF_Registers.h:71
arm64_dwarf::z22
@ z22
Definition: ARM64_DWARF_Registers.h:137
arm64_dwarf::z28
@ z28
Definition: ARM64_DWARF_Registers.h:143
LLDB_REGNUM_GENERIC_ARG8
#define LLDB_REGNUM_GENERIC_ARG8
Definition: lldb-defines.h:82
fpu_s14
@ fpu_s14
Definition: RegisterContextDarwin_arm.cpp:68
x21
@ x21
Definition: CompactUnwindInfo.cpp:1238
arm64_dwarf::v19
@ v19
Definition: ARM64_DWARF_Registers.h:100
LLDB_REGNUM_GENERIC_ARG7
#define LLDB_REGNUM_GENERIC_ARG7
Definition: lldb-defines.h:80
fp
@ fp
Definition: CompactUnwindInfo.cpp:1247
arm64_dwarf::p13
@ p13
Definition: ARM64_DWARF_Registers.h:76
arm64_dwarf::v5
@ v5
Definition: ARM64_DWARF_Registers.h:86
fpu_s28
@ fpu_s28
Definition: RegisterContextDarwin_arm.cpp:82
arm64_dwarf::v16
@ v16
Definition: ARM64_DWARF_Registers.h:97
fpu_s8
@ fpu_s8
Definition: RegisterContextDarwin_arm.cpp:62
arm64_dwarf::p1
@ p1
Definition: ARM64_DWARF_Registers.h:64
v14
@ v14
Definition: CompactUnwindInfo.cpp:1263
arm64_dwarf::v23
@ v23
Definition: ARM64_DWARF_Registers.h:104
arm64_dwarf::lr
@ lr
Definition: ARM64_DWARF_Registers.h:49
arm64_dwarf::x30
@ x30
Definition: ARM64_DWARF_Registers.h:48
arm64_dwarf::v30
@ v30
Definition: ARM64_DWARF_Registers.h:111
arm64_dwarf::z26
@ z26
Definition: ARM64_DWARF_Registers.h:141
arm64_dwarf::x5
@ x5
Definition: ARM64_DWARF_Registers.h:22
arm64_dwarf::z15
@ z15
Definition: ARM64_DWARF_Registers.h:130
arm64_dwarf::v6
@ v6
Definition: ARM64_DWARF_Registers.h:87
arm64_dwarf::v26
@ v26
Definition: ARM64_DWARF_Registers.h:107
LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:66
arm64_dwarf::z8
@ z8
Definition: ARM64_DWARF_Registers.h:123
fpu_s27
@ fpu_s27
Definition: RegisterContextDarwin_arm.cpp:81