9#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
68#error SVE_OFFSET_VG must be defined before including this header file
71static uint32_t g_sve_s0_invalidates[] = {sve_z0, fpu_v0, fpu_d0,
73static uint32_t g_sve_s1_invalidates[] = {sve_z1, fpu_v1, fpu_d1,
75static uint32_t g_sve_s2_invalidates[] = {sve_z2, fpu_v2, fpu_d2,
77static uint32_t g_sve_s3_invalidates[] = {sve_z3, fpu_v3, fpu_d3,
79static uint32_t g_sve_s4_invalidates[] = {sve_z4, fpu_v4, fpu_d4,
81static uint32_t g_sve_s5_invalidates[] = {sve_z5, fpu_v5, fpu_d5,
83static uint32_t g_sve_s6_invalidates[] = {sve_z6, fpu_v6, fpu_d6,
85static uint32_t g_sve_s7_invalidates[] = {sve_z7, fpu_v7, fpu_d7,
87static uint32_t g_sve_s8_invalidates[] = {sve_z8, fpu_v8, fpu_d8,
89static uint32_t g_sve_s9_invalidates[] = {sve_z9, fpu_v9, fpu_d9,
91static uint32_t g_sve_s10_invalidates[] = {sve_z10, fpu_v10, fpu_d10,
93static uint32_t g_sve_s11_invalidates[] = {sve_z11, fpu_v11, fpu_d11,
95static uint32_t g_sve_s12_invalidates[] = {sve_z12, fpu_v12, fpu_d12,
97static uint32_t g_sve_s13_invalidates[] = {sve_z13, fpu_v13, fpu_d13,
99static uint32_t g_sve_s14_invalidates[] = {sve_z14, fpu_v14, fpu_d14,
101static uint32_t g_sve_s15_invalidates[] = {sve_z15, fpu_v15, fpu_d15,
103static uint32_t g_sve_s16_invalidates[] = {sve_z16, fpu_v16, fpu_d16,
105static uint32_t g_sve_s17_invalidates[] = {sve_z17, fpu_v17, fpu_d17,
107static uint32_t g_sve_s18_invalidates[] = {sve_z18, fpu_v18, fpu_d18,
109static uint32_t g_sve_s19_invalidates[] = {sve_z19, fpu_v19, fpu_d19,
111static uint32_t g_sve_s20_invalidates[] = {sve_z20, fpu_v20, fpu_d20,
113static uint32_t g_sve_s21_invalidates[] = {sve_z21, fpu_v21, fpu_d21,
115static uint32_t g_sve_s22_invalidates[] = {sve_z22, fpu_v22, fpu_d22,
117static uint32_t g_sve_s23_invalidates[] = {sve_z23, fpu_v23, fpu_d23,
119static uint32_t g_sve_s24_invalidates[] = {sve_z24, fpu_v24, fpu_d24,
121static uint32_t g_sve_s25_invalidates[] = {sve_z25, fpu_v25, fpu_d25,
123static uint32_t g_sve_s26_invalidates[] = {sve_z26, fpu_v26, fpu_d26,
125static uint32_t g_sve_s27_invalidates[] = {sve_z27, fpu_v27, fpu_d27,
127static uint32_t g_sve_s28_invalidates[] = {sve_z28, fpu_v28, fpu_d28,
129static uint32_t g_sve_s29_invalidates[] = {sve_z29, fpu_v29, fpu_d29,
131static uint32_t g_sve_s30_invalidates[] = {sve_z30, fpu_v30, fpu_d30,
133static uint32_t g_sve_s31_invalidates[] = {sve_z31, fpu_v31, fpu_d31,
136static uint32_t g_sve_d0_invalidates[] = {sve_z0, fpu_v0,
fpu_s0,
138static uint32_t g_sve_d1_invalidates[] = {sve_z1, fpu_v1,
fpu_s1,
140static uint32_t g_sve_d2_invalidates[] = {sve_z2, fpu_v2,
fpu_s2,
142static uint32_t g_sve_d3_invalidates[] = {sve_z3, fpu_v3,
fpu_s3,
144static uint32_t g_sve_d4_invalidates[] = {sve_z4, fpu_v4,
fpu_s4,
146static uint32_t g_sve_d5_invalidates[] = {sve_z5, fpu_v5,
fpu_s5,
148static uint32_t g_sve_d6_invalidates[] = {sve_z6, fpu_v6,
fpu_s6,
150static uint32_t g_sve_d7_invalidates[] = {sve_z7, fpu_v7,
fpu_s7,
152static uint32_t g_sve_d8_invalidates[] = {sve_z8, fpu_v8,
fpu_s8,
154static uint32_t g_sve_d9_invalidates[] = {sve_z9, fpu_v9,
fpu_s9,
156static uint32_t g_sve_d10_invalidates[] = {sve_z10, fpu_v10,
fpu_s10,
158static uint32_t g_sve_d11_invalidates[] = {sve_z11, fpu_v11,
fpu_s11,
160static uint32_t g_sve_d12_invalidates[] = {sve_z12, fpu_v12,
fpu_s12,
162static uint32_t g_sve_d13_invalidates[] = {sve_z13, fpu_v13,
fpu_s13,
164static uint32_t g_sve_d14_invalidates[] = {sve_z14, fpu_v14,
fpu_s14,
166static uint32_t g_sve_d15_invalidates[] = {sve_z15, fpu_v15,
fpu_s15,
168static uint32_t g_sve_d16_invalidates[] = {sve_z16, fpu_v16,
fpu_s16,
170static uint32_t g_sve_d17_invalidates[] = {sve_z17, fpu_v17,
fpu_s17,
172static uint32_t g_sve_d18_invalidates[] = {sve_z18, fpu_v18,
fpu_s18,
174static uint32_t g_sve_d19_invalidates[] = {sve_z19, fpu_v19,
fpu_s19,
176static uint32_t g_sve_d20_invalidates[] = {sve_z20, fpu_v20,
fpu_s20,
178static uint32_t g_sve_d21_invalidates[] = {sve_z21, fpu_v21,
fpu_s21,
180static uint32_t g_sve_d22_invalidates[] = {sve_z22, fpu_v22,
fpu_s22,
182static uint32_t g_sve_d23_invalidates[] = {sve_z23, fpu_v23,
fpu_s23,
184static uint32_t g_sve_d24_invalidates[] = {sve_z24, fpu_v24,
fpu_s24,
186static uint32_t g_sve_d25_invalidates[] = {sve_z25, fpu_v25,
fpu_s25,
188static uint32_t g_sve_d26_invalidates[] = {sve_z26, fpu_v26,
fpu_s26,
190static uint32_t g_sve_d27_invalidates[] = {sve_z27, fpu_v27,
fpu_s27,
192static uint32_t g_sve_d28_invalidates[] = {sve_z28, fpu_v28,
fpu_s28,
194static uint32_t g_sve_d29_invalidates[] = {sve_z29, fpu_v29,
fpu_s29,
196static uint32_t g_sve_d30_invalidates[] = {sve_z30, fpu_v30,
fpu_s30,
198static uint32_t g_sve_d31_invalidates[] = {sve_z31, fpu_v31,
fpu_s31,
201static uint32_t g_sve_v0_invalidates[] = {sve_z0, fpu_d0,
fpu_s0,
203static uint32_t g_sve_v1_invalidates[] = {sve_z1, fpu_d1,
fpu_s1,
205static uint32_t g_sve_v2_invalidates[] = {sve_z2, fpu_d2,
fpu_s2,
207static uint32_t g_sve_v3_invalidates[] = {sve_z3, fpu_d3,
fpu_s3,
209static uint32_t g_sve_v4_invalidates[] = {sve_z4, fpu_d4,
fpu_s4,
211static uint32_t g_sve_v5_invalidates[] = {sve_z5, fpu_d5,
fpu_s5,
213static uint32_t g_sve_v6_invalidates[] = {sve_z6, fpu_d6,
fpu_s6,
215static uint32_t g_sve_v7_invalidates[] = {sve_z7, fpu_d7,
fpu_s7,
217static uint32_t g_sve_v8_invalidates[] = {sve_z8, fpu_d8,
fpu_s8,
219static uint32_t g_sve_v9_invalidates[] = {sve_z9, fpu_d9,
fpu_s9,
221static uint32_t g_sve_v10_invalidates[] = {sve_z10, fpu_d10,
fpu_s10,
223static uint32_t g_sve_v11_invalidates[] = {sve_z11, fpu_d11,
fpu_s11,
225static uint32_t g_sve_v12_invalidates[] = {sve_z12, fpu_d12,
fpu_s12,
227static uint32_t g_sve_v13_invalidates[] = {sve_z13, fpu_d13,
fpu_s13,
229static uint32_t g_sve_v14_invalidates[] = {sve_z14, fpu_d14,
fpu_s14,
231static uint32_t g_sve_v15_invalidates[] = {sve_z15, fpu_d15,
fpu_s15,
233static uint32_t g_sve_v16_invalidates[] = {sve_z16, fpu_d16,
fpu_s16,
235static uint32_t g_sve_v17_invalidates[] = {sve_z17, fpu_d17,
fpu_s17,
237static uint32_t g_sve_v18_invalidates[] = {sve_z18, fpu_d18,
fpu_s18,
239static uint32_t g_sve_v19_invalidates[] = {sve_z19, fpu_d19,
fpu_s19,
241static uint32_t g_sve_v20_invalidates[] = {sve_z20, fpu_d20,
fpu_s20,
243static uint32_t g_sve_v21_invalidates[] = {sve_z21, fpu_d21,
fpu_s21,
245static uint32_t g_sve_v22_invalidates[] = {sve_z22, fpu_d22,
fpu_s22,
247static uint32_t g_sve_v23_invalidates[] = {sve_z23, fpu_d23,
fpu_s23,
249static uint32_t g_sve_v24_invalidates[] = {sve_z24, fpu_d24,
fpu_s24,
251static uint32_t g_sve_v25_invalidates[] = {sve_z25, fpu_d25,
fpu_s25,
253static uint32_t g_sve_v26_invalidates[] = {sve_z26, fpu_d26,
fpu_s26,
255static uint32_t g_sve_v27_invalidates[] = {sve_z27, fpu_d27,
fpu_s27,
257static uint32_t g_sve_v28_invalidates[] = {sve_z28, fpu_d28,
fpu_s28,
259static uint32_t g_sve_v29_invalidates[] = {sve_z29, fpu_d29,
fpu_s29,
261static uint32_t g_sve_v30_invalidates[] = {sve_z30, fpu_d30,
fpu_s30,
263static uint32_t g_sve_v31_invalidates[] = {sve_z31, fpu_d31,
fpu_s31,
299#define VG_OFFSET_NAME(reg) SVE_OFFSET_VG
301#define SVE_REG_KIND(reg) MISC_KIND(reg, sve, LLDB_INVALID_REGNUM)
302#define MISC_VG_KIND(lldb_kind) MISC_KIND(vg, sve, LLDB_INVALID_REGNUM)
310#define DEFINE_VREG_SVE(vreg, zreg) \
312 #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
313 VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \
318#define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg) \
320 #reg, nullptr, size, 0, lldb::eEncodingIEEE754, lldb::eFormatFloat, \
321 LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates, \
326#define DEFINE_ZREG(reg) \
328 #reg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
329 SVE_REG_KIND(reg), nullptr, nullptr, nullptr, \
333#define DEFINE_PREG(reg) \
335 #reg, nullptr, 2, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
336 SVE_REG_KIND(reg), nullptr, nullptr, nullptr, \
380 DEFINE_GPR32(w0, x0),
381 DEFINE_GPR32(w1, x1),
382 DEFINE_GPR32(w2, x2),
383 DEFINE_GPR32(w3, x3),
384 DEFINE_GPR32(w4, x4),
385 DEFINE_GPR32(w5, x5),
386 DEFINE_GPR32(w6, x6),
387 DEFINE_GPR32(w7, x7),
388 DEFINE_GPR32(w8, x8),
389 DEFINE_GPR32(w9, x9),
390 DEFINE_GPR32(w10, x10),
391 DEFINE_GPR32(w11, x11),
392 DEFINE_GPR32(w12, x12),
393 DEFINE_GPR32(w13, x13),
394 DEFINE_GPR32(w14, x14),
395 DEFINE_GPR32(w15, x15),
396 DEFINE_GPR32(w16, x16),
397 DEFINE_GPR32(w17, x17),
398 DEFINE_GPR32(w18, x18),
399 DEFINE_GPR32(w19,
x19),
400 DEFINE_GPR32(w20,
x20),
401 DEFINE_GPR32(w21,
x21),
402 DEFINE_GPR32(w22,
x22),
403 DEFINE_GPR32(w23,
x23),
404 DEFINE_GPR32(w24,
x24),
405 DEFINE_GPR32(w25,
x25),
406 DEFINE_GPR32(w26,
x26),
407 DEFINE_GPR32(w27,
x27),
408 DEFINE_GPR32(w28,
x28),
411 DEFINE_VREG_SVE(v0, z0),
412 DEFINE_VREG_SVE(v1, z1),
413 DEFINE_VREG_SVE(v2, z2),
414 DEFINE_VREG_SVE(v3, z3),
415 DEFINE_VREG_SVE(v4, z4),
416 DEFINE_VREG_SVE(v5, z5),
417 DEFINE_VREG_SVE(v6, z6),
418 DEFINE_VREG_SVE(v7, z7),
419 DEFINE_VREG_SVE(
v8, z8),
420 DEFINE_VREG_SVE(
v9, z9),
421 DEFINE_VREG_SVE(
v10, z10),
422 DEFINE_VREG_SVE(
v11, z11),
423 DEFINE_VREG_SVE(
v12, z12),
424 DEFINE_VREG_SVE(
v13, z13),
425 DEFINE_VREG_SVE(
v14, z14),
426 DEFINE_VREG_SVE(
v15, z15),
427 DEFINE_VREG_SVE(v16, z16),
428 DEFINE_VREG_SVE(v17, z17),
429 DEFINE_VREG_SVE(v18, z18),
430 DEFINE_VREG_SVE(v19, z19),
431 DEFINE_VREG_SVE(v20, z20),
432 DEFINE_VREG_SVE(v21, z21),
433 DEFINE_VREG_SVE(v22, z22),
434 DEFINE_VREG_SVE(v23, z23),
435 DEFINE_VREG_SVE(v24, z24),
436 DEFINE_VREG_SVE(v25, z25),
437 DEFINE_VREG_SVE(v26, z26),
438 DEFINE_VREG_SVE(v27, z27),
439 DEFINE_VREG_SVE(v28, z28),
440 DEFINE_VREG_SVE(v29, z29),
441 DEFINE_VREG_SVE(v30, z30),
442 DEFINE_VREG_SVE(v31, z31),
445 DEFINE_FPU_PSEUDO_SVE(s0, 4, z0),
446 DEFINE_FPU_PSEUDO_SVE(s1, 4, z1),
447 DEFINE_FPU_PSEUDO_SVE(s2, 4, z2),
448 DEFINE_FPU_PSEUDO_SVE(s3, 4, z3),
449 DEFINE_FPU_PSEUDO_SVE(s4, 4, z4),
450 DEFINE_FPU_PSEUDO_SVE(s5, 4, z5),
451 DEFINE_FPU_PSEUDO_SVE(s6, 4, z6),
452 DEFINE_FPU_PSEUDO_SVE(s7, 4, z7),
453 DEFINE_FPU_PSEUDO_SVE(s8, 4, z8),
454 DEFINE_FPU_PSEUDO_SVE(s9, 4, z9),
455 DEFINE_FPU_PSEUDO_SVE(s10, 4, z10),
456 DEFINE_FPU_PSEUDO_SVE(s11, 4, z11),
457 DEFINE_FPU_PSEUDO_SVE(s12, 4, z12),
458 DEFINE_FPU_PSEUDO_SVE(s13, 4, z13),
459 DEFINE_FPU_PSEUDO_SVE(s14, 4, z14),
460 DEFINE_FPU_PSEUDO_SVE(s15, 4, z15),
461 DEFINE_FPU_PSEUDO_SVE(s16, 4, z16),
462 DEFINE_FPU_PSEUDO_SVE(s17, 4, z17),
463 DEFINE_FPU_PSEUDO_SVE(s18, 4, z18),
464 DEFINE_FPU_PSEUDO_SVE(s19, 4, z19),
465 DEFINE_FPU_PSEUDO_SVE(s20, 4, z20),
466 DEFINE_FPU_PSEUDO_SVE(s21, 4, z21),
467 DEFINE_FPU_PSEUDO_SVE(s22, 4, z22),
468 DEFINE_FPU_PSEUDO_SVE(s23, 4, z23),
469 DEFINE_FPU_PSEUDO_SVE(s24, 4, z24),
470 DEFINE_FPU_PSEUDO_SVE(s25, 4, z25),
471 DEFINE_FPU_PSEUDO_SVE(s26, 4, z26),
472 DEFINE_FPU_PSEUDO_SVE(s27, 4, z27),
473 DEFINE_FPU_PSEUDO_SVE(s28, 4, z28),
474 DEFINE_FPU_PSEUDO_SVE(s29, 4, z29),
475 DEFINE_FPU_PSEUDO_SVE(s30, 4, z30),
476 DEFINE_FPU_PSEUDO_SVE(s31, 4, z31),
478 DEFINE_FPU_PSEUDO_SVE(d0, 8, z0),
479 DEFINE_FPU_PSEUDO_SVE(d1, 8, z1),
480 DEFINE_FPU_PSEUDO_SVE(d2, 8, z2),
481 DEFINE_FPU_PSEUDO_SVE(d3, 8, z3),
482 DEFINE_FPU_PSEUDO_SVE(d4, 8, z4),
483 DEFINE_FPU_PSEUDO_SVE(d5, 8, z5),
484 DEFINE_FPU_PSEUDO_SVE(d6, 8, z6),
485 DEFINE_FPU_PSEUDO_SVE(d7, 8, z7),
486 DEFINE_FPU_PSEUDO_SVE(d8, 8, z8),
487 DEFINE_FPU_PSEUDO_SVE(d9, 8, z9),
488 DEFINE_FPU_PSEUDO_SVE(d10, 8, z10),
489 DEFINE_FPU_PSEUDO_SVE(d11, 8, z11),
490 DEFINE_FPU_PSEUDO_SVE(d12, 8, z12),
491 DEFINE_FPU_PSEUDO_SVE(d13, 8, z13),
492 DEFINE_FPU_PSEUDO_SVE(d14, 8, z14),
493 DEFINE_FPU_PSEUDO_SVE(d15, 8, z15),
494 DEFINE_FPU_PSEUDO_SVE(d16, 8, z16),
495 DEFINE_FPU_PSEUDO_SVE(d17, 8, z17),
496 DEFINE_FPU_PSEUDO_SVE(d18, 8, z18),
497 DEFINE_FPU_PSEUDO_SVE(d19, 8, z19),
498 DEFINE_FPU_PSEUDO_SVE(d20, 8, z20),
499 DEFINE_FPU_PSEUDO_SVE(d21, 8, z21),
500 DEFINE_FPU_PSEUDO_SVE(d22, 8, z22),
501 DEFINE_FPU_PSEUDO_SVE(d23, 8, z23),
502 DEFINE_FPU_PSEUDO_SVE(d24, 8, z24),
503 DEFINE_FPU_PSEUDO_SVE(d25, 8, z25),
504 DEFINE_FPU_PSEUDO_SVE(d26, 8, z26),
505 DEFINE_FPU_PSEUDO_SVE(d27, 8, z27),
506 DEFINE_FPU_PSEUDO_SVE(d28, 8, z28),
507 DEFINE_FPU_PSEUDO_SVE(d29, 8, z29),
508 DEFINE_FPU_PSEUDO_SVE(d30, 8, z30),
509 DEFINE_FPU_PSEUDO_SVE(d31, 8, z31),
512 DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
513 DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
515 DEFINE_MISC_REGS(vg, 8, VG, sve_vg),
#define LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_ARG8
#define LLDB_REGNUM_GENERIC_ARG6
#define LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG7
#define LLDB_INVALID_REGNUM
#define LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_ARG5
Every register is described in detail including its name, alternate name (optional),...