9#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
68#error SVE_OFFSET_VG must be defined before including this header file
71static uint32_t g_sve_s0_invalidates[] = {sve_z0, fpu_v0, fpu_d0,
73static uint32_t g_sve_s1_invalidates[] = {sve_z1, fpu_v1, fpu_d1,
75static uint32_t g_sve_s2_invalidates[] = {sve_z2, fpu_v2, fpu_d2,
77static uint32_t g_sve_s3_invalidates[] = {sve_z3, fpu_v3, fpu_d3,
79static uint32_t g_sve_s4_invalidates[] = {sve_z4, fpu_v4, fpu_d4,
81static uint32_t g_sve_s5_invalidates[] = {sve_z5, fpu_v5, fpu_d5,
83static uint32_t g_sve_s6_invalidates[] = {sve_z6, fpu_v6, fpu_d6,
85static uint32_t g_sve_s7_invalidates[] = {sve_z7, fpu_v7, fpu_d7,
87static uint32_t g_sve_s8_invalidates[] = {sve_z8, fpu_v8, fpu_d8,
89static uint32_t g_sve_s9_invalidates[] = {sve_z9, fpu_v9, fpu_d9,
91static uint32_t g_sve_s10_invalidates[] = {sve_z10, fpu_v10, fpu_d10,
93static uint32_t g_sve_s11_invalidates[] = {sve_z11, fpu_v11, fpu_d11,
95static uint32_t g_sve_s12_invalidates[] = {sve_z12, fpu_v12, fpu_d12,
97static uint32_t g_sve_s13_invalidates[] = {sve_z13, fpu_v13, fpu_d13,
99static uint32_t g_sve_s14_invalidates[] = {sve_z14, fpu_v14, fpu_d14,
101static uint32_t g_sve_s15_invalidates[] = {sve_z15, fpu_v15, fpu_d15,
103static uint32_t g_sve_s16_invalidates[] = {sve_z16, fpu_v16, fpu_d16,
105static uint32_t g_sve_s17_invalidates[] = {sve_z17, fpu_v17, fpu_d17,
107static uint32_t g_sve_s18_invalidates[] = {sve_z18, fpu_v18, fpu_d18,
109static uint32_t g_sve_s19_invalidates[] = {sve_z19, fpu_v19, fpu_d19,
111static uint32_t g_sve_s20_invalidates[] = {sve_z20, fpu_v20, fpu_d20,
113static uint32_t g_sve_s21_invalidates[] = {sve_z21, fpu_v21, fpu_d21,
115static uint32_t g_sve_s22_invalidates[] = {sve_z22, fpu_v22, fpu_d22,
117static uint32_t g_sve_s23_invalidates[] = {sve_z23, fpu_v23, fpu_d23,
119static uint32_t g_sve_s24_invalidates[] = {sve_z24, fpu_v24, fpu_d24,
121static uint32_t g_sve_s25_invalidates[] = {sve_z25, fpu_v25, fpu_d25,
123static uint32_t g_sve_s26_invalidates[] = {sve_z26, fpu_v26, fpu_d26,
125static uint32_t g_sve_s27_invalidates[] = {sve_z27, fpu_v27, fpu_d27,
127static uint32_t g_sve_s28_invalidates[] = {sve_z28, fpu_v28, fpu_d28,
129static uint32_t g_sve_s29_invalidates[] = {sve_z29, fpu_v29, fpu_d29,
131static uint32_t g_sve_s30_invalidates[] = {sve_z30, fpu_v30, fpu_d30,
133static uint32_t g_sve_s31_invalidates[] = {sve_z31, fpu_v31, fpu_d31,
299#define VG_OFFSET_NAME(reg) SVE_OFFSET_VG
301#define SVE_REG_KIND(reg) MISC_KIND(reg, sve, LLDB_INVALID_REGNUM)
302#define MISC_VG_KIND(lldb_kind) MISC_KIND(vg, sve, LLDB_INVALID_REGNUM)
310#define DEFINE_VREG_SVE(vreg, zreg) \
312 #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
313 VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \
317#define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg) \
319 #reg, nullptr, size, 0, lldb::eEncodingIEEE754, lldb::eFormatFloat, \
320 LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates, \
324#define DEFINE_ZREG(reg) \
326 #reg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
327 SVE_REG_KIND(reg), nullptr, nullptr, \
331#define DEFINE_PREG(reg) \
333 #reg, nullptr, 2, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
334 SVE_REG_KIND(reg), nullptr, nullptr, \
337static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
378 DEFINE_GPR32(w0, x0),
379 DEFINE_GPR32(w1, x1),
380 DEFINE_GPR32(w2, x2),
381 DEFINE_GPR32(w3, x3),
382 DEFINE_GPR32(w4, x4),
383 DEFINE_GPR32(w5, x5),
384 DEFINE_GPR32(w6, x6),
385 DEFINE_GPR32(w7, x7),
386 DEFINE_GPR32(w8, x8),
387 DEFINE_GPR32(w9, x9),
388 DEFINE_GPR32(w10, x10),
389 DEFINE_GPR32(w11, x11),
390 DEFINE_GPR32(w12, x12),
391 DEFINE_GPR32(w13, x13),
392 DEFINE_GPR32(w14, x14),
393 DEFINE_GPR32(w15, x15),
394 DEFINE_GPR32(w16, x16),
395 DEFINE_GPR32(w17, x17),
396 DEFINE_GPR32(w18, x18),
397 DEFINE_GPR32(w19,
x19),
398 DEFINE_GPR32(w20,
x20),
399 DEFINE_GPR32(w21,
x21),
400 DEFINE_GPR32(w22,
x22),
401 DEFINE_GPR32(w23,
x23),
402 DEFINE_GPR32(w24,
x24),
403 DEFINE_GPR32(w25,
x25),
404 DEFINE_GPR32(w26,
x26),
405 DEFINE_GPR32(w27,
x27),
406 DEFINE_GPR32(w28,
x28),
409 DEFINE_VREG_SVE(v0, z0),
410 DEFINE_VREG_SVE(v1, z1),
411 DEFINE_VREG_SVE(v2, z2),
412 DEFINE_VREG_SVE(v3, z3),
413 DEFINE_VREG_SVE(v4, z4),
414 DEFINE_VREG_SVE(v5, z5),
415 DEFINE_VREG_SVE(v6, z6),
416 DEFINE_VREG_SVE(v7, z7),
417 DEFINE_VREG_SVE(
v8, z8),
418 DEFINE_VREG_SVE(
v9, z9),
419 DEFINE_VREG_SVE(
v10, z10),
420 DEFINE_VREG_SVE(
v11, z11),
421 DEFINE_VREG_SVE(
v12, z12),
422 DEFINE_VREG_SVE(
v13, z13),
423 DEFINE_VREG_SVE(
v14, z14),
424 DEFINE_VREG_SVE(
v15, z15),
425 DEFINE_VREG_SVE(v16, z16),
426 DEFINE_VREG_SVE(v17, z17),
427 DEFINE_VREG_SVE(v18, z18),
428 DEFINE_VREG_SVE(v19, z19),
429 DEFINE_VREG_SVE(v20, z20),
430 DEFINE_VREG_SVE(v21, z21),
431 DEFINE_VREG_SVE(v22, z22),
432 DEFINE_VREG_SVE(v23, z23),
433 DEFINE_VREG_SVE(v24, z24),
434 DEFINE_VREG_SVE(v25, z25),
435 DEFINE_VREG_SVE(v26, z26),
436 DEFINE_VREG_SVE(v27, z27),
437 DEFINE_VREG_SVE(v28, z28),
438 DEFINE_VREG_SVE(v29, z29),
439 DEFINE_VREG_SVE(v30, z30),
440 DEFINE_VREG_SVE(v31, z31),
443 DEFINE_FPU_PSEUDO_SVE(s0, 4, z0),
444 DEFINE_FPU_PSEUDO_SVE(s1, 4, z1),
445 DEFINE_FPU_PSEUDO_SVE(s2, 4, z2),
446 DEFINE_FPU_PSEUDO_SVE(s3, 4, z3),
447 DEFINE_FPU_PSEUDO_SVE(s4, 4, z4),
448 DEFINE_FPU_PSEUDO_SVE(s5, 4, z5),
449 DEFINE_FPU_PSEUDO_SVE(s6, 4, z6),
450 DEFINE_FPU_PSEUDO_SVE(s7, 4, z7),
451 DEFINE_FPU_PSEUDO_SVE(s8, 4, z8),
452 DEFINE_FPU_PSEUDO_SVE(s9, 4, z9),
453 DEFINE_FPU_PSEUDO_SVE(s10, 4, z10),
454 DEFINE_FPU_PSEUDO_SVE(s11, 4, z11),
455 DEFINE_FPU_PSEUDO_SVE(s12, 4, z12),
456 DEFINE_FPU_PSEUDO_SVE(s13, 4, z13),
457 DEFINE_FPU_PSEUDO_SVE(s14, 4, z14),
458 DEFINE_FPU_PSEUDO_SVE(s15, 4, z15),
459 DEFINE_FPU_PSEUDO_SVE(s16, 4, z16),
460 DEFINE_FPU_PSEUDO_SVE(s17, 4, z17),
461 DEFINE_FPU_PSEUDO_SVE(s18, 4, z18),
462 DEFINE_FPU_PSEUDO_SVE(s19, 4, z19),
463 DEFINE_FPU_PSEUDO_SVE(s20, 4, z20),
464 DEFINE_FPU_PSEUDO_SVE(s21, 4, z21),
465 DEFINE_FPU_PSEUDO_SVE(s22, 4, z22),
466 DEFINE_FPU_PSEUDO_SVE(s23, 4, z23),
467 DEFINE_FPU_PSEUDO_SVE(s24, 4, z24),
468 DEFINE_FPU_PSEUDO_SVE(s25, 4, z25),
469 DEFINE_FPU_PSEUDO_SVE(s26, 4, z26),
470 DEFINE_FPU_PSEUDO_SVE(s27, 4, z27),
471 DEFINE_FPU_PSEUDO_SVE(s28, 4, z28),
472 DEFINE_FPU_PSEUDO_SVE(s29, 4, z29),
473 DEFINE_FPU_PSEUDO_SVE(s30, 4, z30),
474 DEFINE_FPU_PSEUDO_SVE(s31, 4, z31),
476 DEFINE_FPU_PSEUDO_SVE(d0, 8, z0),
477 DEFINE_FPU_PSEUDO_SVE(d1, 8, z1),
478 DEFINE_FPU_PSEUDO_SVE(d2, 8, z2),
479 DEFINE_FPU_PSEUDO_SVE(d3, 8, z3),
480 DEFINE_FPU_PSEUDO_SVE(d4, 8, z4),
481 DEFINE_FPU_PSEUDO_SVE(d5, 8, z5),
482 DEFINE_FPU_PSEUDO_SVE(d6, 8, z6),
483 DEFINE_FPU_PSEUDO_SVE(d7, 8, z7),
484 DEFINE_FPU_PSEUDO_SVE(d8, 8, z8),
485 DEFINE_FPU_PSEUDO_SVE(d9, 8, z9),
486 DEFINE_FPU_PSEUDO_SVE(d10, 8, z10),
487 DEFINE_FPU_PSEUDO_SVE(d11, 8, z11),
488 DEFINE_FPU_PSEUDO_SVE(d12, 8, z12),
489 DEFINE_FPU_PSEUDO_SVE(d13, 8, z13),
490 DEFINE_FPU_PSEUDO_SVE(d14, 8, z14),
491 DEFINE_FPU_PSEUDO_SVE(d15, 8, z15),
492 DEFINE_FPU_PSEUDO_SVE(d16, 8, z16),
493 DEFINE_FPU_PSEUDO_SVE(d17, 8, z17),
494 DEFINE_FPU_PSEUDO_SVE(d18, 8, z18),
495 DEFINE_FPU_PSEUDO_SVE(d19, 8, z19),
496 DEFINE_FPU_PSEUDO_SVE(d20, 8, z20),
497 DEFINE_FPU_PSEUDO_SVE(d21, 8, z21),
498 DEFINE_FPU_PSEUDO_SVE(d22, 8, z22),
499 DEFINE_FPU_PSEUDO_SVE(d23, 8, z23),
500 DEFINE_FPU_PSEUDO_SVE(d24, 8, z24),
501 DEFINE_FPU_PSEUDO_SVE(d25, 8, z25),
502 DEFINE_FPU_PSEUDO_SVE(d26, 8, z26),
503 DEFINE_FPU_PSEUDO_SVE(d27, 8, z27),
504 DEFINE_FPU_PSEUDO_SVE(d28, 8, z28),
505 DEFINE_FPU_PSEUDO_SVE(d29, 8, z29),
506 DEFINE_FPU_PSEUDO_SVE(d30, 8, z30),
507 DEFINE_FPU_PSEUDO_SVE(d31, 8, z31),
510 DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
511 DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
513 DEFINE_MISC_REGS(vg, 8, VG, sve_vg),
#define LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_ARG8
#define LLDB_REGNUM_GENERIC_ARG6
#define LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG7
#define LLDB_INVALID_REGNUM
#define LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_ARG5