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RegisterInfos_arm64_sve.h
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1//===-- RegisterInfos_arm64_sve.h -------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
10
11enum {
12 sve_vg = exc_far,
13
14 sve_z0,
15 sve_z1,
16 sve_z2,
17 sve_z3,
18 sve_z4,
19 sve_z5,
20 sve_z6,
21 sve_z7,
22 sve_z8,
23 sve_z9,
24 sve_z10,
25 sve_z11,
26 sve_z12,
27 sve_z13,
28 sve_z14,
29 sve_z15,
30 sve_z16,
31 sve_z17,
32 sve_z18,
33 sve_z19,
34 sve_z20,
35 sve_z21,
36 sve_z22,
37 sve_z23,
38 sve_z24,
39 sve_z25,
40 sve_z26,
41 sve_z27,
42 sve_z28,
43 sve_z29,
44 sve_z30,
45 sve_z31,
46
47 sve_p0,
48 sve_p1,
49 sve_p2,
50 sve_p3,
51 sve_p4,
52 sve_p5,
53 sve_p6,
54 sve_p7,
55 sve_p8,
56 sve_p9,
57 sve_p10,
58 sve_p11,
59 sve_p12,
60 sve_p13,
61 sve_p14,
62 sve_p15,
63
64 sve_ffr,
65};
66
67#ifndef SVE_OFFSET_VG
68#error SVE_OFFSET_VG must be defined before including this header file
69#endif
70
71static uint32_t g_sve_s0_invalidates[] = {sve_z0, fpu_v0, fpu_d0,
73static uint32_t g_sve_s1_invalidates[] = {sve_z1, fpu_v1, fpu_d1,
75static uint32_t g_sve_s2_invalidates[] = {sve_z2, fpu_v2, fpu_d2,
77static uint32_t g_sve_s3_invalidates[] = {sve_z3, fpu_v3, fpu_d3,
79static uint32_t g_sve_s4_invalidates[] = {sve_z4, fpu_v4, fpu_d4,
81static uint32_t g_sve_s5_invalidates[] = {sve_z5, fpu_v5, fpu_d5,
83static uint32_t g_sve_s6_invalidates[] = {sve_z6, fpu_v6, fpu_d6,
85static uint32_t g_sve_s7_invalidates[] = {sve_z7, fpu_v7, fpu_d7,
87static uint32_t g_sve_s8_invalidates[] = {sve_z8, fpu_v8, fpu_d8,
89static uint32_t g_sve_s9_invalidates[] = {sve_z9, fpu_v9, fpu_d9,
91static uint32_t g_sve_s10_invalidates[] = {sve_z10, fpu_v10, fpu_d10,
93static uint32_t g_sve_s11_invalidates[] = {sve_z11, fpu_v11, fpu_d11,
95static uint32_t g_sve_s12_invalidates[] = {sve_z12, fpu_v12, fpu_d12,
97static uint32_t g_sve_s13_invalidates[] = {sve_z13, fpu_v13, fpu_d13,
99static uint32_t g_sve_s14_invalidates[] = {sve_z14, fpu_v14, fpu_d14,
101static uint32_t g_sve_s15_invalidates[] = {sve_z15, fpu_v15, fpu_d15,
103static uint32_t g_sve_s16_invalidates[] = {sve_z16, fpu_v16, fpu_d16,
105static uint32_t g_sve_s17_invalidates[] = {sve_z17, fpu_v17, fpu_d17,
107static uint32_t g_sve_s18_invalidates[] = {sve_z18, fpu_v18, fpu_d18,
109static uint32_t g_sve_s19_invalidates[] = {sve_z19, fpu_v19, fpu_d19,
111static uint32_t g_sve_s20_invalidates[] = {sve_z20, fpu_v20, fpu_d20,
113static uint32_t g_sve_s21_invalidates[] = {sve_z21, fpu_v21, fpu_d21,
115static uint32_t g_sve_s22_invalidates[] = {sve_z22, fpu_v22, fpu_d22,
117static uint32_t g_sve_s23_invalidates[] = {sve_z23, fpu_v23, fpu_d23,
119static uint32_t g_sve_s24_invalidates[] = {sve_z24, fpu_v24, fpu_d24,
121static uint32_t g_sve_s25_invalidates[] = {sve_z25, fpu_v25, fpu_d25,
123static uint32_t g_sve_s26_invalidates[] = {sve_z26, fpu_v26, fpu_d26,
125static uint32_t g_sve_s27_invalidates[] = {sve_z27, fpu_v27, fpu_d27,
127static uint32_t g_sve_s28_invalidates[] = {sve_z28, fpu_v28, fpu_d28,
129static uint32_t g_sve_s29_invalidates[] = {sve_z29, fpu_v29, fpu_d29,
131static uint32_t g_sve_s30_invalidates[] = {sve_z30, fpu_v30, fpu_d30,
133static uint32_t g_sve_s31_invalidates[] = {sve_z31, fpu_v31, fpu_d31,
135
136static uint32_t g_sve_d0_invalidates[] = {sve_z0, fpu_v0, fpu_s0,
138static uint32_t g_sve_d1_invalidates[] = {sve_z1, fpu_v1, fpu_s1,
140static uint32_t g_sve_d2_invalidates[] = {sve_z2, fpu_v2, fpu_s2,
142static uint32_t g_sve_d3_invalidates[] = {sve_z3, fpu_v3, fpu_s3,
144static uint32_t g_sve_d4_invalidates[] = {sve_z4, fpu_v4, fpu_s4,
146static uint32_t g_sve_d5_invalidates[] = {sve_z5, fpu_v5, fpu_s5,
148static uint32_t g_sve_d6_invalidates[] = {sve_z6, fpu_v6, fpu_s6,
150static uint32_t g_sve_d7_invalidates[] = {sve_z7, fpu_v7, fpu_s7,
152static uint32_t g_sve_d8_invalidates[] = {sve_z8, fpu_v8, fpu_s8,
154static uint32_t g_sve_d9_invalidates[] = {sve_z9, fpu_v9, fpu_s9,
156static uint32_t g_sve_d10_invalidates[] = {sve_z10, fpu_v10, fpu_s10,
158static uint32_t g_sve_d11_invalidates[] = {sve_z11, fpu_v11, fpu_s11,
160static uint32_t g_sve_d12_invalidates[] = {sve_z12, fpu_v12, fpu_s12,
162static uint32_t g_sve_d13_invalidates[] = {sve_z13, fpu_v13, fpu_s13,
164static uint32_t g_sve_d14_invalidates[] = {sve_z14, fpu_v14, fpu_s14,
166static uint32_t g_sve_d15_invalidates[] = {sve_z15, fpu_v15, fpu_s15,
168static uint32_t g_sve_d16_invalidates[] = {sve_z16, fpu_v16, fpu_s16,
170static uint32_t g_sve_d17_invalidates[] = {sve_z17, fpu_v17, fpu_s17,
172static uint32_t g_sve_d18_invalidates[] = {sve_z18, fpu_v18, fpu_s18,
174static uint32_t g_sve_d19_invalidates[] = {sve_z19, fpu_v19, fpu_s19,
176static uint32_t g_sve_d20_invalidates[] = {sve_z20, fpu_v20, fpu_s20,
178static uint32_t g_sve_d21_invalidates[] = {sve_z21, fpu_v21, fpu_s21,
180static uint32_t g_sve_d22_invalidates[] = {sve_z22, fpu_v22, fpu_s22,
182static uint32_t g_sve_d23_invalidates[] = {sve_z23, fpu_v23, fpu_s23,
184static uint32_t g_sve_d24_invalidates[] = {sve_z24, fpu_v24, fpu_s24,
186static uint32_t g_sve_d25_invalidates[] = {sve_z25, fpu_v25, fpu_s25,
188static uint32_t g_sve_d26_invalidates[] = {sve_z26, fpu_v26, fpu_s26,
190static uint32_t g_sve_d27_invalidates[] = {sve_z27, fpu_v27, fpu_s27,
192static uint32_t g_sve_d28_invalidates[] = {sve_z28, fpu_v28, fpu_s28,
194static uint32_t g_sve_d29_invalidates[] = {sve_z29, fpu_v29, fpu_s29,
196static uint32_t g_sve_d30_invalidates[] = {sve_z30, fpu_v30, fpu_s30,
198static uint32_t g_sve_d31_invalidates[] = {sve_z31, fpu_v31, fpu_s31,
200
201static uint32_t g_sve_v0_invalidates[] = {sve_z0, fpu_d0, fpu_s0,
203static uint32_t g_sve_v1_invalidates[] = {sve_z1, fpu_d1, fpu_s1,
205static uint32_t g_sve_v2_invalidates[] = {sve_z2, fpu_d2, fpu_s2,
207static uint32_t g_sve_v3_invalidates[] = {sve_z3, fpu_d3, fpu_s3,
209static uint32_t g_sve_v4_invalidates[] = {sve_z4, fpu_d4, fpu_s4,
211static uint32_t g_sve_v5_invalidates[] = {sve_z5, fpu_d5, fpu_s5,
213static uint32_t g_sve_v6_invalidates[] = {sve_z6, fpu_d6, fpu_s6,
215static uint32_t g_sve_v7_invalidates[] = {sve_z7, fpu_d7, fpu_s7,
217static uint32_t g_sve_v8_invalidates[] = {sve_z8, fpu_d8, fpu_s8,
219static uint32_t g_sve_v9_invalidates[] = {sve_z9, fpu_d9, fpu_s9,
221static uint32_t g_sve_v10_invalidates[] = {sve_z10, fpu_d10, fpu_s10,
223static uint32_t g_sve_v11_invalidates[] = {sve_z11, fpu_d11, fpu_s11,
225static uint32_t g_sve_v12_invalidates[] = {sve_z12, fpu_d12, fpu_s12,
227static uint32_t g_sve_v13_invalidates[] = {sve_z13, fpu_d13, fpu_s13,
229static uint32_t g_sve_v14_invalidates[] = {sve_z14, fpu_d14, fpu_s14,
231static uint32_t g_sve_v15_invalidates[] = {sve_z15, fpu_d15, fpu_s15,
233static uint32_t g_sve_v16_invalidates[] = {sve_z16, fpu_d16, fpu_s16,
235static uint32_t g_sve_v17_invalidates[] = {sve_z17, fpu_d17, fpu_s17,
237static uint32_t g_sve_v18_invalidates[] = {sve_z18, fpu_d18, fpu_s18,
239static uint32_t g_sve_v19_invalidates[] = {sve_z19, fpu_d19, fpu_s19,
241static uint32_t g_sve_v20_invalidates[] = {sve_z20, fpu_d20, fpu_s20,
243static uint32_t g_sve_v21_invalidates[] = {sve_z21, fpu_d21, fpu_s21,
245static uint32_t g_sve_v22_invalidates[] = {sve_z22, fpu_d22, fpu_s22,
247static uint32_t g_sve_v23_invalidates[] = {sve_z23, fpu_d23, fpu_s23,
249static uint32_t g_sve_v24_invalidates[] = {sve_z24, fpu_d24, fpu_s24,
251static uint32_t g_sve_v25_invalidates[] = {sve_z25, fpu_d25, fpu_s25,
253static uint32_t g_sve_v26_invalidates[] = {sve_z26, fpu_d26, fpu_s26,
255static uint32_t g_sve_v27_invalidates[] = {sve_z27, fpu_d27, fpu_s27,
257static uint32_t g_sve_v28_invalidates[] = {sve_z28, fpu_d28, fpu_s28,
259static uint32_t g_sve_v29_invalidates[] = {sve_z29, fpu_d29, fpu_s29,
261static uint32_t g_sve_v30_invalidates[] = {sve_z30, fpu_d30, fpu_s30,
263static uint32_t g_sve_v31_invalidates[] = {sve_z31, fpu_d31, fpu_s31,
265
266static uint32_t g_contained_z0[] = {sve_z0, LLDB_INVALID_REGNUM};
267static uint32_t g_contained_z1[] = {sve_z1, LLDB_INVALID_REGNUM};
268static uint32_t g_contained_z2[] = {sve_z2, LLDB_INVALID_REGNUM};
269static uint32_t g_contained_z3[] = {sve_z3, LLDB_INVALID_REGNUM};
270static uint32_t g_contained_z4[] = {sve_z4, LLDB_INVALID_REGNUM};
271static uint32_t g_contained_z5[] = {sve_z5, LLDB_INVALID_REGNUM};
272static uint32_t g_contained_z6[] = {sve_z6, LLDB_INVALID_REGNUM};
273static uint32_t g_contained_z7[] = {sve_z7, LLDB_INVALID_REGNUM};
274static uint32_t g_contained_z8[] = {sve_z8, LLDB_INVALID_REGNUM};
275static uint32_t g_contained_z9[] = {sve_z9, LLDB_INVALID_REGNUM};
276static uint32_t g_contained_z10[] = {sve_z10, LLDB_INVALID_REGNUM};
277static uint32_t g_contained_z11[] = {sve_z11, LLDB_INVALID_REGNUM};
278static uint32_t g_contained_z12[] = {sve_z12, LLDB_INVALID_REGNUM};
279static uint32_t g_contained_z13[] = {sve_z13, LLDB_INVALID_REGNUM};
280static uint32_t g_contained_z14[] = {sve_z14, LLDB_INVALID_REGNUM};
281static uint32_t g_contained_z15[] = {sve_z15, LLDB_INVALID_REGNUM};
282static uint32_t g_contained_z16[] = {sve_z16, LLDB_INVALID_REGNUM};
283static uint32_t g_contained_z17[] = {sve_z17, LLDB_INVALID_REGNUM};
284static uint32_t g_contained_z18[] = {sve_z18, LLDB_INVALID_REGNUM};
285static uint32_t g_contained_z19[] = {sve_z19, LLDB_INVALID_REGNUM};
286static uint32_t g_contained_z20[] = {sve_z20, LLDB_INVALID_REGNUM};
287static uint32_t g_contained_z21[] = {sve_z21, LLDB_INVALID_REGNUM};
288static uint32_t g_contained_z22[] = {sve_z22, LLDB_INVALID_REGNUM};
289static uint32_t g_contained_z23[] = {sve_z23, LLDB_INVALID_REGNUM};
290static uint32_t g_contained_z24[] = {sve_z24, LLDB_INVALID_REGNUM};
291static uint32_t g_contained_z25[] = {sve_z25, LLDB_INVALID_REGNUM};
292static uint32_t g_contained_z26[] = {sve_z26, LLDB_INVALID_REGNUM};
293static uint32_t g_contained_z27[] = {sve_z27, LLDB_INVALID_REGNUM};
294static uint32_t g_contained_z28[] = {sve_z28, LLDB_INVALID_REGNUM};
295static uint32_t g_contained_z29[] = {sve_z29, LLDB_INVALID_REGNUM};
296static uint32_t g_contained_z30[] = {sve_z30, LLDB_INVALID_REGNUM};
297static uint32_t g_contained_z31[] = {sve_z31, LLDB_INVALID_REGNUM};
298
299#define VG_OFFSET_NAME(reg) SVE_OFFSET_VG
300
301#define SVE_REG_KIND(reg) MISC_KIND(reg, sve, LLDB_INVALID_REGNUM)
302#define MISC_VG_KIND(lldb_kind) MISC_KIND(vg, sve, LLDB_INVALID_REGNUM)
303
304// Default offset SVE Z registers and all corresponding pseudo registers
305// ( S, D and V registers) is zero and will be configured during execution.
306
307// clang-format off
308
309// Defines sve pseudo vector (V) register with 16-byte size
310#define DEFINE_VREG_SVE(vreg, zreg) \
311 { \
312 #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
313 VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \
314 }
315
316// Defines S and D pseudo registers mapping over corresponding vector register
317#define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg) \
318 { \
319 #reg, nullptr, size, 0, lldb::eEncodingIEEE754, lldb::eFormatFloat, \
320 LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates, \
321 }
322
323// Defines a Z vector register with 16-byte default size
324#define DEFINE_ZREG(reg) \
325 { \
326 #reg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
327 SVE_REG_KIND(reg), nullptr, nullptr, \
328 }
329
330// Defines a P vector register with 2-byte default size
331#define DEFINE_PREG(reg) \
332 { \
333 #reg, nullptr, 2, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
334 SVE_REG_KIND(reg), nullptr, nullptr, \
335 }
336
337static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
338 // DEFINE_GPR64(name, GENERIC KIND)
339 DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
340 DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2),
341 DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3),
342 DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4),
343 DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5),
344 DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6),
345 DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7),
346 DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8),
347 DEFINE_GPR64(x8, LLDB_INVALID_REGNUM),
348 DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
349 DEFINE_GPR64(x10, LLDB_INVALID_REGNUM),
350 DEFINE_GPR64(x11, LLDB_INVALID_REGNUM),
351 DEFINE_GPR64(x12, LLDB_INVALID_REGNUM),
352 DEFINE_GPR64(x13, LLDB_INVALID_REGNUM),
353 DEFINE_GPR64(x14, LLDB_INVALID_REGNUM),
354 DEFINE_GPR64(x15, LLDB_INVALID_REGNUM),
355 DEFINE_GPR64(x16, LLDB_INVALID_REGNUM),
356 DEFINE_GPR64(x17, LLDB_INVALID_REGNUM),
357 DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
358 DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
359 DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
360 DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
361 DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
362 DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
363 DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
364 DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
365 DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
366 DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
367 DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
368 // DEFINE_GPR64(name, GENERIC KIND)
369 DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP),
370 DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA),
371 DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
372 DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
373
374 // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
375 DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
376
377 // DEFINE_GPR32(name, parent name)
378 DEFINE_GPR32(w0, x0),
379 DEFINE_GPR32(w1, x1),
380 DEFINE_GPR32(w2, x2),
381 DEFINE_GPR32(w3, x3),
382 DEFINE_GPR32(w4, x4),
383 DEFINE_GPR32(w5, x5),
384 DEFINE_GPR32(w6, x6),
385 DEFINE_GPR32(w7, x7),
386 DEFINE_GPR32(w8, x8),
387 DEFINE_GPR32(w9, x9),
388 DEFINE_GPR32(w10, x10),
389 DEFINE_GPR32(w11, x11),
390 DEFINE_GPR32(w12, x12),
391 DEFINE_GPR32(w13, x13),
392 DEFINE_GPR32(w14, x14),
393 DEFINE_GPR32(w15, x15),
394 DEFINE_GPR32(w16, x16),
395 DEFINE_GPR32(w17, x17),
396 DEFINE_GPR32(w18, x18),
397 DEFINE_GPR32(w19, x19),
398 DEFINE_GPR32(w20, x20),
399 DEFINE_GPR32(w21, x21),
400 DEFINE_GPR32(w22, x22),
401 DEFINE_GPR32(w23, x23),
402 DEFINE_GPR32(w24, x24),
403 DEFINE_GPR32(w25, x25),
404 DEFINE_GPR32(w26, x26),
405 DEFINE_GPR32(w27, x27),
406 DEFINE_GPR32(w28, x28),
407
408 // DEFINE_VREG_SVE(v register, z register)
409 DEFINE_VREG_SVE(v0, z0),
410 DEFINE_VREG_SVE(v1, z1),
411 DEFINE_VREG_SVE(v2, z2),
412 DEFINE_VREG_SVE(v3, z3),
413 DEFINE_VREG_SVE(v4, z4),
414 DEFINE_VREG_SVE(v5, z5),
415 DEFINE_VREG_SVE(v6, z6),
416 DEFINE_VREG_SVE(v7, z7),
417 DEFINE_VREG_SVE(v8, z8),
418 DEFINE_VREG_SVE(v9, z9),
419 DEFINE_VREG_SVE(v10, z10),
420 DEFINE_VREG_SVE(v11, z11),
421 DEFINE_VREG_SVE(v12, z12),
422 DEFINE_VREG_SVE(v13, z13),
423 DEFINE_VREG_SVE(v14, z14),
424 DEFINE_VREG_SVE(v15, z15),
425 DEFINE_VREG_SVE(v16, z16),
426 DEFINE_VREG_SVE(v17, z17),
427 DEFINE_VREG_SVE(v18, z18),
428 DEFINE_VREG_SVE(v19, z19),
429 DEFINE_VREG_SVE(v20, z20),
430 DEFINE_VREG_SVE(v21, z21),
431 DEFINE_VREG_SVE(v22, z22),
432 DEFINE_VREG_SVE(v23, z23),
433 DEFINE_VREG_SVE(v24, z24),
434 DEFINE_VREG_SVE(v25, z25),
435 DEFINE_VREG_SVE(v26, z26),
436 DEFINE_VREG_SVE(v27, z27),
437 DEFINE_VREG_SVE(v28, z28),
438 DEFINE_VREG_SVE(v29, z29),
439 DEFINE_VREG_SVE(v30, z30),
440 DEFINE_VREG_SVE(v31, z31),
441
442 // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register)
443 DEFINE_FPU_PSEUDO_SVE(s0, 4, z0),
444 DEFINE_FPU_PSEUDO_SVE(s1, 4, z1),
445 DEFINE_FPU_PSEUDO_SVE(s2, 4, z2),
446 DEFINE_FPU_PSEUDO_SVE(s3, 4, z3),
447 DEFINE_FPU_PSEUDO_SVE(s4, 4, z4),
448 DEFINE_FPU_PSEUDO_SVE(s5, 4, z5),
449 DEFINE_FPU_PSEUDO_SVE(s6, 4, z6),
450 DEFINE_FPU_PSEUDO_SVE(s7, 4, z7),
451 DEFINE_FPU_PSEUDO_SVE(s8, 4, z8),
452 DEFINE_FPU_PSEUDO_SVE(s9, 4, z9),
453 DEFINE_FPU_PSEUDO_SVE(s10, 4, z10),
454 DEFINE_FPU_PSEUDO_SVE(s11, 4, z11),
455 DEFINE_FPU_PSEUDO_SVE(s12, 4, z12),
456 DEFINE_FPU_PSEUDO_SVE(s13, 4, z13),
457 DEFINE_FPU_PSEUDO_SVE(s14, 4, z14),
458 DEFINE_FPU_PSEUDO_SVE(s15, 4, z15),
459 DEFINE_FPU_PSEUDO_SVE(s16, 4, z16),
460 DEFINE_FPU_PSEUDO_SVE(s17, 4, z17),
461 DEFINE_FPU_PSEUDO_SVE(s18, 4, z18),
462 DEFINE_FPU_PSEUDO_SVE(s19, 4, z19),
463 DEFINE_FPU_PSEUDO_SVE(s20, 4, z20),
464 DEFINE_FPU_PSEUDO_SVE(s21, 4, z21),
465 DEFINE_FPU_PSEUDO_SVE(s22, 4, z22),
466 DEFINE_FPU_PSEUDO_SVE(s23, 4, z23),
467 DEFINE_FPU_PSEUDO_SVE(s24, 4, z24),
468 DEFINE_FPU_PSEUDO_SVE(s25, 4, z25),
469 DEFINE_FPU_PSEUDO_SVE(s26, 4, z26),
470 DEFINE_FPU_PSEUDO_SVE(s27, 4, z27),
471 DEFINE_FPU_PSEUDO_SVE(s28, 4, z28),
472 DEFINE_FPU_PSEUDO_SVE(s29, 4, z29),
473 DEFINE_FPU_PSEUDO_SVE(s30, 4, z30),
474 DEFINE_FPU_PSEUDO_SVE(s31, 4, z31),
475
476 DEFINE_FPU_PSEUDO_SVE(d0, 8, z0),
477 DEFINE_FPU_PSEUDO_SVE(d1, 8, z1),
478 DEFINE_FPU_PSEUDO_SVE(d2, 8, z2),
479 DEFINE_FPU_PSEUDO_SVE(d3, 8, z3),
480 DEFINE_FPU_PSEUDO_SVE(d4, 8, z4),
481 DEFINE_FPU_PSEUDO_SVE(d5, 8, z5),
482 DEFINE_FPU_PSEUDO_SVE(d6, 8, z6),
483 DEFINE_FPU_PSEUDO_SVE(d7, 8, z7),
484 DEFINE_FPU_PSEUDO_SVE(d8, 8, z8),
485 DEFINE_FPU_PSEUDO_SVE(d9, 8, z9),
486 DEFINE_FPU_PSEUDO_SVE(d10, 8, z10),
487 DEFINE_FPU_PSEUDO_SVE(d11, 8, z11),
488 DEFINE_FPU_PSEUDO_SVE(d12, 8, z12),
489 DEFINE_FPU_PSEUDO_SVE(d13, 8, z13),
490 DEFINE_FPU_PSEUDO_SVE(d14, 8, z14),
491 DEFINE_FPU_PSEUDO_SVE(d15, 8, z15),
492 DEFINE_FPU_PSEUDO_SVE(d16, 8, z16),
493 DEFINE_FPU_PSEUDO_SVE(d17, 8, z17),
494 DEFINE_FPU_PSEUDO_SVE(d18, 8, z18),
495 DEFINE_FPU_PSEUDO_SVE(d19, 8, z19),
496 DEFINE_FPU_PSEUDO_SVE(d20, 8, z20),
497 DEFINE_FPU_PSEUDO_SVE(d21, 8, z21),
498 DEFINE_FPU_PSEUDO_SVE(d22, 8, z22),
499 DEFINE_FPU_PSEUDO_SVE(d23, 8, z23),
500 DEFINE_FPU_PSEUDO_SVE(d24, 8, z24),
501 DEFINE_FPU_PSEUDO_SVE(d25, 8, z25),
502 DEFINE_FPU_PSEUDO_SVE(d26, 8, z26),
503 DEFINE_FPU_PSEUDO_SVE(d27, 8, z27),
504 DEFINE_FPU_PSEUDO_SVE(d28, 8, z28),
505 DEFINE_FPU_PSEUDO_SVE(d29, 8, z29),
506 DEFINE_FPU_PSEUDO_SVE(d30, 8, z30),
507 DEFINE_FPU_PSEUDO_SVE(d31, 8, z31),
508
509 // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
510 DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
511 DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
512
513 DEFINE_MISC_REGS(vg, 8, VG, sve_vg),
514 // DEFINE_ZREG(name)
515 DEFINE_ZREG(z0),
516 DEFINE_ZREG(z1),
517 DEFINE_ZREG(z2),
518 DEFINE_ZREG(z3),
519 DEFINE_ZREG(z4),
520 DEFINE_ZREG(z5),
521 DEFINE_ZREG(z6),
522 DEFINE_ZREG(z7),
523 DEFINE_ZREG(z8),
524 DEFINE_ZREG(z9),
525 DEFINE_ZREG(z10),
526 DEFINE_ZREG(z11),
527 DEFINE_ZREG(z12),
528 DEFINE_ZREG(z13),
529 DEFINE_ZREG(z14),
530 DEFINE_ZREG(z15),
531 DEFINE_ZREG(z16),
532 DEFINE_ZREG(z17),
533 DEFINE_ZREG(z18),
534 DEFINE_ZREG(z19),
535 DEFINE_ZREG(z20),
536 DEFINE_ZREG(z21),
537 DEFINE_ZREG(z22),
538 DEFINE_ZREG(z23),
539 DEFINE_ZREG(z24),
540 DEFINE_ZREG(z25),
541 DEFINE_ZREG(z26),
542 DEFINE_ZREG(z27),
543 DEFINE_ZREG(z28),
544 DEFINE_ZREG(z29),
545 DEFINE_ZREG(z30),
546 DEFINE_ZREG(z31),
547
548 // DEFINE_PREG(name)
549 DEFINE_PREG(p0),
550 DEFINE_PREG(p1),
551 DEFINE_PREG(p2),
552 DEFINE_PREG(p3),
553 DEFINE_PREG(p4),
554 DEFINE_PREG(p5),
555 DEFINE_PREG(p6),
556 DEFINE_PREG(p7),
557 DEFINE_PREG(p8),
558 DEFINE_PREG(p9),
559 DEFINE_PREG(p10),
560 DEFINE_PREG(p11),
561 DEFINE_PREG(p12),
562 DEFINE_PREG(p13),
563 DEFINE_PREG(p14),
564 DEFINE_PREG(p15),
565
566 // DEFINE FFR
567 DEFINE_PREG(ffr)
568 // clang-format on
569};
570
571#endif // DECLARE_REGISTER_INFOS_ARM64_SVE_STRUCT
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:54
#define LLDB_REGNUM_GENERIC_ARG8
Definition: lldb-defines.h:70
#define LLDB_REGNUM_GENERIC_ARG6
Definition: lldb-defines.h:66
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:52
#define LLDB_REGNUM_GENERIC_ARG4
Definition: lldb-defines.h:62
#define LLDB_REGNUM_GENERIC_ARG3
Definition: lldb-defines.h:60
#define LLDB_REGNUM_GENERIC_ARG1
Definition: lldb-defines.h:56
#define LLDB_REGNUM_GENERIC_ARG7
Definition: lldb-defines.h:68
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:79
#define LLDB_REGNUM_GENERIC_ARG2
Definition: lldb-defines.h:58
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:51
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:53
#define LLDB_REGNUM_GENERIC_ARG5
Definition: lldb-defines.h:64