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RegisterContext_mips.h
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1 //===-- RegisterContext_mips.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef liblldb_RegisterContext_mips64_H_
10 #define liblldb_RegisterContext_mips64_H_
11 
12 #include <cstddef>
13 #include <cstdint>
14 
15 // eh_frame and DWARF Register numbers (eRegisterKindEHFrame &
16 // eRegisterKindDWARF)
17 
18 enum {
19  // GP Registers
129 };
130 
131 enum {
241 };
242 
243 // GP registers
245  uint64_t zero;
246  uint64_t r1;
247  uint64_t r2;
248  uint64_t r3;
249  uint64_t r4;
250  uint64_t r5;
251  uint64_t r6;
252  uint64_t r7;
253  uint64_t r8;
254  uint64_t r9;
255  uint64_t r10;
256  uint64_t r11;
257  uint64_t r12;
258  uint64_t r13;
259  uint64_t r14;
260  uint64_t r15;
261  uint64_t r16;
262  uint64_t r17;
263  uint64_t r18;
264  uint64_t r19;
265  uint64_t r20;
266  uint64_t r21;
267  uint64_t r22;
268  uint64_t r23;
269  uint64_t r24;
270  uint64_t r25;
271  uint64_t r26;
272  uint64_t r27;
273  uint64_t gp;
274  uint64_t sp;
275  uint64_t r30;
276  uint64_t ra;
277  uint64_t mullo;
278  uint64_t mulhi;
279  uint64_t pc;
280  uint64_t badvaddr;
281  uint64_t sr;
282  uint64_t cause;
283  uint64_t config5;
284 };
285 
287  uint64_t f0;
288  uint64_t f1;
289  uint64_t f2;
290  uint64_t f3;
291  uint64_t f4;
292  uint64_t f5;
293  uint64_t f6;
294  uint64_t f7;
295  uint64_t f8;
296  uint64_t f9;
297  uint64_t f10;
298  uint64_t f11;
299  uint64_t f12;
300  uint64_t f13;
301  uint64_t f14;
302  uint64_t f15;
303  uint64_t f16;
304  uint64_t f17;
305  uint64_t f18;
306  uint64_t f19;
307  uint64_t f20;
308  uint64_t f21;
309  uint64_t f22;
310  uint64_t f23;
311  uint64_t f24;
312  uint64_t f25;
313  uint64_t f26;
314  uint64_t f27;
315  uint64_t f28;
316  uint64_t f29;
317  uint64_t f30;
318  uint64_t f31;
322 };
323 
324 struct MSAReg {
325  uint8_t byte[16];
326 };
327 
361  uint32_t fcsr; /* FPU control status register */
362  uint32_t fir; /* FPU implementaion revision */
363  uint32_t mcsr; /* MSA control status register */
364  uint32_t mir; /* MSA implementation revision */
365  uint32_t config5; /* Config5 register */
366 };
367 
368 struct UserArea {
369  GPR_linux_mips gpr; // General purpose registers.
370  FPR_linux_mips fpr; // Floating point registers.
371  MSA_linux_mips msa; // MSA registers.
372 };
373 
374 #endif // liblldb_RegisterContext_mips64_H_
MSA_linux_mips msa
GPR_linux_mips gpr
FPR_linux_mips fpr