9#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_RISCV_REGISTER_ENUMS_H
10#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_RISCV_REGISTER_ENUMS_H
@ csr_mhpmcounter6h_riscv
@ csr_mhpmcounter16h_riscv
@ csr_mhpmcounter29h_riscv
@ csr_qc_mclicilvl24_riscv
@ csr_qc_mclicilvl31_riscv
@ csr_hpmcounter16h_riscv
@ csr_qc_mclicilvl25_riscv
@ csr_mhpmcounter17_riscv
@ csr_mhpmcounter4h_riscv
@ csr_mhpmcounter22h_riscv
@ csr_mhpmcounter14_riscv
@ csr_hpmcounter27h_riscv
@ csr_qc_mclicilvl22_riscv
@ csr_hpmcounter15h_riscv
@ csr_mhpmcounter7h_riscv
@ csr_mhpmcounter5h_riscv
@ csr_qc_mclicilvl17_riscv
@ csr_hpmcounter20h_riscv
@ csr_mhpmcounter24_riscv
@ csr_scountinhibit_riscv
@ csr_qc_mwpstartaddr3_riscv
@ csr_mhpmcounter18_riscv
@ csr_qc_mclicilvl13_riscv
@ csr_hpmcounter25h_riscv
@ csr_hpmcounter30h_riscv
@ csr_mhpmcounter25h_riscv
@ csr_mhpmcounter10_riscv
@ csr_qc_mclicilvl7_riscv
@ csr_qc_mclicilvl8_riscv
@ csr_mhpmcounter19_riscv
@ csr_hpmcounter29h_riscv
@ csr_qc_mclicilvl26_riscv
@ csr_qc_mclicilvl16_riscv
@ csr_qc_mwpstartaddr0_riscv
@ csr_mhpmcounter25_riscv
@ csr_qc_mwpstartaddr1_riscv
@ csr_qc_mclicilvl1_riscv
@ csr_hpmcounter17h_riscv
@ csr_hpmcounter13h_riscv
@ csr_hpmcounter22h_riscv
@ csr_qc_mclicilvl10_riscv
@ csr_hpmcounter19h_riscv
@ csr_qc_mwpendaddr2_riscv
@ csr_qc_mclicilvl14_riscv
@ csr_mhpmcounter23h_riscv
@ csr_mhpmcounter13h_riscv
@ csr_mhpmcounter26h_riscv
@ csr_qc_mclicilvl29_riscv
@ csr_mhpmcounter26_riscv
@ csr_hpmcounter12h_riscv
@ csr_qc_mclicilvl19_riscv
@ csr_qc_mclicilvl4_riscv
@ csr_mcountinhibit_riscv
@ csr_qc_mclicilvl27_riscv
@ csr_mhpmcounter11_riscv
@ csr_mhpmcounter30_riscv
@ csr_qc_mclicilvl3_riscv
@ csr_mhpmcounter21_riscv
@ csr_qc_mstkbottomaddr_riscv
@ csr_mhpmcounter11h_riscv
@ csr_qc_mclicilvl30_riscv
@ csr_qc_mwpstartaddr2_riscv
@ csr_qc_mwpendaddr0_riscv
@ csr_hpmcounter21h_riscv
@ csr_hpmcounter11h_riscv
@ csr_mhpmcounter29_riscv
@ csr_mhpmcounter3h_riscv
@ csr_mhpmcounter31_riscv
@ csr_qc_mclicilvl21_riscv
@ csr_hpmcounter10h_riscv
@ csr_mhpmcounter12_riscv
@ csr_qc_mwpendaddr3_riscv
@ csr_mhpmcounter19h_riscv
@ csr_mhpmcounter12h_riscv
@ csr_mhpmcounter27_riscv
@ csr_mhpmcounter28h_riscv
@ csr_mhpmcounter28_riscv
@ csr_hpmcounter14h_riscv
@ csr_mhpmcounter22_riscv
@ csr_mhpmcounter9h_riscv
@ csr_mhpmcounter23_riscv
@ csr_qc_mclicilvl6_riscv
@ csr_hpmcounter28h_riscv
@ csr_hpmcounter31h_riscv
@ csr_mhpmcounter15h_riscv
@ csr_mhpmcounter24h_riscv
@ csr_qc_mthreadptr_riscv
@ csr_mhpmcounter20_riscv
@ csr_mhpmcounter10h_riscv
@ csr_mhpmcounter27h_riscv
@ csr_mhpmcounter14h_riscv
@ csr_mhpmcounter30h_riscv
@ csr_qc_mclicilvl23_riscv
@ csr_mhpmcounter15_riscv
@ csr_qc_mclicilvl18_riscv
@ csr_hpmcounter23h_riscv
@ csr_qc_mclicilvl20_riscv
@ csr_mhpmcounter17h_riscv
@ csr_qc_mclicilvl0_riscv
@ csr_mhpmcounter13_riscv
@ csr_qc_mstktopaddr_riscv
@ csr_qc_mclicilvl11_riscv
@ csr_qc_mwpendaddr1_riscv
@ csr_mhpmcounter18h_riscv
@ csr_mhpmcounter16_riscv
@ csr_hpmcounter26h_riscv
@ csr_qc_mclicilvl28_riscv
@ csr_qc_mclicilvl2_riscv
@ csr_hpmcounter24h_riscv
@ csr_mhpmcounter8h_riscv
@ csr_mhpmcounter20h_riscv
@ csr_qc_mclicilvl5_riscv
@ csr_qc_mclicilvl12_riscv
@ csr_mhpmcounter31h_riscv
@ csr_qc_mclicilvl15_riscv
@ csr_mhpmcounter21h_riscv
@ csr_hpmcounter18h_riscv
@ csr_qc_mclicilvl9_riscv