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ARM64_DWARF_Registers.h
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1 //===-- ARM64_DWARF_Registers.h ---------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLDB_SOURCE_UTILITY_ARM64_DWARF_REGISTERS_H
10 #define LLDB_SOURCE_UTILITY_ARM64_DWARF_REGISTERS_H
11 
12 #include "lldb/lldb-private.h"
13 
14 namespace arm64_dwarf {
15 
16 enum {
17  x0 = 0,
18  x1,
19  x2,
20  x3,
21  x4,
22  x5,
23  x6,
24  x7,
25  x8,
26  x9,
27  x10,
28  x11,
29  x12,
30  x13,
31  x14,
32  x15,
33  x16,
34  x17,
35  x18,
36  x19,
37  x20,
38  x21,
39  x22,
40  x23,
41  x24,
42  x25,
43  x26,
44  x27,
45  x28,
46  x29 = 29,
47  fp = x29,
48  x30 = 30,
49  lr = x30,
50  x31 = 31,
51  sp = x31,
52  pc = 32,
53  cpsr = 33,
54  // 34-45 reserved
55 
56  // 64-bit SVE Vector granule pseudo register
57  vg = 46,
58 
59  // VG ́8-bit SVE first fault register
60  ffr = 47,
61 
62  // VG x ́8-bit SVE predicate registers
63  p0 = 48,
64  p1,
65  p2,
66  p3,
67  p4,
68  p5,
69  p6,
70  p7,
71  p8,
72  p9,
73  p10,
74  p11,
75  p12,
76  p13,
77  p14,
78  p15,
79 
80  // V0-V31 (128 bit vector registers)
81  v0 = 64,
82  v1,
83  v2,
84  v3,
85  v4,
86  v5,
87  v6,
88  v7,
89  v8,
90  v9,
91  v10,
92  v11,
93  v12,
94  v13,
95  v14,
96  v15,
97  v16,
98  v17,
99  v18,
113 
114  // VG ́64-bit SVE vector registers
115  z0 = 96,
116  z1,
117  z2,
118  z3,
119  z4,
120  z5,
121  z6,
122  z7,
123  z8,
124  z9,
147 };
148 
149 } // namespace arm64_dwarf
150 
151 #endif // LLDB_SOURCE_UTILITY_ARM64_DWARF_REGISTERS_H