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RISCV_DWARF_Registers.h
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1//===-- RISCV_DWARF_Registers.h ---------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLDB_SOURCE_UTILITY_RISCV_DWARF_REGISTERS_H
10#define LLDB_SOURCE_UTILITY_RISCV_DWARF_REGISTERS_H
11
12#include "lldb/lldb-private.h"
13
14namespace riscv_dwarf {
15
16enum {
49
82
83 // alternate frame return column
85
118
1143
2168
4217
4219 // The single-precision floating-point extension adds a floating-point CSR
4220 // (fcsr) to a base scalar RISC-V ISA.
4222 // The vector extension adds seven unprivileged CSRs (vstart, vxsat, vxrm,
4223 // vcsr, vtype, vl, vlenb) to a base scalar RISC-V ISA.
4232
4233 // register ABI name
4266
4299
4674
4675 // mock pc regnum
4677};
4678
4679} // namespace riscv_dwarf
4680
4681#endif // LLDB_SOURCE_UTILITY_RISCV_DWARF_REGISTERS_H