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RegisterContext_x86.h
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1//===-- RegisterContext_x86.h -----------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_X86_H
10#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_X86_H
11
12#include <cstddef>
13#include <cstdint>
14
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/BitmaskEnum.h"
17#include "llvm/Support/Compiler.h"
18
19namespace lldb_private {
20// i386 ehframe, dwarf regnums
21
22// Register numbers seen in eh_frame (eRegisterKindEHFrame) on i386 systems
23// (non-Darwin)
24//
25enum {
30
31 // on Darwin esp & ebp are reversed in the eh_frame section for i386 (versus
32 // dwarf's reg numbering).
33 // To be specific:
34 // i386+darwin eh_frame: 4 is ebp, 5 is esp
35 // i386+everyone else eh_frame: 4 is esp, 5 is ebp
36 // i386 dwarf: 4 is esp, 5 is ebp
37 // lldb will get the darwin-specific eh_frame reg numberings from debugserver,
38 // or the ABI, so we
39 // only encode the generally correct 4 == esp, 5 == ebp numbers in this
40 // generic header.
41
72};
73
74// DWARF register numbers (eRegisterKindDWARF)
75// Intel's x86 or IA-32
76enum {
77 // General Purpose Registers.
88 // Floating Point Registers
97 // SSE Registers
106 // MMX Registers
115 dwarf_fctrl_i386 = 37, // x87 control word
116 dwarf_fstat_i386 = 38, // x87 status word
124
125 // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and
126 // then differentiate based on size of the register.
131};
132
133// AMD x86_64, AMD64, Intel EM64T, or Intel 64 ehframe, dwarf regnums
134
135// EHFrame and DWARF Register numbers (eRegisterKindEHFrame &
136// eRegisterKindDWARF)
137// This is the spec I used (as opposed to x86-64-abi-0.99.pdf):
138// http://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf
139enum {
140 // GP Registers
149 // Extended GP Registers
158 // Return Address (RA) mapped to RIP
160 // SSE Vector Registers
177 // Floating Point Registers
186 // MMX Registers
195 // Control and Status Flags Register
197 // selector registers
204 // Base registers
207 // Floating point control registers
208 dwarf_mxcsr_x86_64 = 64, // Media Control and Status
209 dwarf_fctrl_x86_64, // x87 control word
210 dwarf_fstat_x86_64, // x87 status word
211 // Upper Vector Registers
228 // MPX registers
233 // AVX2 Vector Mask Registers
234 // dwarf_k0_x86_64 = 118,
235 // dwarf_k1_x86_64,
236 // dwarf_k2_x86_64,
237 // dwarf_k3_x86_64,
238 // dwarf_k4_x86_64,
239 // dwarf_k5_x86_64,
240 // dwarf_k6_x86_64,
241 // dwarf_k7_x86_64,
242};
243
244// Generic floating-point registers
245
246LLVM_PACKED_START
248 uint64_t mantissa;
249 uint16_t sign_exp;
250};
251
252struct MMSReg {
253 union {
254 uint8_t bytes[10];
256 };
257 uint8_t pad[6];
258};
260
261static_assert(sizeof(MMSRegComp) == 10, "MMSRegComp is not 10 bytes of size");
262static_assert(sizeof(MMSReg) == 16, "MMSReg is not 16 bytes of size");
263
264struct XMMReg {
265 uint8_t bytes[16]; // 128-bits for each XMM register
266};
267
268// i387_fxsave_struct
269struct FXSAVE {
270 uint16_t fctrl; // FPU Control Word (fcw)
271 uint16_t fstat; // FPU Status Word (fsw)
272 uint16_t ftag; // FPU Tag Word (ftw)
273 uint16_t fop; // Last Instruction Opcode (fop)
274 union {
275 struct {
276 uint64_t fip; // Instruction Pointer
277 uint64_t fdp; // Data Pointer
279 struct {
280 uint32_t fioff; // FPU IP Offset (fip)
281 uint32_t fiseg; // FPU IP Selector (fcs)
282 uint32_t fooff; // FPU Operand Pointer Offset (foo)
283 uint32_t foseg; // FPU Operand Pointer Selector (fos)
284 } i386_; // Added _ in the end to avoid error with gcc defining i386 in some
285 // cases
287 uint32_t mxcsr; // MXCSR Register State
288 uint32_t mxcsrmask; // MXCSR Mask
289 MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes
290 XMMReg xmm[16]; // 16*16 bytes for each XMM-reg = 256 bytes
291 uint8_t padding1[48];
292 uint64_t xcr0;
293 uint8_t padding2[40];
294};
295
296// Extended floating-point registers
297
298struct YMMHReg {
299 uint8_t bytes[16]; // 16 * 8 bits for the high bytes of each YMM register
300};
301
302struct YMMReg {
303 uint8_t bytes[32]; // 16 * 16 bits for each YMM register
304};
305
306struct YMM {
307 YMMReg ymm[16]; // assembled from ymmh and xmm registers
308};
309
310struct MPXReg {
311 uint8_t bytes[16]; // MPX 128 bit bound registers
312};
313
314struct MPXCsr {
315 uint8_t bytes[8]; // MPX 64 bit bndcfgu and bndstatus registers (collectively
316 // BNDCSR state)
317};
318
319struct MPX {
322};
323
324LLVM_PACKED_START
325struct XSAVE_HDR {
326 enum class XFeature : uint64_t {
327 FP = 1,
328 SSE = FP << 1,
329 YMM = SSE << 1,
330 BNDREGS = YMM << 1,
331 BNDCSR = BNDREGS << 1,
332 OPMASK = BNDCSR << 1,
333 ZMM_Hi256 = OPMASK << 1,
334 Hi16_ZMM = ZMM_Hi256 << 1,
335 PT = Hi16_ZMM << 1,
336 PKRU = PT << 1,
337 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue*/ PKRU)
338 };
339
340 XFeature xstate_bv; // OS enabled xstate mask to determine the extended states
341 // supported by the processor
342 XFeature xcomp_bv; // Mask to indicate the format of the XSAVE area and of
343 // the XRSTOR instruction
344 uint64_t reserved1[1];
345 uint64_t reserved2[5];
346};
347static_assert(sizeof(XSAVE_HDR) == 64, "XSAVE_HDR layout incorrect");
349
350// x86 extensions to FXSAVE (i.e. for AVX and MPX processors)
351LLVM_PACKED_START
352struct XSAVE {
353 FXSAVE i387; // floating point registers typical in i387_fxsave_struct
354 XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the
355 // following extensions are usable
356 YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes
357 // are in FXSAVE.xmm for compatibility with SSE)
358 uint64_t reserved3[16];
359 MPXReg mpxr[4]; // MPX BNDREG state, containing 128-bit bound registers
360 MPXCsr mpxc[2]; // MPX BNDCSR state, containing 64-bit BNDCFGU and
361 // BNDSTATUS registers
362};
364
365// Floating-point registers
366union FPR {
367 FXSAVE fxsave; // Generic floating-point registers.
368 XSAVE xsave; // x86 extended processor state.
369};
370
372
373// Convenience function to combine YMM register data from XSAVE-style input.
374inline YMMReg XStateToYMM(const void* xmm_bytes, const void* ymmh_bytes) {
375 YMMReg ret;
376
377 ::memcpy(ret.bytes, xmm_bytes, sizeof(XMMReg));
378 ::memcpy(ret.bytes + sizeof(XMMReg), ymmh_bytes, sizeof(YMMHReg));
379
380 return ret;
381}
382
383// Convenience function to copy YMM register data into XSAVE-style output.
384inline void YMMToXState(const YMMReg& input, void* xmm_bytes, void* ymmh_bytes) {
385 ::memcpy(xmm_bytes, input.bytes, sizeof(XMMReg));
386 ::memcpy(ymmh_bytes, input.bytes + sizeof(XMMReg), sizeof(YMMHReg));
387}
388
389uint16_t AbridgedToFullTagWord(uint8_t abridged_tw, uint16_t sw,
390 llvm::ArrayRef<MMSReg> st_regs);
391uint8_t FullToAbridgedTagWord(uint16_t tw);
392
393} // namespace lldb_private
394
395#endif
A class that represents a running process on the host machine.
Definition: SBAttachInfo.h:14
void YMMToXState(const YMMReg &input, void *xmm_bytes, void *ymmh_bytes)
uint16_t AbridgedToFullTagWord(uint8_t abridged_tw, uint16_t sw, llvm::ArrayRef< MMSReg > st_regs)
YMMReg XStateToYMM(const void *xmm_bytes, const void *ymmh_bytes)
LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE()
uint8_t FullToAbridgedTagWord(uint16_t tw)
union lldb_private::FXSAVE::@111 ptr
struct lldb_private::FXSAVE::@111::@113 i386_
struct lldb_private::FXSAVE::@111::@112 x86_64