LLDB mainline
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#include "llvm/Support/ErrorHandling.h"
#include <cassert>
#include <cstdint>
Go to the source code of this file.
Namespaces | |
namespace | lldb_private |
A class that represents a running process on the host machine. | |
Macros | |
#define | COND_EQ 0x0 |
#define | COND_NE 0x1 |
#define | COND_CS 0x2 |
#define | COND_HS 0x2 |
#define | COND_CC 0x3 |
#define | COND_LO 0x3 |
#define | COND_MI 0x4 |
#define | COND_PL 0x5 |
#define | COND_VS 0x6 |
#define | COND_VC 0x7 |
#define | COND_HI 0x8 |
#define | COND_LS 0x9 |
#define | COND_GE 0xA |
#define | COND_LT 0xB |
#define | COND_GT 0xC |
#define | COND_LE 0xD |
#define | COND_AL 0xE |
#define | COND_UNCOND 0xF |
#define | CPSR_T_POS 5 |
#define | CPSR_F_POS 6 |
#define | CPSR_I_POS 7 |
#define | CPSR_A_POS 8 |
#define | CPSR_E_POS 9 |
#define | CPSR_J_POS 24 |
#define | CPSR_Q_POS 27 |
#define | CPSR_V_POS 28 |
#define | CPSR_C_POS 29 |
#define | CPSR_Z_POS 30 |
#define | CPSR_N_POS 31 |
#define | CPSR_MODE_USR 0x10u |
#define | CPSR_MODE_FIQ 0x11u |
#define | CPSR_MODE_IRQ 0x12u |
#define | CPSR_MODE_SVC 0x13u |
#define | CPSR_MODE_ABT 0x17u |
#define | CPSR_MODE_UND 0x1bu |
#define | CPSR_MODE_SYS 0x1fu |
#define | MASK_CPSR_MODE_MASK (0x0000001fu) |
#define | MASK_CPSR_IT_MASK (0x0600fc00u) |
#define | MASK_CPSR_T (1u << CPSR_T_POS) |
#define | MASK_CPSR_F (1u << CPSR_F_POS) |
#define | MASK_CPSR_I (1u << CPSR_I_POS) |
#define | MASK_CPSR_A (1u << CPSR_A_POS) |
#define | MASK_CPSR_E (1u << CPSR_E_POS) |
#define | MASK_CPSR_GE_MASK (0x000f0000u) |
#define | MASK_CPSR_J (1u << CPSR_J_POS) |
#define | MASK_CPSR_Q (1u << CPSR_Q_POS) |
#define | MASK_CPSR_V (1u << CPSR_V_POS) |
#define | MASK_CPSR_C (1u << CPSR_C_POS) |
#define | MASK_CPSR_Z (1u << CPSR_Z_POS) |
#define | MASK_CPSR_N (1u << CPSR_N_POS) |
Functions | |
static const char * | lldb_private::ARMCondCodeToString (uint32_t CC) |
static bool | lldb_private::ARMConditionPassed (const uint32_t condition, const uint32_t cpsr) |
#define COND_AL 0xE |
Definition at line 67 of file ARMDefines.h.
#define COND_CC 0x3 |
Definition at line 40 of file ARMDefines.h.
#define COND_CS 0x2 |
Definition at line 37 of file ARMDefines.h.
#define COND_EQ 0x0 |
Definition at line 33 of file ARMDefines.h.
#define COND_GE 0xA |
Definition at line 57 of file ARMDefines.h.
#define COND_GT 0xC |
Definition at line 61 of file ARMDefines.h.
#define COND_HI 0x8 |
Definition at line 51 of file ARMDefines.h.
#define COND_HS 0x2 |
Definition at line 39 of file ARMDefines.h.
#define COND_LE 0xD |
Definition at line 64 of file ARMDefines.h.
#define COND_LO 0x3 |
Definition at line 42 of file ARMDefines.h.
#define COND_LS 0x9 |
Definition at line 54 of file ARMDefines.h.
#define COND_LT 0xB |
Definition at line 59 of file ARMDefines.h.
#define COND_MI 0x4 |
Definition at line 43 of file ARMDefines.h.
#define COND_NE 0x1 |
Definition at line 35 of file ARMDefines.h.
#define COND_PL 0x5 |
Definition at line 45 of file ARMDefines.h.
#define COND_UNCOND 0xF |
Definition at line 69 of file ARMDefines.h.
#define COND_VC 0x7 |
Definition at line 49 of file ARMDefines.h.
#define COND_VS 0x6 |
Definition at line 47 of file ARMDefines.h.
#define CPSR_A_POS 8 |
Definition at line 155 of file ARMDefines.h.
#define CPSR_C_POS 29 |
Definition at line 160 of file ARMDefines.h.
#define CPSR_E_POS 9 |
Definition at line 156 of file ARMDefines.h.
#define CPSR_F_POS 6 |
Definition at line 153 of file ARMDefines.h.
#define CPSR_I_POS 7 |
Definition at line 154 of file ARMDefines.h.
#define CPSR_J_POS 24 |
Definition at line 157 of file ARMDefines.h.
#define CPSR_MODE_ABT 0x17u |
Definition at line 169 of file ARMDefines.h.
#define CPSR_MODE_FIQ 0x11u |
Definition at line 166 of file ARMDefines.h.
#define CPSR_MODE_IRQ 0x12u |
Definition at line 167 of file ARMDefines.h.
#define CPSR_MODE_SVC 0x13u |
Definition at line 168 of file ARMDefines.h.
#define CPSR_MODE_SYS 0x1fu |
Definition at line 171 of file ARMDefines.h.
#define CPSR_MODE_UND 0x1bu |
Definition at line 170 of file ARMDefines.h.
#define CPSR_MODE_USR 0x10u |
Definition at line 165 of file ARMDefines.h.
#define CPSR_N_POS 31 |
Definition at line 162 of file ARMDefines.h.
#define CPSR_Q_POS 27 |
Definition at line 158 of file ARMDefines.h.
#define CPSR_T_POS 5 |
Definition at line 152 of file ARMDefines.h.
#define CPSR_V_POS 28 |
Definition at line 159 of file ARMDefines.h.
#define CPSR_Z_POS 30 |
Definition at line 161 of file ARMDefines.h.
#define MASK_CPSR_A (1u << CPSR_A_POS) |
Definition at line 179 of file ARMDefines.h.
#define MASK_CPSR_C (1u << CPSR_C_POS) |
Definition at line 185 of file ARMDefines.h.
#define MASK_CPSR_E (1u << CPSR_E_POS) |
Definition at line 180 of file ARMDefines.h.
#define MASK_CPSR_F (1u << CPSR_F_POS) |
Definition at line 177 of file ARMDefines.h.
#define MASK_CPSR_GE_MASK (0x000f0000u) |
Definition at line 181 of file ARMDefines.h.
#define MASK_CPSR_I (1u << CPSR_I_POS) |
Definition at line 178 of file ARMDefines.h.
#define MASK_CPSR_IT_MASK (0x0600fc00u) |
Definition at line 175 of file ARMDefines.h.
#define MASK_CPSR_J (1u << CPSR_J_POS) |
Definition at line 182 of file ARMDefines.h.
#define MASK_CPSR_MODE_MASK (0x0000001fu) |
Definition at line 174 of file ARMDefines.h.
#define MASK_CPSR_N (1u << CPSR_N_POS) |
Definition at line 187 of file ARMDefines.h.
#define MASK_CPSR_Q (1u << CPSR_Q_POS) |
Definition at line 183 of file ARMDefines.h.
#define MASK_CPSR_T (1u << CPSR_T_POS) |
Definition at line 176 of file ARMDefines.h.
#define MASK_CPSR_V (1u << CPSR_V_POS) |
Definition at line 184 of file ARMDefines.h.
#define MASK_CPSR_Z (1u << CPSR_Z_POS) |
Definition at line 186 of file ARMDefines.h.