LLDB  mainline
ABISysV_arm.cpp
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1 //===-- ABISysV_arm.cpp ---------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ABISysV_arm.h"
10 
11 #include <vector>
12 
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/Triple.h"
15 
16 #include "lldb/Core/Module.h"
17 #include "lldb/Core/PluginManager.h"
18 #include "lldb/Core/Value.h"
19 #include "lldb/Core/ValueObjectConstResult.h"
20 #include "lldb/Symbol/UnwindPlan.h"
21 #include "lldb/Target/Process.h"
22 #include "lldb/Target/RegisterContext.h"
23 #include "lldb/Target/Target.h"
24 #include "lldb/Target/Thread.h"
25 #include "lldb/Utility/ConstString.h"
26 #include "lldb/Utility/RegisterValue.h"
27 #include "lldb/Utility/Scalar.h"
28 #include "lldb/Utility/Status.h"
29 
30 #include "Plugins/Process/Utility/ARMDefines.h"
31 #include "Utility/ARM_DWARF_Registers.h"
32 #include "Utility/ARM_ehframe_Registers.h"
33 
34 using namespace lldb;
35 using namespace lldb_private;
36 
37 LLDB_PLUGIN_DEFINE(ABISysV_arm)
38 
39 static const RegisterInfo g_register_infos[] = {
40  // NAME ALT SZ OFF ENCODING FORMAT EH_FRAME
41  // DWARF GENERIC PROCESS PLUGIN
42  // LLDB NATIVE VALUE REGS INVALIDATE REGS
43  // ========== ======= == === ============= ============
44  // ======================= =================== ===========================
45  // ======================= ====================== ==========
46  // ===============
47  {"r0",
48  nullptr,
49  4,
50  0,
51  eEncodingUint,
52  eFormatHex,
53  {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM,
54  LLDB_INVALID_REGNUM},
55  nullptr,
56  nullptr,
57  },
58  {"r1",
59  nullptr,
60  4,
61  0,
62  eEncodingUint,
63  eFormatHex,
64  {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM,
65  LLDB_INVALID_REGNUM},
66  nullptr,
67  nullptr,
68  },
69  {"r2",
70  nullptr,
71  4,
72  0,
73  eEncodingUint,
74  eFormatHex,
75  {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM,
76  LLDB_INVALID_REGNUM},
77  nullptr,
78  nullptr,
79  },
80  {"r3",
81  nullptr,
82  4,
83  0,
84  eEncodingUint,
85  eFormatHex,
86  {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM,
87  LLDB_INVALID_REGNUM},
88  nullptr,
89  nullptr,
90  },
91  {"r4",
92  nullptr,
93  4,
94  0,
95  eEncodingUint,
96  eFormatHex,
97  {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
98  LLDB_INVALID_REGNUM},
99  nullptr,
100  nullptr,
101  },
102  {"r5",
103  nullptr,
104  4,
105  0,
106  eEncodingUint,
107  eFormatHex,
108  {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
109  LLDB_INVALID_REGNUM},
110  nullptr,
111  nullptr,
112  },
113  {"r6",
114  nullptr,
115  4,
116  0,
117  eEncodingUint,
118  eFormatHex,
119  {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
120  LLDB_INVALID_REGNUM},
121  nullptr,
122  nullptr,
123  },
124  {"r7",
125  nullptr,
126  4,
127  0,
128  eEncodingUint,
129  eFormatHex,
130  {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM,
131  LLDB_INVALID_REGNUM},
132  nullptr,
133  nullptr,
134  },
135  {"r8",
136  nullptr,
137  4,
138  0,
139  eEncodingUint,
140  eFormatHex,
141  {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
142  LLDB_INVALID_REGNUM},
143  nullptr,
144  nullptr,
145  },
146  {"r9",
147  nullptr,
148  4,
149  0,
150  eEncodingUint,
151  eFormatHex,
152  {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
153  LLDB_INVALID_REGNUM},
154  nullptr,
155  nullptr,
156  },
157  {"r10",
158  nullptr,
159  4,
160  0,
161  eEncodingUint,
162  eFormatHex,
163  {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
164  LLDB_INVALID_REGNUM},
165  nullptr,
166  nullptr,
167  },
168  {"r11",
169  nullptr,
170  4,
171  0,
172  eEncodingUint,
173  eFormatHex,
174  {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
175  LLDB_INVALID_REGNUM},
176  nullptr,
177  nullptr,
178  },
179  {"r12",
180  nullptr,
181  4,
182  0,
183  eEncodingUint,
184  eFormatHex,
185  {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
186  LLDB_INVALID_REGNUM},
187  nullptr,
188  nullptr,
189  },
190  {"sp",
191  "r13",
192  4,
193  0,
194  eEncodingUint,
195  eFormatHex,
196  {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM,
197  LLDB_INVALID_REGNUM},
198  nullptr,
199  nullptr,
200  },
201  {"lr",
202  "r14",
203  4,
204  0,
205  eEncodingUint,
206  eFormatHex,
207  {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM,
208  LLDB_INVALID_REGNUM},
209  nullptr,
210  nullptr,
211  },
212  {"pc",
213  "r15",
214  4,
215  0,
216  eEncodingUint,
217  eFormatHex,
218  {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM,
219  LLDB_INVALID_REGNUM},
220  nullptr,
221  nullptr,
222  },
223  {"cpsr",
224  "psr",
225  4,
226  0,
227  eEncodingUint,
228  eFormatHex,
229  {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM,
230  LLDB_INVALID_REGNUM},
231  nullptr,
232  nullptr,
233  },
234  {"s0",
235  nullptr,
236  4,
237  0,
238  eEncodingIEEE754,
239  eFormatFloat,
240  {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
241  LLDB_INVALID_REGNUM},
242  nullptr,
243  nullptr,
244  },
245  {"s1",
246  nullptr,
247  4,
248  0,
249  eEncodingIEEE754,
250  eFormatFloat,
251  {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
252  LLDB_INVALID_REGNUM},
253  nullptr,
254  nullptr,
255  },
256  {"s2",
257  nullptr,
258  4,
259  0,
260  eEncodingIEEE754,
261  eFormatFloat,
262  {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
263  LLDB_INVALID_REGNUM},
264  nullptr,
265  nullptr,
266  },
267  {"s3",
268  nullptr,
269  4,
270  0,
271  eEncodingIEEE754,
272  eFormatFloat,
273  {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
274  LLDB_INVALID_REGNUM},
275  nullptr,
276  nullptr,
277  },
278  {"s4",
279  nullptr,
280  4,
281  0,
282  eEncodingIEEE754,
283  eFormatFloat,
284  {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
285  LLDB_INVALID_REGNUM},
286  nullptr,
287  nullptr,
288  },
289  {"s5",
290  nullptr,
291  4,
292  0,
293  eEncodingIEEE754,
294  eFormatFloat,
295  {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
296  LLDB_INVALID_REGNUM},
297  nullptr,
298  nullptr,
299  },
300  {"s6",
301  nullptr,
302  4,
303  0,
304  eEncodingIEEE754,
305  eFormatFloat,
306  {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
307  LLDB_INVALID_REGNUM},
308  nullptr,
309  nullptr,
310  },
311  {"s7",
312  nullptr,
313  4,
314  0,
315  eEncodingIEEE754,
316  eFormatFloat,
317  {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
318  LLDB_INVALID_REGNUM},
319  nullptr,
320  nullptr,
321  },
322  {"s8",
323  nullptr,
324  4,
325  0,
326  eEncodingIEEE754,
327  eFormatFloat,
328  {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
329  LLDB_INVALID_REGNUM},
330  nullptr,
331  nullptr,
332  },
333  {"s9",
334  nullptr,
335  4,
336  0,
337  eEncodingIEEE754,
338  eFormatFloat,
339  {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
340  LLDB_INVALID_REGNUM},
341  nullptr,
342  nullptr,
343  },
344  {"s10",
345  nullptr,
346  4,
347  0,
348  eEncodingIEEE754,
349  eFormatFloat,
350  {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
351  LLDB_INVALID_REGNUM},
352  nullptr,
353  nullptr,
354  },
355  {"s11",
356  nullptr,
357  4,
358  0,
359  eEncodingIEEE754,
360  eFormatFloat,
361  {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
362  LLDB_INVALID_REGNUM},
363  nullptr,
364  nullptr,
365  },
366  {"s12",
367  nullptr,
368  4,
369  0,
370  eEncodingIEEE754,
371  eFormatFloat,
372  {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
373  LLDB_INVALID_REGNUM},
374  nullptr,
375  nullptr,
376  },
377  {"s13",
378  nullptr,
379  4,
380  0,
381  eEncodingIEEE754,
382  eFormatFloat,
383  {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
384  LLDB_INVALID_REGNUM},
385  nullptr,
386  nullptr,
387  },
388  {"s14",
389  nullptr,
390  4,
391  0,
392  eEncodingIEEE754,
393  eFormatFloat,
394  {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
395  LLDB_INVALID_REGNUM},
396  nullptr,
397  nullptr,
398  },
399  {"s15",
400  nullptr,
401  4,
402  0,
403  eEncodingIEEE754,
404  eFormatFloat,
405  {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
406  LLDB_INVALID_REGNUM},
407  nullptr,
408  nullptr,
409  },
410  {"s16",
411  nullptr,
412  4,
413  0,
414  eEncodingIEEE754,
415  eFormatFloat,
416  {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
417  LLDB_INVALID_REGNUM},
418  nullptr,
419  nullptr,
420  },
421  {"s17",
422  nullptr,
423  4,
424  0,
425  eEncodingIEEE754,
426  eFormatFloat,
427  {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
428  LLDB_INVALID_REGNUM},
429  nullptr,
430  nullptr,
431  },
432  {"s18",
433  nullptr,
434  4,
435  0,
436  eEncodingIEEE754,
437  eFormatFloat,
438  {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
439  LLDB_INVALID_REGNUM},
440  nullptr,
441  nullptr,
442  },
443  {"s19",
444  nullptr,
445  4,
446  0,
447  eEncodingIEEE754,
448  eFormatFloat,
449  {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
450  LLDB_INVALID_REGNUM},
451  nullptr,
452  nullptr,
453  },
454  {"s20",
455  nullptr,
456  4,
457  0,
458  eEncodingIEEE754,
459  eFormatFloat,
460  {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
461  LLDB_INVALID_REGNUM},
462  nullptr,
463  nullptr,
464  },
465  {"s21",
466  nullptr,
467  4,
468  0,
469  eEncodingIEEE754,
470  eFormatFloat,
471  {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
472  LLDB_INVALID_REGNUM},
473  nullptr,
474  nullptr,
475  },
476  {"s22",
477  nullptr,
478  4,
479  0,
480  eEncodingIEEE754,
481  eFormatFloat,
482  {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
483  LLDB_INVALID_REGNUM},
484  nullptr,
485  nullptr,
486  },
487  {"s23",
488  nullptr,
489  4,
490  0,
491  eEncodingIEEE754,
492  eFormatFloat,
493  {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
494  LLDB_INVALID_REGNUM},
495  nullptr,
496  nullptr,
497  },
498  {"s24",
499  nullptr,
500  4,
501  0,
502  eEncodingIEEE754,
503  eFormatFloat,
504  {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
505  LLDB_INVALID_REGNUM},
506  nullptr,
507  nullptr,
508  },
509  {"s25",
510  nullptr,
511  4,
512  0,
513  eEncodingIEEE754,
514  eFormatFloat,
515  {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
516  LLDB_INVALID_REGNUM},
517  nullptr,
518  nullptr,
519  },
520  {"s26",
521  nullptr,
522  4,
523  0,
524  eEncodingIEEE754,
525  eFormatFloat,
526  {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
527  LLDB_INVALID_REGNUM},
528  nullptr,
529  nullptr,
530  },
531  {"s27",
532  nullptr,
533  4,
534  0,
535  eEncodingIEEE754,
536  eFormatFloat,
537  {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
538  LLDB_INVALID_REGNUM},
539  nullptr,
540  nullptr,
541  },
542  {"s28",
543  nullptr,
544  4,
545  0,
546  eEncodingIEEE754,
547  eFormatFloat,
548  {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
549  LLDB_INVALID_REGNUM},
550  nullptr,
551  nullptr,
552  },
553  {"s29",
554  nullptr,
555  4,
556  0,
557  eEncodingIEEE754,
558  eFormatFloat,
559  {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
560  LLDB_INVALID_REGNUM},
561  nullptr,
562  nullptr,
563  },
564  {"s30",
565  nullptr,
566  4,
567  0,
568  eEncodingIEEE754,
569  eFormatFloat,
570  {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
571  LLDB_INVALID_REGNUM},
572  nullptr,
573  nullptr,
574  },
575  {"s31",
576  nullptr,
577  4,
578  0,
579  eEncodingIEEE754,
580  eFormatFloat,
581  {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
582  LLDB_INVALID_REGNUM},
583  nullptr,
584  nullptr,
585  },
586  {"fpscr",
587  nullptr,
588  4,
589  0,
590  eEncodingUint,
591  eFormatHex,
592  {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
593  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
594  nullptr,
595  nullptr,
596  },
597  {"d0",
598  nullptr,
599  8,
600  0,
601  eEncodingIEEE754,
602  eFormatFloat,
603  {LLDB_INVALID_REGNUM, dwarf_d0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
604  LLDB_INVALID_REGNUM},
605  nullptr,
606  nullptr,
607  },
608  {"d1",
609  nullptr,
610  8,
611  0,
612  eEncodingIEEE754,
613  eFormatFloat,
614  {LLDB_INVALID_REGNUM, dwarf_d1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
615  LLDB_INVALID_REGNUM},
616  nullptr,
617  nullptr,
618  },
619  {"d2",
620  nullptr,
621  8,
622  0,
623  eEncodingIEEE754,
624  eFormatFloat,
625  {LLDB_INVALID_REGNUM, dwarf_d2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
626  LLDB_INVALID_REGNUM},
627  nullptr,
628  nullptr,
629  },
630  {"d3",
631  nullptr,
632  8,
633  0,
634  eEncodingIEEE754,
635  eFormatFloat,
636  {LLDB_INVALID_REGNUM, dwarf_d3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
637  LLDB_INVALID_REGNUM},
638  nullptr,
639  nullptr,
640  },
641  {"d4",
642  nullptr,
643  8,
644  0,
645  eEncodingIEEE754,
646  eFormatFloat,
647  {LLDB_INVALID_REGNUM, dwarf_d4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
648  LLDB_INVALID_REGNUM},
649  nullptr,
650  nullptr,
651  },
652  {"d5",
653  nullptr,
654  8,
655  0,
656  eEncodingIEEE754,
657  eFormatFloat,
658  {LLDB_INVALID_REGNUM, dwarf_d5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
659  LLDB_INVALID_REGNUM},
660  nullptr,
661  nullptr,
662  },
663  {"d6",
664  nullptr,
665  8,
666  0,
667  eEncodingIEEE754,
668  eFormatFloat,
669  {LLDB_INVALID_REGNUM, dwarf_d6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
670  LLDB_INVALID_REGNUM},
671  nullptr,
672  nullptr,
673  },
674  {"d7",
675  nullptr,
676  8,
677  0,
678  eEncodingIEEE754,
679  eFormatFloat,
680  {LLDB_INVALID_REGNUM, dwarf_d7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
681  LLDB_INVALID_REGNUM},
682  nullptr,
683  nullptr,
684  },
685  {"d8",
686  nullptr,
687  8,
688  0,
689  eEncodingIEEE754,
690  eFormatFloat,
691  {LLDB_INVALID_REGNUM, dwarf_d8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
692  LLDB_INVALID_REGNUM},
693  nullptr,
694  nullptr,
695  },
696  {"d9",
697  nullptr,
698  8,
699  0,
700  eEncodingIEEE754,
701  eFormatFloat,
702  {LLDB_INVALID_REGNUM, dwarf_d9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
703  LLDB_INVALID_REGNUM},
704  nullptr,
705  nullptr,
706  },
707  {"d10",
708  nullptr,
709  8,
710  0,
711  eEncodingIEEE754,
712  eFormatFloat,
713  {LLDB_INVALID_REGNUM, dwarf_d10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
714  LLDB_INVALID_REGNUM},
715  nullptr,
716  nullptr,
717  },
718  {"d11",
719  nullptr,
720  8,
721  0,
722  eEncodingIEEE754,
723  eFormatFloat,
724  {LLDB_INVALID_REGNUM, dwarf_d11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
725  LLDB_INVALID_REGNUM},
726  nullptr,
727  nullptr,
728  },
729  {"d12",
730  nullptr,
731  8,
732  0,
733  eEncodingIEEE754,
734  eFormatFloat,
735  {LLDB_INVALID_REGNUM, dwarf_d12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
736  LLDB_INVALID_REGNUM},
737  nullptr,
738  nullptr,
739  },
740  {"d13",
741  nullptr,
742  8,
743  0,
744  eEncodingIEEE754,
745  eFormatFloat,
746  {LLDB_INVALID_REGNUM, dwarf_d13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
747  LLDB_INVALID_REGNUM},
748  nullptr,
749  nullptr,
750  },
751  {"d14",
752  nullptr,
753  8,
754  0,
755  eEncodingIEEE754,
756  eFormatFloat,
757  {LLDB_INVALID_REGNUM, dwarf_d14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
758  LLDB_INVALID_REGNUM},
759  nullptr,
760  nullptr,
761  },
762  {"d15",
763  nullptr,
764  8,
765  0,
766  eEncodingIEEE754,
767  eFormatFloat,
768  {LLDB_INVALID_REGNUM, dwarf_d15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
769  LLDB_INVALID_REGNUM},
770  nullptr,
771  nullptr,
772  },
773  {"d16",
774  nullptr,
775  8,
776  0,
777  eEncodingIEEE754,
778  eFormatFloat,
779  {LLDB_INVALID_REGNUM, dwarf_d16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
780  LLDB_INVALID_REGNUM},
781  nullptr,
782  nullptr,
783  },
784  {"d17",
785  nullptr,
786  8,
787  0,
788  eEncodingIEEE754,
789  eFormatFloat,
790  {LLDB_INVALID_REGNUM, dwarf_d17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
791  LLDB_INVALID_REGNUM},
792  nullptr,
793  nullptr,
794  },
795  {"d18",
796  nullptr,
797  8,
798  0,
799  eEncodingIEEE754,
800  eFormatFloat,
801  {LLDB_INVALID_REGNUM, dwarf_d18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
802  LLDB_INVALID_REGNUM},
803  nullptr,
804  nullptr,
805  },
806  {"d19",
807  nullptr,
808  8,
809  0,
810  eEncodingIEEE754,
811  eFormatFloat,
812  {LLDB_INVALID_REGNUM, dwarf_d19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
813  LLDB_INVALID_REGNUM},
814  nullptr,
815  nullptr,
816  },
817  {"d20",
818  nullptr,
819  8,
820  0,
821  eEncodingIEEE754,
822  eFormatFloat,
823  {LLDB_INVALID_REGNUM, dwarf_d20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
824  LLDB_INVALID_REGNUM},
825  nullptr,
826  nullptr,
827  },
828  {"d21",
829  nullptr,
830  8,
831  0,
832  eEncodingIEEE754,
833  eFormatFloat,
834  {LLDB_INVALID_REGNUM, dwarf_d21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
835  LLDB_INVALID_REGNUM},
836  nullptr,
837  nullptr,
838  },
839  {"d22",
840  nullptr,
841  8,
842  0,
843  eEncodingIEEE754,
844  eFormatFloat,
845  {LLDB_INVALID_REGNUM, dwarf_d22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
846  LLDB_INVALID_REGNUM},
847  nullptr,
848  nullptr,
849  },
850  {"d23",
851  nullptr,
852  8,
853  0,
854  eEncodingIEEE754,
855  eFormatFloat,
856  {LLDB_INVALID_REGNUM, dwarf_d23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
857  LLDB_INVALID_REGNUM},
858  nullptr,
859  nullptr,
860  },
861  {"d24",
862  nullptr,
863  8,
864  0,
865  eEncodingIEEE754,
866  eFormatFloat,
867  {LLDB_INVALID_REGNUM, dwarf_d24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
868  LLDB_INVALID_REGNUM},
869  nullptr,
870  nullptr,
871  },
872  {"d25",
873  nullptr,
874  8,
875  0,
876  eEncodingIEEE754,
877  eFormatFloat,
878  {LLDB_INVALID_REGNUM, dwarf_d25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
879  LLDB_INVALID_REGNUM},
880  nullptr,
881  nullptr,
882  },
883  {"d26",
884  nullptr,
885  8,
886  0,
887  eEncodingIEEE754,
888  eFormatFloat,
889  {LLDB_INVALID_REGNUM, dwarf_d26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
890  LLDB_INVALID_REGNUM},
891  nullptr,
892  nullptr,
893  },
894  {"d27",
895  nullptr,
896  8,
897  0,
898  eEncodingIEEE754,
899  eFormatFloat,
900  {LLDB_INVALID_REGNUM, dwarf_d27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
901  LLDB_INVALID_REGNUM},
902  nullptr,
903  nullptr,
904  },
905  {"d28",
906  nullptr,
907  8,
908  0,
909  eEncodingIEEE754,
910  eFormatFloat,
911  {LLDB_INVALID_REGNUM, dwarf_d28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
912  LLDB_INVALID_REGNUM},
913  nullptr,
914  nullptr,
915  },
916  {"d29",
917  nullptr,
918  8,
919  0,
920  eEncodingIEEE754,
921  eFormatFloat,
922  {LLDB_INVALID_REGNUM, dwarf_d29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
923  LLDB_INVALID_REGNUM},
924  nullptr,
925  nullptr,
926  },
927  {"d30",
928  nullptr,
929  8,
930  0,
931  eEncodingIEEE754,
932  eFormatFloat,
933  {LLDB_INVALID_REGNUM, dwarf_d30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
934  LLDB_INVALID_REGNUM},
935  nullptr,
936  nullptr,
937  },
938  {"d31",
939  nullptr,
940  8,
941  0,
942  eEncodingIEEE754,
943  eFormatFloat,
944  {LLDB_INVALID_REGNUM, dwarf_d31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
945  LLDB_INVALID_REGNUM},
946  nullptr,
947  nullptr,
948  },
949  {"r8_usr",
950  nullptr,
951  4,
952  0,
953  eEncodingUint,
954  eFormatHex,
955  {LLDB_INVALID_REGNUM, dwarf_r8_usr, LLDB_INVALID_REGNUM,
956  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
957  nullptr,
958  nullptr,
959  },
960  {"r9_usr",
961  nullptr,
962  4,
963  0,
964  eEncodingUint,
965  eFormatHex,
966  {LLDB_INVALID_REGNUM, dwarf_r9_usr, LLDB_INVALID_REGNUM,
967  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
968  nullptr,
969  nullptr,
970  },
971  {"r10_usr",
972  nullptr,
973  4,
974  0,
975  eEncodingUint,
976  eFormatHex,
977  {LLDB_INVALID_REGNUM, dwarf_r10_usr, LLDB_INVALID_REGNUM,
978  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
979  nullptr,
980  nullptr,
981  },
982  {"r11_usr",
983  nullptr,
984  4,
985  0,
986  eEncodingUint,
987  eFormatHex,
988  {LLDB_INVALID_REGNUM, dwarf_r11_usr, LLDB_INVALID_REGNUM,
989  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
990  nullptr,
991  nullptr,
992  },
993  {"r12_usr",
994  nullptr,
995  4,
996  0,
997  eEncodingUint,
998  eFormatHex,
999  {LLDB_INVALID_REGNUM, dwarf_r12_usr, LLDB_INVALID_REGNUM,
1000  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1001  nullptr,
1002  nullptr,
1003  },
1004  {"r13_usr",
1005  "sp_usr",
1006  4,
1007  0,
1008  eEncodingUint,
1009  eFormatHex,
1010  {LLDB_INVALID_REGNUM, dwarf_r13_usr, LLDB_INVALID_REGNUM,
1011  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1012  nullptr,
1013  nullptr,
1014  },
1015  {"r14_usr",
1016  "lr_usr",
1017  4,
1018  0,
1019  eEncodingUint,
1020  eFormatHex,
1021  {LLDB_INVALID_REGNUM, dwarf_r14_usr, LLDB_INVALID_REGNUM,
1022  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1023  nullptr,
1024  nullptr,
1025  },
1026  {"r8_fiq",
1027  nullptr,
1028  4,
1029  0,
1030  eEncodingUint,
1031  eFormatHex,
1032  {LLDB_INVALID_REGNUM, dwarf_r8_fiq, LLDB_INVALID_REGNUM,
1033  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1034  nullptr,
1035  nullptr,
1036  },
1037  {"r9_fiq",
1038  nullptr,
1039  4,
1040  0,
1041  eEncodingUint,
1042  eFormatHex,
1043  {LLDB_INVALID_REGNUM, dwarf_r9_fiq, LLDB_INVALID_REGNUM,
1044  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1045  nullptr,
1046  nullptr,
1047  },
1048  {"r10_fiq",
1049  nullptr,
1050  4,
1051  0,
1052  eEncodingUint,
1053  eFormatHex,
1054  {LLDB_INVALID_REGNUM, dwarf_r10_fiq, LLDB_INVALID_REGNUM,
1055  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1056  nullptr,
1057  nullptr,
1058  },
1059  {"r11_fiq",
1060  nullptr,
1061  4,
1062  0,
1063  eEncodingUint,
1064  eFormatHex,
1065  {LLDB_INVALID_REGNUM, dwarf_r11_fiq, LLDB_INVALID_REGNUM,
1066  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1067  nullptr,
1068  nullptr,
1069  },
1070  {"r12_fiq",
1071  nullptr,
1072  4,
1073  0,
1074  eEncodingUint,
1075  eFormatHex,
1076  {LLDB_INVALID_REGNUM, dwarf_r12_fiq, LLDB_INVALID_REGNUM,
1077  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1078  nullptr,
1079  nullptr,
1080  },
1081  {"r13_fiq",
1082  "sp_fiq",
1083  4,
1084  0,
1085  eEncodingUint,
1086  eFormatHex,
1087  {LLDB_INVALID_REGNUM, dwarf_r13_fiq, LLDB_INVALID_REGNUM,
1088  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1089  nullptr,
1090  nullptr,
1091  },
1092  {"r14_fiq",
1093  "lr_fiq",
1094  4,
1095  0,
1096  eEncodingUint,
1097  eFormatHex,
1098  {LLDB_INVALID_REGNUM, dwarf_r14_fiq, LLDB_INVALID_REGNUM,
1099  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1100  nullptr,
1101  nullptr,
1102  },
1103  {"r13_irq",
1104  "sp_irq",
1105  4,
1106  0,
1107  eEncodingUint,
1108  eFormatHex,
1109  {LLDB_INVALID_REGNUM, dwarf_r13_irq, LLDB_INVALID_REGNUM,
1110  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1111  nullptr,
1112  nullptr,
1113  },
1114  {"r14_irq",
1115  "lr_irq",
1116  4,
1117  0,
1118  eEncodingUint,
1119  eFormatHex,
1120  {LLDB_INVALID_REGNUM, dwarf_r14_irq, LLDB_INVALID_REGNUM,
1121  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1122  nullptr,
1123  nullptr,
1124  },
1125  {"r13_abt",
1126  "sp_abt",
1127  4,
1128  0,
1129  eEncodingUint,
1130  eFormatHex,
1131  {LLDB_INVALID_REGNUM, dwarf_r13_abt, LLDB_INVALID_REGNUM,
1132  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1133  nullptr,
1134  nullptr,
1135  },
1136  {"r14_abt",
1137  "lr_abt",
1138  4,
1139  0,
1140  eEncodingUint,
1141  eFormatHex,
1142  {LLDB_INVALID_REGNUM, dwarf_r14_abt, LLDB_INVALID_REGNUM,
1143  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1144  nullptr,
1145  nullptr,
1146  },
1147  {"r13_und",
1148  "sp_und",
1149  4,
1150  0,
1151  eEncodingUint,
1152  eFormatHex,
1153  {LLDB_INVALID_REGNUM, dwarf_r13_und, LLDB_INVALID_REGNUM,
1154  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1155  nullptr,
1156  nullptr,
1157  },
1158  {"r14_und",
1159  "lr_und",
1160  4,
1161  0,
1162  eEncodingUint,
1163  eFormatHex,
1164  {LLDB_INVALID_REGNUM, dwarf_r14_und, LLDB_INVALID_REGNUM,
1165  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1166  nullptr,
1167  nullptr,
1168  },
1169  {"r13_svc",
1170  "sp_svc",
1171  4,
1172  0,
1173  eEncodingUint,
1174  eFormatHex,
1175  {LLDB_INVALID_REGNUM, dwarf_r13_svc, LLDB_INVALID_REGNUM,
1176  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1177  nullptr,
1178  nullptr,
1179  },
1180  {"r14_svc",
1181  "lr_svc",
1182  4,
1183  0,
1184  eEncodingUint,
1185  eFormatHex,
1186  {LLDB_INVALID_REGNUM, dwarf_r14_svc, LLDB_INVALID_REGNUM,
1187  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1188  nullptr,
1189  nullptr,
1190  }};
1191 
1192 static const uint32_t k_num_register_infos = std::size(g_register_infos);
1193 
1194 const lldb_private::RegisterInfo *
1195 ABISysV_arm::GetRegisterInfoArray(uint32_t &count) {
1196  count = k_num_register_infos;
1197  return g_register_infos;
1198 }
1199 
1200 size_t ABISysV_arm::GetRedZoneSize() const { return 0; }
1201 
1202 // Static Functions
1203 
1204 ABISP
1205 ABISysV_arm::CreateInstance(lldb::ProcessSP process_sp, const ArchSpec &arch) {
1206  const llvm::Triple::ArchType arch_type = arch.GetTriple().getArch();
1207  const llvm::Triple::VendorType vendor_type = arch.GetTriple().getVendor();
1208 
1209  if (vendor_type != llvm::Triple::Apple) {
1210  if ((arch_type == llvm::Triple::arm) ||
1211  (arch_type == llvm::Triple::thumb)) {
1212  return ABISP(
1213  new ABISysV_arm(std::move(process_sp), MakeMCRegisterInfo(arch)));
1214  }
1215  }
1216 
1217  return ABISP();
1218 }
1219 
1220 bool ABISysV_arm::PrepareTrivialCall(Thread &thread, addr_t sp,
1221  addr_t function_addr, addr_t return_addr,
1222  llvm::ArrayRef<addr_t> args) const {
1223  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1224  if (!reg_ctx)
1225  return false;
1226 
1227  const uint32_t pc_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1228  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
1229  const uint32_t sp_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1230  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
1231  const uint32_t ra_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1232  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
1233 
1234  RegisterValue reg_value;
1235 
1236  const uint8_t reg_names[] = {
1237  LLDB_REGNUM_GENERIC_ARG1, LLDB_REGNUM_GENERIC_ARG2,
1238  LLDB_REGNUM_GENERIC_ARG3, LLDB_REGNUM_GENERIC_ARG4};
1239 
1240  llvm::ArrayRef<addr_t>::iterator ai = args.begin(), ae = args.end();
1241 
1242  for (size_t i = 0; i < std::size(reg_names); ++i) {
1243  if (ai == ae)
1244  break;
1245 
1246  reg_value.SetUInt32(*ai);
1247  if (!reg_ctx->WriteRegister(
1248  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, reg_names[i]),
1249  reg_value))
1250  return false;
1251 
1252  ++ai;
1253  }
1254 
1255  if (ai != ae) {
1256  // Spill onto the stack
1257  size_t num_stack_regs = ae - ai;
1258 
1259  sp -= (num_stack_regs * 4);
1260  // Keep the stack 8 byte aligned, not that we need to
1261  sp &= ~(8ull - 1ull);
1262 
1263  // just using arg1 to get the right size
1264  const RegisterInfo *reg_info = reg_ctx->GetRegisterInfo(
1265  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
1266 
1267  addr_t arg_pos = sp;
1268 
1269  for (; ai != ae; ++ai) {
1270  reg_value.SetUInt32(*ai);
1271  if (reg_ctx
1272  ->WriteRegisterValueToMemory(reg_info, arg_pos,
1273  reg_info->byte_size, reg_value)
1274  .Fail())
1275  return false;
1276  arg_pos += reg_info->byte_size;
1277  }
1278  }
1279 
1280  TargetSP target_sp(thread.CalculateTarget());
1281  Address so_addr;
1282 
1283  // Figure out if our return address is ARM or Thumb by using the
1284  // Address::GetCallableLoadAddress(Target*) which will figure out the ARM
1285  // thumb-ness and set the correct address bits for us.
1286  so_addr.SetLoadAddress(return_addr, target_sp.get());
1287  return_addr = so_addr.GetCallableLoadAddress(target_sp.get());
1288 
1289  // Set "lr" to the return address
1290  if (!reg_ctx->WriteRegisterFromUnsigned(ra_reg_num, return_addr))
1291  return false;
1292 
1293  // Set "sp" to the requested value
1294  if (!reg_ctx->WriteRegisterFromUnsigned(sp_reg_num, sp))
1295  return false;
1296 
1297  // If bit zero or 1 is set, this must be a thumb function, no need to figure
1298  // this out from the symbols.
1299  so_addr.SetLoadAddress(function_addr, target_sp.get());
1300  function_addr = so_addr.GetCallableLoadAddress(target_sp.get());
1301 
1302  const RegisterInfo *cpsr_reg_info =
1303  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS);
1304  const uint32_t curr_cpsr = reg_ctx->ReadRegisterAsUnsigned(cpsr_reg_info, 0);
1305 
1306  // Make a new CPSR and mask out any Thumb IT (if/then) bits
1307  uint32_t new_cpsr = curr_cpsr & ~MASK_CPSR_IT_MASK;
1308  // If bit zero or 1 is set, this must be thumb...
1309  if (function_addr & 1ull)
1310  new_cpsr |= MASK_CPSR_T; // Set T bit in CPSR
1311  else
1312  new_cpsr &= ~MASK_CPSR_T; // Clear T bit in CPSR
1313 
1314  if (new_cpsr != curr_cpsr) {
1315  if (!reg_ctx->WriteRegisterFromUnsigned(cpsr_reg_info, new_cpsr))
1316  return false;
1317  }
1318 
1319  function_addr &=
1320  ~1ull; // clear bit zero since the CPSR will take care of the mode for us
1321 
1322  // Set "pc" to the address requested
1323  return reg_ctx->WriteRegisterFromUnsigned(pc_reg_num, function_addr);
1324 }
1325 
1326 bool ABISysV_arm::GetArgumentValues(Thread &thread, ValueList &values) const {
1327  uint32_t num_values = values.GetSize();
1328 
1329  ExecutionContext exe_ctx(thread.shared_from_this());
1330  // For now, assume that the types in the AST values come from the Target's
1331  // scratch AST.
1332 
1333  // Extract the register context so we can read arguments from registers
1334 
1335  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1336 
1337  if (!reg_ctx)
1338  return false;
1339 
1340  addr_t sp = 0;
1341 
1342  for (uint32_t value_idx = 0; value_idx < num_values; ++value_idx) {
1343  // We currently only support extracting values with Clang QualTypes. Do we
1344  // care about others?
1345  Value *value = values.GetValueAtIndex(value_idx);
1346 
1347  if (!value)
1348  return false;
1349 
1350  CompilerType compiler_type = value->GetCompilerType();
1351  if (compiler_type) {
1352  bool is_signed = false;
1353  size_t bit_width = 0;
1354  if (compiler_type.IsIntegerOrEnumerationType(is_signed) ||
1355  compiler_type.IsPointerOrReferenceType()) {
1356  if (llvm::Optional<uint64_t> size = compiler_type.GetBitSize(&thread))
1357  bit_width = *size;
1358  } else {
1359  // We only handle integer, pointer and reference types currently...
1360  return false;
1361  }
1362 
1363  if (bit_width <= (exe_ctx.GetProcessRef().GetAddressByteSize() * 8)) {
1364  if (value_idx < 4) {
1365  // Arguments 1-4 are in r0-r3...
1366  const RegisterInfo *arg_reg_info = nullptr;
1367  arg_reg_info = reg_ctx->GetRegisterInfo(
1368  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1 + value_idx);
1369  if (arg_reg_info) {
1370  RegisterValue reg_value;
1371 
1372  if (reg_ctx->ReadRegister(arg_reg_info, reg_value)) {
1373  if (is_signed)
1374  reg_value.SignExtend(bit_width);
1375  if (!reg_value.GetScalarValue(value->GetScalar()))
1376  return false;
1377  continue;
1378  }
1379  }
1380  return false;
1381  } else {
1382  if (sp == 0) {
1383  // Read the stack pointer if it already hasn't been read
1384  sp = reg_ctx->GetSP(0);
1385  if (sp == 0)
1386  return false;
1387  }
1388 
1389  // Arguments 5 on up are on the stack
1390  const uint32_t arg_byte_size = (bit_width + (8 - 1)) / 8;
1391  Status error;
1392  if (!exe_ctx.GetProcessRef().ReadScalarIntegerFromMemory(
1393  sp, arg_byte_size, is_signed, value->GetScalar(), error))
1394  return false;
1395 
1396  sp += arg_byte_size;
1397  }
1398  }
1399  }
1400  }
1401  return true;
1402 }
1403 
1404 static bool GetReturnValuePassedInMemory(Thread &thread,
1405  RegisterContext *reg_ctx,
1406  size_t byte_size, Value &value) {
1407  Status error;
1408  DataBufferHeap buffer(byte_size, 0);
1409 
1410  const RegisterInfo *r0_reg_info =
1411  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
1412  uint32_t address =
1413  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1414  thread.GetProcess()->ReadMemory(address, buffer.GetBytes(),
1415  buffer.GetByteSize(), error);
1416 
1417  if (error.Fail())
1418  return false;
1419 
1420  value.SetBytes(buffer.GetBytes(), buffer.GetByteSize());
1421  return true;
1422 }
1423 
1424 bool ABISysV_arm::IsArmHardFloat(Thread &thread) const {
1425  ProcessSP process_sp(thread.GetProcess());
1426  if (process_sp) {
1427  const ArchSpec &arch(process_sp->GetTarget().GetArchitecture());
1428 
1429  return (arch.GetFlags() & ArchSpec::eARM_abi_hard_float) != 0;
1430  }
1431 
1432  return false;
1433 }
1434 
1435 ValueObjectSP ABISysV_arm::GetReturnValueObjectImpl(
1436  Thread &thread, lldb_private::CompilerType &compiler_type) const {
1437  Value value;
1438  ValueObjectSP return_valobj_sp;
1439 
1440  if (!compiler_type)
1441  return return_valobj_sp;
1442 
1443  // value.SetContext (Value::eContextTypeClangType,
1444  // compiler_type.GetOpaqueQualType());
1445  value.SetCompilerType(compiler_type);
1446 
1447  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1448  if (!reg_ctx)
1449  return return_valobj_sp;
1450 
1451  bool is_signed;
1452  bool is_complex;
1453  uint32_t float_count;
1454  bool is_vfp_candidate = false;
1455  uint8_t vfp_count = 0;
1456  uint8_t vfp_byte_size = 0;
1457 
1458  // Get the pointer to the first stack argument so we have a place to start
1459  // when reading data
1460 
1461  const RegisterInfo *r0_reg_info =
1462  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
1463  llvm::Optional<uint64_t> bit_width = compiler_type.GetBitSize(&thread);
1464  llvm::Optional<uint64_t> byte_size = compiler_type.GetByteSize(&thread);
1465  if (!bit_width || !byte_size)
1466  return return_valobj_sp;
1467 
1468  if (compiler_type.IsIntegerOrEnumerationType(is_signed)) {
1469  switch (*bit_width) {
1470  default:
1471  return return_valobj_sp;
1472  case 64: {
1473  const RegisterInfo *r1_reg_info = reg_ctx->GetRegisterInfo(
1474  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2);
1475  uint64_t raw_value;
1476  raw_value = reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1477  raw_value |= ((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(r1_reg_info, 0) &
1478  UINT32_MAX))
1479  << 32;
1480  if (is_signed)
1481  value.GetScalar() = (int64_t)raw_value;
1482  else
1483  value.GetScalar() = (uint64_t)raw_value;
1484  } break;
1485  case 32:
1486  if (is_signed)
1487  value.GetScalar() = (int32_t)(
1488  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX);
1489  else
1490  value.GetScalar() = (uint32_t)(
1491  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX);
1492  break;
1493  case 16:
1494  if (is_signed)
1495  value.GetScalar() = (int16_t)(
1496  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT16_MAX);
1497  else
1498  value.GetScalar() = (uint16_t)(
1499  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT16_MAX);
1500  break;
1501  case 8:
1502  if (is_signed)
1503  value.GetScalar() = (int8_t)(
1504  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT8_MAX);
1505  else
1506  value.GetScalar() = (uint8_t)(
1507  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT8_MAX);
1508  break;
1509  }
1510  } else if (compiler_type.IsPointerType()) {
1511  uint32_t ptr =
1512  thread.GetRegisterContext()->ReadRegisterAsUnsigned(r0_reg_info, 0) &
1513  UINT32_MAX;
1514  value.GetScalar() = ptr;
1515  } else if (compiler_type.IsVectorType()) {
1516  if (IsArmHardFloat(thread) && (*byte_size == 8 || *byte_size == 16)) {
1517  is_vfp_candidate = true;
1518  vfp_byte_size = 8;
1519  vfp_count = (*byte_size == 8 ? 1 : 2);
1520  } else if (*byte_size <= 16) {
1521  DataBufferHeap buffer(16, 0);
1522  uint32_t *buffer_ptr = (uint32_t *)buffer.GetBytes();
1523 
1524  for (uint32_t i = 0; 4 * i < *byte_size; ++i) {
1525  const RegisterInfo *reg_info = reg_ctx->GetRegisterInfo(
1526  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1 + i);
1527  buffer_ptr[i] =
1528  reg_ctx->ReadRegisterAsUnsigned(reg_info, 0) & UINT32_MAX;
1529  }
1530  value.SetBytes(buffer.GetBytes(), *byte_size);
1531  } else {
1532  if (!GetReturnValuePassedInMemory(thread, reg_ctx, *byte_size, value))
1533  return return_valobj_sp;
1534  }
1535  } else if (compiler_type.IsFloatingPointType(float_count, is_complex)) {
1536  if (float_count == 1 && !is_complex) {
1537  switch (*bit_width) {
1538  default:
1539  return return_valobj_sp;
1540  case 64: {
1541  static_assert(sizeof(double) == sizeof(uint64_t));
1542 
1543  if (IsArmHardFloat(thread)) {
1544  RegisterValue reg_value;
1545  const RegisterInfo *d0_reg_info =
1546  reg_ctx->GetRegisterInfoByName("d0", 0);
1547  reg_ctx->ReadRegister(d0_reg_info, reg_value);
1548  value.GetScalar() = reg_value.GetAsDouble();
1549  } else {
1550  uint64_t raw_value;
1551  const RegisterInfo *r1_reg_info = reg_ctx->GetRegisterInfo(
1552  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2);
1553  raw_value =
1554  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1555  raw_value |=
1556  ((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(r1_reg_info, 0) &
1557  UINT32_MAX))
1558  << 32;
1559  value.GetScalar() = *reinterpret_cast<double *>(&raw_value);
1560  }
1561  break;
1562  }
1563  case 16: // Half precision returned after a conversion to single precision
1564  case 32: {
1565  static_assert(sizeof(float) == sizeof(uint32_t));
1566 
1567  if (IsArmHardFloat(thread)) {
1568  RegisterValue reg_value;
1569  const RegisterInfo *s0_reg_info =
1570  reg_ctx->GetRegisterInfoByName("s0", 0);
1571  reg_ctx->ReadRegister(s0_reg_info, reg_value);
1572  value.GetScalar() = reg_value.GetAsFloat();
1573  } else {
1574  uint32_t raw_value;
1575  raw_value =
1576  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1577  value.GetScalar() = *reinterpret_cast<float *>(&raw_value);
1578  }
1579  break;
1580  }
1581  }
1582  } else if (is_complex && float_count == 2) {
1583  if (IsArmHardFloat(thread)) {
1584  is_vfp_candidate = true;
1585  vfp_byte_size = *byte_size / 2;
1586  vfp_count = 2;
1587  } else if (!GetReturnValuePassedInMemory(thread, reg_ctx, *bit_width / 8,
1588  value))
1589  return return_valobj_sp;
1590  } else
1591  // not handled yet
1592  return return_valobj_sp;
1593  } else if (compiler_type.IsAggregateType()) {
1594  if (IsArmHardFloat(thread)) {
1595  CompilerType base_type;
1596  const uint32_t homogeneous_count =
1597  compiler_type.IsHomogeneousAggregate(&base_type);
1598 
1599  if (homogeneous_count > 0 && homogeneous_count <= 4) {
1600  llvm::Optional<uint64_t> base_byte_size =
1601  base_type.GetByteSize(&thread);
1602  if (base_type.IsVectorType()) {
1603  if (base_byte_size &&
1604  (*base_byte_size == 8 || *base_byte_size == 16)) {
1605  is_vfp_candidate = true;
1606  vfp_byte_size = 8;
1607  vfp_count = (*base_byte_size == 8 ? homogeneous_count
1608  : homogeneous_count * 2);
1609  }
1610  } else if (base_type.IsFloatingPointType(float_count, is_complex)) {
1611  if (float_count == 1 && !is_complex) {
1612  is_vfp_candidate = true;
1613  if (base_byte_size)
1614  vfp_byte_size = *base_byte_size;
1615  vfp_count = homogeneous_count;
1616  }
1617  }
1618  } else if (homogeneous_count == 0) {
1619  const uint32_t num_children = compiler_type.GetNumFields();
1620 
1621  if (num_children > 0 && num_children <= 2) {
1622  uint32_t index = 0;
1623  for (index = 0; index < num_children; index++) {
1624  std::string name;
1625  base_type = compiler_type.GetFieldAtIndex(index, name, nullptr,
1626  nullptr, nullptr);
1627 
1628  if (base_type.IsFloatingPointType(float_count, is_complex)) {
1629  llvm::Optional<uint64_t> base_byte_size =
1630  base_type.GetByteSize(&thread);
1631  if (float_count == 2 && is_complex) {
1632  if (index != 0 && base_byte_size &&
1633  vfp_byte_size != *base_byte_size)
1634  break;
1635  else if (base_byte_size)
1636  vfp_byte_size = *base_byte_size;
1637  } else
1638  break;
1639  } else
1640  break;
1641  }
1642 
1643  if (index == num_children) {
1644  is_vfp_candidate = true;
1645  vfp_byte_size = (vfp_byte_size >> 1);
1646  vfp_count = (num_children << 1);
1647  }
1648  }
1649  }
1650  }
1651 
1652  if (*byte_size <= 4) {
1653  RegisterValue r0_reg_value;
1654  uint32_t raw_value =
1655  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1656  value.SetBytes(&raw_value, *byte_size);
1657  } else if (!is_vfp_candidate) {
1658  if (!GetReturnValuePassedInMemory(thread, reg_ctx, *byte_size, value))
1659  return return_valobj_sp;
1660  }
1661  } else {
1662  // not handled yet
1663  return return_valobj_sp;
1664  }
1665 
1666  if (is_vfp_candidate) {
1667  ProcessSP process_sp(thread.GetProcess());
1668  ByteOrder byte_order = process_sp->GetByteOrder();
1669 
1670  WritableDataBufferSP data_sp(new DataBufferHeap(*byte_size, 0));
1671  uint32_t data_offset = 0;
1672 
1673  for (uint32_t reg_index = 0; reg_index < vfp_count; reg_index++) {
1674  uint32_t regnum = 0;
1675 
1676  if (vfp_byte_size == 4)
1677  regnum = dwarf_s0 + reg_index;
1678  else if (vfp_byte_size == 8)
1679  regnum = dwarf_d0 + reg_index;
1680  else
1681  break;
1682 
1683  const RegisterInfo *reg_info =
1684  reg_ctx->GetRegisterInfo(eRegisterKindDWARF, regnum);
1685  if (reg_info == nullptr)
1686  break;
1687 
1688  RegisterValue reg_value;
1689  if (!reg_ctx->ReadRegister(reg_info, reg_value))
1690  break;
1691 
1692  // Make sure we have enough room in "data_sp"
1693  if ((data_offset + vfp_byte_size) <= data_sp->GetByteSize()) {
1694  Status error;
1695  const size_t bytes_copied = reg_value.GetAsMemoryData(
1696  *reg_info, data_sp->GetBytes() + data_offset, vfp_byte_size,
1697  byte_order, error);
1698  if (bytes_copied != vfp_byte_size)
1699  break;
1700 
1701  data_offset += bytes_copied;
1702  }
1703  }
1704 
1705  if (data_offset == *byte_size) {
1706  DataExtractor data;
1707  data.SetByteOrder(byte_order);
1708  data.SetAddressByteSize(process_sp->GetAddressByteSize());
1709  data.SetData(data_sp);
1710 
1711  return ValueObjectConstResult::Create(&thread, compiler_type,
1712  ConstString(""), data);
1713  } else { // Some error occurred while getting values from registers
1714  return return_valobj_sp;
1715  }
1716  }
1717 
1718  // If we get here, we have a valid Value, so make our ValueObject out of it:
1719 
1720  return_valobj_sp = ValueObjectConstResult::Create(
1721  thread.GetStackFrameAtIndex(0).get(), value, ConstString(""));
1722  return return_valobj_sp;
1723 }
1724 
1725 Status ABISysV_arm::SetReturnValueObject(lldb::StackFrameSP &frame_sp,
1726  lldb::ValueObjectSP &new_value_sp) {
1727  Status error;
1728  if (!new_value_sp) {
1729  error.SetErrorString("Empty value object for return value.");
1730  return error;
1731  }
1732 
1733  CompilerType compiler_type = new_value_sp->GetCompilerType();
1734  if (!compiler_type) {
1735  error.SetErrorString("Null clang type for return value.");
1736  return error;
1737  }
1738 
1739  Thread *thread = frame_sp->GetThread().get();
1740 
1741  bool is_signed;
1742  uint32_t count;
1743  bool is_complex;
1744 
1745  RegisterContext *reg_ctx = thread->GetRegisterContext().get();
1746 
1747  bool set_it_simple = false;
1748  if (compiler_type.IsIntegerOrEnumerationType(is_signed) ||
1749  compiler_type.IsPointerType()) {
1750  DataExtractor data;
1751  Status data_error;
1752  size_t num_bytes = new_value_sp->GetData(data, data_error);
1753  if (data_error.Fail()) {
1754  error.SetErrorStringWithFormat(
1755  "Couldn't convert return value to raw data: %s",
1756  data_error.AsCString());
1757  return error;
1758  }
1759  lldb::offset_t offset = 0;
1760  if (num_bytes <= 8) {
1761  const RegisterInfo *r0_info = reg_ctx->GetRegisterInfo(
1762  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
1763  if (num_bytes <= 4) {
1764  uint32_t raw_value = data.GetMaxU32(&offset, num_bytes);
1765 
1766  if (reg_ctx->WriteRegisterFromUnsigned(r0_info, raw_value))
1767  set_it_simple = true;
1768  } else {
1769  uint32_t raw_value = data.GetMaxU32(&offset, 4);
1770 
1771  if (reg_ctx->WriteRegisterFromUnsigned(r0_info, raw_value)) {
1772  const RegisterInfo *r1_info = reg_ctx->GetRegisterInfo(
1773  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2);
1774  uint32_t raw_value = data.GetMaxU32(&offset, num_bytes - offset);
1775 
1776  if (reg_ctx->WriteRegisterFromUnsigned(r1_info, raw_value))
1777  set_it_simple = true;
1778  }
1779  }
1780  } else {
1781  error.SetErrorString("We don't support returning longer than 64 bit "
1782  "integer values at present.");
1783  }
1784  } else if (compiler_type.IsFloatingPointType(count, is_complex)) {
1785  if (is_complex)
1786  error.SetErrorString(
1787  "We don't support returning complex values at present");
1788  else
1789  error.SetErrorString(
1790  "We don't support returning float values at present");
1791  }
1792 
1793  if (!set_it_simple)
1794  error.SetErrorString(
1795  "We only support setting simple integer return types at present.");
1796 
1797  return error;
1798 }
1799 
1800 bool ABISysV_arm::CreateFunctionEntryUnwindPlan(UnwindPlan &unwind_plan) {
1801  unwind_plan.Clear();
1802  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
1803 
1804  uint32_t lr_reg_num = dwarf_lr;
1805  uint32_t sp_reg_num = dwarf_sp;
1806  uint32_t pc_reg_num = dwarf_pc;
1807 
1808  UnwindPlan::RowSP row(new UnwindPlan::Row);
1809 
1810  // Our Call Frame Address is the stack pointer value
1811  row->GetCFAValue().SetIsRegisterPlusOffset(sp_reg_num, 0);
1812 
1813  // The previous PC is in the LR
1814  row->SetRegisterLocationToRegister(pc_reg_num, lr_reg_num, true);
1815  unwind_plan.AppendRow(row);
1816 
1817  // All other registers are the same.
1818 
1819  unwind_plan.SetSourceName("arm at-func-entry default");
1820  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1821 
1822  return true;
1823 }
1824 
1825 bool ABISysV_arm::CreateDefaultUnwindPlan(UnwindPlan &unwind_plan) {
1826  unwind_plan.Clear();
1827  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
1828 
1829  // TODO: Handle thumb
1830  uint32_t fp_reg_num = dwarf_r11;
1831  uint32_t pc_reg_num = dwarf_pc;
1832 
1833  UnwindPlan::RowSP row(new UnwindPlan::Row);
1834  const int32_t ptr_size = 4;
1835 
1836  row->GetCFAValue().SetIsRegisterPlusOffset(fp_reg_num, 2 * ptr_size);
1837  row->SetOffset(0);
1838  row->SetUnspecifiedRegistersAreUndefined(true);
1839 
1840  row->SetRegisterLocationToAtCFAPlusOffset(fp_reg_num, ptr_size * -2, true);
1841  row->SetRegisterLocationToAtCFAPlusOffset(pc_reg_num, ptr_size * -1, true);
1842 
1843  unwind_plan.AppendRow(row);
1844  unwind_plan.SetSourceName("arm default unwind plan");
1845  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1846  unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolNo);
1847  unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo);
1848 
1849  return true;
1850 }
1851 
1852 // cf. "ARMv6 Function Calling Conventions"
1853 
1854 // ARMv7 on GNU/Linux general purpose reg rules:
1855 // r0-r3 not preserved (used for argument passing)
1856 // r4-r11 preserved (v1-v8)
1857 // r12 not presrved
1858 // r13 preserved (stack pointer)
1859 // r14 preserved (link register)
1860 // r15 preserved (pc)
1861 // cpsr not preserved (different rules for different bits)
1862 
1863 // ARMv7 VFP register rules:
1864 // d0-d7 not preserved (aka s0-s15, q0-q3)
1865 // d8-d15 preserved (aka s16-s31, q4-q7)
1866 // d16-d31 not preserved (aka q8-q15)
1867 
1868 bool ABISysV_arm::RegisterIsVolatile(const RegisterInfo *reg_info) {
1869  if (reg_info) {
1870  // Volatile registers are: r0, r1, r2, r3, r9, r12, r13 (aka sp)
1871  const char *name = reg_info->name;
1872  if (name[0] == 'r') {
1873  switch (name[1]) {
1874  case '0':
1875  return name[2] == '\0'; // r0
1876  case '1':
1877  switch (name[2]) {
1878  case '\0':
1879  return true; // r1
1880  case '2':
1881  return name[3] == '\0'; // r12
1882  default:
1883  break;
1884  }
1885  break;
1886 
1887  case '2':
1888  return name[2] == '\0'; // r2
1889  case '3':
1890  return name[2] == '\0'; // r3
1891  default:
1892  break;
1893  }
1894  } else if (name[0] == 'd') {
1895  switch (name[1]) {
1896  case '0':
1897  return name[2] == '\0'; // d0 is volatile
1898 
1899  case '1':
1900  switch (name[2]) {
1901  case '\0':
1902  return true; // d1 is volatile
1903  case '6':
1904  case '7':
1905  case '8':
1906  case '9':
1907  return name[3] == '\0'; // d16 - d19 are volatile
1908  default:
1909  break;
1910  }
1911  break;
1912 
1913  case '2':
1914  switch (name[2]) {
1915  case '\0':
1916  return true; // d2 is volatile
1917  case '0':
1918  case '1':
1919  case '2':
1920  case '3':
1921  case '4':
1922  case '5':
1923  case '6':
1924  case '7':
1925  case '8':
1926  case '9':
1927  return name[3] == '\0'; // d20 - d29 are volatile
1928  default:
1929  break;
1930  }
1931  break;
1932 
1933  case '3':
1934  switch (name[2]) {
1935  case '\0':
1936  return true; // d3 is volatile
1937  case '0':
1938  case '1':
1939  return name[3] == '\0'; // d30 - d31 are volatile
1940  default:
1941  break;
1942  }
1943  break;
1944  case '4':
1945  case '5':
1946  case '6':
1947  case '7':
1948  return name[2] == '\0'; // d4 - d7 are volatile
1949 
1950  default:
1951  break;
1952  }
1953  } else if (name[0] == 's') {
1954  switch (name[1]) {
1955  case '0':
1956  return name[2] == '\0'; // s0 is volatile
1957 
1958  case '1':
1959  switch (name[2]) {
1960  case '\0':
1961  return true; // s1 is volatile
1962  case '0':
1963  case '1':
1964  case '2':
1965  case '3':
1966  case '4':
1967  case '5':
1968  return name[3] == '\0'; // s10 - s15 are volatile
1969  default:
1970  break;
1971  }
1972  break;
1973 
1974  case '2':
1975  case '3':
1976  case '4':
1977  case '5':
1978  case '6':
1979  case '7':
1980  case '8':
1981  case '9':
1982  return name[2] == '\0'; // s2 - s9 are volatile
1983 
1984  default:
1985  break;
1986  }
1987  } else if (name[0] == 'q') {
1988  switch (name[1]) {
1989  case '1':
1990  switch (name[2]) {
1991  case '\0':
1992  return true; // q1 is volatile
1993  case '0':
1994  case '1':
1995  case '2':
1996  case '3':
1997  case '4':
1998  case '5':
1999  return true; // q10-q15 are volatile
2000  default:
2001  return false;
2002  }
2003  break;
2004 
2005  case '0':
2006  case '2':
2007  case '3':
2008  return name[2] == '\0'; // q0-q3 are volatile
2009  case '8':
2010  case '9':
2011  return name[2] == '\0'; // q8-q9 are volatile
2012  default:
2013  break;
2014  }
2015  } else if (name[0] == 's' && name[1] == 'p' && name[2] == '\0')
2016  return true;
2017  }
2018  return false;
2019 }
2020 
2021 void ABISysV_arm::Initialize() {
2022  PluginManager::RegisterPlugin(GetPluginNameStatic(),
2023  "SysV ABI for arm targets", CreateInstance);
2024 }
2025 
2026 void ABISysV_arm::Terminate() {
2027  PluginManager::UnregisterPlugin(CreateInstance);
2028 }
dwarf_d9
@ dwarf_d9
Definition: ARM_DWARF_Registers.h:164
dwarf_s10
@ dwarf_s10
Definition: ARM_DWARF_Registers.h:43
lldb_private::Address::SetLoadAddress
bool SetLoadAddress(lldb::addr_t load_addr, Target *target, bool allow_section_end=false)
Set the address to represent load_addr.
Definition: Address.cpp:1040
dwarf_r9
@ dwarf_r9
Definition: ABISysV_mips.cpp:48
ABISysV_arm::GetRegisterInfoArray
const lldb_private::RegisterInfo * GetRegisterInfoArray(uint32_t &count) override
Definition: ABISysV_arm.cpp:1195
lldb_private::RegisterContext::WriteRegister
virtual bool WriteRegister(const RegisterInfo *reg_info, const RegisterValue &reg_value)=0
lldb_private::CompilerType::IsPointerOrReferenceType
bool IsPointerOrReferenceType(CompilerType *pointee_type=nullptr) const
Definition: CompilerType.cpp:192
dwarf_r9_fiq
@ dwarf_r9_fiq
Definition: ARM_DWARF_Registers.h:129
LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_ARG2
Definition: lldb-defines.h:58
dwarf_d19
@ dwarf_d19
Definition: ARM_DWARF_Registers.h:174
LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG3
Definition: lldb-defines.h:60
ABISysV_arm::CreateFunctionEntryUnwindPlan
bool CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override
Definition: ABISysV_arm.cpp:1800
lldb_private::ExecutionContext
Definition: ExecutionContext.h:292
dwarf_d15
@ dwarf_d15
Definition: ARM_DWARF_Registers.h:170
lldb_private::DataBufferHeap::GetByteSize
lldb::offset_t GetByteSize() const override
Definition: DataBufferHeap.cpp:43
dwarf_r14_svc
@ dwarf_r14_svc
Definition: ARM_DWARF_Registers.h:142
ehframe_r1
@ ehframe_r1
Definition: ARM_ehframe_Registers.h:18
Scalar.h
ehframe_r12
@ ehframe_r12
Definition: ARM_ehframe_Registers.h:29
dwarf_s7
@ dwarf_s7
Definition: ARM_DWARF_Registers.h:40
lldb_private::UnwindPlan::AppendRow
void AppendRow(const RowSP &row_sp)
Definition: UnwindPlan.cpp:362
lldb_private::ArchSpec
Definition: ArchSpec.h:32
LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG1
Definition: lldb-defines.h:56
dwarf_r12_fiq
@ dwarf_r12_fiq
Definition: ARM_DWARF_Registers.h:132
dwarf_d7
@ dwarf_d7
Definition: ARM_DWARF_Registers.h:162
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:79
dwarf_s0
@ dwarf_s0
Definition: ARM_DWARF_Registers.h:33
dwarf_r12_usr
@ dwarf_r12_usr
Definition: ARM_DWARF_Registers.h:125
GetReturnValuePassedInMemory
static bool GetReturnValuePassedInMemory(Thread &thread, RegisterContext *reg_ctx, size_t byte_size, Value &value)
Definition: ABISysV_arm.cpp:1404
dwarf_d27
@ dwarf_d27
Definition: ARM_DWARF_Registers.h:182
ABISysV_arm::SetReturnValueObject
lldb_private::Status SetReturnValueObject(lldb::StackFrameSP &frame_sp, lldb::ValueObjectSP &new_value) override
Definition: ABISysV_arm.cpp:1725
lldb_private::RegisterValue
Definition: RegisterValue.h:28
lldb_private::Process::ReadScalarIntegerFromMemory
size_t ReadScalarIntegerFromMemory(lldb::addr_t addr, uint32_t byte_size, bool is_signed, Scalar &scalar, Status &error)
Definition: Process.cpp:2224
lldb_private::UnwindPlan::SetRegisterKind
void SetRegisterKind(lldb::RegisterKind kind)
Definition: UnwindPlan.h:437
lldb::eRegisterKindDWARF
@ eRegisterKindDWARF
the register numbers seen DWARF
Definition: lldb-enumerations.h:230
dwarf_d30
@ dwarf_d30
Definition: ARM_DWARF_Registers.h:185
lldb_private::Value
Definition: Value.h:38
lldb::eRegisterKindGeneric
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target
Definition: lldb-enumerations.h:231
dwarf_r13_svc
@ dwarf_r13_svc
Definition: ARM_DWARF_Registers.h:141
dwarf_s16
@ dwarf_s16
Definition: ARM_DWARF_Registers.h:49
dwarf_r9_usr
@ dwarf_r9_usr
Definition: ARM_DWARF_Registers.h:122
dwarf_r14_usr
@ dwarf_r14_usr
Definition: ARM_DWARF_Registers.h:127
dwarf_r11_fiq
@ dwarf_r11_fiq
Definition: ARM_DWARF_Registers.h:131
lldb_private::ValueList::GetValueAtIndex
Value * GetValueAtIndex(size_t idx)
Definition: Value.cpp:669
lldb_private::CompilerType::IsVectorType
bool IsVectorType(CompilerType *element_type=nullptr, uint64_t *size=nullptr) const
Definition: CompilerType.cpp:68
lldb_private::UnwindPlan::SetUnwindPlanValidAtAllInstructions
void SetUnwindPlanValidAtAllInstructions(lldb_private::LazyBool valid_at_all_insn)
Definition: UnwindPlan.h:490
dwarf_d31
@ dwarf_d31
Definition: ARM_DWARF_Registers.h:186
dwarf_s29
@ dwarf_s29
Definition: ARM_DWARF_Registers.h:62
lldb_private::RegisterContext::ReadRegister
virtual bool ReadRegister(const RegisterInfo *reg_info, RegisterValue &reg_value)=0
dwarf_d10
@ dwarf_d10
Definition: ARM_DWARF_Registers.h:165
ABISysV_arm::RegisterIsVolatile
bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override
Definition: ABISysV_arm.cpp:1868
lldb_private::Thread::CalculateTarget
lldb::TargetSP CalculateTarget() override
Definition: Thread.cpp:1405
Module.h
lldb::eEncodingIEEE754
@ eEncodingIEEE754
float
Definition: lldb-enumerations.h:151
lldb_private::RegisterContext::ConvertRegisterKindToRegisterNumber
virtual uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, uint32_t num)
Convert from a given register numbering scheme to the lldb register numbering scheme.
Definition: RegisterContext.cpp:268
lldb_private::RegisterContext::ReadRegisterAsUnsigned
uint64_t ReadRegisterAsUnsigned(uint32_t reg, uint64_t fail_value)
Definition: RegisterContext.cpp:188
dwarf_r12
@ dwarf_r12
Definition: ABISysV_mips.cpp:51
dwarf_s4
@ dwarf_s4
Definition: ARM_DWARF_Registers.h:37
dwarf_d2
@ dwarf_d2
Definition: ARM_DWARF_Registers.h:157
lldb_private::ArchSpec::GetFlags
uint32_t GetFlags() const
Definition: ArchSpec.h:539
ehframe_sp
@ ehframe_sp
Definition: ARM_ehframe_Registers.h:30
ehframe_r10
@ ehframe_r10
Definition: ARM_ehframe_Registers.h:27
lldb_private::CompilerType::GetByteSize
llvm::Optional< uint64_t > GetByteSize(ExecutionContextScope *exe_scope) const
Return the size of the type in bytes.
Definition: CompilerType.cpp:552
lldb_private::UnwindPlan::SetUnwindPlanForSignalTrap
void SetUnwindPlanForSignalTrap(lldb_private::LazyBool is_for_signal_trap)
Definition: UnwindPlan.h:502
lldb::offset_t
uint64_t offset_t
Definition: lldb-types.h:87
RegisterValue.h
lldb_private::ValueList
Definition: Value.h:157
lldb_private::RegisterValue::GetAsMemoryData
uint32_t GetAsMemoryData(const RegisterInfo &reg_info, void *dst, uint32_t dst_len, lldb::ByteOrder dst_byte_order, Status &error) const
Definition: RegisterValue.cpp:38
dwarf_r13_irq
@ dwarf_r13_irq
Definition: ARM_DWARF_Registers.h:135
ABISysV_arm::CreateInstance
static lldb::ABISP CreateInstance(lldb::ProcessSP process_sp, const lldb_private::ArchSpec &arch)
Definition: ABISysV_arm.cpp:1205
lldb_private::ArchSpec::GetTriple
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:463
lldb_private::CompilerType::IsAggregateType
bool IsAggregateType() const
Definition: CompilerType.cpp:31
lldb::addr_t
uint64_t addr_t
Definition: lldb-types.h:83
lldb_private::CompilerType::IsFloatingPointType
bool IsFloatingPointType(uint32_t &count, bool &is_complex) const
Definition: CompilerType.cpp:220
dwarf_r5
@ dwarf_r5
Definition: ABISysV_mips.cpp:44
dwarf_d12
@ dwarf_d12
Definition: ARM_DWARF_Registers.h:167
dwarf_d4
@ dwarf_d4
Definition: ARM_DWARF_Registers.h:159
dwarf_s17
@ dwarf_s17
Definition: ARM_DWARF_Registers.h:50
dwarf_r10_usr
@ dwarf_r10_usr
Definition: ARM_DWARF_Registers.h:123
dwarf_d6
@ dwarf_d6
Definition: ARM_DWARF_Registers.h:161
lldb_private::UnwindPlan::SetSourceName
void SetSourceName(const char *)
Definition: UnwindPlan.cpp:564
lldb_private::ValueList::GetSize
size_t GetSize()
Definition: Value.cpp:667
dwarf_s20
@ dwarf_s20
Definition: ARM_DWARF_Registers.h:53
ehframe_r7
@ ehframe_r7
Definition: ARM_ehframe_Registers.h:24
lldb_private::DataExtractor::SetData
lldb::offset_t SetData(const void *bytes, lldb::offset_t length, lldb::ByteOrder byte_order)
Set data with a buffer that is caller owned.
Definition: DataExtractor.cpp:223
lldb_private::ExecutionContext::GetProcessRef
Process & GetProcessRef() const
Returns a reference to the process object.
Definition: ExecutionContext.cpp:229
dwarf_d13
@ dwarf_d13
Definition: ARM_DWARF_Registers.h:168
dwarf_s26
@ dwarf_s26
Definition: ARM_DWARF_Registers.h:59
Process.h
dwarf_d20
@ dwarf_d20
Definition: ARM_DWARF_Registers.h:175
lldb_private::CompilerType::IsIntegerOrEnumerationType
bool IsIntegerOrEnumerationType(bool &is_signed) const
Definition: CompilerType.cpp:178
lldb_private::Value::SetCompilerType
void SetCompilerType(const CompilerType &compiler_type)
Definition: Value.cpp:251
dwarf_s27
@ dwarf_s27
Definition: ARM_DWARF_Registers.h:60
dwarf_pc
@ dwarf_pc
Definition: ABISysV_mips.cpp:76
Target.h
lldb_private::DataExtractor::SetByteOrder
void SetByteOrder(lldb::ByteOrder byte_order)
Set the byte_order value.
Definition: DataExtractor.h:931
lldb_private::Value::GetScalar
const Scalar & GetScalar() const
Definition: Value.h:112
lldb_private::CompilerType::IsHomogeneousAggregate
uint32_t IsHomogeneousAggregate(CompilerType *base_type_ptr) const
Definition: CompilerType.cpp:127
lldb_private::Thread::GetProcess
lldb::ProcessSP GetProcess() const
Definition: Thread.h:153
LLDB_REGNUM_GENERIC_FLAGS
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:55
error
static llvm::raw_ostream & error(Stream &strm)
Definition: CommandReturnObject.cpp:17
dwarf_d26
@ dwarf_d26
Definition: ARM_DWARF_Registers.h:181
dwarf_r4
@ dwarf_r4
Definition: ABISysV_mips.cpp:43
ARM_ehframe_Registers.h
dwarf_d14
@ dwarf_d14
Definition: ARM_DWARF_Registers.h:169
dwarf_d29
@ dwarf_d29
Definition: ARM_DWARF_Registers.h:184
ehframe_r2
@ ehframe_r2
Definition: ARM_ehframe_Registers.h:19
dwarf_r13_abt
@ dwarf_r13_abt
Definition: ARM_DWARF_Registers.h:137
dwarf_s28
@ dwarf_s28
Definition: ARM_DWARF_Registers.h:61
lldb_private::DataExtractor
Definition: DataExtractor.h:48
ehframe_r9
@ ehframe_r9
Definition: ARM_ehframe_Registers.h:26
lldb_private::Thread
Definition: Thread.h:61
ehframe_r8
@ ehframe_r8
Definition: ARM_ehframe_Registers.h:25
lldb_private::Address::GetCallableLoadAddress
lldb::addr_t GetCallableLoadAddress(Target *target, bool is_indirect=false) const
Get the load address as a callable code load address.
Definition: Address.cpp:336
lldb_private::Status::Fail
bool Fail() const
Test for error condition.
Definition: Status.cpp:181
lldb_private::DataExtractor::GetMaxU32
uint32_t GetMaxU32(lldb::offset_t *offset_ptr, size_t byte_size) const
Extract an integer of size byte_size from *offset_ptr.
Definition: DataExtractor.cpp:518
ABISysV_arm::CreateDefaultUnwindPlan
bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override
Definition: ABISysV_arm.cpp:1825
lldb_private::DataExtractor::SetAddressByteSize
void SetAddressByteSize(uint32_t addr_size)
Set the address byte size.
Definition: DataExtractor.h:845
dwarf_r2
@ dwarf_r2
Definition: ABISysV_mips.cpp:41
dwarf_d25
@ dwarf_d25
Definition: ARM_DWARF_Registers.h:180
dwarf_d17
@ dwarf_d17
Definition: ARM_DWARF_Registers.h:172
lldb_private::RegisterContext::GetRegisterInfo
const RegisterInfo * GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num)
Definition: RegisterContext.cpp:80
lldb_private::UnwindPlan::SetSourcedFromCompiler
void SetSourcedFromCompiler(lldb_private::LazyBool from_compiler)
Definition: UnwindPlan.h:478
dwarf_r7
@ dwarf_r7
Definition: ABISysV_mips.cpp:46
lldb_private::Process::GetAddressByteSize
uint32_t GetAddressByteSize() const
Definition: Process.cpp:3366
lldb::eEncodingUint
@ eEncodingUint
unsigned integer
Definition: lldb-enumerations.h:149
dwarf_r1
@ dwarf_r1
Definition: ABISysV_mips.cpp:40
lldb_private::ConstString
Definition: ConstString.h:39
dwarf_d0
@ dwarf_d0
Definition: ARM_DWARF_Registers.h:155
ehframe_r0
@ ehframe_r0
Definition: ARM_ehframe_Registers.h:17
dwarf_r8_fiq
@ dwarf_r8_fiq
Definition: ARM_DWARF_Registers.h:128
dwarf_s14
@ dwarf_s14
Definition: ARM_DWARF_Registers.h:47
dwarf_s18
@ dwarf_s18
Definition: ARM_DWARF_Registers.h:51
dwarf_r8_usr
@ dwarf_r8_usr
Definition: ARM_DWARF_Registers.h:121
dwarf_d23
@ dwarf_d23
Definition: ARM_DWARF_Registers.h:178
dwarf_s3
@ dwarf_s3
Definition: ARM_DWARF_Registers.h:36
ARMDefines.h
MASK_CPSR_T
#define MASK_CPSR_T
Definition: ARMDefines.h:176
dwarf_s13
@ dwarf_s13
Definition: ARM_DWARF_Registers.h:46
dwarf_d24
@ dwarf_d24
Definition: ARM_DWARF_Registers.h:179
ehframe_r3
@ ehframe_r3
Definition: ARM_ehframe_Registers.h:20
dwarf_s1
@ dwarf_s1
Definition: ARM_DWARF_Registers.h:34
dwarf_s8
@ dwarf_s8
Definition: ARM_DWARF_Registers.h:41
dwarf_s5
@ dwarf_s5
Definition: ARM_DWARF_Registers.h:38
ehframe_r4
@ ehframe_r4
Definition: ARM_ehframe_Registers.h:21
dwarf_s22
@ dwarf_s22
Definition: ARM_DWARF_Registers.h:55
ehframe_pc
@ ehframe_pc
Definition: ARM_ehframe_Registers.h:32
sp
@ sp
Definition: CompactUnwindInfo.cpp:1250
dwarf_s15
@ dwarf_s15
Definition: ARM_DWARF_Registers.h:48
dwarf_r14_irq
@ dwarf_r14_irq
Definition: ARM_DWARF_Registers.h:136
lldb_private::CompilerType::GetNumFields
uint32_t GetNumFields() const
Definition: CompilerType.cpp:604
string
string(SUBSTRING ${p} 10 -1 pStripped) if($
Definition: Plugins/CMakeLists.txt:40
dwarf_r10
@ dwarf_r10
Definition: ABISysV_mips.cpp:49
dwarf_lr
@ dwarf_lr
Definition: ABISysV_ppc.cpp:106
Thread.h
dwarf_s6
@ dwarf_s6
Definition: ARM_DWARF_Registers.h:39
ehframe_lr
@ ehframe_lr
Definition: ARM_ehframe_Registers.h:31
UnwindPlan.h
lldb_private::RegisterContext::GetSP
uint64_t GetSP(uint64_t fail_value=LLDB_INVALID_ADDRESS)
Definition: RegisterContext.cpp:152
dwarf_s31
@ dwarf_s31
Definition: ARM_DWARF_Registers.h:64
lldb_private::RegisterContext
Definition: RegisterContext.h:17
dwarf_d16
@ dwarf_d16
Definition: ARM_DWARF_Registers.h:171
ehframe_cpsr
@ ehframe_cpsr
Definition: ARM_ehframe_Registers.h:33
ARM_DWARF_Registers.h
ABISysV_arm::GetReturnValueObjectImpl
lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread &thread, lldb_private::CompilerType &ast_type) const override
Definition: ABISysV_arm.cpp:1435
lldb_private::RegisterValue::GetAsDouble
double GetAsDouble(double fail_value=0.0, bool *success_ptr=nullptr) const
Definition: RegisterValue.cpp:645
ABISysV_arm.h
dwarf_r0
@ dwarf_r0
Definition: ABISysV_mips.cpp:39
ValueObjectConstResult.h
lldb_private::UnwindPlan::RowSP
std::shared_ptr< Row > RowSP
Definition: UnwindPlan.h:395
dwarf_d22
@ dwarf_d22
Definition: ARM_DWARF_Registers.h:177
dwarf_r11_usr
@ dwarf_r11_usr
Definition: ARM_DWARF_Registers.h:124
lldb_private::RegisterValue::SetUInt32
void SetUInt32(uint32_t uint, Type t=eTypeUInt32)
Definition: RegisterValue.h:200
dwarf_s12
@ dwarf_s12
Definition: ARM_DWARF_Registers.h:45
dwarf_d1
@ dwarf_d1
Definition: ARM_DWARF_Registers.h:156
dwarf_r13_fiq
@ dwarf_r13_fiq
Definition: ARM_DWARF_Registers.h:133
dwarf_cpsr
@ dwarf_cpsr
Definition: ARM_DWARF_Registers.h:31
dwarf_sp
@ dwarf_sp
Definition: ARM_DWARF_Registers.h:28
lldb_private::UnwindPlan::Clear
void Clear()
Definition: UnwindPlan.h:508
lldb_private::Status
Definition: Status.h:44
k_num_register_infos
static const uint32_t k_num_register_infos
Definition: ABISysV_arm.cpp:1192
lldb_private::RegisterContext::WriteRegisterFromUnsigned
bool WriteRegisterFromUnsigned(uint32_t reg, uint64_t uval)
Definition: RegisterContext.cpp:205
lldb_private::UnwindPlan::Row
Definition: UnwindPlan.h:55
uint32_t
lldb_private::eLazyBoolNo
@ eLazyBoolNo
Definition: lldb-private-enumerations.h:115
lldb_private::Address
Definition: Address.h:59
LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:52
lldb_private::CompilerType::IsPointerType
bool IsPointerType(CompilerType *pointee_type=nullptr) const
Definition: CompilerType.cpp:182
dwarf_r8
@ dwarf_r8
Definition: ABISysV_mips.cpp:47
lldb_private::CompilerType::GetBitSize
llvm::Optional< uint64_t > GetBitSize(ExecutionContextScope *exe_scope) const
Return the size of the type in bits.
Definition: CompilerType.cpp:544
dwarf_d5
@ dwarf_d5
Definition: ARM_DWARF_Registers.h:160
dwarf_s9
@ dwarf_s9
Definition: ARM_DWARF_Registers.h:42
dwarf_d8
@ dwarf_d8
Definition: ARM_DWARF_Registers.h:163
dwarf_r14_und
@ dwarf_r14_und
Definition: ARM_DWARF_Registers.h:140
UINT32_MAX
#define UINT32_MAX
Definition: lldb-defines.h:19
dwarf_r11
@ dwarf_r11
Definition: ABISysV_mips.cpp:50
lldb_private::RegisterValue::GetAsFloat
float GetAsFloat(float fail_value=0.0f, bool *success_ptr=nullptr) const
Definition: RegisterValue.cpp:626
uint16_t
dwarf_s19
@ dwarf_s19
Definition: ARM_DWARF_Registers.h:52
dwarf_s21
@ dwarf_s21
Definition: ARM_DWARF_Registers.h:54
dwarf_r10_fiq
@ dwarf_r10_fiq
Definition: ARM_DWARF_Registers.h:130
ABISysV_arm::Terminate
static void Terminate()
Definition: ABISysV_arm.cpp:2026
PluginManager.h
ehframe_r11
@ ehframe_r11
Definition: ARM_ehframe_Registers.h:28
lldb_private::CompilerType
Generic representation of a type in a programming language.
Definition: CompilerType.h:35
g_register_infos
static const RegisterInfo g_register_infos[]
Definition: ABISysV_arm.cpp:39
dwarf_d11
@ dwarf_d11
Definition: ARM_DWARF_Registers.h:166
lldb_private::Value::GetCompilerType
const CompilerType & GetCompilerType()
Definition: Value.cpp:222
Status.h
LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG4
Definition: lldb-defines.h:62
lldb_private::Value::SetBytes
void SetBytes(const void *bytes, int len)
Definition: Value.cpp:87
ehframe_r5
@ ehframe_r5
Definition: ARM_ehframe_Registers.h:22
dwarf_s25
@ dwarf_s25
Definition: ARM_DWARF_Registers.h:58
lldb_private
A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
lldb::eFormatHex
@ eFormatHex
Definition: lldb-enumerations.h:170
ABISysV_arm::IsArmHardFloat
bool IsArmHardFloat(lldb_private::Thread &thread) const
Definition: ABISysV_arm.cpp:1424
LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:53
dwarf_s24
@ dwarf_s24
Definition: ARM_DWARF_Registers.h:57
dwarf_s2
@ dwarf_s2
Definition: ARM_DWARF_Registers.h:35
dwarf_r3
@ dwarf_r3
Definition: ABISysV_mips.cpp:42
ABISysV_arm::GetRedZoneSize
size_t GetRedZoneSize() const override
Definition: ABISysV_arm.cpp:1200
LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:51
ABISysV_arm::GetArgumentValues
bool GetArgumentValues(lldb_private::Thread &thread, lldb_private::ValueList &values) const override
Definition: ABISysV_arm.cpp:1326
ConstString.h
ABISysV_arm
Definition: ABISysV_arm.h:15
lldb_private::RegisterValue::SignExtend
bool SignExtend(uint32_t sign_bitpos)
Definition: RegisterValue.cpp:452
dwarf_d28
@ dwarf_d28
Definition: ARM_DWARF_Registers.h:183
dwarf_r14_fiq
@ dwarf_r14_fiq
Definition: ARM_DWARF_Registers.h:134
LLDB_PLUGIN_DEFINE
#define LLDB_PLUGIN_DEFINE(PluginName)
Definition: PluginManager.h:31
lldb_private::CompilerType::GetFieldAtIndex
CompilerType GetFieldAtIndex(size_t idx, std::string &name, uint64_t *bit_offset_ptr, uint32_t *bitfield_bit_size_ptr, bool *is_bitfield_ptr) const
Definition: CompilerType.cpp:611
dwarf_s23
@ dwarf_s23
Definition: ARM_DWARF_Registers.h:56
dwarf_r14_abt
@ dwarf_r14_abt
Definition: ARM_DWARF_Registers.h:138
lldb_private::Thread::GetStackFrameAtIndex
virtual lldb::StackFrameSP GetStackFrameAtIndex(uint32_t idx)
Definition: Thread.h:399
dwarf_r6
@ dwarf_r6
Definition: ABISysV_mips.cpp:45
ehframe_r6
@ ehframe_r6
Definition: ARM_ehframe_Registers.h:23
lldb_private::Thread::GetRegisterContext
virtual lldb::RegisterContextSP GetRegisterContext()=0
dwarf_r13_usr
@ dwarf_r13_usr
Definition: ARM_DWARF_Registers.h:126
ABISysV_arm::PrepareTrivialCall
bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp, lldb::addr_t func_addr, lldb::addr_t returnAddress, llvm::ArrayRef< lldb::addr_t > args) const override
Definition: ABISysV_arm.cpp:1220
lldb::eFormatFloat
@ eFormatFloat
Definition: lldb-enumerations.h:172
lldb_private::DataBufferHeap
Definition: DataBufferHeap.h:30
dwarf_d3
@ dwarf_d3
Definition: ARM_DWARF_Registers.h:158
dwarf_s30
@ dwarf_s30
Definition: ARM_DWARF_Registers.h:63
dwarf_r13_und
@ dwarf_r13_und
Definition: ARM_DWARF_Registers.h:139
lldb_private::UnwindPlan
Definition: UnwindPlan.h:53
lldb
Definition: SBAddress.h:15
RegisterContext.h
Value.h
lldb_private::RegisterValue::GetScalarValue
bool GetScalarValue(Scalar &scalar) const
Definition: RegisterValue.cpp:126
dwarf_s11
@ dwarf_s11
Definition: ARM_DWARF_Registers.h:44
ABISysV_arm::Initialize
static void Initialize()
Definition: ABISysV_arm.cpp:2021
dwarf_d18
@ dwarf_d18
Definition: ARM_DWARF_Registers.h:173
lldb_private::RegisterContext::GetRegisterInfoByName
const RegisterInfo * GetRegisterInfoByName(llvm::StringRef reg_name, uint32_t start_idx=0)
Definition: RegisterContext.cpp:52
MASK_CPSR_IT_MASK
#define MASK_CPSR_IT_MASK
Definition: ARMDefines.h:175
dwarf_d21
@ dwarf_d21
Definition: ARM_DWARF_Registers.h:176
lldb::ByteOrder
ByteOrder
Byte ordering definitions.
Definition: lldb-enumerations.h:139
lldb_private::Status::AsCString
const char * AsCString(const char *default_error_str="unknown error") const
Get the error string associated with the current error.
Definition: Status.cpp:130
LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:54
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