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ABISysV_arm.cpp
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1 //===-- ABISysV_arm.cpp -----------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ABISysV_arm.h"
10 
11 #include <vector>
12 
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/Triple.h"
15 
16 #include "lldb/Core/Module.h"
17 #include "lldb/Core/PluginManager.h"
18 #include "lldb/Core/Value.h"
19 #include "lldb/Core/ValueObjectConstResult.h"
20 #include "lldb/Symbol/UnwindPlan.h"
21 #include "lldb/Target/Process.h"
22 #include "lldb/Target/RegisterContext.h"
23 #include "lldb/Target/Target.h"
24 #include "lldb/Target/Thread.h"
25 #include "lldb/Utility/ConstString.h"
26 #include "lldb/Utility/RegisterValue.h"
27 #include "lldb/Utility/Scalar.h"
28 #include "lldb/Utility/Status.h"
29 
30 #include "Plugins/Process/Utility/ARMDefines.h"
31 #include "Utility/ARM_DWARF_Registers.h"
32 #include "Utility/ARM_ehframe_Registers.h"
33 
34 using namespace lldb;
35 using namespace lldb_private;
36 
37 static RegisterInfo g_register_infos[] = {
38  // NAME ALT SZ OFF ENCODING FORMAT EH_FRAME
39  // DWARF GENERIC PROCESS PLUGIN
40  // LLDB NATIVE VALUE REGS INVALIDATE REGS
41  // ========== ======= == === ============= ============
42  // ======================= =================== ===========================
43  // ======================= ====================== ==========
44  // ===============
45  {"r0",
46  "arg1",
47  4,
48  0,
49  eEncodingUint,
50  eFormatHex,
51  {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM,
52  LLDB_INVALID_REGNUM},
53  nullptr,
54  nullptr,
55  nullptr,
56  0},
57  {"r1",
58  "arg2",
59  4,
60  0,
61  eEncodingUint,
62  eFormatHex,
63  {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM,
64  LLDB_INVALID_REGNUM},
65  nullptr,
66  nullptr,
67  nullptr,
68  0},
69  {"r2",
70  "arg3",
71  4,
72  0,
73  eEncodingUint,
74  eFormatHex,
75  {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM,
76  LLDB_INVALID_REGNUM},
77  nullptr,
78  nullptr,
79  nullptr,
80  0},
81  {"r3",
82  "arg4",
83  4,
84  0,
85  eEncodingUint,
86  eFormatHex,
87  {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM,
88  LLDB_INVALID_REGNUM},
89  nullptr,
90  nullptr,
91  nullptr,
92  0},
93  {"r4",
94  nullptr,
95  4,
96  0,
97  eEncodingUint,
98  eFormatHex,
99  {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
100  LLDB_INVALID_REGNUM},
101  nullptr,
102  nullptr,
103  nullptr,
104  0},
105  {"r5",
106  nullptr,
107  4,
108  0,
109  eEncodingUint,
110  eFormatHex,
111  {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
112  LLDB_INVALID_REGNUM},
113  nullptr,
114  nullptr,
115  nullptr,
116  0},
117  {"r6",
118  nullptr,
119  4,
120  0,
121  eEncodingUint,
122  eFormatHex,
123  {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
124  LLDB_INVALID_REGNUM},
125  nullptr,
126  nullptr,
127  nullptr,
128  0},
129  {"r7",
130  nullptr,
131  4,
132  0,
133  eEncodingUint,
134  eFormatHex,
135  {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM,
136  LLDB_INVALID_REGNUM},
137  nullptr,
138  nullptr,
139  nullptr,
140  0},
141  {"r8",
142  nullptr,
143  4,
144  0,
145  eEncodingUint,
146  eFormatHex,
147  {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
148  LLDB_INVALID_REGNUM},
149  nullptr,
150  nullptr,
151  nullptr,
152  0},
153  {"r9",
154  nullptr,
155  4,
156  0,
157  eEncodingUint,
158  eFormatHex,
159  {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
160  LLDB_INVALID_REGNUM},
161  nullptr,
162  nullptr,
163  nullptr,
164  0},
165  {"r10",
166  nullptr,
167  4,
168  0,
169  eEncodingUint,
170  eFormatHex,
171  {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
172  LLDB_INVALID_REGNUM},
173  nullptr,
174  nullptr,
175  nullptr,
176  0},
177  {"r11",
178  nullptr,
179  4,
180  0,
181  eEncodingUint,
182  eFormatHex,
183  {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
184  LLDB_INVALID_REGNUM},
185  nullptr,
186  nullptr,
187  nullptr,
188  0},
189  {"r12",
190  nullptr,
191  4,
192  0,
193  eEncodingUint,
194  eFormatHex,
195  {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
196  LLDB_INVALID_REGNUM},
197  nullptr,
198  nullptr,
199  nullptr,
200  0},
201  {"sp",
202  "r13",
203  4,
204  0,
205  eEncodingUint,
206  eFormatHex,
207  {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM,
208  LLDB_INVALID_REGNUM},
209  nullptr,
210  nullptr,
211  nullptr,
212  0},
213  {"lr",
214  "r14",
215  4,
216  0,
217  eEncodingUint,
218  eFormatHex,
219  {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM,
220  LLDB_INVALID_REGNUM},
221  nullptr,
222  nullptr,
223  nullptr,
224  0},
225  {"pc",
226  "r15",
227  4,
228  0,
229  eEncodingUint,
230  eFormatHex,
231  {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM,
232  LLDB_INVALID_REGNUM},
233  nullptr,
234  nullptr,
235  nullptr,
236  0},
237  {"cpsr",
238  "psr",
239  4,
240  0,
241  eEncodingUint,
242  eFormatHex,
243  {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM,
244  LLDB_INVALID_REGNUM},
245  nullptr,
246  nullptr,
247  nullptr,
248  0},
249  {"s0",
250  nullptr,
251  4,
252  0,
253  eEncodingIEEE754,
254  eFormatFloat,
255  {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
256  LLDB_INVALID_REGNUM},
257  nullptr,
258  nullptr,
259  nullptr,
260  0},
261  {"s1",
262  nullptr,
263  4,
264  0,
265  eEncodingIEEE754,
266  eFormatFloat,
267  {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
268  LLDB_INVALID_REGNUM},
269  nullptr,
270  nullptr,
271  nullptr,
272  0},
273  {"s2",
274  nullptr,
275  4,
276  0,
277  eEncodingIEEE754,
278  eFormatFloat,
279  {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
280  LLDB_INVALID_REGNUM},
281  nullptr,
282  nullptr,
283  nullptr,
284  0},
285  {"s3",
286  nullptr,
287  4,
288  0,
289  eEncodingIEEE754,
290  eFormatFloat,
291  {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
292  LLDB_INVALID_REGNUM},
293  nullptr,
294  nullptr,
295  nullptr,
296  0},
297  {"s4",
298  nullptr,
299  4,
300  0,
301  eEncodingIEEE754,
302  eFormatFloat,
303  {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
304  LLDB_INVALID_REGNUM},
305  nullptr,
306  nullptr,
307  nullptr,
308  0},
309  {"s5",
310  nullptr,
311  4,
312  0,
313  eEncodingIEEE754,
314  eFormatFloat,
315  {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
316  LLDB_INVALID_REGNUM},
317  nullptr,
318  nullptr,
319  nullptr,
320  0},
321  {"s6",
322  nullptr,
323  4,
324  0,
325  eEncodingIEEE754,
326  eFormatFloat,
327  {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
328  LLDB_INVALID_REGNUM},
329  nullptr,
330  nullptr,
331  nullptr,
332  0},
333  {"s7",
334  nullptr,
335  4,
336  0,
337  eEncodingIEEE754,
338  eFormatFloat,
339  {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
340  LLDB_INVALID_REGNUM},
341  nullptr,
342  nullptr,
343  nullptr,
344  0},
345  {"s8",
346  nullptr,
347  4,
348  0,
349  eEncodingIEEE754,
350  eFormatFloat,
351  {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
352  LLDB_INVALID_REGNUM},
353  nullptr,
354  nullptr,
355  nullptr,
356  0},
357  {"s9",
358  nullptr,
359  4,
360  0,
361  eEncodingIEEE754,
362  eFormatFloat,
363  {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
364  LLDB_INVALID_REGNUM},
365  nullptr,
366  nullptr,
367  nullptr,
368  0},
369  {"s10",
370  nullptr,
371  4,
372  0,
373  eEncodingIEEE754,
374  eFormatFloat,
375  {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
376  LLDB_INVALID_REGNUM},
377  nullptr,
378  nullptr,
379  nullptr,
380  0},
381  {"s11",
382  nullptr,
383  4,
384  0,
385  eEncodingIEEE754,
386  eFormatFloat,
387  {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
388  LLDB_INVALID_REGNUM},
389  nullptr,
390  nullptr,
391  nullptr,
392  0},
393  {"s12",
394  nullptr,
395  4,
396  0,
397  eEncodingIEEE754,
398  eFormatFloat,
399  {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
400  LLDB_INVALID_REGNUM},
401  nullptr,
402  nullptr,
403  nullptr,
404  0},
405  {"s13",
406  nullptr,
407  4,
408  0,
409  eEncodingIEEE754,
410  eFormatFloat,
411  {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
412  LLDB_INVALID_REGNUM},
413  nullptr,
414  nullptr,
415  nullptr,
416  0},
417  {"s14",
418  nullptr,
419  4,
420  0,
421  eEncodingIEEE754,
422  eFormatFloat,
423  {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
424  LLDB_INVALID_REGNUM},
425  nullptr,
426  nullptr,
427  nullptr,
428  0},
429  {"s15",
430  nullptr,
431  4,
432  0,
433  eEncodingIEEE754,
434  eFormatFloat,
435  {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
436  LLDB_INVALID_REGNUM},
437  nullptr,
438  nullptr,
439  nullptr,
440  0},
441  {"s16",
442  nullptr,
443  4,
444  0,
445  eEncodingIEEE754,
446  eFormatFloat,
447  {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
448  LLDB_INVALID_REGNUM},
449  nullptr,
450  nullptr,
451  nullptr,
452  0},
453  {"s17",
454  nullptr,
455  4,
456  0,
457  eEncodingIEEE754,
458  eFormatFloat,
459  {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
460  LLDB_INVALID_REGNUM},
461  nullptr,
462  nullptr,
463  nullptr,
464  0},
465  {"s18",
466  nullptr,
467  4,
468  0,
469  eEncodingIEEE754,
470  eFormatFloat,
471  {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
472  LLDB_INVALID_REGNUM},
473  nullptr,
474  nullptr,
475  nullptr,
476  0},
477  {"s19",
478  nullptr,
479  4,
480  0,
481  eEncodingIEEE754,
482  eFormatFloat,
483  {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
484  LLDB_INVALID_REGNUM},
485  nullptr,
486  nullptr,
487  nullptr,
488  0},
489  {"s20",
490  nullptr,
491  4,
492  0,
493  eEncodingIEEE754,
494  eFormatFloat,
495  {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
496  LLDB_INVALID_REGNUM},
497  nullptr,
498  nullptr,
499  nullptr,
500  0},
501  {"s21",
502  nullptr,
503  4,
504  0,
505  eEncodingIEEE754,
506  eFormatFloat,
507  {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
508  LLDB_INVALID_REGNUM},
509  nullptr,
510  nullptr,
511  nullptr,
512  0},
513  {"s22",
514  nullptr,
515  4,
516  0,
517  eEncodingIEEE754,
518  eFormatFloat,
519  {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
520  LLDB_INVALID_REGNUM},
521  nullptr,
522  nullptr,
523  nullptr,
524  0},
525  {"s23",
526  nullptr,
527  4,
528  0,
529  eEncodingIEEE754,
530  eFormatFloat,
531  {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
532  LLDB_INVALID_REGNUM},
533  nullptr,
534  nullptr,
535  nullptr,
536  0},
537  {"s24",
538  nullptr,
539  4,
540  0,
541  eEncodingIEEE754,
542  eFormatFloat,
543  {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
544  LLDB_INVALID_REGNUM},
545  nullptr,
546  nullptr,
547  nullptr,
548  0},
549  {"s25",
550  nullptr,
551  4,
552  0,
553  eEncodingIEEE754,
554  eFormatFloat,
555  {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
556  LLDB_INVALID_REGNUM},
557  nullptr,
558  nullptr,
559  nullptr,
560  0},
561  {"s26",
562  nullptr,
563  4,
564  0,
565  eEncodingIEEE754,
566  eFormatFloat,
567  {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
568  LLDB_INVALID_REGNUM},
569  nullptr,
570  nullptr,
571  nullptr,
572  0},
573  {"s27",
574  nullptr,
575  4,
576  0,
577  eEncodingIEEE754,
578  eFormatFloat,
579  {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
580  LLDB_INVALID_REGNUM},
581  nullptr,
582  nullptr,
583  nullptr,
584  0},
585  {"s28",
586  nullptr,
587  4,
588  0,
589  eEncodingIEEE754,
590  eFormatFloat,
591  {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
592  LLDB_INVALID_REGNUM},
593  nullptr,
594  nullptr,
595  nullptr,
596  0},
597  {"s29",
598  nullptr,
599  4,
600  0,
601  eEncodingIEEE754,
602  eFormatFloat,
603  {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
604  LLDB_INVALID_REGNUM},
605  nullptr,
606  nullptr,
607  nullptr,
608  0},
609  {"s30",
610  nullptr,
611  4,
612  0,
613  eEncodingIEEE754,
614  eFormatFloat,
615  {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
616  LLDB_INVALID_REGNUM},
617  nullptr,
618  nullptr,
619  nullptr,
620  0},
621  {"s31",
622  nullptr,
623  4,
624  0,
625  eEncodingIEEE754,
626  eFormatFloat,
627  {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
628  LLDB_INVALID_REGNUM},
629  nullptr,
630  nullptr,
631  nullptr,
632  0},
633  {"fpscr",
634  nullptr,
635  4,
636  0,
637  eEncodingUint,
638  eFormatHex,
639  {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
640  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
641  nullptr,
642  nullptr,
643  nullptr,
644  0},
645  {"d0",
646  nullptr,
647  8,
648  0,
649  eEncodingIEEE754,
650  eFormatFloat,
651  {LLDB_INVALID_REGNUM, dwarf_d0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
652  LLDB_INVALID_REGNUM},
653  nullptr,
654  nullptr,
655  nullptr,
656  0},
657  {"d1",
658  nullptr,
659  8,
660  0,
661  eEncodingIEEE754,
662  eFormatFloat,
663  {LLDB_INVALID_REGNUM, dwarf_d1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
664  LLDB_INVALID_REGNUM},
665  nullptr,
666  nullptr,
667  nullptr,
668  0},
669  {"d2",
670  nullptr,
671  8,
672  0,
673  eEncodingIEEE754,
674  eFormatFloat,
675  {LLDB_INVALID_REGNUM, dwarf_d2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
676  LLDB_INVALID_REGNUM},
677  nullptr,
678  nullptr,
679  nullptr,
680  0},
681  {"d3",
682  nullptr,
683  8,
684  0,
685  eEncodingIEEE754,
686  eFormatFloat,
687  {LLDB_INVALID_REGNUM, dwarf_d3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
688  LLDB_INVALID_REGNUM},
689  nullptr,
690  nullptr,
691  nullptr,
692  0},
693  {"d4",
694  nullptr,
695  8,
696  0,
697  eEncodingIEEE754,
698  eFormatFloat,
699  {LLDB_INVALID_REGNUM, dwarf_d4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
700  LLDB_INVALID_REGNUM},
701  nullptr,
702  nullptr,
703  nullptr,
704  0},
705  {"d5",
706  nullptr,
707  8,
708  0,
709  eEncodingIEEE754,
710  eFormatFloat,
711  {LLDB_INVALID_REGNUM, dwarf_d5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
712  LLDB_INVALID_REGNUM},
713  nullptr,
714  nullptr,
715  nullptr,
716  0},
717  {"d6",
718  nullptr,
719  8,
720  0,
721  eEncodingIEEE754,
722  eFormatFloat,
723  {LLDB_INVALID_REGNUM, dwarf_d6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
724  LLDB_INVALID_REGNUM},
725  nullptr,
726  nullptr,
727  nullptr,
728  0},
729  {"d7",
730  nullptr,
731  8,
732  0,
733  eEncodingIEEE754,
734  eFormatFloat,
735  {LLDB_INVALID_REGNUM, dwarf_d7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
736  LLDB_INVALID_REGNUM},
737  nullptr,
738  nullptr,
739  nullptr,
740  0},
741  {"d8",
742  nullptr,
743  8,
744  0,
745  eEncodingIEEE754,
746  eFormatFloat,
747  {LLDB_INVALID_REGNUM, dwarf_d8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
748  LLDB_INVALID_REGNUM},
749  nullptr,
750  nullptr,
751  nullptr,
752  0},
753  {"d9",
754  nullptr,
755  8,
756  0,
757  eEncodingIEEE754,
758  eFormatFloat,
759  {LLDB_INVALID_REGNUM, dwarf_d9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
760  LLDB_INVALID_REGNUM},
761  nullptr,
762  nullptr,
763  nullptr,
764  0},
765  {"d10",
766  nullptr,
767  8,
768  0,
769  eEncodingIEEE754,
770  eFormatFloat,
771  {LLDB_INVALID_REGNUM, dwarf_d10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
772  LLDB_INVALID_REGNUM},
773  nullptr,
774  nullptr,
775  nullptr,
776  0},
777  {"d11",
778  nullptr,
779  8,
780  0,
781  eEncodingIEEE754,
782  eFormatFloat,
783  {LLDB_INVALID_REGNUM, dwarf_d11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
784  LLDB_INVALID_REGNUM},
785  nullptr,
786  nullptr,
787  nullptr,
788  0},
789  {"d12",
790  nullptr,
791  8,
792  0,
793  eEncodingIEEE754,
794  eFormatFloat,
795  {LLDB_INVALID_REGNUM, dwarf_d12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
796  LLDB_INVALID_REGNUM},
797  nullptr,
798  nullptr,
799  nullptr,
800  0},
801  {"d13",
802  nullptr,
803  8,
804  0,
805  eEncodingIEEE754,
806  eFormatFloat,
807  {LLDB_INVALID_REGNUM, dwarf_d13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
808  LLDB_INVALID_REGNUM},
809  nullptr,
810  nullptr,
811  nullptr,
812  0},
813  {"d14",
814  nullptr,
815  8,
816  0,
817  eEncodingIEEE754,
818  eFormatFloat,
819  {LLDB_INVALID_REGNUM, dwarf_d14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
820  LLDB_INVALID_REGNUM},
821  nullptr,
822  nullptr,
823  nullptr,
824  0},
825  {"d15",
826  nullptr,
827  8,
828  0,
829  eEncodingIEEE754,
830  eFormatFloat,
831  {LLDB_INVALID_REGNUM, dwarf_d15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
832  LLDB_INVALID_REGNUM},
833  nullptr,
834  nullptr,
835  nullptr,
836  0},
837  {"d16",
838  nullptr,
839  8,
840  0,
841  eEncodingIEEE754,
842  eFormatFloat,
843  {LLDB_INVALID_REGNUM, dwarf_d16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
844  LLDB_INVALID_REGNUM},
845  nullptr,
846  nullptr,
847  nullptr,
848  0},
849  {"d17",
850  nullptr,
851  8,
852  0,
853  eEncodingIEEE754,
854  eFormatFloat,
855  {LLDB_INVALID_REGNUM, dwarf_d17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
856  LLDB_INVALID_REGNUM},
857  nullptr,
858  nullptr,
859  nullptr,
860  0},
861  {"d18",
862  nullptr,
863  8,
864  0,
865  eEncodingIEEE754,
866  eFormatFloat,
867  {LLDB_INVALID_REGNUM, dwarf_d18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
868  LLDB_INVALID_REGNUM},
869  nullptr,
870  nullptr,
871  nullptr,
872  0},
873  {"d19",
874  nullptr,
875  8,
876  0,
877  eEncodingIEEE754,
878  eFormatFloat,
879  {LLDB_INVALID_REGNUM, dwarf_d19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
880  LLDB_INVALID_REGNUM},
881  nullptr,
882  nullptr,
883  nullptr,
884  0},
885  {"d20",
886  nullptr,
887  8,
888  0,
889  eEncodingIEEE754,
890  eFormatFloat,
891  {LLDB_INVALID_REGNUM, dwarf_d20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
892  LLDB_INVALID_REGNUM},
893  nullptr,
894  nullptr,
895  nullptr,
896  0},
897  {"d21",
898  nullptr,
899  8,
900  0,
901  eEncodingIEEE754,
902  eFormatFloat,
903  {LLDB_INVALID_REGNUM, dwarf_d21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
904  LLDB_INVALID_REGNUM},
905  nullptr,
906  nullptr,
907  nullptr,
908  0},
909  {"d22",
910  nullptr,
911  8,
912  0,
913  eEncodingIEEE754,
914  eFormatFloat,
915  {LLDB_INVALID_REGNUM, dwarf_d22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
916  LLDB_INVALID_REGNUM},
917  nullptr,
918  nullptr,
919  nullptr,
920  0},
921  {"d23",
922  nullptr,
923  8,
924  0,
925  eEncodingIEEE754,
926  eFormatFloat,
927  {LLDB_INVALID_REGNUM, dwarf_d23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
928  LLDB_INVALID_REGNUM},
929  nullptr,
930  nullptr,
931  nullptr,
932  0},
933  {"d24",
934  nullptr,
935  8,
936  0,
937  eEncodingIEEE754,
938  eFormatFloat,
939  {LLDB_INVALID_REGNUM, dwarf_d24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
940  LLDB_INVALID_REGNUM},
941  nullptr,
942  nullptr,
943  nullptr,
944  0},
945  {"d25",
946  nullptr,
947  8,
948  0,
949  eEncodingIEEE754,
950  eFormatFloat,
951  {LLDB_INVALID_REGNUM, dwarf_d25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
952  LLDB_INVALID_REGNUM},
953  nullptr,
954  nullptr,
955  nullptr,
956  0},
957  {"d26",
958  nullptr,
959  8,
960  0,
961  eEncodingIEEE754,
962  eFormatFloat,
963  {LLDB_INVALID_REGNUM, dwarf_d26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
964  LLDB_INVALID_REGNUM},
965  nullptr,
966  nullptr,
967  nullptr,
968  0},
969  {"d27",
970  nullptr,
971  8,
972  0,
973  eEncodingIEEE754,
974  eFormatFloat,
975  {LLDB_INVALID_REGNUM, dwarf_d27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
976  LLDB_INVALID_REGNUM},
977  nullptr,
978  nullptr,
979  nullptr,
980  0},
981  {"d28",
982  nullptr,
983  8,
984  0,
985  eEncodingIEEE754,
986  eFormatFloat,
987  {LLDB_INVALID_REGNUM, dwarf_d28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
988  LLDB_INVALID_REGNUM},
989  nullptr,
990  nullptr,
991  nullptr,
992  0},
993  {"d29",
994  nullptr,
995  8,
996  0,
997  eEncodingIEEE754,
998  eFormatFloat,
999  {LLDB_INVALID_REGNUM, dwarf_d29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1000  LLDB_INVALID_REGNUM},
1001  nullptr,
1002  nullptr,
1003  nullptr,
1004  0},
1005  {"d30",
1006  nullptr,
1007  8,
1008  0,
1009  eEncodingIEEE754,
1010  eFormatFloat,
1011  {LLDB_INVALID_REGNUM, dwarf_d30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1012  LLDB_INVALID_REGNUM},
1013  nullptr,
1014  nullptr,
1015  nullptr,
1016  0},
1017  {"d31",
1018  nullptr,
1019  8,
1020  0,
1021  eEncodingIEEE754,
1022  eFormatFloat,
1023  {LLDB_INVALID_REGNUM, dwarf_d31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1024  LLDB_INVALID_REGNUM},
1025  nullptr,
1026  nullptr,
1027  nullptr,
1028  0},
1029  {"r8_usr",
1030  nullptr,
1031  4,
1032  0,
1033  eEncodingUint,
1034  eFormatHex,
1035  {LLDB_INVALID_REGNUM, dwarf_r8_usr, LLDB_INVALID_REGNUM,
1036  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1037  nullptr,
1038  nullptr,
1039  nullptr,
1040  0},
1041  {"r9_usr",
1042  nullptr,
1043  4,
1044  0,
1045  eEncodingUint,
1046  eFormatHex,
1047  {LLDB_INVALID_REGNUM, dwarf_r9_usr, LLDB_INVALID_REGNUM,
1048  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1049  nullptr,
1050  nullptr,
1051  nullptr,
1052  0},
1053  {"r10_usr",
1054  nullptr,
1055  4,
1056  0,
1057  eEncodingUint,
1058  eFormatHex,
1059  {LLDB_INVALID_REGNUM, dwarf_r10_usr, LLDB_INVALID_REGNUM,
1060  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1061  nullptr,
1062  nullptr,
1063  nullptr,
1064  0},
1065  {"r11_usr",
1066  nullptr,
1067  4,
1068  0,
1069  eEncodingUint,
1070  eFormatHex,
1071  {LLDB_INVALID_REGNUM, dwarf_r11_usr, LLDB_INVALID_REGNUM,
1072  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1073  nullptr,
1074  nullptr,
1075  nullptr,
1076  0},
1077  {"r12_usr",
1078  nullptr,
1079  4,
1080  0,
1081  eEncodingUint,
1082  eFormatHex,
1083  {LLDB_INVALID_REGNUM, dwarf_r12_usr, LLDB_INVALID_REGNUM,
1084  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1085  nullptr,
1086  nullptr,
1087  nullptr,
1088  0},
1089  {"r13_usr",
1090  "sp_usr",
1091  4,
1092  0,
1093  eEncodingUint,
1094  eFormatHex,
1095  {LLDB_INVALID_REGNUM, dwarf_r13_usr, LLDB_INVALID_REGNUM,
1096  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1097  nullptr,
1098  nullptr,
1099  nullptr,
1100  0},
1101  {"r14_usr",
1102  "lr_usr",
1103  4,
1104  0,
1105  eEncodingUint,
1106  eFormatHex,
1107  {LLDB_INVALID_REGNUM, dwarf_r14_usr, LLDB_INVALID_REGNUM,
1108  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1109  nullptr,
1110  nullptr,
1111  nullptr,
1112  0},
1113  {"r8_fiq",
1114  nullptr,
1115  4,
1116  0,
1117  eEncodingUint,
1118  eFormatHex,
1119  {LLDB_INVALID_REGNUM, dwarf_r8_fiq, LLDB_INVALID_REGNUM,
1120  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1121  nullptr,
1122  nullptr,
1123  nullptr,
1124  0},
1125  {"r9_fiq",
1126  nullptr,
1127  4,
1128  0,
1129  eEncodingUint,
1130  eFormatHex,
1131  {LLDB_INVALID_REGNUM, dwarf_r9_fiq, LLDB_INVALID_REGNUM,
1132  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1133  nullptr,
1134  nullptr,
1135  nullptr,
1136  0},
1137  {"r10_fiq",
1138  nullptr,
1139  4,
1140  0,
1141  eEncodingUint,
1142  eFormatHex,
1143  {LLDB_INVALID_REGNUM, dwarf_r10_fiq, LLDB_INVALID_REGNUM,
1144  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1145  nullptr,
1146  nullptr,
1147  nullptr,
1148  0},
1149  {"r11_fiq",
1150  nullptr,
1151  4,
1152  0,
1153  eEncodingUint,
1154  eFormatHex,
1155  {LLDB_INVALID_REGNUM, dwarf_r11_fiq, LLDB_INVALID_REGNUM,
1156  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1157  nullptr,
1158  nullptr,
1159  nullptr,
1160  0},
1161  {"r12_fiq",
1162  nullptr,
1163  4,
1164  0,
1165  eEncodingUint,
1166  eFormatHex,
1167  {LLDB_INVALID_REGNUM, dwarf_r12_fiq, LLDB_INVALID_REGNUM,
1168  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1169  nullptr,
1170  nullptr,
1171  nullptr,
1172  0},
1173  {"r13_fiq",
1174  "sp_fiq",
1175  4,
1176  0,
1177  eEncodingUint,
1178  eFormatHex,
1179  {LLDB_INVALID_REGNUM, dwarf_r13_fiq, LLDB_INVALID_REGNUM,
1180  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1181  nullptr,
1182  nullptr,
1183  nullptr,
1184  0},
1185  {"r14_fiq",
1186  "lr_fiq",
1187  4,
1188  0,
1189  eEncodingUint,
1190  eFormatHex,
1191  {LLDB_INVALID_REGNUM, dwarf_r14_fiq, LLDB_INVALID_REGNUM,
1192  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1193  nullptr,
1194  nullptr,
1195  nullptr,
1196  0},
1197  {"r13_irq",
1198  "sp_irq",
1199  4,
1200  0,
1201  eEncodingUint,
1202  eFormatHex,
1203  {LLDB_INVALID_REGNUM, dwarf_r13_irq, LLDB_INVALID_REGNUM,
1204  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1205  nullptr,
1206  nullptr,
1207  nullptr,
1208  0},
1209  {"r14_irq",
1210  "lr_irq",
1211  4,
1212  0,
1213  eEncodingUint,
1214  eFormatHex,
1215  {LLDB_INVALID_REGNUM, dwarf_r14_irq, LLDB_INVALID_REGNUM,
1216  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1217  nullptr,
1218  nullptr,
1219  nullptr,
1220  0},
1221  {"r13_abt",
1222  "sp_abt",
1223  4,
1224  0,
1225  eEncodingUint,
1226  eFormatHex,
1227  {LLDB_INVALID_REGNUM, dwarf_r13_abt, LLDB_INVALID_REGNUM,
1228  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1229  nullptr,
1230  nullptr,
1231  nullptr,
1232  0},
1233  {"r14_abt",
1234  "lr_abt",
1235  4,
1236  0,
1237  eEncodingUint,
1238  eFormatHex,
1239  {LLDB_INVALID_REGNUM, dwarf_r14_abt, LLDB_INVALID_REGNUM,
1240  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1241  nullptr,
1242  nullptr,
1243  nullptr,
1244  0},
1245  {"r13_und",
1246  "sp_und",
1247  4,
1248  0,
1249  eEncodingUint,
1250  eFormatHex,
1251  {LLDB_INVALID_REGNUM, dwarf_r13_und, LLDB_INVALID_REGNUM,
1252  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1253  nullptr,
1254  nullptr,
1255  nullptr,
1256  0},
1257  {"r14_und",
1258  "lr_und",
1259  4,
1260  0,
1261  eEncodingUint,
1262  eFormatHex,
1263  {LLDB_INVALID_REGNUM, dwarf_r14_und, LLDB_INVALID_REGNUM,
1264  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1265  nullptr,
1266  nullptr,
1267  nullptr,
1268  0},
1269  {"r13_svc",
1270  "sp_svc",
1271  4,
1272  0,
1273  eEncodingUint,
1274  eFormatHex,
1275  {LLDB_INVALID_REGNUM, dwarf_r13_svc, LLDB_INVALID_REGNUM,
1276  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1277  nullptr,
1278  nullptr,
1279  nullptr,
1280  0},
1281  {"r14_svc",
1282  "lr_svc",
1283  4,
1284  0,
1285  eEncodingUint,
1286  eFormatHex,
1287  {LLDB_INVALID_REGNUM, dwarf_r14_svc, LLDB_INVALID_REGNUM,
1288  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
1289  nullptr,
1290  nullptr,
1291  nullptr,
1292  0}};
1293 
1294 static const uint32_t k_num_register_infos =
1295  llvm::array_lengthof(g_register_infos);
1296 static bool g_register_info_names_constified = false;
1297 
1298 const lldb_private::RegisterInfo *
1299 ABISysV_arm::GetRegisterInfoArray(uint32_t &count) {
1300  // Make the C-string names and alt_names for the register infos into const
1301  // C-string values by having the ConstString unique the names in the global
1302  // constant C-string pool.
1303  if (!g_register_info_names_constified) {
1304  g_register_info_names_constified = true;
1305  for (uint32_t i = 0; i < k_num_register_infos; ++i) {
1306  if (g_register_infos[i].name)
1307  g_register_infos[i].name =
1308  ConstString(g_register_infos[i].name).GetCString();
1309  if (g_register_infos[i].alt_name)
1310  g_register_infos[i].alt_name =
1311  ConstString(g_register_infos[i].alt_name).GetCString();
1312  }
1313  }
1314  count = k_num_register_infos;
1315  return g_register_infos;
1316 }
1317 
1318 size_t ABISysV_arm::GetRedZoneSize() const { return 0; }
1319 
1320 // Static Functions
1321 
1322 ABISP
1323 ABISysV_arm::CreateInstance(lldb::ProcessSP process_sp, const ArchSpec &arch) {
1324  const llvm::Triple::ArchType arch_type = arch.GetTriple().getArch();
1325  const llvm::Triple::VendorType vendor_type = arch.GetTriple().getVendor();
1326 
1327  if (vendor_type != llvm::Triple::Apple) {
1328  if ((arch_type == llvm::Triple::arm) ||
1329  (arch_type == llvm::Triple::thumb)) {
1330  return ABISP(new ABISysV_arm(process_sp));
1331  }
1332  }
1333 
1334  return ABISP();
1335 }
1336 
1337 bool ABISysV_arm::PrepareTrivialCall(Thread &thread, addr_t sp,
1338  addr_t function_addr, addr_t return_addr,
1339  llvm::ArrayRef<addr_t> args) const {
1340  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1341  if (!reg_ctx)
1342  return false;
1343 
1344  const uint32_t pc_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1345  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
1346  const uint32_t sp_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1347  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
1348  const uint32_t ra_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1349  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
1350 
1351  RegisterValue reg_value;
1352 
1353  const uint8_t reg_names[] = {
1354  LLDB_REGNUM_GENERIC_ARG1, LLDB_REGNUM_GENERIC_ARG2,
1355  LLDB_REGNUM_GENERIC_ARG3, LLDB_REGNUM_GENERIC_ARG4};
1356 
1357  llvm::ArrayRef<addr_t>::iterator ai = args.begin(), ae = args.end();
1358 
1359  for (size_t i = 0; i < llvm::array_lengthof(reg_names); ++i) {
1360  if (ai == ae)
1361  break;
1362 
1363  reg_value.SetUInt32(*ai);
1364  if (!reg_ctx->WriteRegister(
1365  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, reg_names[i]),
1366  reg_value))
1367  return false;
1368 
1369  ++ai;
1370  }
1371 
1372  if (ai != ae) {
1373  // Spill onto the stack
1374  size_t num_stack_regs = ae - ai;
1375 
1376  sp -= (num_stack_regs * 4);
1377  // Keep the stack 8 byte aligned, not that we need to
1378  sp &= ~(8ull - 1ull);
1379 
1380  // just using arg1 to get the right size
1381  const RegisterInfo *reg_info = reg_ctx->GetRegisterInfo(
1382  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
1383 
1384  addr_t arg_pos = sp;
1385 
1386  for (; ai != ae; ++ai) {
1387  reg_value.SetUInt32(*ai);
1388  if (reg_ctx
1389  ->WriteRegisterValueToMemory(reg_info, arg_pos,
1390  reg_info->byte_size, reg_value)
1391  .Fail())
1392  return false;
1393  arg_pos += reg_info->byte_size;
1394  }
1395  }
1396 
1397  TargetSP target_sp(thread.CalculateTarget());
1398  Address so_addr;
1399 
1400  // Figure out if our return address is ARM or Thumb by using the
1401  // Address::GetCallableLoadAddress(Target*) which will figure out the ARM
1402  // thumb-ness and set the correct address bits for us.
1403  so_addr.SetLoadAddress(return_addr, target_sp.get());
1404  return_addr = so_addr.GetCallableLoadAddress(target_sp.get());
1405 
1406  // Set "lr" to the return address
1407  if (!reg_ctx->WriteRegisterFromUnsigned(ra_reg_num, return_addr))
1408  return false;
1409 
1410  // Set "sp" to the requested value
1411  if (!reg_ctx->WriteRegisterFromUnsigned(sp_reg_num, sp))
1412  return false;
1413 
1414  // If bit zero or 1 is set, this must be a thumb function, no need to figure
1415  // this out from the symbols.
1416  so_addr.SetLoadAddress(function_addr, target_sp.get());
1417  function_addr = so_addr.GetCallableLoadAddress(target_sp.get());
1418 
1419  const RegisterInfo *cpsr_reg_info =
1420  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS);
1421  const uint32_t curr_cpsr = reg_ctx->ReadRegisterAsUnsigned(cpsr_reg_info, 0);
1422 
1423  // Make a new CPSR and mask out any Thumb IT (if/then) bits
1424  uint32_t new_cpsr = curr_cpsr & ~MASK_CPSR_IT_MASK;
1425  // If bit zero or 1 is set, this must be thumb...
1426  if (function_addr & 1ull)
1427  new_cpsr |= MASK_CPSR_T; // Set T bit in CPSR
1428  else
1429  new_cpsr &= ~MASK_CPSR_T; // Clear T bit in CPSR
1430 
1431  if (new_cpsr != curr_cpsr) {
1432  if (!reg_ctx->WriteRegisterFromUnsigned(cpsr_reg_info, new_cpsr))
1433  return false;
1434  }
1435 
1436  function_addr &=
1437  ~1ull; // clear bit zero since the CPSR will take care of the mode for us
1438 
1439  // Set "pc" to the address requested
1440  return reg_ctx->WriteRegisterFromUnsigned(pc_reg_num, function_addr);
1441 }
1442 
1443 bool ABISysV_arm::GetArgumentValues(Thread &thread, ValueList &values) const {
1444  uint32_t num_values = values.GetSize();
1445 
1446  ExecutionContext exe_ctx(thread.shared_from_this());
1447  // For now, assume that the types in the AST values come from the Target's
1448  // scratch AST.
1449 
1450  // Extract the register context so we can read arguments from registers
1451 
1452  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1453 
1454  if (!reg_ctx)
1455  return false;
1456 
1457  addr_t sp = 0;
1458 
1459  for (uint32_t value_idx = 0; value_idx < num_values; ++value_idx) {
1460  // We currently only support extracting values with Clang QualTypes. Do we
1461  // care about others?
1462  Value *value = values.GetValueAtIndex(value_idx);
1463 
1464  if (!value)
1465  return false;
1466 
1467  CompilerType compiler_type = value->GetCompilerType();
1468  if (compiler_type) {
1469  bool is_signed = false;
1470  size_t bit_width = 0;
1471  if (compiler_type.IsIntegerOrEnumerationType(is_signed) ||
1472  compiler_type.IsPointerOrReferenceType()) {
1473  if (llvm::Optional<uint64_t> size = compiler_type.GetBitSize(&thread))
1474  bit_width = *size;
1475  } else {
1476  // We only handle integer, pointer and reference types currently...
1477  return false;
1478  }
1479 
1480  if (bit_width <= (exe_ctx.GetProcessRef().GetAddressByteSize() * 8)) {
1481  if (value_idx < 4) {
1482  // Arguments 1-4 are in r0-r3...
1483  const RegisterInfo *arg_reg_info = nullptr;
1484  arg_reg_info = reg_ctx->GetRegisterInfo(
1485  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1 + value_idx);
1486  if (arg_reg_info) {
1487  RegisterValue reg_value;
1488 
1489  if (reg_ctx->ReadRegister(arg_reg_info, reg_value)) {
1490  if (is_signed)
1491  reg_value.SignExtend(bit_width);
1492  if (!reg_value.GetScalarValue(value->GetScalar()))
1493  return false;
1494  continue;
1495  }
1496  }
1497  return false;
1498  } else {
1499  if (sp == 0) {
1500  // Read the stack pointer if it already hasn't been read
1501  sp = reg_ctx->GetSP(0);
1502  if (sp == 0)
1503  return false;
1504  }
1505 
1506  // Arguments 5 on up are on the stack
1507  const uint32_t arg_byte_size = (bit_width + (8 - 1)) / 8;
1508  Status error;
1509  if (!exe_ctx.GetProcessRef().ReadScalarIntegerFromMemory(
1510  sp, arg_byte_size, is_signed, value->GetScalar(), error))
1511  return false;
1512 
1513  sp += arg_byte_size;
1514  }
1515  }
1516  }
1517  }
1518  return true;
1519 }
1520 
1521 static bool GetReturnValuePassedInMemory(Thread &thread,
1522  RegisterContext *reg_ctx,
1523  size_t byte_size, Value &value) {
1524  Status error;
1525  DataBufferHeap buffer(byte_size, 0);
1526 
1527  const RegisterInfo *r0_reg_info =
1528  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
1529  uint32_t address =
1530  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1531  thread.GetProcess()->ReadMemory(address, buffer.GetBytes(),
1532  buffer.GetByteSize(), error);
1533 
1534  if (error.Fail())
1535  return false;
1536 
1537  value.SetBytes(buffer.GetBytes(), buffer.GetByteSize());
1538  return true;
1539 }
1540 
1541 bool ABISysV_arm::IsArmHardFloat(Thread &thread) const {
1542  ProcessSP process_sp(thread.GetProcess());
1543  if (process_sp) {
1544  const ArchSpec &arch(process_sp->GetTarget().GetArchitecture());
1545 
1546  return (arch.GetFlags() & ArchSpec::eARM_abi_hard_float) != 0;
1547  }
1548 
1549  return false;
1550 }
1551 
1552 ValueObjectSP ABISysV_arm::GetReturnValueObjectImpl(
1553  Thread &thread, lldb_private::CompilerType &compiler_type) const {
1554  Value value;
1555  ValueObjectSP return_valobj_sp;
1556 
1557  if (!compiler_type)
1558  return return_valobj_sp;
1559 
1560  // value.SetContext (Value::eContextTypeClangType,
1561  // compiler_type.GetOpaqueQualType());
1562  value.SetCompilerType(compiler_type);
1563 
1564  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1565  if (!reg_ctx)
1566  return return_valobj_sp;
1567 
1568  bool is_signed;
1569  bool is_complex;
1570  uint32_t float_count;
1571  bool is_vfp_candidate = false;
1572  uint8_t vfp_count = 0;
1573  uint8_t vfp_byte_size = 0;
1574 
1575  // Get the pointer to the first stack argument so we have a place to start
1576  // when reading data
1577 
1578  const RegisterInfo *r0_reg_info =
1579  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
1580  llvm::Optional<uint64_t> bit_width = compiler_type.GetBitSize(&thread);
1581  llvm::Optional<uint64_t> byte_size = compiler_type.GetByteSize(&thread);
1582  if (!bit_width || !byte_size)
1583  return return_valobj_sp;
1584 
1585  if (compiler_type.IsIntegerOrEnumerationType(is_signed)) {
1586  switch (*bit_width) {
1587  default:
1588  return return_valobj_sp;
1589  case 64: {
1590  const RegisterInfo *r1_reg_info = reg_ctx->GetRegisterInfo(
1591  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2);
1592  uint64_t raw_value;
1593  raw_value = reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1594  raw_value |= ((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(r1_reg_info, 0) &
1595  UINT32_MAX))
1596  << 32;
1597  if (is_signed)
1598  value.GetScalar() = (int64_t)raw_value;
1599  else
1600  value.GetScalar() = (uint64_t)raw_value;
1601  } break;
1602  case 32:
1603  if (is_signed)
1604  value.GetScalar() = (int32_t)(
1605  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX);
1606  else
1607  value.GetScalar() = (uint32_t)(
1608  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX);
1609  break;
1610  case 16:
1611  if (is_signed)
1612  value.GetScalar() = (int16_t)(
1613  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT16_MAX);
1614  else
1615  value.GetScalar() = (uint16_t)(
1616  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT16_MAX);
1617  break;
1618  case 8:
1619  if (is_signed)
1620  value.GetScalar() = (int8_t)(
1621  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT8_MAX);
1622  else
1623  value.GetScalar() = (uint8_t)(
1624  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT8_MAX);
1625  break;
1626  }
1627  } else if (compiler_type.IsPointerType()) {
1628  uint32_t ptr =
1629  thread.GetRegisterContext()->ReadRegisterAsUnsigned(r0_reg_info, 0) &
1630  UINT32_MAX;
1631  value.GetScalar() = ptr;
1632  } else if (compiler_type.IsVectorType(nullptr, nullptr)) {
1633  if (IsArmHardFloat(thread) && (*byte_size == 8 || *byte_size == 16)) {
1634  is_vfp_candidate = true;
1635  vfp_byte_size = 8;
1636  vfp_count = (*byte_size == 8 ? 1 : 2);
1637  } else if (*byte_size <= 16) {
1638  DataBufferHeap buffer(16, 0);
1639  uint32_t *buffer_ptr = (uint32_t *)buffer.GetBytes();
1640 
1641  for (uint32_t i = 0; 4 * i < *byte_size; ++i) {
1642  const RegisterInfo *reg_info = reg_ctx->GetRegisterInfo(
1643  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1 + i);
1644  buffer_ptr[i] =
1645  reg_ctx->ReadRegisterAsUnsigned(reg_info, 0) & UINT32_MAX;
1646  }
1647  value.SetBytes(buffer.GetBytes(), *byte_size);
1648  } else {
1649  if (!GetReturnValuePassedInMemory(thread, reg_ctx, *byte_size, value))
1650  return return_valobj_sp;
1651  }
1652  } else if (compiler_type.IsFloatingPointType(float_count, is_complex)) {
1653  if (float_count == 1 && !is_complex) {
1654  switch (*bit_width) {
1655  default:
1656  return return_valobj_sp;
1657  case 64: {
1658  static_assert(sizeof(double) == sizeof(uint64_t), "");
1659 
1660  if (IsArmHardFloat(thread)) {
1661  RegisterValue reg_value;
1662  const RegisterInfo *d0_reg_info =
1663  reg_ctx->GetRegisterInfoByName("d0", 0);
1664  reg_ctx->ReadRegister(d0_reg_info, reg_value);
1665  value.GetScalar() = reg_value.GetAsDouble();
1666  } else {
1667  uint64_t raw_value;
1668  const RegisterInfo *r1_reg_info = reg_ctx->GetRegisterInfo(
1669  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2);
1670  raw_value =
1671  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1672  raw_value |=
1673  ((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(r1_reg_info, 0) &
1674  UINT32_MAX))
1675  << 32;
1676  value.GetScalar() = *reinterpret_cast<double *>(&raw_value);
1677  }
1678  break;
1679  }
1680  case 16: // Half precision returned after a conversion to single precision
1681  case 32: {
1682  static_assert(sizeof(float) == sizeof(uint32_t), "");
1683 
1684  if (IsArmHardFloat(thread)) {
1685  RegisterValue reg_value;
1686  const RegisterInfo *s0_reg_info =
1687  reg_ctx->GetRegisterInfoByName("s0", 0);
1688  reg_ctx->ReadRegister(s0_reg_info, reg_value);
1689  value.GetScalar() = reg_value.GetAsFloat();
1690  } else {
1691  uint32_t raw_value;
1692  raw_value =
1693  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1694  value.GetScalar() = *reinterpret_cast<float *>(&raw_value);
1695  }
1696  break;
1697  }
1698  }
1699  } else if (is_complex && float_count == 2) {
1700  if (IsArmHardFloat(thread)) {
1701  is_vfp_candidate = true;
1702  vfp_byte_size = *byte_size / 2;
1703  vfp_count = 2;
1704  } else if (!GetReturnValuePassedInMemory(thread, reg_ctx, *bit_width / 8,
1705  value))
1706  return return_valobj_sp;
1707  } else
1708  // not handled yet
1709  return return_valobj_sp;
1710  } else if (compiler_type.IsAggregateType()) {
1711  if (IsArmHardFloat(thread)) {
1712  CompilerType base_type;
1713  const uint32_t homogeneous_count =
1714  compiler_type.IsHomogeneousAggregate(&base_type);
1715 
1716  if (homogeneous_count > 0 && homogeneous_count <= 4) {
1717  llvm::Optional<uint64_t> base_byte_size =
1718  base_type.GetByteSize(nullptr);
1719  if (base_type.IsVectorType(nullptr, nullptr)) {
1720  if (base_byte_size &&
1721  (*base_byte_size == 8 || *base_byte_size == 16)) {
1722  is_vfp_candidate = true;
1723  vfp_byte_size = 8;
1724  vfp_count = (*base_byte_size == 8 ? homogeneous_count
1725  : homogeneous_count * 2);
1726  }
1727  } else if (base_type.IsFloatingPointType(float_count, is_complex)) {
1728  if (float_count == 1 && !is_complex) {
1729  is_vfp_candidate = true;
1730  if (base_byte_size)
1731  vfp_byte_size = *base_byte_size;
1732  vfp_count = homogeneous_count;
1733  }
1734  }
1735  } else if (homogeneous_count == 0) {
1736  const uint32_t num_children = compiler_type.GetNumFields();
1737 
1738  if (num_children > 0 && num_children <= 2) {
1739  uint32_t index = 0;
1740  for (index = 0; index < num_children; index++) {
1741  std::string name;
1742  base_type =
1743  compiler_type.GetFieldAtIndex(index, name, NULL, NULL, NULL);
1744 
1745  if (base_type.IsFloatingPointType(float_count, is_complex)) {
1746  llvm::Optional<uint64_t> base_byte_size =
1747  base_type.GetByteSize(nullptr);
1748  if (float_count == 2 && is_complex) {
1749  if (index != 0 && base_byte_size &&
1750  vfp_byte_size != *base_byte_size)
1751  break;
1752  else if (base_byte_size)
1753  vfp_byte_size = *base_byte_size;
1754  } else
1755  break;
1756  } else
1757  break;
1758  }
1759 
1760  if (index == num_children) {
1761  is_vfp_candidate = true;
1762  vfp_byte_size = (vfp_byte_size >> 1);
1763  vfp_count = (num_children << 1);
1764  }
1765  }
1766  }
1767  }
1768 
1769  if (*byte_size <= 4) {
1770  RegisterValue r0_reg_value;
1771  uint32_t raw_value =
1772  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1773  value.SetBytes(&raw_value, *byte_size);
1774  } else if (!is_vfp_candidate) {
1775  if (!GetReturnValuePassedInMemory(thread, reg_ctx, *byte_size, value))
1776  return return_valobj_sp;
1777  }
1778  } else {
1779  // not handled yet
1780  return return_valobj_sp;
1781  }
1782 
1783  if (is_vfp_candidate) {
1784  ProcessSP process_sp(thread.GetProcess());
1785  ByteOrder byte_order = process_sp->GetByteOrder();
1786 
1787  DataBufferSP data_sp(new DataBufferHeap(*byte_size, 0));
1788  uint32_t data_offset = 0;
1789 
1790  for (uint32_t reg_index = 0; reg_index < vfp_count; reg_index++) {
1791  uint32_t regnum = 0;
1792 
1793  if (vfp_byte_size == 4)
1794  regnum = dwarf_s0 + reg_index;
1795  else if (vfp_byte_size == 8)
1796  regnum = dwarf_d0 + reg_index;
1797  else
1798  break;
1799 
1800  const RegisterInfo *reg_info =
1801  reg_ctx->GetRegisterInfo(eRegisterKindDWARF, regnum);
1802  if (reg_info == NULL)
1803  break;
1804 
1805  RegisterValue reg_value;
1806  if (!reg_ctx->ReadRegister(reg_info, reg_value))
1807  break;
1808 
1809  // Make sure we have enough room in "data_sp"
1810  if ((data_offset + vfp_byte_size) <= data_sp->GetByteSize()) {
1811  Status error;
1812  const size_t bytes_copied = reg_value.GetAsMemoryData(
1813  reg_info, data_sp->GetBytes() + data_offset, vfp_byte_size,
1814  byte_order, error);
1815  if (bytes_copied != vfp_byte_size)
1816  break;
1817 
1818  data_offset += bytes_copied;
1819  }
1820  }
1821 
1822  if (data_offset == *byte_size) {
1823  DataExtractor data;
1824  data.SetByteOrder(byte_order);
1825  data.SetAddressByteSize(process_sp->GetAddressByteSize());
1826  data.SetData(data_sp);
1827 
1828  return ValueObjectConstResult::Create(&thread, compiler_type,
1829  ConstString(""), data);
1830  } else { // Some error occurred while getting values from registers
1831  return return_valobj_sp;
1832  }
1833  }
1834 
1835  // If we get here, we have a valid Value, so make our ValueObject out of it:
1836 
1837  return_valobj_sp = ValueObjectConstResult::Create(
1838  thread.GetStackFrameAtIndex(0).get(), value, ConstString(""));
1839  return return_valobj_sp;
1840 }
1841 
1842 Status ABISysV_arm::SetReturnValueObject(lldb::StackFrameSP &frame_sp,
1843  lldb::ValueObjectSP &new_value_sp) {
1844  Status error;
1845  if (!new_value_sp) {
1846  error.SetErrorString("Empty value object for return value.");
1847  return error;
1848  }
1849 
1850  CompilerType compiler_type = new_value_sp->GetCompilerType();
1851  if (!compiler_type) {
1852  error.SetErrorString("Null clang type for return value.");
1853  return error;
1854  }
1855 
1856  Thread *thread = frame_sp->GetThread().get();
1857 
1858  bool is_signed;
1859  uint32_t count;
1860  bool is_complex;
1861 
1862  RegisterContext *reg_ctx = thread->GetRegisterContext().get();
1863 
1864  bool set_it_simple = false;
1865  if (compiler_type.IsIntegerOrEnumerationType(is_signed) ||
1866  compiler_type.IsPointerType()) {
1867  DataExtractor data;
1868  Status data_error;
1869  size_t num_bytes = new_value_sp->GetData(data, data_error);
1870  if (data_error.Fail()) {
1871  error.SetErrorStringWithFormat(
1872  "Couldn't convert return value to raw data: %s",
1873  data_error.AsCString());
1874  return error;
1875  }
1876  lldb::offset_t offset = 0;
1877  if (num_bytes <= 8) {
1878  const RegisterInfo *r0_info = reg_ctx->GetRegisterInfo(
1879  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
1880  if (num_bytes <= 4) {
1881  uint32_t raw_value = data.GetMaxU32(&offset, num_bytes);
1882 
1883  if (reg_ctx->WriteRegisterFromUnsigned(r0_info, raw_value))
1884  set_it_simple = true;
1885  } else {
1886  uint32_t raw_value = data.GetMaxU32(&offset, 4);
1887 
1888  if (reg_ctx->WriteRegisterFromUnsigned(r0_info, raw_value)) {
1889  const RegisterInfo *r1_info = reg_ctx->GetRegisterInfo(
1890  eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2);
1891  uint32_t raw_value = data.GetMaxU32(&offset, num_bytes - offset);
1892 
1893  if (reg_ctx->WriteRegisterFromUnsigned(r1_info, raw_value))
1894  set_it_simple = true;
1895  }
1896  }
1897  } else {
1898  error.SetErrorString("We don't support returning longer than 64 bit "
1899  "integer values at present.");
1900  }
1901  } else if (compiler_type.IsFloatingPointType(count, is_complex)) {
1902  if (is_complex)
1903  error.SetErrorString(
1904  "We don't support returning complex values at present");
1905  else
1906  error.SetErrorString(
1907  "We don't support returning float values at present");
1908  }
1909 
1910  if (!set_it_simple)
1911  error.SetErrorString(
1912  "We only support setting simple integer return types at present.");
1913 
1914  return error;
1915 }
1916 
1917 bool ABISysV_arm::CreateFunctionEntryUnwindPlan(UnwindPlan &unwind_plan) {
1918  unwind_plan.Clear();
1919  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
1920 
1921  uint32_t lr_reg_num = dwarf_lr;
1922  uint32_t sp_reg_num = dwarf_sp;
1923  uint32_t pc_reg_num = dwarf_pc;
1924 
1925  UnwindPlan::RowSP row(new UnwindPlan::Row);
1926 
1927  // Our Call Frame Address is the stack pointer value
1928  row->GetCFAValue().SetIsRegisterPlusOffset(sp_reg_num, 0);
1929 
1930  // The previous PC is in the LR
1931  row->SetRegisterLocationToRegister(pc_reg_num, lr_reg_num, true);
1932  unwind_plan.AppendRow(row);
1933 
1934  // All other registers are the same.
1935 
1936  unwind_plan.SetSourceName("arm at-func-entry default");
1937  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1938 
1939  return true;
1940 }
1941 
1942 bool ABISysV_arm::CreateDefaultUnwindPlan(UnwindPlan &unwind_plan) {
1943  unwind_plan.Clear();
1944  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
1945 
1946  // TODO: Handle thumb
1947  uint32_t fp_reg_num = dwarf_r11;
1948  uint32_t pc_reg_num = dwarf_pc;
1949 
1950  UnwindPlan::RowSP row(new UnwindPlan::Row);
1951  const int32_t ptr_size = 4;
1952 
1953  row->GetCFAValue().SetIsRegisterPlusOffset(fp_reg_num, 2 * ptr_size);
1954  row->SetOffset(0);
1955 
1956  row->SetRegisterLocationToAtCFAPlusOffset(fp_reg_num, ptr_size * -2, true);
1957  row->SetRegisterLocationToAtCFAPlusOffset(pc_reg_num, ptr_size * -1, true);
1958 
1959  unwind_plan.AppendRow(row);
1960  unwind_plan.SetSourceName("arm default unwind plan");
1961  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1962  unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolNo);
1963 
1964  return true;
1965 }
1966 
1967 // cf. "ARMv6 Function Calling Conventions"
1968 
1969 // ARMv7 on GNU/Linux general purpose reg rules:
1970 // r0-r3 not preserved (used for argument passing)
1971 // r4-r11 preserved (v1-v8)
1972 // r12 not presrved
1973 // r13 preserved (stack pointer)
1974 // r14 preserved (link register)
1975 // r15 preserved (pc)
1976 // cpsr not preserved (different rules for different bits)
1977 
1978 // ARMv7 VFP register rules:
1979 // d0-d7 not preserved (aka s0-s15, q0-q3)
1980 // d8-d15 preserved (aka s16-s31, q4-q7)
1981 // d16-d31 not preserved (aka q8-q15)
1982 
1983 bool ABISysV_arm::RegisterIsVolatile(const RegisterInfo *reg_info) {
1984  if (reg_info) {
1985  // Volatile registers are: r0, r1, r2, r3, r9, r12, r13 (aka sp)
1986  const char *name = reg_info->name;
1987  if (name[0] == 'r') {
1988  switch (name[1]) {
1989  case '0':
1990  return name[2] == '\0'; // r0
1991  case '1':
1992  switch (name[2]) {
1993  case '\0':
1994  return true; // r1
1995  case '2':
1996  return name[3] == '\0'; // r12
1997  default:
1998  break;
1999  }
2000  break;
2001 
2002  case '2':
2003  return name[2] == '\0'; // r2
2004  case '3':
2005  return name[2] == '\0'; // r3
2006  default:
2007  break;
2008  }
2009  } else if (name[0] == 'd') {
2010  switch (name[1]) {
2011  case '0':
2012  return name[2] == '\0'; // d0 is volatile
2013 
2014  case '1':
2015  switch (name[2]) {
2016  case '\0':
2017  return true; // d1 is volatile
2018  case '6':
2019  case '7':
2020  case '8':
2021  case '9':
2022  return name[3] == '\0'; // d16 - d19 are volatile
2023  default:
2024  break;
2025  }
2026  break;
2027 
2028  case '2':
2029  switch (name[2]) {
2030  case '\0':
2031  return true; // d2 is volatile
2032  case '0':
2033  case '1':
2034  case '2':
2035  case '3':
2036  case '4':
2037  case '5':
2038  case '6':
2039  case '7':
2040  case '8':
2041  case '9':
2042  return name[3] == '\0'; // d20 - d29 are volatile
2043  default:
2044  break;
2045  }
2046  break;
2047 
2048  case '3':
2049  switch (name[2]) {
2050  case '\0':
2051  return true; // d3 is volatile
2052  case '0':
2053  case '1':
2054  return name[3] == '\0'; // d30 - d31 are volatile
2055  default:
2056  break;
2057  }
2058  break;
2059  case '4':
2060  case '5':
2061  case '6':
2062  case '7':
2063  return name[2] == '\0'; // d4 - d7 are volatile
2064 
2065  default:
2066  break;
2067  }
2068  } else if (name[0] == 's') {
2069  switch (name[1]) {
2070  case '0':
2071  return name[2] == '\0'; // s0 is volatile
2072 
2073  case '1':
2074  switch (name[2]) {
2075  case '\0':
2076  return true; // s1 is volatile
2077  case '0':
2078  case '1':
2079  case '2':
2080  case '3':
2081  case '4':
2082  case '5':
2083  return name[3] == '\0'; // s10 - s15 are volatile
2084  default:
2085  break;
2086  }
2087  break;
2088 
2089  case '2':
2090  case '3':
2091  case '4':
2092  case '5':
2093  case '6':
2094  case '7':
2095  case '8':
2096  case '9':
2097  return name[2] == '\0'; // s2 - s9 are volatile
2098 
2099  default:
2100  break;
2101  }
2102  } else if (name[0] == 'q') {
2103  switch (name[1]) {
2104  case '1':
2105  switch (name[2]) {
2106  case '\0':
2107  return true; // q1 is volatile
2108  case '0':
2109  case '1':
2110  case '2':
2111  case '3':
2112  case '4':
2113  case '5':
2114  return true; // q10-q15 are volatile
2115  default:
2116  return false;
2117  }
2118  break;
2119 
2120  case '0':
2121  case '2':
2122  case '3':
2123  return name[2] == '\0'; // q0-q3 are volatile
2124  case '8':
2125  case '9':
2126  return name[2] == '\0'; // q8-q9 are volatile
2127  default:
2128  break;
2129  }
2130  } else if (name[0] == 's' && name[1] == 'p' && name[2] == '\0')
2131  return true;
2132  }
2133  return false;
2134 }
2135 
2136 void ABISysV_arm::Initialize() {
2137  PluginManager::RegisterPlugin(GetPluginNameStatic(),
2138  "SysV ABI for arm targets", CreateInstance);
2139 }
2140 
2141 void ABISysV_arm::Terminate() {
2142  PluginManager::UnregisterPlugin(CreateInstance);
2143 }
2144 
2145 lldb_private::ConstString ABISysV_arm::GetPluginNameStatic() {
2146  static ConstString g_name("SysV-arm");
2147  return g_name;
2148 }
2149 
2150 // PluginInterface protocol
2151 
2152 lldb_private::ConstString ABISysV_arm::GetPluginName() {
2153  return GetPluginNameStatic();
2154 }
2155 
2156 uint32_t ABISysV_arm::GetPluginVersion() { return 1; }
ABISysV_arm::GetRedZoneSize
size_t GetRedZoneSize() const override
Definition: ABISysV_arm.cpp:1318
dwarf_d16
Definition: ARM_DWARF_Registers.h:171
GetReturnValuePassedInMemory
static bool GetReturnValuePassedInMemory(Thread &thread, RegisterContext *reg_ctx, size_t byte_size, Value &value)
Definition: ABISysV_arm.cpp:1521
ehframe_r4
Definition: ARM_ehframe_Registers.h:21
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Definition: ARM_DWARF_Registers.h:47
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Definition: ABISysV_arm.cpp:2141
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Definition: DataExtractor.h:47
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Definition: ARM_DWARF_Registers.h:158
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Definition: ARM_ehframe_Registers.h:26
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Definition: UnwindPlan.h:53
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Definition: ARM_DWARF_Registers.h:166
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Definition: ARM_DWARF_Registers.h:43
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Definition: UnwindPlan.cpp:542
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Enumerations for broadcasting.
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Definition: ARM_ehframe_Registers.h:28
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Definition: ARM_DWARF_Registers.h:184
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Definition: ARM_DWARF_Registers.h:162
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Definition: ARM_DWARF_Registers.h:168
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bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp, lldb::addr_t func_addr, lldb::addr_t returnAddress, llvm::ArrayRef< lldb::addr_t > args) const override
Definition: ABISysV_arm.cpp:1337
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Definition: ARM_DWARF_Registers.h:62
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Definition: ARM_DWARF_Registers.h:167
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Definition: ARM_ehframe_Registers.h:17
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Definition: ARM_DWARF_Registers.h:129
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Definition: lldb-defines.h:66
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Definition: ABISysV_arm.cpp:1443
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Definition: RegisterContext.cpp:202
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Definition: ARM_DWARF_Registers.h:60
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Definition: ARM_DWARF_Registers.h:50
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Definition: ARMDefines.h:174
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Definition: ABISysV_arm.cpp:1323
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Definition: ARM_DWARF_Registers.h:55
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Definition: ARM_ehframe_Registers.h:30
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#define LLDB_REGNUM_GENERIC_ARG4
Definition: lldb-defines.h:74
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Definition: RegisterValue.cpp:39
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Definition: CompilerType.cpp:162
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Definition: ARM_DWARF_Registers.h:31
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Definition: ARM_ehframe_Registers.h:18
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virtual uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, uint32_t num)=0
Convert from a given register numbering scheme to the lldb register numbering scheme.
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Definition: ARM_DWARF_Registers.h:125
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Definition: ABISysV_mips.cpp:40
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An architecture specification class.
Definition: ArchSpec.h:32
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Definition: ARM_DWARF_Registers.h:183
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Definition: ARM_DWARF_Registers.h:33
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Definition: ARM_DWARF_Registers.h:38
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Definition: ARM_DWARF_Registers.h:176
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virtual bool WriteRegister(const RegisterInfo *reg_info, const RegisterValue &reg_value)=0
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Definition: Value.cpp:701
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Definition: UnwindPlan.h:55
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"lldb/Target/ExecutionContext.h" A class that contains an execution context.
Definition: ExecutionContext.h:291
ABISysV_arm::CreateFunctionEntryUnwindPlan
bool CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override
Definition: ABISysV_arm.cpp:1917
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void Clear()
Definition: UnwindPlan.h:468
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void SetAddressByteSize(uint32_t addr_size)
Set the address byte size.
Definition: DataExtractor.h:858
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#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:64
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Definition: ARM_DWARF_Registers.h:28
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static lldb_private::ConstString GetPluginNameStatic()
Definition: ABISysV_arm.cpp:2145
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Definition: ARM_DWARF_Registers.h:63
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Definition: ARM_DWARF_Registers.h:180
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bool SetLoadAddress(lldb::addr_t load_addr, Target *target, bool allow_section_end=false)
Set the address to represent load_addr.
Definition: Address.cpp:998
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Definition: ARM_DWARF_Registers.h:177
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llvm::Optional< uint64_t > GetByteSize(ExecutionContextScope *exe_scope) const
Return the size of the type in bytes.
Definition: CompilerType.cpp:500
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Definition: ARM_DWARF_Registers.h:173
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Definition: CompilerType.cpp:46
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uint32_t GetNumFields() const
Definition: CompilerType.cpp:548
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uint32_t GetPluginVersion() override
Definition: ABISysV_arm.cpp:2156
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Definition: ARM_ehframe_Registers.h:23
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A subclass of DataBuffer that stores a data buffer on the heap.
Definition: DataBufferHeap.h:30
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Definition: ARM_ehframe_Registers.h:19
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Definition: ARM_DWARF_Registers.h:137
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#define LLDB_REGNUM_GENERIC_ARG1
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Definition: ARM_DWARF_Registers.h:41
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Definition: CompilerType.cpp:166
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Definition: ABISysV_arm.cpp:1983
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llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:431
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Definition: ARM_DWARF_Registers.h:157
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Definition: ARM_DWARF_Registers.h:49
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Definition: ARM_DWARF_Registers.h:40
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Definition: ARM_DWARF_Registers.h:175
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Definition: CompilerType.cpp:73
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Definition: ARM_DWARF_Registers.h:155
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Definition: ARM_DWARF_Registers.h:57
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Definition: Value.h:48
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Definition: ARM_ehframe_Registers.h:24
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Definition: ARM_DWARF_Registers.h:54
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Definition: ABISysV_mips.cpp:45
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Definition: ARM_ehframe_Registers.h:27
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Definition: lldb-defines.h:31
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Definition: ARM_DWARF_Registers.h:42
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Definition: ARM_DWARF_Registers.h:126
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Definition: ARM_DWARF_Registers.h:123
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Definition: ARM_DWARF_Registers.h:139
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Definition: ARM_DWARF_Registers.h:45
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Definition: ARM_DWARF_Registers.h:61
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Set data with a buffer that is caller owned.
Definition: DataExtractor.cpp:227
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Definition: ARM_DWARF_Registers.h:56
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Definition: ARM_DWARF_Registers.h:130
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Definition: ABISysV_ppc.cpp:103
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Definition: ARM_DWARF_Registers.h:138
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Definition: ARM_DWARF_Registers.h:142
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Definition: Value.h:247
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Definition: ARM_DWARF_Registers.h:46
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Definition: ABISysV_mips.cpp:38
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Definition: UnwindPlan.h:366
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lldb::TargetSP CalculateTarget() override
Definition: Thread.cpp:1584
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Definition: ABISysV_mips.cpp:36
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Definition: ABISysV_mips.cpp:73
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Definition: ABISysV_mips.cpp:46
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Set the current error string to err_str.
Definition: Status.cpp:241
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Definition: ARM_DWARF_Registers.h:131
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Definition: ABISysV_arm.cpp:1942
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virtual bool ReadRegister(const RegisterInfo *reg_info, RegisterValue &reg_value)=0
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Definition: ARM_DWARF_Registers.h:134
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Definition: ABISysV_arm.cpp:37
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Definition: ARM_DWARF_Registers.h:51
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Definition: ARM_ehframe_Registers.h:20
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Definition: ARM_DWARF_Registers.h:135
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Definition: ARM_DWARF_Registers.h:179
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Definition: ABISysV_mips.cpp:43
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Definition: ARM_DWARF_Registers.h:163
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Definition: ABISysV_arm.cpp:1294
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A section + offset based address class.
Definition: Address.h:80
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Definition: ARM_ehframe_Registers.h:33
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Definition: ARM_DWARF_Registers.h:165
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Definition: ARM_DWARF_Registers.h:170
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Definition: ARM_DWARF_Registers.h:182
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Definition: ARM_DWARF_Registers.h:48
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Definition: ARM_DWARF_Registers.h:161
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Definition: ABISysV_arm.cpp:2152
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Definition: ARM_DWARF_Registers.h:186
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Definition: ARM_DWARF_Registers.h:181
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Definition: ARM_DWARF_Registers.h:159
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Definition: RegisterContext.h:17
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Definition: ARM_DWARF_Registers.h:124
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Definition: ARM_DWARF_Registers.h:59
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A uniqued constant string class.
Definition: ConstString.h:38
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Definition: ARM_DWARF_Registers.h:136
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Test for error condition.
Definition: Status.cpp:181
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Get the string value as a C string.
Definition: ConstString.h:247
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Definition: ARM_DWARF_Registers.h:34
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Definition: ARM_DWARF_Registers.h:185
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Return the size of the type in bits.
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Definition: ARM_ehframe_Registers.h:22
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lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread &thread, lldb_private::CompilerType &ast_type) const override
Definition: ABISysV_arm.cpp:1552
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Extract an integer of size byte_size from *offset_ptr.
Definition: DataExtractor.cpp:515
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Definition: ARM_DWARF_Registers.h:122
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Definition: ARM_ehframe_Registers.h:32
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#define LLDB_REGNUM_GENERIC_ARG3
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Definition: CompilerType.h:31
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Definition: ARM_DWARF_Registers.h:36
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Definition: ABISysV_arm.h:15
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Definition: Thread.h:59
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Definition: RegisterValue.cpp:137
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uint8_t * GetBytes() override
Definition: DataBufferHeap.cpp:34
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Definition: ARM_DWARF_Registers.h:141
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Definition: RegisterValue.h:27
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Definition: ARM_DWARF_Registers.h:169
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CompilerType GetFieldAtIndex(size_t idx, std::string &name, uint64_t *bit_offset_ptr, uint32_t *bitfield_bit_size_ptr, bool *is_bitfield_ptr) const
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Definition: ARM_ehframe_Registers.h:25
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Definition: ARM_DWARF_Registers.h:160
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Set the current error string to a formatted error string.
Definition: Status.cpp:255
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Definition: Value.cpp:268
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Definition: ARMDefines.h:175
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Definition: ARM_DWARF_Registers.h:140
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const Scalar & GetScalar() const
Definition: Value.h:178
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Definition: ARM_DWARF_Registers.h:44
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const char * AsCString(const char *default_error_str="unknown error") const
Get the error string associated with the current error.
Definition: Status.cpp:130
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Definition: ARM_DWARF_Registers.h:35
ABISysV_arm::SetReturnValueObject
lldb_private::Status SetReturnValueObject(lldb::StackFrameSP &frame_sp, lldb::ValueObjectSP &new_value) override
Definition: ABISysV_arm.cpp:1842
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virtual lldb::StackFrameSP GetStackFrameAtIndex(uint32_t idx)
Definition: Thread.h:395
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lldb::offset_t GetByteSize() const override
Definition: DataBufferHeap.cpp:45
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Definition: ARM_ehframe_Registers.h:29
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Definition: ABISysV_mips.cpp:41
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Definition: ARM_DWARF_Registers.h:52
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Definition: ABISysV_mips.cpp:47
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ABISysV_arm::GetRegisterInfoArray
const lldb_private::RegisterInfo * GetRegisterInfoArray(uint32_t &count) override
Definition: ABISysV_arm.cpp:1299
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float GetAsFloat(float fail_value=0.0f, bool *success_ptr=nullptr) const
Definition: RegisterValue.cpp:630
dwarf_d23
Definition: ARM_DWARF_Registers.h:178
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Definition: ARM_DWARF_Registers.h:37
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Definition: ARM_DWARF_Registers.h:39
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void SetSourcedFromCompiler(lldb_private::LazyBool from_compiler)
Definition: UnwindPlan.h:449
dwarf_s31
Definition: ARM_DWARF_Registers.h:64
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Definition: ARM_DWARF_Registers.h:53
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Definition: ARM_DWARF_Registers.h:172
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Definition: ARM_DWARF_Registers.h:58
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Definition: ABISysV_mips.cpp:39
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Definition: ARM_DWARF_Registers.h:132
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Definition: ARM_DWARF_Registers.h:133
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An error handling class.
Definition: Status.h:44
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void SetByteOrder(lldb::ByteOrder byte_order)
Set the byte_order value.
Definition: DataExtractor.h:944
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:90
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