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ABISysV_arm.cpp
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1 //===-- ABISysV_arm.cpp ---------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ABISysV_arm.h"
10 
11 #include <vector>
12 
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/Triple.h"
15 
16 #include "lldb/Core/Module.h"
18 #include "lldb/Core/Value.h"
20 #include "lldb/Symbol/UnwindPlan.h"
21 #include "lldb/Target/Process.h"
23 #include "lldb/Target/Target.h"
24 #include "lldb/Target/Thread.h"
27 #include "lldb/Utility/Scalar.h"
28 #include "lldb/Utility/Status.h"
29 
33 
34 using namespace lldb;
35 using namespace lldb_private;
36 
38 
39 static const RegisterInfo g_register_infos[] = {
40  // NAME ALT SZ OFF ENCODING FORMAT EH_FRAME
41  // DWARF GENERIC PROCESS PLUGIN
42  // LLDB NATIVE VALUE REGS INVALIDATE REGS
43  // ========== ======= == === ============= ============
44  // ======================= =================== ===========================
45  // ======================= ====================== ==========
46  // ===============
47  {"r0",
48  nullptr,
49  4,
50  0,
52  eFormatHex,
55  nullptr,
56  nullptr,
57  },
58  {"r1",
59  nullptr,
60  4,
61  0,
63  eFormatHex,
66  nullptr,
67  nullptr,
68  },
69  {"r2",
70  nullptr,
71  4,
72  0,
74  eFormatHex,
77  nullptr,
78  nullptr,
79  },
80  {"r3",
81  nullptr,
82  4,
83  0,
85  eFormatHex,
88  nullptr,
89  nullptr,
90  },
91  {"r4",
92  nullptr,
93  4,
94  0,
96  eFormatHex,
99  nullptr,
100  nullptr,
101  },
102  {"r5",
103  nullptr,
104  4,
105  0,
107  eFormatHex,
110  nullptr,
111  nullptr,
112  },
113  {"r6",
114  nullptr,
115  4,
116  0,
118  eFormatHex,
121  nullptr,
122  nullptr,
123  },
124  {"r7",
125  nullptr,
126  4,
127  0,
129  eFormatHex,
132  nullptr,
133  nullptr,
134  },
135  {"r8",
136  nullptr,
137  4,
138  0,
140  eFormatHex,
143  nullptr,
144  nullptr,
145  },
146  {"r9",
147  nullptr,
148  4,
149  0,
151  eFormatHex,
154  nullptr,
155  nullptr,
156  },
157  {"r10",
158  nullptr,
159  4,
160  0,
162  eFormatHex,
165  nullptr,
166  nullptr,
167  },
168  {"r11",
169  nullptr,
170  4,
171  0,
173  eFormatHex,
176  nullptr,
177  nullptr,
178  },
179  {"r12",
180  nullptr,
181  4,
182  0,
184  eFormatHex,
187  nullptr,
188  nullptr,
189  },
190  {"sp",
191  "r13",
192  4,
193  0,
195  eFormatHex,
198  nullptr,
199  nullptr,
200  },
201  {"lr",
202  "r14",
203  4,
204  0,
206  eFormatHex,
209  nullptr,
210  nullptr,
211  },
212  {"pc",
213  "r15",
214  4,
215  0,
217  eFormatHex,
220  nullptr,
221  nullptr,
222  },
223  {"cpsr",
224  "psr",
225  4,
226  0,
228  eFormatHex,
231  nullptr,
232  nullptr,
233  },
234  {"s0",
235  nullptr,
236  4,
237  0,
239  eFormatFloat,
242  nullptr,
243  nullptr,
244  },
245  {"s1",
246  nullptr,
247  4,
248  0,
250  eFormatFloat,
253  nullptr,
254  nullptr,
255  },
256  {"s2",
257  nullptr,
258  4,
259  0,
261  eFormatFloat,
264  nullptr,
265  nullptr,
266  },
267  {"s3",
268  nullptr,
269  4,
270  0,
272  eFormatFloat,
275  nullptr,
276  nullptr,
277  },
278  {"s4",
279  nullptr,
280  4,
281  0,
283  eFormatFloat,
286  nullptr,
287  nullptr,
288  },
289  {"s5",
290  nullptr,
291  4,
292  0,
294  eFormatFloat,
297  nullptr,
298  nullptr,
299  },
300  {"s6",
301  nullptr,
302  4,
303  0,
305  eFormatFloat,
308  nullptr,
309  nullptr,
310  },
311  {"s7",
312  nullptr,
313  4,
314  0,
316  eFormatFloat,
319  nullptr,
320  nullptr,
321  },
322  {"s8",
323  nullptr,
324  4,
325  0,
327  eFormatFloat,
330  nullptr,
331  nullptr,
332  },
333  {"s9",
334  nullptr,
335  4,
336  0,
338  eFormatFloat,
341  nullptr,
342  nullptr,
343  },
344  {"s10",
345  nullptr,
346  4,
347  0,
349  eFormatFloat,
352  nullptr,
353  nullptr,
354  },
355  {"s11",
356  nullptr,
357  4,
358  0,
360  eFormatFloat,
363  nullptr,
364  nullptr,
365  },
366  {"s12",
367  nullptr,
368  4,
369  0,
371  eFormatFloat,
374  nullptr,
375  nullptr,
376  },
377  {"s13",
378  nullptr,
379  4,
380  0,
382  eFormatFloat,
385  nullptr,
386  nullptr,
387  },
388  {"s14",
389  nullptr,
390  4,
391  0,
393  eFormatFloat,
396  nullptr,
397  nullptr,
398  },
399  {"s15",
400  nullptr,
401  4,
402  0,
404  eFormatFloat,
407  nullptr,
408  nullptr,
409  },
410  {"s16",
411  nullptr,
412  4,
413  0,
415  eFormatFloat,
418  nullptr,
419  nullptr,
420  },
421  {"s17",
422  nullptr,
423  4,
424  0,
426  eFormatFloat,
429  nullptr,
430  nullptr,
431  },
432  {"s18",
433  nullptr,
434  4,
435  0,
437  eFormatFloat,
440  nullptr,
441  nullptr,
442  },
443  {"s19",
444  nullptr,
445  4,
446  0,
448  eFormatFloat,
451  nullptr,
452  nullptr,
453  },
454  {"s20",
455  nullptr,
456  4,
457  0,
459  eFormatFloat,
462  nullptr,
463  nullptr,
464  },
465  {"s21",
466  nullptr,
467  4,
468  0,
470  eFormatFloat,
473  nullptr,
474  nullptr,
475  },
476  {"s22",
477  nullptr,
478  4,
479  0,
481  eFormatFloat,
484  nullptr,
485  nullptr,
486  },
487  {"s23",
488  nullptr,
489  4,
490  0,
492  eFormatFloat,
495  nullptr,
496  nullptr,
497  },
498  {"s24",
499  nullptr,
500  4,
501  0,
503  eFormatFloat,
506  nullptr,
507  nullptr,
508  },
509  {"s25",
510  nullptr,
511  4,
512  0,
514  eFormatFloat,
517  nullptr,
518  nullptr,
519  },
520  {"s26",
521  nullptr,
522  4,
523  0,
525  eFormatFloat,
528  nullptr,
529  nullptr,
530  },
531  {"s27",
532  nullptr,
533  4,
534  0,
536  eFormatFloat,
539  nullptr,
540  nullptr,
541  },
542  {"s28",
543  nullptr,
544  4,
545  0,
547  eFormatFloat,
550  nullptr,
551  nullptr,
552  },
553  {"s29",
554  nullptr,
555  4,
556  0,
558  eFormatFloat,
561  nullptr,
562  nullptr,
563  },
564  {"s30",
565  nullptr,
566  4,
567  0,
569  eFormatFloat,
572  nullptr,
573  nullptr,
574  },
575  {"s31",
576  nullptr,
577  4,
578  0,
580  eFormatFloat,
583  nullptr,
584  nullptr,
585  },
586  {"fpscr",
587  nullptr,
588  4,
589  0,
591  eFormatHex,
594  nullptr,
595  nullptr,
596  },
597  {"d0",
598  nullptr,
599  8,
600  0,
602  eFormatFloat,
605  nullptr,
606  nullptr,
607  },
608  {"d1",
609  nullptr,
610  8,
611  0,
613  eFormatFloat,
616  nullptr,
617  nullptr,
618  },
619  {"d2",
620  nullptr,
621  8,
622  0,
624  eFormatFloat,
627  nullptr,
628  nullptr,
629  },
630  {"d3",
631  nullptr,
632  8,
633  0,
635  eFormatFloat,
638  nullptr,
639  nullptr,
640  },
641  {"d4",
642  nullptr,
643  8,
644  0,
646  eFormatFloat,
649  nullptr,
650  nullptr,
651  },
652  {"d5",
653  nullptr,
654  8,
655  0,
657  eFormatFloat,
660  nullptr,
661  nullptr,
662  },
663  {"d6",
664  nullptr,
665  8,
666  0,
668  eFormatFloat,
671  nullptr,
672  nullptr,
673  },
674  {"d7",
675  nullptr,
676  8,
677  0,
679  eFormatFloat,
682  nullptr,
683  nullptr,
684  },
685  {"d8",
686  nullptr,
687  8,
688  0,
690  eFormatFloat,
693  nullptr,
694  nullptr,
695  },
696  {"d9",
697  nullptr,
698  8,
699  0,
701  eFormatFloat,
704  nullptr,
705  nullptr,
706  },
707  {"d10",
708  nullptr,
709  8,
710  0,
712  eFormatFloat,
715  nullptr,
716  nullptr,
717  },
718  {"d11",
719  nullptr,
720  8,
721  0,
723  eFormatFloat,
726  nullptr,
727  nullptr,
728  },
729  {"d12",
730  nullptr,
731  8,
732  0,
734  eFormatFloat,
737  nullptr,
738  nullptr,
739  },
740  {"d13",
741  nullptr,
742  8,
743  0,
745  eFormatFloat,
748  nullptr,
749  nullptr,
750  },
751  {"d14",
752  nullptr,
753  8,
754  0,
756  eFormatFloat,
759  nullptr,
760  nullptr,
761  },
762  {"d15",
763  nullptr,
764  8,
765  0,
767  eFormatFloat,
770  nullptr,
771  nullptr,
772  },
773  {"d16",
774  nullptr,
775  8,
776  0,
778  eFormatFloat,
781  nullptr,
782  nullptr,
783  },
784  {"d17",
785  nullptr,
786  8,
787  0,
789  eFormatFloat,
792  nullptr,
793  nullptr,
794  },
795  {"d18",
796  nullptr,
797  8,
798  0,
800  eFormatFloat,
803  nullptr,
804  nullptr,
805  },
806  {"d19",
807  nullptr,
808  8,
809  0,
811  eFormatFloat,
814  nullptr,
815  nullptr,
816  },
817  {"d20",
818  nullptr,
819  8,
820  0,
822  eFormatFloat,
825  nullptr,
826  nullptr,
827  },
828  {"d21",
829  nullptr,
830  8,
831  0,
833  eFormatFloat,
836  nullptr,
837  nullptr,
838  },
839  {"d22",
840  nullptr,
841  8,
842  0,
844  eFormatFloat,
847  nullptr,
848  nullptr,
849  },
850  {"d23",
851  nullptr,
852  8,
853  0,
855  eFormatFloat,
858  nullptr,
859  nullptr,
860  },
861  {"d24",
862  nullptr,
863  8,
864  0,
866  eFormatFloat,
869  nullptr,
870  nullptr,
871  },
872  {"d25",
873  nullptr,
874  8,
875  0,
877  eFormatFloat,
880  nullptr,
881  nullptr,
882  },
883  {"d26",
884  nullptr,
885  8,
886  0,
888  eFormatFloat,
891  nullptr,
892  nullptr,
893  },
894  {"d27",
895  nullptr,
896  8,
897  0,
899  eFormatFloat,
902  nullptr,
903  nullptr,
904  },
905  {"d28",
906  nullptr,
907  8,
908  0,
910  eFormatFloat,
913  nullptr,
914  nullptr,
915  },
916  {"d29",
917  nullptr,
918  8,
919  0,
921  eFormatFloat,
924  nullptr,
925  nullptr,
926  },
927  {"d30",
928  nullptr,
929  8,
930  0,
932  eFormatFloat,
935  nullptr,
936  nullptr,
937  },
938  {"d31",
939  nullptr,
940  8,
941  0,
943  eFormatFloat,
946  nullptr,
947  nullptr,
948  },
949  {"r8_usr",
950  nullptr,
951  4,
952  0,
954  eFormatHex,
957  nullptr,
958  nullptr,
959  },
960  {"r9_usr",
961  nullptr,
962  4,
963  0,
965  eFormatHex,
968  nullptr,
969  nullptr,
970  },
971  {"r10_usr",
972  nullptr,
973  4,
974  0,
976  eFormatHex,
979  nullptr,
980  nullptr,
981  },
982  {"r11_usr",
983  nullptr,
984  4,
985  0,
987  eFormatHex,
990  nullptr,
991  nullptr,
992  },
993  {"r12_usr",
994  nullptr,
995  4,
996  0,
998  eFormatHex,
1001  nullptr,
1002  nullptr,
1003  },
1004  {"r13_usr",
1005  "sp_usr",
1006  4,
1007  0,
1008  eEncodingUint,
1009  eFormatHex,
1012  nullptr,
1013  nullptr,
1014  },
1015  {"r14_usr",
1016  "lr_usr",
1017  4,
1018  0,
1019  eEncodingUint,
1020  eFormatHex,
1023  nullptr,
1024  nullptr,
1025  },
1026  {"r8_fiq",
1027  nullptr,
1028  4,
1029  0,
1030  eEncodingUint,
1031  eFormatHex,
1034  nullptr,
1035  nullptr,
1036  },
1037  {"r9_fiq",
1038  nullptr,
1039  4,
1040  0,
1041  eEncodingUint,
1042  eFormatHex,
1045  nullptr,
1046  nullptr,
1047  },
1048  {"r10_fiq",
1049  nullptr,
1050  4,
1051  0,
1052  eEncodingUint,
1053  eFormatHex,
1056  nullptr,
1057  nullptr,
1058  },
1059  {"r11_fiq",
1060  nullptr,
1061  4,
1062  0,
1063  eEncodingUint,
1064  eFormatHex,
1067  nullptr,
1068  nullptr,
1069  },
1070  {"r12_fiq",
1071  nullptr,
1072  4,
1073  0,
1074  eEncodingUint,
1075  eFormatHex,
1078  nullptr,
1079  nullptr,
1080  },
1081  {"r13_fiq",
1082  "sp_fiq",
1083  4,
1084  0,
1085  eEncodingUint,
1086  eFormatHex,
1089  nullptr,
1090  nullptr,
1091  },
1092  {"r14_fiq",
1093  "lr_fiq",
1094  4,
1095  0,
1096  eEncodingUint,
1097  eFormatHex,
1100  nullptr,
1101  nullptr,
1102  },
1103  {"r13_irq",
1104  "sp_irq",
1105  4,
1106  0,
1107  eEncodingUint,
1108  eFormatHex,
1111  nullptr,
1112  nullptr,
1113  },
1114  {"r14_irq",
1115  "lr_irq",
1116  4,
1117  0,
1118  eEncodingUint,
1119  eFormatHex,
1122  nullptr,
1123  nullptr,
1124  },
1125  {"r13_abt",
1126  "sp_abt",
1127  4,
1128  0,
1129  eEncodingUint,
1130  eFormatHex,
1133  nullptr,
1134  nullptr,
1135  },
1136  {"r14_abt",
1137  "lr_abt",
1138  4,
1139  0,
1140  eEncodingUint,
1141  eFormatHex,
1144  nullptr,
1145  nullptr,
1146  },
1147  {"r13_und",
1148  "sp_und",
1149  4,
1150  0,
1151  eEncodingUint,
1152  eFormatHex,
1155  nullptr,
1156  nullptr,
1157  },
1158  {"r14_und",
1159  "lr_und",
1160  4,
1161  0,
1162  eEncodingUint,
1163  eFormatHex,
1166  nullptr,
1167  nullptr,
1168  },
1169  {"r13_svc",
1170  "sp_svc",
1171  4,
1172  0,
1173  eEncodingUint,
1174  eFormatHex,
1177  nullptr,
1178  nullptr,
1179  },
1180  {"r14_svc",
1181  "lr_svc",
1182  4,
1183  0,
1184  eEncodingUint,
1185  eFormatHex,
1188  nullptr,
1189  nullptr,
1190  }};
1191 
1193  llvm::array_lengthof(g_register_infos);
1194 
1195 const lldb_private::RegisterInfo *
1197  count = k_num_register_infos;
1198  return g_register_infos;
1199 }
1200 
1201 size_t ABISysV_arm::GetRedZoneSize() const { return 0; }
1202 
1203 // Static Functions
1204 
1205 ABISP
1206 ABISysV_arm::CreateInstance(lldb::ProcessSP process_sp, const ArchSpec &arch) {
1207  const llvm::Triple::ArchType arch_type = arch.GetTriple().getArch();
1208  const llvm::Triple::VendorType vendor_type = arch.GetTriple().getVendor();
1209 
1210  if (vendor_type != llvm::Triple::Apple) {
1211  if ((arch_type == llvm::Triple::arm) ||
1212  (arch_type == llvm::Triple::thumb)) {
1213  return ABISP(
1214  new ABISysV_arm(std::move(process_sp), MakeMCRegisterInfo(arch)));
1215  }
1216  }
1217 
1218  return ABISP();
1219 }
1220 
1222  addr_t function_addr, addr_t return_addr,
1223  llvm::ArrayRef<addr_t> args) const {
1224  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1225  if (!reg_ctx)
1226  return false;
1227 
1228  const uint32_t pc_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1230  const uint32_t sp_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1232  const uint32_t ra_reg_num = reg_ctx->ConvertRegisterKindToRegisterNumber(
1234 
1235  RegisterValue reg_value;
1236 
1237  const uint8_t reg_names[] = {
1240 
1241  llvm::ArrayRef<addr_t>::iterator ai = args.begin(), ae = args.end();
1242 
1243  for (size_t i = 0; i < llvm::array_lengthof(reg_names); ++i) {
1244  if (ai == ae)
1245  break;
1246 
1247  reg_value.SetUInt32(*ai);
1248  if (!reg_ctx->WriteRegister(
1249  reg_ctx->GetRegisterInfo(eRegisterKindGeneric, reg_names[i]),
1250  reg_value))
1251  return false;
1252 
1253  ++ai;
1254  }
1255 
1256  if (ai != ae) {
1257  // Spill onto the stack
1258  size_t num_stack_regs = ae - ai;
1259 
1260  sp -= (num_stack_regs * 4);
1261  // Keep the stack 8 byte aligned, not that we need to
1262  sp &= ~(8ull - 1ull);
1263 
1264  // just using arg1 to get the right size
1265  const RegisterInfo *reg_info = reg_ctx->GetRegisterInfo(
1267 
1268  addr_t arg_pos = sp;
1269 
1270  for (; ai != ae; ++ai) {
1271  reg_value.SetUInt32(*ai);
1272  if (reg_ctx
1273  ->WriteRegisterValueToMemory(reg_info, arg_pos,
1274  reg_info->byte_size, reg_value)
1275  .Fail())
1276  return false;
1277  arg_pos += reg_info->byte_size;
1278  }
1279  }
1280 
1281  TargetSP target_sp(thread.CalculateTarget());
1282  Address so_addr;
1283 
1284  // Figure out if our return address is ARM or Thumb by using the
1285  // Address::GetCallableLoadAddress(Target*) which will figure out the ARM
1286  // thumb-ness and set the correct address bits for us.
1287  so_addr.SetLoadAddress(return_addr, target_sp.get());
1288  return_addr = so_addr.GetCallableLoadAddress(target_sp.get());
1289 
1290  // Set "lr" to the return address
1291  if (!reg_ctx->WriteRegisterFromUnsigned(ra_reg_num, return_addr))
1292  return false;
1293 
1294  // Set "sp" to the requested value
1295  if (!reg_ctx->WriteRegisterFromUnsigned(sp_reg_num, sp))
1296  return false;
1297 
1298  // If bit zero or 1 is set, this must be a thumb function, no need to figure
1299  // this out from the symbols.
1300  so_addr.SetLoadAddress(function_addr, target_sp.get());
1301  function_addr = so_addr.GetCallableLoadAddress(target_sp.get());
1302 
1303  const RegisterInfo *cpsr_reg_info =
1305  const uint32_t curr_cpsr = reg_ctx->ReadRegisterAsUnsigned(cpsr_reg_info, 0);
1306 
1307  // Make a new CPSR and mask out any Thumb IT (if/then) bits
1308  uint32_t new_cpsr = curr_cpsr & ~MASK_CPSR_IT_MASK;
1309  // If bit zero or 1 is set, this must be thumb...
1310  if (function_addr & 1ull)
1311  new_cpsr |= MASK_CPSR_T; // Set T bit in CPSR
1312  else
1313  new_cpsr &= ~MASK_CPSR_T; // Clear T bit in CPSR
1314 
1315  if (new_cpsr != curr_cpsr) {
1316  if (!reg_ctx->WriteRegisterFromUnsigned(cpsr_reg_info, new_cpsr))
1317  return false;
1318  }
1319 
1320  function_addr &=
1321  ~1ull; // clear bit zero since the CPSR will take care of the mode for us
1322 
1323  // Set "pc" to the address requested
1324  return reg_ctx->WriteRegisterFromUnsigned(pc_reg_num, function_addr);
1325 }
1326 
1327 bool ABISysV_arm::GetArgumentValues(Thread &thread, ValueList &values) const {
1328  uint32_t num_values = values.GetSize();
1329 
1330  ExecutionContext exe_ctx(thread.shared_from_this());
1331  // For now, assume that the types in the AST values come from the Target's
1332  // scratch AST.
1333 
1334  // Extract the register context so we can read arguments from registers
1335 
1336  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1337 
1338  if (!reg_ctx)
1339  return false;
1340 
1341  addr_t sp = 0;
1342 
1343  for (uint32_t value_idx = 0; value_idx < num_values; ++value_idx) {
1344  // We currently only support extracting values with Clang QualTypes. Do we
1345  // care about others?
1346  Value *value = values.GetValueAtIndex(value_idx);
1347 
1348  if (!value)
1349  return false;
1350 
1351  CompilerType compiler_type = value->GetCompilerType();
1352  if (compiler_type) {
1353  bool is_signed = false;
1354  size_t bit_width = 0;
1355  if (compiler_type.IsIntegerOrEnumerationType(is_signed) ||
1356  compiler_type.IsPointerOrReferenceType()) {
1357  if (llvm::Optional<uint64_t> size = compiler_type.GetBitSize(&thread))
1358  bit_width = *size;
1359  } else {
1360  // We only handle integer, pointer and reference types currently...
1361  return false;
1362  }
1363 
1364  if (bit_width <= (exe_ctx.GetProcessRef().GetAddressByteSize() * 8)) {
1365  if (value_idx < 4) {
1366  // Arguments 1-4 are in r0-r3...
1367  const RegisterInfo *arg_reg_info = nullptr;
1368  arg_reg_info = reg_ctx->GetRegisterInfo(
1370  if (arg_reg_info) {
1371  RegisterValue reg_value;
1372 
1373  if (reg_ctx->ReadRegister(arg_reg_info, reg_value)) {
1374  if (is_signed)
1375  reg_value.SignExtend(bit_width);
1376  if (!reg_value.GetScalarValue(value->GetScalar()))
1377  return false;
1378  continue;
1379  }
1380  }
1381  return false;
1382  } else {
1383  if (sp == 0) {
1384  // Read the stack pointer if it already hasn't been read
1385  sp = reg_ctx->GetSP(0);
1386  if (sp == 0)
1387  return false;
1388  }
1389 
1390  // Arguments 5 on up are on the stack
1391  const uint32_t arg_byte_size = (bit_width + (8 - 1)) / 8;
1392  Status error;
1394  sp, arg_byte_size, is_signed, value->GetScalar(), error))
1395  return false;
1396 
1397  sp += arg_byte_size;
1398  }
1399  }
1400  }
1401  }
1402  return true;
1403 }
1404 
1406  RegisterContext *reg_ctx,
1407  size_t byte_size, Value &value) {
1408  Status error;
1409  DataBufferHeap buffer(byte_size, 0);
1410 
1411  const RegisterInfo *r0_reg_info =
1413  uint32_t address =
1414  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1415  thread.GetProcess()->ReadMemory(address, buffer.GetBytes(),
1416  buffer.GetByteSize(), error);
1417 
1418  if (error.Fail())
1419  return false;
1420 
1421  value.SetBytes(buffer.GetBytes(), buffer.GetByteSize());
1422  return true;
1423 }
1424 
1426  ProcessSP process_sp(thread.GetProcess());
1427  if (process_sp) {
1428  const ArchSpec &arch(process_sp->GetTarget().GetArchitecture());
1429 
1430  return (arch.GetFlags() & ArchSpec::eARM_abi_hard_float) != 0;
1431  }
1432 
1433  return false;
1434 }
1435 
1437  Thread &thread, lldb_private::CompilerType &compiler_type) const {
1438  Value value;
1439  ValueObjectSP return_valobj_sp;
1440 
1441  if (!compiler_type)
1442  return return_valobj_sp;
1443 
1444  // value.SetContext (Value::eContextTypeClangType,
1445  // compiler_type.GetOpaqueQualType());
1446  value.SetCompilerType(compiler_type);
1447 
1448  RegisterContext *reg_ctx = thread.GetRegisterContext().get();
1449  if (!reg_ctx)
1450  return return_valobj_sp;
1451 
1452  bool is_signed;
1453  bool is_complex;
1454  uint32_t float_count;
1455  bool is_vfp_candidate = false;
1456  uint8_t vfp_count = 0;
1457  uint8_t vfp_byte_size = 0;
1458 
1459  // Get the pointer to the first stack argument so we have a place to start
1460  // when reading data
1461 
1462  const RegisterInfo *r0_reg_info =
1464  llvm::Optional<uint64_t> bit_width = compiler_type.GetBitSize(&thread);
1465  llvm::Optional<uint64_t> byte_size = compiler_type.GetByteSize(&thread);
1466  if (!bit_width || !byte_size)
1467  return return_valobj_sp;
1468 
1469  if (compiler_type.IsIntegerOrEnumerationType(is_signed)) {
1470  switch (*bit_width) {
1471  default:
1472  return return_valobj_sp;
1473  case 64: {
1474  const RegisterInfo *r1_reg_info = reg_ctx->GetRegisterInfo(
1476  uint64_t raw_value;
1477  raw_value = reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1478  raw_value |= ((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(r1_reg_info, 0) &
1479  UINT32_MAX))
1480  << 32;
1481  if (is_signed)
1482  value.GetScalar() = (int64_t)raw_value;
1483  else
1484  value.GetScalar() = (uint64_t)raw_value;
1485  } break;
1486  case 32:
1487  if (is_signed)
1488  value.GetScalar() = (int32_t)(
1489  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX);
1490  else
1491  value.GetScalar() = (uint32_t)(
1492  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX);
1493  break;
1494  case 16:
1495  if (is_signed)
1496  value.GetScalar() = (int16_t)(
1497  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT16_MAX);
1498  else
1499  value.GetScalar() = (uint16_t)(
1500  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT16_MAX);
1501  break;
1502  case 8:
1503  if (is_signed)
1504  value.GetScalar() = (int8_t)(
1505  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT8_MAX);
1506  else
1507  value.GetScalar() = (uint8_t)(
1508  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT8_MAX);
1509  break;
1510  }
1511  } else if (compiler_type.IsPointerType()) {
1512  uint32_t ptr =
1513  thread.GetRegisterContext()->ReadRegisterAsUnsigned(r0_reg_info, 0) &
1514  UINT32_MAX;
1515  value.GetScalar() = ptr;
1516  } else if (compiler_type.IsVectorType()) {
1517  if (IsArmHardFloat(thread) && (*byte_size == 8 || *byte_size == 16)) {
1518  is_vfp_candidate = true;
1519  vfp_byte_size = 8;
1520  vfp_count = (*byte_size == 8 ? 1 : 2);
1521  } else if (*byte_size <= 16) {
1522  DataBufferHeap buffer(16, 0);
1523  uint32_t *buffer_ptr = (uint32_t *)buffer.GetBytes();
1524 
1525  for (uint32_t i = 0; 4 * i < *byte_size; ++i) {
1526  const RegisterInfo *reg_info = reg_ctx->GetRegisterInfo(
1528  buffer_ptr[i] =
1529  reg_ctx->ReadRegisterAsUnsigned(reg_info, 0) & UINT32_MAX;
1530  }
1531  value.SetBytes(buffer.GetBytes(), *byte_size);
1532  } else {
1533  if (!GetReturnValuePassedInMemory(thread, reg_ctx, *byte_size, value))
1534  return return_valobj_sp;
1535  }
1536  } else if (compiler_type.IsFloatingPointType(float_count, is_complex)) {
1537  if (float_count == 1 && !is_complex) {
1538  switch (*bit_width) {
1539  default:
1540  return return_valobj_sp;
1541  case 64: {
1542  static_assert(sizeof(double) == sizeof(uint64_t), "");
1543 
1544  if (IsArmHardFloat(thread)) {
1545  RegisterValue reg_value;
1546  const RegisterInfo *d0_reg_info =
1547  reg_ctx->GetRegisterInfoByName("d0", 0);
1548  reg_ctx->ReadRegister(d0_reg_info, reg_value);
1549  value.GetScalar() = reg_value.GetAsDouble();
1550  } else {
1551  uint64_t raw_value;
1552  const RegisterInfo *r1_reg_info = reg_ctx->GetRegisterInfo(
1554  raw_value =
1555  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1556  raw_value |=
1557  ((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(r1_reg_info, 0) &
1558  UINT32_MAX))
1559  << 32;
1560  value.GetScalar() = *reinterpret_cast<double *>(&raw_value);
1561  }
1562  break;
1563  }
1564  case 16: // Half precision returned after a conversion to single precision
1565  case 32: {
1566  static_assert(sizeof(float) == sizeof(uint32_t), "");
1567 
1568  if (IsArmHardFloat(thread)) {
1569  RegisterValue reg_value;
1570  const RegisterInfo *s0_reg_info =
1571  reg_ctx->GetRegisterInfoByName("s0", 0);
1572  reg_ctx->ReadRegister(s0_reg_info, reg_value);
1573  value.GetScalar() = reg_value.GetAsFloat();
1574  } else {
1575  uint32_t raw_value;
1576  raw_value =
1577  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1578  value.GetScalar() = *reinterpret_cast<float *>(&raw_value);
1579  }
1580  break;
1581  }
1582  }
1583  } else if (is_complex && float_count == 2) {
1584  if (IsArmHardFloat(thread)) {
1585  is_vfp_candidate = true;
1586  vfp_byte_size = *byte_size / 2;
1587  vfp_count = 2;
1588  } else if (!GetReturnValuePassedInMemory(thread, reg_ctx, *bit_width / 8,
1589  value))
1590  return return_valobj_sp;
1591  } else
1592  // not handled yet
1593  return return_valobj_sp;
1594  } else if (compiler_type.IsAggregateType()) {
1595  if (IsArmHardFloat(thread)) {
1596  CompilerType base_type;
1597  const uint32_t homogeneous_count =
1598  compiler_type.IsHomogeneousAggregate(&base_type);
1599 
1600  if (homogeneous_count > 0 && homogeneous_count <= 4) {
1601  llvm::Optional<uint64_t> base_byte_size =
1602  base_type.GetByteSize(&thread);
1603  if (base_type.IsVectorType()) {
1604  if (base_byte_size &&
1605  (*base_byte_size == 8 || *base_byte_size == 16)) {
1606  is_vfp_candidate = true;
1607  vfp_byte_size = 8;
1608  vfp_count = (*base_byte_size == 8 ? homogeneous_count
1609  : homogeneous_count * 2);
1610  }
1611  } else if (base_type.IsFloatingPointType(float_count, is_complex)) {
1612  if (float_count == 1 && !is_complex) {
1613  is_vfp_candidate = true;
1614  if (base_byte_size)
1615  vfp_byte_size = *base_byte_size;
1616  vfp_count = homogeneous_count;
1617  }
1618  }
1619  } else if (homogeneous_count == 0) {
1620  const uint32_t num_children = compiler_type.GetNumFields();
1621 
1622  if (num_children > 0 && num_children <= 2) {
1623  uint32_t index = 0;
1624  for (index = 0; index < num_children; index++) {
1625  std::string name;
1626  base_type = compiler_type.GetFieldAtIndex(index, name, nullptr,
1627  nullptr, nullptr);
1628 
1629  if (base_type.IsFloatingPointType(float_count, is_complex)) {
1630  llvm::Optional<uint64_t> base_byte_size =
1631  base_type.GetByteSize(&thread);
1632  if (float_count == 2 && is_complex) {
1633  if (index != 0 && base_byte_size &&
1634  vfp_byte_size != *base_byte_size)
1635  break;
1636  else if (base_byte_size)
1637  vfp_byte_size = *base_byte_size;
1638  } else
1639  break;
1640  } else
1641  break;
1642  }
1643 
1644  if (index == num_children) {
1645  is_vfp_candidate = true;
1646  vfp_byte_size = (vfp_byte_size >> 1);
1647  vfp_count = (num_children << 1);
1648  }
1649  }
1650  }
1651  }
1652 
1653  if (*byte_size <= 4) {
1654  RegisterValue r0_reg_value;
1655  uint32_t raw_value =
1656  reg_ctx->ReadRegisterAsUnsigned(r0_reg_info, 0) & UINT32_MAX;
1657  value.SetBytes(&raw_value, *byte_size);
1658  } else if (!is_vfp_candidate) {
1659  if (!GetReturnValuePassedInMemory(thread, reg_ctx, *byte_size, value))
1660  return return_valobj_sp;
1661  }
1662  } else {
1663  // not handled yet
1664  return return_valobj_sp;
1665  }
1666 
1667  if (is_vfp_candidate) {
1668  ProcessSP process_sp(thread.GetProcess());
1669  ByteOrder byte_order = process_sp->GetByteOrder();
1670 
1671  DataBufferSP data_sp(new DataBufferHeap(*byte_size, 0));
1672  uint32_t data_offset = 0;
1673 
1674  for (uint32_t reg_index = 0; reg_index < vfp_count; reg_index++) {
1675  uint32_t regnum = 0;
1676 
1677  if (vfp_byte_size == 4)
1678  regnum = dwarf_s0 + reg_index;
1679  else if (vfp_byte_size == 8)
1680  regnum = dwarf_d0 + reg_index;
1681  else
1682  break;
1683 
1684  const RegisterInfo *reg_info =
1685  reg_ctx->GetRegisterInfo(eRegisterKindDWARF, regnum);
1686  if (reg_info == nullptr)
1687  break;
1688 
1689  RegisterValue reg_value;
1690  if (!reg_ctx->ReadRegister(reg_info, reg_value))
1691  break;
1692 
1693  // Make sure we have enough room in "data_sp"
1694  if ((data_offset + vfp_byte_size) <= data_sp->GetByteSize()) {
1695  Status error;
1696  const size_t bytes_copied = reg_value.GetAsMemoryData(
1697  reg_info, data_sp->GetBytes() + data_offset, vfp_byte_size,
1698  byte_order, error);
1699  if (bytes_copied != vfp_byte_size)
1700  break;
1701 
1702  data_offset += bytes_copied;
1703  }
1704  }
1705 
1706  if (data_offset == *byte_size) {
1707  DataExtractor data;
1708  data.SetByteOrder(byte_order);
1709  data.SetAddressByteSize(process_sp->GetAddressByteSize());
1710  data.SetData(data_sp);
1711 
1712  return ValueObjectConstResult::Create(&thread, compiler_type,
1713  ConstString(""), data);
1714  } else { // Some error occurred while getting values from registers
1715  return return_valobj_sp;
1716  }
1717  }
1718 
1719  // If we get here, we have a valid Value, so make our ValueObject out of it:
1720 
1721  return_valobj_sp = ValueObjectConstResult::Create(
1722  thread.GetStackFrameAtIndex(0).get(), value, ConstString(""));
1723  return return_valobj_sp;
1724 }
1725 
1726 Status ABISysV_arm::SetReturnValueObject(lldb::StackFrameSP &frame_sp,
1727  lldb::ValueObjectSP &new_value_sp) {
1728  Status error;
1729  if (!new_value_sp) {
1730  error.SetErrorString("Empty value object for return value.");
1731  return error;
1732  }
1733 
1734  CompilerType compiler_type = new_value_sp->GetCompilerType();
1735  if (!compiler_type) {
1736  error.SetErrorString("Null clang type for return value.");
1737  return error;
1738  }
1739 
1740  Thread *thread = frame_sp->GetThread().get();
1741 
1742  bool is_signed;
1743  uint32_t count;
1744  bool is_complex;
1745 
1746  RegisterContext *reg_ctx = thread->GetRegisterContext().get();
1747 
1748  bool set_it_simple = false;
1749  if (compiler_type.IsIntegerOrEnumerationType(is_signed) ||
1750  compiler_type.IsPointerType()) {
1751  DataExtractor data;
1752  Status data_error;
1753  size_t num_bytes = new_value_sp->GetData(data, data_error);
1754  if (data_error.Fail()) {
1755  error.SetErrorStringWithFormat(
1756  "Couldn't convert return value to raw data: %s",
1757  data_error.AsCString());
1758  return error;
1759  }
1760  lldb::offset_t offset = 0;
1761  if (num_bytes <= 8) {
1762  const RegisterInfo *r0_info = reg_ctx->GetRegisterInfo(
1764  if (num_bytes <= 4) {
1765  uint32_t raw_value = data.GetMaxU32(&offset, num_bytes);
1766 
1767  if (reg_ctx->WriteRegisterFromUnsigned(r0_info, raw_value))
1768  set_it_simple = true;
1769  } else {
1770  uint32_t raw_value = data.GetMaxU32(&offset, 4);
1771 
1772  if (reg_ctx->WriteRegisterFromUnsigned(r0_info, raw_value)) {
1773  const RegisterInfo *r1_info = reg_ctx->GetRegisterInfo(
1775  uint32_t raw_value = data.GetMaxU32(&offset, num_bytes - offset);
1776 
1777  if (reg_ctx->WriteRegisterFromUnsigned(r1_info, raw_value))
1778  set_it_simple = true;
1779  }
1780  }
1781  } else {
1782  error.SetErrorString("We don't support returning longer than 64 bit "
1783  "integer values at present.");
1784  }
1785  } else if (compiler_type.IsFloatingPointType(count, is_complex)) {
1786  if (is_complex)
1787  error.SetErrorString(
1788  "We don't support returning complex values at present");
1789  else
1790  error.SetErrorString(
1791  "We don't support returning float values at present");
1792  }
1793 
1794  if (!set_it_simple)
1795  error.SetErrorString(
1796  "We only support setting simple integer return types at present.");
1797 
1798  return error;
1799 }
1800 
1802  unwind_plan.Clear();
1803  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
1804 
1805  uint32_t lr_reg_num = dwarf_lr;
1806  uint32_t sp_reg_num = dwarf_sp;
1807  uint32_t pc_reg_num = dwarf_pc;
1808 
1810 
1811  // Our Call Frame Address is the stack pointer value
1812  row->GetCFAValue().SetIsRegisterPlusOffset(sp_reg_num, 0);
1813 
1814  // The previous PC is in the LR
1815  row->SetRegisterLocationToRegister(pc_reg_num, lr_reg_num, true);
1816  unwind_plan.AppendRow(row);
1817 
1818  // All other registers are the same.
1819 
1820  unwind_plan.SetSourceName("arm at-func-entry default");
1821  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1822 
1823  return true;
1824 }
1825 
1827  unwind_plan.Clear();
1828  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
1829 
1830  // TODO: Handle thumb
1831  uint32_t fp_reg_num = dwarf_r11;
1832  uint32_t pc_reg_num = dwarf_pc;
1833 
1835  const int32_t ptr_size = 4;
1836 
1837  row->GetCFAValue().SetIsRegisterPlusOffset(fp_reg_num, 2 * ptr_size);
1838  row->SetOffset(0);
1839  row->SetUnspecifiedRegistersAreUndefined(true);
1840 
1841  row->SetRegisterLocationToAtCFAPlusOffset(fp_reg_num, ptr_size * -2, true);
1842  row->SetRegisterLocationToAtCFAPlusOffset(pc_reg_num, ptr_size * -1, true);
1843 
1844  unwind_plan.AppendRow(row);
1845  unwind_plan.SetSourceName("arm default unwind plan");
1846  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1849 
1850  return true;
1851 }
1852 
1853 // cf. "ARMv6 Function Calling Conventions"
1854 
1855 // ARMv7 on GNU/Linux general purpose reg rules:
1856 // r0-r3 not preserved (used for argument passing)
1857 // r4-r11 preserved (v1-v8)
1858 // r12 not presrved
1859 // r13 preserved (stack pointer)
1860 // r14 preserved (link register)
1861 // r15 preserved (pc)
1862 // cpsr not preserved (different rules for different bits)
1863 
1864 // ARMv7 VFP register rules:
1865 // d0-d7 not preserved (aka s0-s15, q0-q3)
1866 // d8-d15 preserved (aka s16-s31, q4-q7)
1867 // d16-d31 not preserved (aka q8-q15)
1868 
1869 bool ABISysV_arm::RegisterIsVolatile(const RegisterInfo *reg_info) {
1870  if (reg_info) {
1871  // Volatile registers are: r0, r1, r2, r3, r9, r12, r13 (aka sp)
1872  const char *name = reg_info->name;
1873  if (name[0] == 'r') {
1874  switch (name[1]) {
1875  case '0':
1876  return name[2] == '\0'; // r0
1877  case '1':
1878  switch (name[2]) {
1879  case '\0':
1880  return true; // r1
1881  case '2':
1882  return name[3] == '\0'; // r12
1883  default:
1884  break;
1885  }
1886  break;
1887 
1888  case '2':
1889  return name[2] == '\0'; // r2
1890  case '3':
1891  return name[2] == '\0'; // r3
1892  default:
1893  break;
1894  }
1895  } else if (name[0] == 'd') {
1896  switch (name[1]) {
1897  case '0':
1898  return name[2] == '\0'; // d0 is volatile
1899 
1900  case '1':
1901  switch (name[2]) {
1902  case '\0':
1903  return true; // d1 is volatile
1904  case '6':
1905  case '7':
1906  case '8':
1907  case '9':
1908  return name[3] == '\0'; // d16 - d19 are volatile
1909  default:
1910  break;
1911  }
1912  break;
1913 
1914  case '2':
1915  switch (name[2]) {
1916  case '\0':
1917  return true; // d2 is volatile
1918  case '0':
1919  case '1':
1920  case '2':
1921  case '3':
1922  case '4':
1923  case '5':
1924  case '6':
1925  case '7':
1926  case '8':
1927  case '9':
1928  return name[3] == '\0'; // d20 - d29 are volatile
1929  default:
1930  break;
1931  }
1932  break;
1933 
1934  case '3':
1935  switch (name[2]) {
1936  case '\0':
1937  return true; // d3 is volatile
1938  case '0':
1939  case '1':
1940  return name[3] == '\0'; // d30 - d31 are volatile
1941  default:
1942  break;
1943  }
1944  break;
1945  case '4':
1946  case '5':
1947  case '6':
1948  case '7':
1949  return name[2] == '\0'; // d4 - d7 are volatile
1950 
1951  default:
1952  break;
1953  }
1954  } else if (name[0] == 's') {
1955  switch (name[1]) {
1956  case '0':
1957  return name[2] == '\0'; // s0 is volatile
1958 
1959  case '1':
1960  switch (name[2]) {
1961  case '\0':
1962  return true; // s1 is volatile
1963  case '0':
1964  case '1':
1965  case '2':
1966  case '3':
1967  case '4':
1968  case '5':
1969  return name[3] == '\0'; // s10 - s15 are volatile
1970  default:
1971  break;
1972  }
1973  break;
1974 
1975  case '2':
1976  case '3':
1977  case '4':
1978  case '5':
1979  case '6':
1980  case '7':
1981  case '8':
1982  case '9':
1983  return name[2] == '\0'; // s2 - s9 are volatile
1984 
1985  default:
1986  break;
1987  }
1988  } else if (name[0] == 'q') {
1989  switch (name[1]) {
1990  case '1':
1991  switch (name[2]) {
1992  case '\0':
1993  return true; // q1 is volatile
1994  case '0':
1995  case '1':
1996  case '2':
1997  case '3':
1998  case '4':
1999  case '5':
2000  return true; // q10-q15 are volatile
2001  default:
2002  return false;
2003  }
2004  break;
2005 
2006  case '0':
2007  case '2':
2008  case '3':
2009  return name[2] == '\0'; // q0-q3 are volatile
2010  case '8':
2011  case '9':
2012  return name[2] == '\0'; // q8-q9 are volatile
2013  default:
2014  break;
2015  }
2016  } else if (name[0] == 's' && name[1] == 'p' && name[2] == '\0')
2017  return true;
2018  }
2019  return false;
2020 }
2021 
2023  PluginManager::RegisterPlugin(GetPluginNameStatic(),
2024  "SysV ABI for arm targets", CreateInstance);
2025 }
2026 
2028  PluginManager::UnregisterPlugin(CreateInstance);
2029 }
2030 
2032  static ConstString g_name("SysV-arm");
2033  return g_name;
2034 }
2035 
2036 // PluginInterface protocol
2037 
2039  return GetPluginNameStatic();
2040 }
lldb_private::Address::SetLoadAddress
bool SetLoadAddress(lldb::addr_t load_addr, Target *target, bool allow_section_end=false)
Set the address to represent load_addr.
Definition: Address.cpp:1023
dwarf_r9
@ dwarf_r9
Definition: ABISysV_mips.cpp:47
dwarf_r14_irq
@ dwarf_r14_irq
Definition: ARM_DWARF_Registers.h:136
ABISysV_arm::GetRegisterInfoArray
const lldb_private::RegisterInfo * GetRegisterInfoArray(uint32_t &count) override
Definition: ABISysV_arm.cpp:1196
lldb_private::RegisterContext::WriteRegister
virtual bool WriteRegister(const RegisterInfo *reg_info, const RegisterValue &reg_value)=0
lldb_private::CompilerType::IsPointerOrReferenceType
bool IsPointerOrReferenceType(CompilerType *pointee_type=nullptr) const
Definition: CompilerType.cpp:166
LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_ARG2
Definition: lldb-defines.h:70
dwarf_sp
@ dwarf_sp
Definition: ARM_DWARF_Registers.h:28
LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG3
Definition: lldb-defines.h:72
dwarf_d25
@ dwarf_d25
Definition: ARM_DWARF_Registers.h:180
ABISysV_arm::CreateFunctionEntryUnwindPlan
bool CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override
Definition: ABISysV_arm.cpp:1801
lldb_private::ExecutionContext
Definition: ExecutionContext.h:292
dwarf_d7
@ dwarf_d7
Definition: ARM_DWARF_Registers.h:162
lldb_private::DataBufferHeap::GetBytes
uint8_t * GetBytes() override
Definition: DataBufferHeap.cpp:34
lldb_private::DataBufferHeap::GetByteSize
lldb::offset_t GetByteSize() const override
Definition: DataBufferHeap.cpp:45
Scalar.h
lldb_private::UnwindPlan::AppendRow
void AppendRow(const RowSP &row_sp)
Definition: UnwindPlan.cpp:360
lldb_private::ArchSpec
Definition: ArchSpec.h:33
LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG1
Definition: lldb-defines.h:68
dwarf_s7
@ dwarf_s7
Definition: ARM_DWARF_Registers.h:40
ehframe_r3
@ ehframe_r3
Definition: ARM_ehframe_Registers.h:20
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:91
dwarf_s14
@ dwarf_s14
Definition: ARM_DWARF_Registers.h:47
GetReturnValuePassedInMemory
static bool GetReturnValuePassedInMemory(Thread &thread, RegisterContext *reg_ctx, size_t byte_size, Value &value)
Definition: ABISysV_arm.cpp:1405
ABISysV_arm::SetReturnValueObject
lldb_private::Status SetReturnValueObject(lldb::StackFrameSP &frame_sp, lldb::ValueObjectSP &new_value) override
Definition: ABISysV_arm.cpp:1726
dwarf_r14_fiq
@ dwarf_r14_fiq
Definition: ARM_DWARF_Registers.h:134
lldb_private::RegisterValue
Definition: RegisterValue.h:28
lldb_private::Process::ReadScalarIntegerFromMemory
size_t ReadScalarIntegerFromMemory(lldb::addr_t addr, uint32_t byte_size, bool is_signed, Scalar &scalar, Status &error)
Definition: Process.cpp:2255
lldb_private::UnwindPlan::SetRegisterKind
void SetRegisterKind(lldb::RegisterKind kind)
Definition: UnwindPlan.h:439
lldb::eRegisterKindDWARF
@ eRegisterKindDWARF
the register numbers seen DWARF
Definition: lldb-enumerations.h:229
ehframe_cpsr
@ ehframe_cpsr
Definition: ARM_ehframe_Registers.h:33
lldb_private::Value
Definition: Value.h:38
dwarf_d20
@ dwarf_d20
Definition: ARM_DWARF_Registers.h:175
dwarf_d29
@ dwarf_d29
Definition: ARM_DWARF_Registers.h:184
ehframe_r1
@ ehframe_r1
Definition: ARM_ehframe_Registers.h:18
lldb::eRegisterKindGeneric
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target
Definition: lldb-enumerations.h:230
dwarf_d23
@ dwarf_d23
Definition: ARM_DWARF_Registers.h:178
dwarf_s29
@ dwarf_s29
Definition: ARM_DWARF_Registers.h:62
lldb_private::ValueList::GetValueAtIndex
Value * GetValueAtIndex(size_t idx)
Definition: Value.cpp:679
lldb_private::CompilerType::IsVectorType
bool IsVectorType(CompilerType *element_type=nullptr, uint64_t *size=nullptr) const
Definition: CompilerType.cpp:64
lldb_private::UnwindPlan::SetUnwindPlanValidAtAllInstructions
void SetUnwindPlanValidAtAllInstructions(lldb_private::LazyBool valid_at_all_insn)
Definition: UnwindPlan.h:492
dwarf_r8_fiq
@ dwarf_r8_fiq
Definition: ARM_DWARF_Registers.h:128
dwarf_d18
@ dwarf_d18
Definition: ARM_DWARF_Registers.h:173
lldb_private::RegisterContext::ReadRegister
virtual bool ReadRegister(const RegisterInfo *reg_info, RegisterValue &reg_value)=0
dwarf_r13_abt
@ dwarf_r13_abt
Definition: ARM_DWARF_Registers.h:137
ABISysV_arm::RegisterIsVolatile
bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override
Definition: ABISysV_arm.cpp:1869
dwarf_s31
@ dwarf_s31
Definition: ARM_DWARF_Registers.h:64
lldb_private::Thread::CalculateTarget
lldb::TargetSP CalculateTarget() override
Definition: Thread.cpp:1389
dwarf_d21
@ dwarf_d21
Definition: ARM_DWARF_Registers.h:176
Module.h
lldb::eEncodingIEEE754
@ eEncodingIEEE754
float
Definition: lldb-enumerations.h:150
lldb_private::RegisterContext::ConvertRegisterKindToRegisterNumber
virtual uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, uint32_t num)
Convert from a given register numbering scheme to the lldb register numbering scheme.
Definition: RegisterContext.cpp:268
lldb_private::RegisterContext::ReadRegisterAsUnsigned
uint64_t ReadRegisterAsUnsigned(uint32_t reg, uint64_t fail_value)
Definition: RegisterContext.cpp:188
dwarf_s28
@ dwarf_s28
Definition: ARM_DWARF_Registers.h:61
dwarf_r12
@ dwarf_r12
Definition: ABISysV_mips.cpp:50
dwarf_r10_fiq
@ dwarf_r10_fiq
Definition: ARM_DWARF_Registers.h:130
lldb_private::ArchSpec::GetFlags
uint32_t GetFlags() const
Definition: ArchSpec.h:514
ehframe_r2
@ ehframe_r2
Definition: ARM_ehframe_Registers.h:19
lldb_private::CompilerType::GetByteSize
llvm::Optional< uint64_t > GetByteSize(ExecutionContextScope *exe_scope) const
Return the size of the type in bytes.
Definition: CompilerType.cpp:489
lldb_private::UnwindPlan::SetUnwindPlanForSignalTrap
void SetUnwindPlanForSignalTrap(lldb_private::LazyBool is_for_signal_trap)
Definition: UnwindPlan.h:504
lldb::offset_t
uint64_t offset_t
Definition: lldb-types.h:87
RegisterValue.h
lldb_private::ValueList
Definition: Value.h:157
ABISysV_arm::CreateInstance
static lldb::ABISP CreateInstance(lldb::ProcessSP process_sp, const lldb_private::ArchSpec &arch)
Definition: ABISysV_arm.cpp:1206
lldb_private::ArchSpec::GetTriple
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:444
lldb_private::CompilerType::IsAggregateType
bool IsAggregateType() const
Definition: CompilerType.cpp:31
lldb::addr_t
uint64_t addr_t
Definition: lldb-types.h:83
lldb_private::CompilerType::IsFloatingPointType
bool IsFloatingPointType(uint32_t &count, bool &is_complex) const
Definition: CompilerType.cpp:191
dwarf_d28
@ dwarf_d28
Definition: ARM_DWARF_Registers.h:183
dwarf_r5
@ dwarf_r5
Definition: ABISysV_mips.cpp:43
dwarf_d12
@ dwarf_d12
Definition: ARM_DWARF_Registers.h:167
dwarf_d0
@ dwarf_d0
Definition: ARM_DWARF_Registers.h:155
lldb_private::UnwindPlan::SetSourceName
void SetSourceName(const char *)
Definition: UnwindPlan.cpp:562
lldb_private::ValueList::GetSize
size_t GetSize()
Definition: Value.cpp:677
dwarf_d11
@ dwarf_d11
Definition: ARM_DWARF_Registers.h:166
dwarf_s12
@ dwarf_s12
Definition: ARM_DWARF_Registers.h:45
lldb_private::DataExtractor::SetData
lldb::offset_t SetData(const void *bytes, lldb::offset_t length, lldb::ByteOrder byte_order)
Set data with a buffer that is caller owned.
Definition: DataExtractor.cpp:225
lldb_private::ExecutionContext::GetProcessRef
Process & GetProcessRef() const
Returns a reference to the process object.
Definition: ExecutionContext.cpp:231
dwarf_d2
@ dwarf_d2
Definition: ARM_DWARF_Registers.h:157
dwarf_s22
@ dwarf_s22
Definition: ARM_DWARF_Registers.h:55
dwarf_r13_svc
@ dwarf_r13_svc
Definition: ARM_DWARF_Registers.h:141
Process.h
dwarf_r14_abt
@ dwarf_r14_abt
Definition: ARM_DWARF_Registers.h:138
dwarf_s13
@ dwarf_s13
Definition: ARM_DWARF_Registers.h:46
dwarf_r14_svc
@ dwarf_r14_svc
Definition: ARM_DWARF_Registers.h:142
dwarf_s18
@ dwarf_s18
Definition: ARM_DWARF_Registers.h:51
lldb_private::CompilerType::IsIntegerOrEnumerationType
bool IsIntegerOrEnumerationType(bool &is_signed) const
Definition: CompilerType.cpp:153
dwarf_s3
@ dwarf_s3
Definition: ARM_DWARF_Registers.h:36
lldb_private::Value::SetCompilerType
void SetCompilerType(const CompilerType &compiler_type)
Definition: Value.cpp:254
dwarf_pc
@ dwarf_pc
Definition: ABISysV_mips.cpp:75
Target.h
dwarf_r10_usr
@ dwarf_r10_usr
Definition: ARM_DWARF_Registers.h:123
lldb_private::DataExtractor::SetByteOrder
void SetByteOrder(lldb::ByteOrder byte_order)
Set the byte_order value.
Definition: DataExtractor.h:931
lldb_private::Value::GetScalar
const Scalar & GetScalar() const
Definition: Value.h:112
lldb_private::CompilerType::IsHomogeneousAggregate
uint32_t IsHomogeneousAggregate(CompilerType *base_type_ptr) const
Definition: CompilerType.cpp:109
lldb_private::Thread::GetProcess
lldb::ProcessSP GetProcess() const
Definition: Thread.h:152
ehframe_r12
@ ehframe_r12
Definition: ARM_ehframe_Registers.h:29
LLDB_REGNUM_GENERIC_FLAGS
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:67
error
static llvm::raw_ostream & error(Stream &strm)
Definition: CommandReturnObject.cpp:17
dwarf_r4
@ dwarf_r4
Definition: ABISysV_mips.cpp:42
ARM_ehframe_Registers.h
dwarf_d10
@ dwarf_d10
Definition: ARM_DWARF_Registers.h:165
dwarf_s9
@ dwarf_s9
Definition: ARM_DWARF_Registers.h:42
ehframe_r8
@ ehframe_r8
Definition: ARM_ehframe_Registers.h:25
dwarf_s17
@ dwarf_s17
Definition: ARM_DWARF_Registers.h:50
lldb_private::DataExtractor
Definition: DataExtractor.h:48
dwarf_s15
@ dwarf_s15
Definition: ARM_DWARF_Registers.h:48
dwarf_r13_und
@ dwarf_r13_und
Definition: ARM_DWARF_Registers.h:139
lldb_private::Thread
Definition: Thread.h:60
dwarf_s21
@ dwarf_s21
Definition: ARM_DWARF_Registers.h:54
lldb_private::Address::GetCallableLoadAddress
lldb::addr_t GetCallableLoadAddress(Target *target, bool is_indirect=false) const
Get the load address as a callable code load address.
Definition: Address.cpp:335
dwarf_d19
@ dwarf_d19
Definition: ARM_DWARF_Registers.h:174
lldb_private::Status::Fail
bool Fail() const
Test for error condition.
Definition: Status.cpp:182
lldb_private::DataExtractor::GetMaxU32
uint32_t GetMaxU32(lldb::offset_t *offset_ptr, size_t byte_size) const
Extract an integer of size byte_size from *offset_ptr.
Definition: DataExtractor.cpp:520
ABISysV_arm::CreateDefaultUnwindPlan
bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override
Definition: ABISysV_arm.cpp:1826
dwarf_s2
@ dwarf_s2
Definition: ARM_DWARF_Registers.h:35
lldb_private::DataExtractor::SetAddressByteSize
void SetAddressByteSize(uint32_t addr_size)
Set the address byte size.
Definition: DataExtractor.h:845
dwarf_d24
@ dwarf_d24
Definition: ARM_DWARF_Registers.h:179
dwarf_r2
@ dwarf_r2
Definition: ABISysV_mips.cpp:40
dwarf_d9
@ dwarf_d9
Definition: ARM_DWARF_Registers.h:164
lldb_private::RegisterContext::GetRegisterInfo
const RegisterInfo * GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num)
Definition: RegisterContext.cpp:80
lldb_private::UnwindPlan::SetSourcedFromCompiler
void SetSourcedFromCompiler(lldb_private::LazyBool from_compiler)
Definition: UnwindPlan.h:480
dwarf_r7
@ dwarf_r7
Definition: ABISysV_mips.cpp:45
dwarf_d6
@ dwarf_d6
Definition: ARM_DWARF_Registers.h:161
lldb_private::Process::GetAddressByteSize
uint32_t GetAddressByteSize() const
Definition: Process.cpp:3340
lldb::eEncodingUint
@ eEncodingUint
unsigned integer
Definition: lldb-enumerations.h:148
dwarf_r1
@ dwarf_r1
Definition: ABISysV_mips.cpp:39
lldb_private::ConstString
Definition: ConstString.h:40
dwarf_s4
@ dwarf_s4
Definition: ARM_DWARF_Registers.h:37
ehframe_r5
@ ehframe_r5
Definition: ARM_ehframe_Registers.h:22
dwarf_r13_irq
@ dwarf_r13_irq
Definition: ARM_DWARF_Registers.h:135
ARMDefines.h
MASK_CPSR_T
#define MASK_CPSR_T
Definition: ARMDefines.h:176
dwarf_r13_usr
@ dwarf_r13_usr
Definition: ARM_DWARF_Registers.h:126
dwarf_r13_fiq
@ dwarf_r13_fiq
Definition: ARM_DWARF_Registers.h:133
ehframe_r4
@ ehframe_r4
Definition: ARM_ehframe_Registers.h:21
dwarf_r14_usr
@ dwarf_r14_usr
Definition: ARM_DWARF_Registers.h:127
ehframe_r6
@ ehframe_r6
Definition: ARM_ehframe_Registers.h:23
sp
@ sp
Definition: CompactUnwindInfo.cpp:1249
dwarf_d8
@ dwarf_d8
Definition: ARM_DWARF_Registers.h:163
lldb_private::CompilerType::GetNumFields
uint32_t GetNumFields() const
Definition: CompilerType.cpp:537
dwarf_s8
@ dwarf_s8
Definition: ARM_DWARF_Registers.h:41
string
string(SUBSTRING ${p} 10 -1 pStripped) if($
Definition: Plugins/CMakeLists.txt:40
dwarf_r11_fiq
@ dwarf_r11_fiq
Definition: ARM_DWARF_Registers.h:131
dwarf_r10
@ dwarf_r10
Definition: ABISysV_mips.cpp:48
dwarf_lr
@ dwarf_lr
Definition: ABISysV_ppc.cpp:105
Thread.h
dwarf_s6
@ dwarf_s6
Definition: ARM_DWARF_Registers.h:39
UnwindPlan.h
lldb_private::RegisterContext::GetSP
uint64_t GetSP(uint64_t fail_value=LLDB_INVALID_ADDRESS)
Definition: RegisterContext.cpp:152
lldb_private::RegisterContext
Definition: RegisterContext.h:17
dwarf_s10
@ dwarf_s10
Definition: ARM_DWARF_Registers.h:43
dwarf_d31
@ dwarf_d31
Definition: ARM_DWARF_Registers.h:186
ARM_DWARF_Registers.h
ehframe_r11
@ ehframe_r11
Definition: ARM_ehframe_Registers.h:28
dwarf_s20
@ dwarf_s20
Definition: ARM_DWARF_Registers.h:53
ABISysV_arm::GetReturnValueObjectImpl
lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread &thread, lldb_private::CompilerType &ast_type) const override
Definition: ABISysV_arm.cpp:1436
lldb_private::RegisterValue::GetAsDouble
double GetAsDouble(double fail_value=0.0, bool *success_ptr=nullptr) const
Definition: RegisterValue.cpp:652
ABISysV_arm.h
dwarf_cpsr
@ dwarf_cpsr
Definition: ARM_DWARF_Registers.h:31
dwarf_r0
@ dwarf_r0
Definition: ABISysV_mips.cpp:38
ValueObjectConstResult.h
lldb_private::UnwindPlan::RowSP
std::shared_ptr< Row > RowSP
Definition: UnwindPlan.h:395
dwarf_s25
@ dwarf_s25
Definition: ARM_DWARF_Registers.h:58
dwarf_d1
@ dwarf_d1
Definition: ARM_DWARF_Registers.h:156
ehframe_pc
@ ehframe_pc
Definition: ARM_ehframe_Registers.h:32
dwarf_r11_usr
@ dwarf_r11_usr
Definition: ARM_DWARF_Registers.h:124
lldb_private::RegisterValue::SetUInt32
void SetUInt32(uint32_t uint, Type t=eTypeUInt32)
Definition: RegisterValue.h:200
dwarf_r8_usr
@ dwarf_r8_usr
Definition: ARM_DWARF_Registers.h:121
lldb_private::UnwindPlan::Clear
void Clear()
Definition: UnwindPlan.h:510
lldb_private::Status
Definition: Status.h:44
k_num_register_infos
static const uint32_t k_num_register_infos
Definition: ABISysV_arm.cpp:1192
dwarf_s0
@ dwarf_s0
Definition: ARM_DWARF_Registers.h:33
dwarf_d4
@ dwarf_d4
Definition: ARM_DWARF_Registers.h:159
ehframe_sp
@ ehframe_sp
Definition: ARM_ehframe_Registers.h:30
lldb_private::RegisterContext::WriteRegisterFromUnsigned
bool WriteRegisterFromUnsigned(uint32_t reg, uint64_t uval)
Definition: RegisterContext.cpp:205
lldb_private::UnwindPlan::Row
Definition: UnwindPlan.h:55
uint32_t
dwarf_s27
@ dwarf_s27
Definition: ARM_DWARF_Registers.h:60
lldb_private::eLazyBoolNo
@ eLazyBoolNo
Definition: lldb-private-enumerations.h:115
dwarf_d17
@ dwarf_d17
Definition: ARM_DWARF_Registers.h:172
dwarf_s26
@ dwarf_s26
Definition: ARM_DWARF_Registers.h:59
lldb_private::Address
Definition: Address.h:59
LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:64
lldb_private::CompilerType::IsPointerType
bool IsPointerType(CompilerType *pointee_type=nullptr) const
Definition: CompilerType.cpp:157
dwarf_r8
@ dwarf_r8
Definition: ABISysV_mips.cpp:46
dwarf_s23
@ dwarf_s23
Definition: ARM_DWARF_Registers.h:56
lldb_private::RegisterValue::GetAsMemoryData
uint32_t GetAsMemoryData(const RegisterInfo *reg_info, void *dst, uint32_t dst_len, lldb::ByteOrder dst_byte_order, Status &error) const
Definition: RegisterValue.cpp:38
dwarf_s16
@ dwarf_s16
Definition: ARM_DWARF_Registers.h:49
dwarf_d30
@ dwarf_d30
Definition: ARM_DWARF_Registers.h:185
lldb_private::CompilerType::GetBitSize
llvm::Optional< uint64_t > GetBitSize(ExecutionContextScope *exe_scope) const
Return the size of the type in bits.
Definition: CompilerType.cpp:482
dwarf_d14
@ dwarf_d14
Definition: ARM_DWARF_Registers.h:169
dwarf_d26
@ dwarf_d26
Definition: ARM_DWARF_Registers.h:181
dwarf_d27
@ dwarf_d27
Definition: ARM_DWARF_Registers.h:182
dwarf_r9_usr
@ dwarf_r9_usr
Definition: ARM_DWARF_Registers.h:122
dwarf_d5
@ dwarf_d5
Definition: ARM_DWARF_Registers.h:160
ehframe_r0
@ ehframe_r0
Definition: ARM_ehframe_Registers.h:17
UINT32_MAX
#define UINT32_MAX
Definition: lldb-defines.h:31
ehframe_lr
@ ehframe_lr
Definition: ARM_ehframe_Registers.h:31
dwarf_r11
@ dwarf_r11
Definition: ABISysV_mips.cpp:49
dwarf_r14_und
@ dwarf_r14_und
Definition: ARM_DWARF_Registers.h:140
lldb_private::RegisterValue::GetAsFloat
float GetAsFloat(float fail_value=0.0f, bool *success_ptr=nullptr) const
Definition: RegisterValue.cpp:633
uint16_t
dwarf_s1
@ dwarf_s1
Definition: ARM_DWARF_Registers.h:34
ABISysV_arm::Terminate
static void Terminate()
Definition: ABISysV_arm.cpp:2027
PluginManager.h
dwarf_s5
@ dwarf_s5
Definition: ARM_DWARF_Registers.h:38
dwarf_d3
@ dwarf_d3
Definition: ARM_DWARF_Registers.h:158
lldb_private::CompilerType
Generic representation of a type in a programming language.
Definition: CompilerType.h:33
dwarf_s24
@ dwarf_s24
Definition: ARM_DWARF_Registers.h:57
g_register_infos
static const RegisterInfo g_register_infos[]
Definition: ABISysV_arm.cpp:39
lldb_private::Value::GetCompilerType
const CompilerType & GetCompilerType()
Definition: Value.cpp:225
Status.h
LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG4
Definition: lldb-defines.h:74
dwarf_d22
@ dwarf_d22
Definition: ARM_DWARF_Registers.h:177
lldb_private::Value::SetBytes
void SetBytes(const void *bytes, int len)
Definition: Value.cpp:90
lldb_private
A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
lldb::eFormatHex
@ eFormatHex
Definition: lldb-enumerations.h:169
ABISysV_arm::IsArmHardFloat
bool IsArmHardFloat(lldb_private::Thread &thread) const
Definition: ABISysV_arm.cpp:1425
dwarf_r9_fiq
@ dwarf_r9_fiq
Definition: ARM_DWARF_Registers.h:129
dwarf_s11
@ dwarf_s11
Definition: ARM_DWARF_Registers.h:44
LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:65
dwarf_r12_fiq
@ dwarf_r12_fiq
Definition: ARM_DWARF_Registers.h:132
dwarf_d15
@ dwarf_d15
Definition: ARM_DWARF_Registers.h:170
ehframe_r10
@ ehframe_r10
Definition: ARM_ehframe_Registers.h:27
dwarf_r3
@ dwarf_r3
Definition: ABISysV_mips.cpp:41
ABISysV_arm::GetPluginName
lldb_private::ConstString GetPluginName() override
Definition: ABISysV_arm.cpp:2038
dwarf_s19
@ dwarf_s19
Definition: ARM_DWARF_Registers.h:52
ABISysV_arm::GetRedZoneSize
size_t GetRedZoneSize() const override
Definition: ABISysV_arm.cpp:1201
LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:63
ABISysV_arm::GetArgumentValues
bool GetArgumentValues(lldb_private::Thread &thread, lldb_private::ValueList &values) const override
Definition: ABISysV_arm.cpp:1327
ConstString.h
ABISysV_arm
Definition: ABISysV_arm.h:15
dwarf_d13
@ dwarf_d13
Definition: ARM_DWARF_Registers.h:168
lldb_private::RegisterValue::SignExtend
bool SignExtend(uint32_t sign_bitpos)
Definition: RegisterValue.cpp:459
ehframe_r7
@ ehframe_r7
Definition: ARM_ehframe_Registers.h:24
LLDB_PLUGIN_DEFINE
#define LLDB_PLUGIN_DEFINE(PluginName)
Definition: PluginManager.h:31
lldb_private::CompilerType::GetFieldAtIndex
CompilerType GetFieldAtIndex(size_t idx, std::string &name, uint64_t *bit_offset_ptr, uint32_t *bitfield_bit_size_ptr, bool *is_bitfield_ptr) const
Definition: CompilerType.cpp:543
dwarf_s30
@ dwarf_s30
Definition: ARM_DWARF_Registers.h:63
lldb_private::Thread::GetStackFrameAtIndex
virtual lldb::StackFrameSP GetStackFrameAtIndex(uint32_t idx)
Definition: Thread.h:397
dwarf_r6
@ dwarf_r6
Definition: ABISysV_mips.cpp:44
lldb_private::Thread::GetRegisterContext
virtual lldb::RegisterContextSP GetRegisterContext()=0
ABISysV_arm::PrepareTrivialCall
bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp, lldb::addr_t func_addr, lldb::addr_t returnAddress, llvm::ArrayRef< lldb::addr_t > args) const override
Definition: ABISysV_arm.cpp:1221
lldb::eFormatFloat
@ eFormatFloat
Definition: lldb-enumerations.h:171
ehframe_r9
@ ehframe_r9
Definition: ARM_ehframe_Registers.h:26
lldb_private::DataBufferHeap
Definition: DataBufferHeap.h:30
lldb_private::UnwindPlan
Definition: UnwindPlan.h:53
lldb
Definition: SBAddress.h:15
RegisterContext.h
dwarf_r12_usr
@ dwarf_r12_usr
Definition: ARM_DWARF_Registers.h:125
Value.h
lldb_private::RegisterValue::GetScalarValue
bool GetScalarValue(Scalar &scalar) const
Definition: RegisterValue.cpp:136
dwarf_d16
@ dwarf_d16
Definition: ARM_DWARF_Registers.h:171
ABISysV_arm::Initialize
static void Initialize()
Definition: ABISysV_arm.cpp:2022
lldb_private::RegisterContext::GetRegisterInfoByName
const RegisterInfo * GetRegisterInfoByName(llvm::StringRef reg_name, uint32_t start_idx=0)
Definition: RegisterContext.cpp:52
MASK_CPSR_IT_MASK
#define MASK_CPSR_IT_MASK
Definition: ARMDefines.h:175
lldb::ByteOrder
ByteOrder
Byte ordering definitions.
Definition: lldb-enumerations.h:138
lldb_private::Status::AsCString
const char * AsCString(const char *default_error_str="unknown error") const
Get the error string associated with the current error.
Definition: Status.cpp:131
LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:66
ABISysV_arm::GetPluginNameStatic
static lldb_private::ConstString GetPluginNameStatic()
Definition: ABISysV_arm.cpp:2031