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EmulateInstructionARM.cpp
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1 //===-- EmulateInstructionARM.cpp -----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include <cstdlib>
10 
11 #include "EmulateInstructionARM.h"
12 #include "EmulationStateARM.h"
13 #include "lldb/Core/Address.h"
15 #include "lldb/Host/PosixApi.h"
18 #include "lldb/Symbol/UnwindPlan.h"
19 #include "lldb/Utility/ArchSpec.h"
21 #include "lldb/Utility/Stream.h"
22 
26 
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/Support/MathExtras.h"
29 
30 using namespace lldb;
31 using namespace lldb_private;
32 
34 
35 // Convenient macro definitions.
36 #define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS)
37 #define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)
38 
39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
40 
41 //
42 // ITSession implementation
43 //
44 
45 static bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo &reg_info) {
46  ::memset(&reg_info, 0, sizeof(RegisterInfo));
47  ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
48 
49  if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
50  reg_info.byte_size = 16;
51  reg_info.format = eFormatVectorOfUInt8;
52  reg_info.encoding = eEncodingVector;
53  }
54 
55  if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) {
56  reg_info.byte_size = 8;
57  reg_info.format = eFormatFloat;
58  reg_info.encoding = eEncodingIEEE754;
59  } else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31) {
60  reg_info.byte_size = 4;
61  reg_info.format = eFormatFloat;
62  reg_info.encoding = eEncodingIEEE754;
63  } else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7) {
64  reg_info.byte_size = 12;
65  reg_info.format = eFormatFloat;
66  reg_info.encoding = eEncodingIEEE754;
67  } else {
68  reg_info.byte_size = 4;
69  reg_info.format = eFormatHex;
70  reg_info.encoding = eEncodingUint;
71  }
72 
73  reg_info.kinds[eRegisterKindDWARF] = reg_num;
74 
75  switch (reg_num) {
76  case dwarf_r0:
77  reg_info.name = "r0";
78  break;
79  case dwarf_r1:
80  reg_info.name = "r1";
81  break;
82  case dwarf_r2:
83  reg_info.name = "r2";
84  break;
85  case dwarf_r3:
86  reg_info.name = "r3";
87  break;
88  case dwarf_r4:
89  reg_info.name = "r4";
90  break;
91  case dwarf_r5:
92  reg_info.name = "r5";
93  break;
94  case dwarf_r6:
95  reg_info.name = "r6";
96  break;
97  case dwarf_r7:
98  reg_info.name = "r7";
100  break;
101  case dwarf_r8:
102  reg_info.name = "r8";
103  break;
104  case dwarf_r9:
105  reg_info.name = "r9";
106  break;
107  case dwarf_r10:
108  reg_info.name = "r10";
109  break;
110  case dwarf_r11:
111  reg_info.name = "r11";
112  break;
113  case dwarf_r12:
114  reg_info.name = "r12";
115  break;
116  case dwarf_sp:
117  reg_info.name = "sp";
118  reg_info.alt_name = "r13";
120  break;
121  case dwarf_lr:
122  reg_info.name = "lr";
123  reg_info.alt_name = "r14";
125  break;
126  case dwarf_pc:
127  reg_info.name = "pc";
128  reg_info.alt_name = "r15";
130  break;
131  case dwarf_cpsr:
132  reg_info.name = "cpsr";
134  break;
135 
136  case dwarf_s0:
137  reg_info.name = "s0";
138  break;
139  case dwarf_s1:
140  reg_info.name = "s1";
141  break;
142  case dwarf_s2:
143  reg_info.name = "s2";
144  break;
145  case dwarf_s3:
146  reg_info.name = "s3";
147  break;
148  case dwarf_s4:
149  reg_info.name = "s4";
150  break;
151  case dwarf_s5:
152  reg_info.name = "s5";
153  break;
154  case dwarf_s6:
155  reg_info.name = "s6";
156  break;
157  case dwarf_s7:
158  reg_info.name = "s7";
159  break;
160  case dwarf_s8:
161  reg_info.name = "s8";
162  break;
163  case dwarf_s9:
164  reg_info.name = "s9";
165  break;
166  case dwarf_s10:
167  reg_info.name = "s10";
168  break;
169  case dwarf_s11:
170  reg_info.name = "s11";
171  break;
172  case dwarf_s12:
173  reg_info.name = "s12";
174  break;
175  case dwarf_s13:
176  reg_info.name = "s13";
177  break;
178  case dwarf_s14:
179  reg_info.name = "s14";
180  break;
181  case dwarf_s15:
182  reg_info.name = "s15";
183  break;
184  case dwarf_s16:
185  reg_info.name = "s16";
186  break;
187  case dwarf_s17:
188  reg_info.name = "s17";
189  break;
190  case dwarf_s18:
191  reg_info.name = "s18";
192  break;
193  case dwarf_s19:
194  reg_info.name = "s19";
195  break;
196  case dwarf_s20:
197  reg_info.name = "s20";
198  break;
199  case dwarf_s21:
200  reg_info.name = "s21";
201  break;
202  case dwarf_s22:
203  reg_info.name = "s22";
204  break;
205  case dwarf_s23:
206  reg_info.name = "s23";
207  break;
208  case dwarf_s24:
209  reg_info.name = "s24";
210  break;
211  case dwarf_s25:
212  reg_info.name = "s25";
213  break;
214  case dwarf_s26:
215  reg_info.name = "s26";
216  break;
217  case dwarf_s27:
218  reg_info.name = "s27";
219  break;
220  case dwarf_s28:
221  reg_info.name = "s28";
222  break;
223  case dwarf_s29:
224  reg_info.name = "s29";
225  break;
226  case dwarf_s30:
227  reg_info.name = "s30";
228  break;
229  case dwarf_s31:
230  reg_info.name = "s31";
231  break;
232 
233  // FPA Registers 0-7
234  case dwarf_f0:
235  reg_info.name = "f0";
236  break;
237  case dwarf_f1:
238  reg_info.name = "f1";
239  break;
240  case dwarf_f2:
241  reg_info.name = "f2";
242  break;
243  case dwarf_f3:
244  reg_info.name = "f3";
245  break;
246  case dwarf_f4:
247  reg_info.name = "f4";
248  break;
249  case dwarf_f5:
250  reg_info.name = "f5";
251  break;
252  case dwarf_f6:
253  reg_info.name = "f6";
254  break;
255  case dwarf_f7:
256  reg_info.name = "f7";
257  break;
258 
259  // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator
260  // register 0 - 7 (they do overlap with wCGR0 - wCGR7)
261  case dwarf_wCGR0:
262  reg_info.name = "wCGR0/ACC0";
263  break;
264  case dwarf_wCGR1:
265  reg_info.name = "wCGR1/ACC1";
266  break;
267  case dwarf_wCGR2:
268  reg_info.name = "wCGR2/ACC2";
269  break;
270  case dwarf_wCGR3:
271  reg_info.name = "wCGR3/ACC3";
272  break;
273  case dwarf_wCGR4:
274  reg_info.name = "wCGR4/ACC4";
275  break;
276  case dwarf_wCGR5:
277  reg_info.name = "wCGR5/ACC5";
278  break;
279  case dwarf_wCGR6:
280  reg_info.name = "wCGR6/ACC6";
281  break;
282  case dwarf_wCGR7:
283  reg_info.name = "wCGR7/ACC7";
284  break;
285 
286  // Intel wireless MMX data registers 0 - 15
287  case dwarf_wR0:
288  reg_info.name = "wR0";
289  break;
290  case dwarf_wR1:
291  reg_info.name = "wR1";
292  break;
293  case dwarf_wR2:
294  reg_info.name = "wR2";
295  break;
296  case dwarf_wR3:
297  reg_info.name = "wR3";
298  break;
299  case dwarf_wR4:
300  reg_info.name = "wR4";
301  break;
302  case dwarf_wR5:
303  reg_info.name = "wR5";
304  break;
305  case dwarf_wR6:
306  reg_info.name = "wR6";
307  break;
308  case dwarf_wR7:
309  reg_info.name = "wR7";
310  break;
311  case dwarf_wR8:
312  reg_info.name = "wR8";
313  break;
314  case dwarf_wR9:
315  reg_info.name = "wR9";
316  break;
317  case dwarf_wR10:
318  reg_info.name = "wR10";
319  break;
320  case dwarf_wR11:
321  reg_info.name = "wR11";
322  break;
323  case dwarf_wR12:
324  reg_info.name = "wR12";
325  break;
326  case dwarf_wR13:
327  reg_info.name = "wR13";
328  break;
329  case dwarf_wR14:
330  reg_info.name = "wR14";
331  break;
332  case dwarf_wR15:
333  reg_info.name = "wR15";
334  break;
335 
336  case dwarf_spsr:
337  reg_info.name = "spsr";
338  break;
339  case dwarf_spsr_fiq:
340  reg_info.name = "spsr_fiq";
341  break;
342  case dwarf_spsr_irq:
343  reg_info.name = "spsr_irq";
344  break;
345  case dwarf_spsr_abt:
346  reg_info.name = "spsr_abt";
347  break;
348  case dwarf_spsr_und:
349  reg_info.name = "spsr_und";
350  break;
351  case dwarf_spsr_svc:
352  reg_info.name = "spsr_svc";
353  break;
354 
355  case dwarf_r8_usr:
356  reg_info.name = "r8_usr";
357  break;
358  case dwarf_r9_usr:
359  reg_info.name = "r9_usr";
360  break;
361  case dwarf_r10_usr:
362  reg_info.name = "r10_usr";
363  break;
364  case dwarf_r11_usr:
365  reg_info.name = "r11_usr";
366  break;
367  case dwarf_r12_usr:
368  reg_info.name = "r12_usr";
369  break;
370  case dwarf_r13_usr:
371  reg_info.name = "r13_usr";
372  break;
373  case dwarf_r14_usr:
374  reg_info.name = "r14_usr";
375  break;
376  case dwarf_r8_fiq:
377  reg_info.name = "r8_fiq";
378  break;
379  case dwarf_r9_fiq:
380  reg_info.name = "r9_fiq";
381  break;
382  case dwarf_r10_fiq:
383  reg_info.name = "r10_fiq";
384  break;
385  case dwarf_r11_fiq:
386  reg_info.name = "r11_fiq";
387  break;
388  case dwarf_r12_fiq:
389  reg_info.name = "r12_fiq";
390  break;
391  case dwarf_r13_fiq:
392  reg_info.name = "r13_fiq";
393  break;
394  case dwarf_r14_fiq:
395  reg_info.name = "r14_fiq";
396  break;
397  case dwarf_r13_irq:
398  reg_info.name = "r13_irq";
399  break;
400  case dwarf_r14_irq:
401  reg_info.name = "r14_irq";
402  break;
403  case dwarf_r13_abt:
404  reg_info.name = "r13_abt";
405  break;
406  case dwarf_r14_abt:
407  reg_info.name = "r14_abt";
408  break;
409  case dwarf_r13_und:
410  reg_info.name = "r13_und";
411  break;
412  case dwarf_r14_und:
413  reg_info.name = "r14_und";
414  break;
415  case dwarf_r13_svc:
416  reg_info.name = "r13_svc";
417  break;
418  case dwarf_r14_svc:
419  reg_info.name = "r14_svc";
420  break;
421 
422  // Intel wireless MMX control register in co-processor 0 - 7
423  case dwarf_wC0:
424  reg_info.name = "wC0";
425  break;
426  case dwarf_wC1:
427  reg_info.name = "wC1";
428  break;
429  case dwarf_wC2:
430  reg_info.name = "wC2";
431  break;
432  case dwarf_wC3:
433  reg_info.name = "wC3";
434  break;
435  case dwarf_wC4:
436  reg_info.name = "wC4";
437  break;
438  case dwarf_wC5:
439  reg_info.name = "wC5";
440  break;
441  case dwarf_wC6:
442  reg_info.name = "wC6";
443  break;
444  case dwarf_wC7:
445  reg_info.name = "wC7";
446  break;
447 
448  // VFP-v3/Neon
449  case dwarf_d0:
450  reg_info.name = "d0";
451  break;
452  case dwarf_d1:
453  reg_info.name = "d1";
454  break;
455  case dwarf_d2:
456  reg_info.name = "d2";
457  break;
458  case dwarf_d3:
459  reg_info.name = "d3";
460  break;
461  case dwarf_d4:
462  reg_info.name = "d4";
463  break;
464  case dwarf_d5:
465  reg_info.name = "d5";
466  break;
467  case dwarf_d6:
468  reg_info.name = "d6";
469  break;
470  case dwarf_d7:
471  reg_info.name = "d7";
472  break;
473  case dwarf_d8:
474  reg_info.name = "d8";
475  break;
476  case dwarf_d9:
477  reg_info.name = "d9";
478  break;
479  case dwarf_d10:
480  reg_info.name = "d10";
481  break;
482  case dwarf_d11:
483  reg_info.name = "d11";
484  break;
485  case dwarf_d12:
486  reg_info.name = "d12";
487  break;
488  case dwarf_d13:
489  reg_info.name = "d13";
490  break;
491  case dwarf_d14:
492  reg_info.name = "d14";
493  break;
494  case dwarf_d15:
495  reg_info.name = "d15";
496  break;
497  case dwarf_d16:
498  reg_info.name = "d16";
499  break;
500  case dwarf_d17:
501  reg_info.name = "d17";
502  break;
503  case dwarf_d18:
504  reg_info.name = "d18";
505  break;
506  case dwarf_d19:
507  reg_info.name = "d19";
508  break;
509  case dwarf_d20:
510  reg_info.name = "d20";
511  break;
512  case dwarf_d21:
513  reg_info.name = "d21";
514  break;
515  case dwarf_d22:
516  reg_info.name = "d22";
517  break;
518  case dwarf_d23:
519  reg_info.name = "d23";
520  break;
521  case dwarf_d24:
522  reg_info.name = "d24";
523  break;
524  case dwarf_d25:
525  reg_info.name = "d25";
526  break;
527  case dwarf_d26:
528  reg_info.name = "d26";
529  break;
530  case dwarf_d27:
531  reg_info.name = "d27";
532  break;
533  case dwarf_d28:
534  reg_info.name = "d28";
535  break;
536  case dwarf_d29:
537  reg_info.name = "d29";
538  break;
539  case dwarf_d30:
540  reg_info.name = "d30";
541  break;
542  case dwarf_d31:
543  reg_info.name = "d31";
544  break;
545 
546  // NEON 128-bit vector registers (overlays the d registers)
547  case dwarf_q0:
548  reg_info.name = "q0";
549  break;
550  case dwarf_q1:
551  reg_info.name = "q1";
552  break;
553  case dwarf_q2:
554  reg_info.name = "q2";
555  break;
556  case dwarf_q3:
557  reg_info.name = "q3";
558  break;
559  case dwarf_q4:
560  reg_info.name = "q4";
561  break;
562  case dwarf_q5:
563  reg_info.name = "q5";
564  break;
565  case dwarf_q6:
566  reg_info.name = "q6";
567  break;
568  case dwarf_q7:
569  reg_info.name = "q7";
570  break;
571  case dwarf_q8:
572  reg_info.name = "q8";
573  break;
574  case dwarf_q9:
575  reg_info.name = "q9";
576  break;
577  case dwarf_q10:
578  reg_info.name = "q10";
579  break;
580  case dwarf_q11:
581  reg_info.name = "q11";
582  break;
583  case dwarf_q12:
584  reg_info.name = "q12";
585  break;
586  case dwarf_q13:
587  reg_info.name = "q13";
588  break;
589  case dwarf_q14:
590  reg_info.name = "q14";
591  break;
592  case dwarf_q15:
593  reg_info.name = "q15";
594  break;
595 
596  default:
597  return false;
598  }
599  return true;
600 }
601 
602 // A8.6.50
603 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
604 static uint32_t CountITSize(uint32_t ITMask) {
605  // First count the trailing zeros of the IT mask.
606  uint32_t TZ = llvm::countTrailingZeros(ITMask);
607  if (TZ > 3) {
608  return 0;
609  }
610  return (4 - TZ);
611 }
612 
613 // Init ITState. Note that at least one bit is always 1 in mask.
614 bool ITSession::InitIT(uint32_t bits7_0) {
615  ITCounter = CountITSize(Bits32(bits7_0, 3, 0));
616  if (ITCounter == 0)
617  return false;
618 
619  // A8.6.50 IT
620  unsigned short FirstCond = Bits32(bits7_0, 7, 4);
621  if (FirstCond == 0xF) {
622  return false;
623  }
624  if (FirstCond == 0xE && ITCounter != 1) {
625  return false;
626  }
627 
628  ITState = bits7_0;
629  return true;
630 }
631 
632 // Update ITState if necessary.
633 void ITSession::ITAdvance() {
634  // assert(ITCounter);
635  --ITCounter;
636  if (ITCounter == 0)
637  ITState = 0;
638  else {
639  unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1;
640  SetBits32(ITState, 4, 0, NewITState4_0);
641  }
642 }
643 
644 // Return true if we're inside an IT Block.
645 bool ITSession::InITBlock() { return ITCounter != 0; }
646 
647 // Return true if we're the last instruction inside an IT Block.
648 bool ITSession::LastInITBlock() { return ITCounter == 1; }
649 
650 // Get condition bits for the current thumb instruction.
651 uint32_t ITSession::GetCond() {
652  if (InITBlock())
653  return Bits32(ITState, 7, 4);
654  else
655  return COND_AL;
656 }
657 
658 // ARM constants used during decoding
659 #define REG_RD 0
660 #define LDM_REGLIST 1
661 #define SP_REG 13
662 #define LR_REG 14
663 #define PC_REG 15
664 #define PC_REGLIST_BIT 0x8000
665 
666 #define ARMv4 (1u << 0)
667 #define ARMv4T (1u << 1)
668 #define ARMv5T (1u << 2)
669 #define ARMv5TE (1u << 3)
670 #define ARMv5TEJ (1u << 4)
671 #define ARMv6 (1u << 5)
672 #define ARMv6K (1u << 6)
673 #define ARMv6T2 (1u << 7)
674 #define ARMv7 (1u << 8)
675 #define ARMv7S (1u << 9)
676 #define ARMv8 (1u << 10)
677 #define ARMvAll (0xffffffffu)
678 
679 #define ARMV4T_ABOVE \
680  (ARMv4T | ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | \
681  ARMv7S | ARMv8)
682 #define ARMV5_ABOVE \
683  (ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | \
684  ARMv8)
685 #define ARMV5TE_ABOVE \
686  (ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
687 #define ARMV5J_ABOVE \
688  (ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
689 #define ARMV6_ABOVE (ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
690 #define ARMV6T2_ABOVE (ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
691 #define ARMV7_ABOVE (ARMv7 | ARMv7S | ARMv8)
692 
693 #define No_VFP 0
694 #define VFPv1 (1u << 1)
695 #define VFPv2 (1u << 2)
696 #define VFPv3 (1u << 3)
697 #define AdvancedSIMD (1u << 4)
698 
699 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
700 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
701 #define VFPv2v3 (VFPv2 | VFPv3)
702 
703 //
704 // EmulateInstructionARM implementation
705 //
706 
707 void EmulateInstructionARM::Initialize() {
708  PluginManager::RegisterPlugin(GetPluginNameStatic(),
709  GetPluginDescriptionStatic(), CreateInstance);
710 }
711 
712 void EmulateInstructionARM::Terminate() {
713  PluginManager::UnregisterPlugin(CreateInstance);
714 }
715 
716 ConstString EmulateInstructionARM::GetPluginNameStatic() {
717  static ConstString g_name("arm");
718  return g_name;
719 }
720 
721 const char *EmulateInstructionARM::GetPluginDescriptionStatic() {
722  return "Emulate instructions for the ARM architecture.";
723 }
724 
726 EmulateInstructionARM::CreateInstance(const ArchSpec &arch,
727  InstructionType inst_type) {
728  if (EmulateInstructionARM::SupportsEmulatingInstructionsOfTypeStatic(
729  inst_type)) {
730  if (arch.GetTriple().getArch() == llvm::Triple::arm) {
731  std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
732  new EmulateInstructionARM(arch));
733 
734  if (emulate_insn_up)
735  return emulate_insn_up.release();
736  } else if (arch.GetTriple().getArch() == llvm::Triple::thumb) {
737  std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
738  new EmulateInstructionARM(arch));
739 
740  if (emulate_insn_up)
741  return emulate_insn_up.release();
742  }
743  }
744 
745  return nullptr;
746 }
747 
748 bool EmulateInstructionARM::SetTargetTriple(const ArchSpec &arch) {
749  if (arch.GetTriple().getArch() == llvm::Triple::arm)
750  return true;
751  else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
752  return true;
753 
754  return false;
755 }
756 
757 // Write "bits (32) UNKNOWN" to memory address "address". Helper function for
758 // many ARM instructions.
759 bool EmulateInstructionARM::WriteBits32UnknownToMemory(addr_t address) {
761  context.type = EmulateInstruction::eContextWriteMemoryRandomBits;
762  context.SetNoArgs();
763 
764  uint32_t random_data = rand();
765  const uint32_t addr_byte_size = GetAddressByteSize();
766 
767  return MemAWrite(context, address, random_data, addr_byte_size);
768 }
769 
770 // Write "bits (32) UNKNOWN" to register n. Helper function for many ARM
771 // instructions.
772 bool EmulateInstructionARM::WriteBits32Unknown(int n) {
774  context.type = EmulateInstruction::eContextWriteRegisterRandomBits;
775  context.SetNoArgs();
776 
777  bool success;
778  uint32_t data =
779  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
780 
781  if (!success)
782  return false;
783 
784  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, data))
785  return false;
786 
787  return true;
788 }
789 
790 bool EmulateInstructionARM::GetRegisterInfo(lldb::RegisterKind reg_kind,
791  uint32_t reg_num,
792  RegisterInfo &reg_info) {
793  if (reg_kind == eRegisterKindGeneric) {
794  switch (reg_num) {
796  reg_kind = eRegisterKindDWARF;
797  reg_num = dwarf_pc;
798  break;
800  reg_kind = eRegisterKindDWARF;
801  reg_num = dwarf_sp;
802  break;
804  reg_kind = eRegisterKindDWARF;
805  reg_num = dwarf_r7;
806  break;
808  reg_kind = eRegisterKindDWARF;
809  reg_num = dwarf_lr;
810  break;
812  reg_kind = eRegisterKindDWARF;
813  reg_num = dwarf_cpsr;
814  break;
815  default:
816  return false;
817  }
818  }
819 
820  if (reg_kind == eRegisterKindDWARF)
821  return GetARMDWARFRegisterInfo(reg_num, reg_info);
822  return false;
823 }
824 
825 uint32_t EmulateInstructionARM::GetFramePointerRegisterNumber() const {
826  if (m_arch.GetTriple().isAndroid())
827  return LLDB_INVALID_REGNUM; // Don't use frame pointer on android
828  bool is_apple = false;
829  if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple)
830  is_apple = true;
831  switch (m_arch.GetTriple().getOS()) {
832  case llvm::Triple::Darwin:
833  case llvm::Triple::MacOSX:
834  case llvm::Triple::IOS:
835  case llvm::Triple::TvOS:
836  case llvm::Triple::WatchOS:
837  // NEED_BRIDGEOS_TRIPLE case llvm::Triple::BridgeOS:
838  is_apple = true;
839  break;
840  default:
841  break;
842  }
843 
844  /* On Apple iOS et al, the frame pointer register is always r7.
845  * Typically on other ARM systems, thumb code uses r7; arm code uses r11.
846  * Windows on ARM, which is in thumb mode, uses r11 though.
847  */
848 
849  uint32_t fp_regnum = 11;
850 
851  if (is_apple)
852  fp_regnum = 7;
853 
854  if (m_opcode_mode == eModeThumb && !m_arch.GetTriple().isOSWindows())
855  fp_regnum = 7;
856 
857  return fp_regnum;
858 }
859 
860 uint32_t EmulateInstructionARM::GetFramePointerDWARFRegisterNumber() const {
861  bool is_apple = false;
862  if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple)
863  is_apple = true;
864  switch (m_arch.GetTriple().getOS()) {
865  case llvm::Triple::Darwin:
866  case llvm::Triple::MacOSX:
867  case llvm::Triple::IOS:
868  is_apple = true;
869  break;
870  default:
871  break;
872  }
873 
874  /* On Apple iOS et al, the frame pointer register is always r7.
875  * Typically on other ARM systems, thumb code uses r7; arm code uses r11.
876  * Windows on ARM, which is in thumb mode, uses r11 though.
877  */
878 
879  uint32_t fp_regnum = dwarf_r11;
880 
881  if (is_apple)
882  fp_regnum = dwarf_r7;
883 
884  if (m_opcode_mode == eModeThumb && !m_arch.GetTriple().isOSWindows())
885  fp_regnum = dwarf_r7;
886 
887  return fp_regnum;
888 }
889 
890 // Push Multiple Registers stores multiple registers to the stack, storing to
891 // consecutive memory locations ending just below the address in SP, and
892 // updates
893 // SP to point to the start of the stored data.
894 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode,
895  const ARMEncoding encoding) {
896 #if 0
897  // ARM pseudo code...
898  if (ConditionPassed())
899  {
900  EncodingSpecificOperations();
901  NullCheckIfThumbEE(13);
902  address = SP - 4*BitCount(registers);
903 
904  for (i = 0 to 14)
905  {
906  if (registers<i> == '1')
907  {
908  if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1
909  MemA[address,4] = bits(32) UNKNOWN;
910  else
911  MemA[address,4] = R[i];
912  address = address + 4;
913  }
914  }
915 
916  if (registers<15> == '1') // Only possible for encoding A1 or A2
917  MemA[address,4] = PCStoreValue();
918 
919  SP = SP - 4*BitCount(registers);
920  }
921 #endif
922 
923  bool success = false;
924  if (ConditionPassed(opcode)) {
925  const uint32_t addr_byte_size = GetAddressByteSize();
926  const addr_t sp = ReadCoreReg(SP_REG, &success);
927  if (!success)
928  return false;
929  uint32_t registers = 0;
930  uint32_t Rt; // the source register
931  switch (encoding) {
932  case eEncodingT1:
933  registers = Bits32(opcode, 7, 0);
934  // The M bit represents LR.
935  if (Bit32(opcode, 8))
936  registers |= (1u << 14);
937  // if BitCount(registers) < 1 then UNPREDICTABLE;
938  if (BitCount(registers) < 1)
939  return false;
940  break;
941  case eEncodingT2:
942  // Ignore bits 15 & 13.
943  registers = Bits32(opcode, 15, 0) & ~0xa000;
944  // if BitCount(registers) < 2 then UNPREDICTABLE;
945  if (BitCount(registers) < 2)
946  return false;
947  break;
948  case eEncodingT3:
949  Rt = Bits32(opcode, 15, 12);
950  // if BadReg(t) then UNPREDICTABLE;
951  if (BadReg(Rt))
952  return false;
953  registers = (1u << Rt);
954  break;
955  case eEncodingA1:
956  registers = Bits32(opcode, 15, 0);
957  // Instead of return false, let's handle the following case as well,
958  // which amounts to pushing one reg onto the full descending stacks.
959  // if BitCount(register_list) < 2 then SEE STMDB / STMFD;
960  break;
961  case eEncodingA2:
962  Rt = Bits32(opcode, 15, 12);
963  // if t == 13 then UNPREDICTABLE;
964  if (Rt == dwarf_sp)
965  return false;
966  registers = (1u << Rt);
967  break;
968  default:
969  return false;
970  }
971  addr_t sp_offset = addr_byte_size * BitCount(registers);
972  addr_t addr = sp - sp_offset;
973  uint32_t i;
974 
976  context.type = EmulateInstruction::eContextPushRegisterOnStack;
977  RegisterInfo reg_info;
978  RegisterInfo sp_reg;
979  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
980  for (i = 0; i < 15; ++i) {
981  if (BitIsSet(registers, i)) {
982  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, reg_info);
983  context.SetRegisterToRegisterPlusOffset(reg_info, sp_reg, addr - sp);
984  uint32_t reg_value = ReadCoreReg(i, &success);
985  if (!success)
986  return false;
987  if (!MemAWrite(context, addr, reg_value, addr_byte_size))
988  return false;
989  addr += addr_byte_size;
990  }
991  }
992 
993  if (BitIsSet(registers, 15)) {
994  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, reg_info);
995  context.SetRegisterToRegisterPlusOffset(reg_info, sp_reg, addr - sp);
996  const uint32_t pc = ReadCoreReg(PC_REG, &success);
997  if (!success)
998  return false;
999  if (!MemAWrite(context, addr, pc, addr_byte_size))
1000  return false;
1001  }
1002 
1003  context.type = EmulateInstruction::eContextAdjustStackPointer;
1004  context.SetImmediateSigned(-sp_offset);
1005 
1006  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
1007  LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
1008  return false;
1009  }
1010  return true;
1011 }
1012 
1013 // Pop Multiple Registers loads multiple registers from the stack, loading from
1014 // consecutive memory locations staring at the address in SP, and updates
1015 // SP to point just above the loaded data.
1016 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode,
1017  const ARMEncoding encoding) {
1018 #if 0
1019  // ARM pseudo code...
1020  if (ConditionPassed())
1021  {
1022  EncodingSpecificOperations(); NullCheckIfThumbEE(13);
1023  address = SP;
1024  for i = 0 to 14
1025  if registers<i> == '1' then
1026  R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
1027  if registers<15> == '1' then
1028  if UnalignedAllowed then
1029  LoadWritePC(MemU[address,4]);
1030  else
1031  LoadWritePC(MemA[address,4]);
1032  if registers<13> == '0' then SP = SP + 4*BitCount(registers);
1033  if registers<13> == '1' then SP = bits(32) UNKNOWN;
1034  }
1035 #endif
1036 
1037  bool success = false;
1038 
1039  if (ConditionPassed(opcode)) {
1040  const uint32_t addr_byte_size = GetAddressByteSize();
1041  const addr_t sp = ReadCoreReg(SP_REG, &success);
1042  if (!success)
1043  return false;
1044  uint32_t registers = 0;
1045  uint32_t Rt; // the destination register
1046  switch (encoding) {
1047  case eEncodingT1:
1048  registers = Bits32(opcode, 7, 0);
1049  // The P bit represents PC.
1050  if (Bit32(opcode, 8))
1051  registers |= (1u << 15);
1052  // if BitCount(registers) < 1 then UNPREDICTABLE;
1053  if (BitCount(registers) < 1)
1054  return false;
1055  break;
1056  case eEncodingT2:
1057  // Ignore bit 13.
1058  registers = Bits32(opcode, 15, 0) & ~0x2000;
1059  // if BitCount(registers) < 2 || (P == '1' && M == '1') then
1060  // UNPREDICTABLE;
1061  if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14)))
1062  return false;
1063  // if registers<15> == '1' && InITBlock() && !LastInITBlock() then
1064  // UNPREDICTABLE;
1065  if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
1066  return false;
1067  break;
1068  case eEncodingT3:
1069  Rt = Bits32(opcode, 15, 12);
1070  // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then
1071  // UNPREDICTABLE;
1072  if (Rt == 13)
1073  return false;
1074  if (Rt == 15 && InITBlock() && !LastInITBlock())
1075  return false;
1076  registers = (1u << Rt);
1077  break;
1078  case eEncodingA1:
1079  registers = Bits32(opcode, 15, 0);
1080  // Instead of return false, let's handle the following case as well,
1081  // which amounts to popping one reg from the full descending stacks.
1082  // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD;
1083 
1084  // if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE;
1085  if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7)
1086  return false;
1087  break;
1088  case eEncodingA2:
1089  Rt = Bits32(opcode, 15, 12);
1090  // if t == 13 then UNPREDICTABLE;
1091  if (Rt == dwarf_sp)
1092  return false;
1093  registers = (1u << Rt);
1094  break;
1095  default:
1096  return false;
1097  }
1098  addr_t sp_offset = addr_byte_size * BitCount(registers);
1099  addr_t addr = sp;
1100  uint32_t i, data;
1101 
1103  context.type = EmulateInstruction::eContextPopRegisterOffStack;
1104 
1105  RegisterInfo sp_reg;
1106  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1107 
1108  for (i = 0; i < 15; ++i) {
1109  if (BitIsSet(registers, i)) {
1110  context.SetAddress(addr);
1111  data = MemARead(context, addr, 4, 0, &success);
1112  if (!success)
1113  return false;
1114  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
1115  data))
1116  return false;
1117  addr += addr_byte_size;
1118  }
1119  }
1120 
1121  if (BitIsSet(registers, 15)) {
1122  context.SetRegisterPlusOffset(sp_reg, addr - sp);
1123  data = MemARead(context, addr, 4, 0, &success);
1124  if (!success)
1125  return false;
1126  // In ARMv5T and above, this is an interworking branch.
1127  if (!LoadWritePC(context, data))
1128  return false;
1129  // addr += addr_byte_size;
1130  }
1131 
1132  context.type = EmulateInstruction::eContextAdjustStackPointer;
1133  context.SetImmediateSigned(sp_offset);
1134 
1135  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
1136  LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
1137  return false;
1138  }
1139  return true;
1140 }
1141 
1142 // Set r7 or ip to point to saved value residing within the stack.
1143 // ADD (SP plus immediate)
1144 bool EmulateInstructionARM::EmulateADDRdSPImm(const uint32_t opcode,
1145  const ARMEncoding encoding) {
1146 #if 0
1147  // ARM pseudo code...
1148  if (ConditionPassed())
1149  {
1150  EncodingSpecificOperations();
1151  (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
1152  if d == 15 then
1153  ALUWritePC(result); // setflags is always FALSE here
1154  else
1155  R[d] = result;
1156  if setflags then
1157  APSR.N = result<31>;
1158  APSR.Z = IsZeroBit(result);
1159  APSR.C = carry;
1160  APSR.V = overflow;
1161  }
1162 #endif
1163 
1164  bool success = false;
1165 
1166  if (ConditionPassed(opcode)) {
1167  const addr_t sp = ReadCoreReg(SP_REG, &success);
1168  if (!success)
1169  return false;
1170  uint32_t Rd; // the destination register
1171  uint32_t imm32;
1172  switch (encoding) {
1173  case eEncodingT1:
1174  Rd = 7;
1175  imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
1176  break;
1177  case eEncodingA1:
1178  Rd = Bits32(opcode, 15, 12);
1179  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1180  break;
1181  default:
1182  return false;
1183  }
1184  addr_t sp_offset = imm32;
1185  addr_t addr = sp + sp_offset; // a pointer to the stack area
1186 
1188  if (Rd == GetFramePointerRegisterNumber())
1189  context.type = eContextSetFramePointer;
1190  else
1191  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1192  RegisterInfo sp_reg;
1193  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1194  context.SetRegisterPlusOffset(sp_reg, sp_offset);
1195 
1196  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd,
1197  addr))
1198  return false;
1199  }
1200  return true;
1201 }
1202 
1203 // Set r7 or ip to the current stack pointer.
1204 // MOV (register)
1205 bool EmulateInstructionARM::EmulateMOVRdSP(const uint32_t opcode,
1206  const ARMEncoding encoding) {
1207 #if 0
1208  // ARM pseudo code...
1209  if (ConditionPassed())
1210  {
1211  EncodingSpecificOperations();
1212  result = R[m];
1213  if d == 15 then
1214  ALUWritePC(result); // setflags is always FALSE here
1215  else
1216  R[d] = result;
1217  if setflags then
1218  APSR.N = result<31>;
1219  APSR.Z = IsZeroBit(result);
1220  // APSR.C unchanged
1221  // APSR.V unchanged
1222  }
1223 #endif
1224 
1225  bool success = false;
1226 
1227  if (ConditionPassed(opcode)) {
1228  const addr_t sp = ReadCoreReg(SP_REG, &success);
1229  if (!success)
1230  return false;
1231  uint32_t Rd; // the destination register
1232  switch (encoding) {
1233  case eEncodingT1:
1234  Rd = 7;
1235  break;
1236  case eEncodingA1:
1237  Rd = 12;
1238  break;
1239  default:
1240  return false;
1241  }
1242 
1244  if (Rd == GetFramePointerRegisterNumber())
1245  context.type = EmulateInstruction::eContextSetFramePointer;
1246  else
1247  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1248  RegisterInfo sp_reg;
1249  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1250  context.SetRegisterPlusOffset(sp_reg, 0);
1251 
1252  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
1253  return false;
1254  }
1255  return true;
1256 }
1257 
1258 // Move from high register (r8-r15) to low register (r0-r7).
1259 // MOV (register)
1260 bool EmulateInstructionARM::EmulateMOVLowHigh(const uint32_t opcode,
1261  const ARMEncoding encoding) {
1262  return EmulateMOVRdRm(opcode, encoding);
1263 }
1264 
1265 // Move from register to register.
1266 // MOV (register)
1267 bool EmulateInstructionARM::EmulateMOVRdRm(const uint32_t opcode,
1268  const ARMEncoding encoding) {
1269 #if 0
1270  // ARM pseudo code...
1271  if (ConditionPassed())
1272  {
1273  EncodingSpecificOperations();
1274  result = R[m];
1275  if d == 15 then
1276  ALUWritePC(result); // setflags is always FALSE here
1277  else
1278  R[d] = result;
1279  if setflags then
1280  APSR.N = result<31>;
1281  APSR.Z = IsZeroBit(result);
1282  // APSR.C unchanged
1283  // APSR.V unchanged
1284  }
1285 #endif
1286 
1287  bool success = false;
1288 
1289  if (ConditionPassed(opcode)) {
1290  uint32_t Rm; // the source register
1291  uint32_t Rd; // the destination register
1292  bool setflags;
1293  switch (encoding) {
1294  case eEncodingT1:
1295  Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
1296  Rm = Bits32(opcode, 6, 3);
1297  setflags = false;
1298  if (Rd == 15 && InITBlock() && !LastInITBlock())
1299  return false;
1300  break;
1301  case eEncodingT2:
1302  Rd = Bits32(opcode, 2, 0);
1303  Rm = Bits32(opcode, 5, 3);
1304  setflags = true;
1305  if (InITBlock())
1306  return false;
1307  break;
1308  case eEncodingT3:
1309  Rd = Bits32(opcode, 11, 8);
1310  Rm = Bits32(opcode, 3, 0);
1311  setflags = BitIsSet(opcode, 20);
1312  // if setflags && (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
1313  if (setflags && (BadReg(Rd) || BadReg(Rm)))
1314  return false;
1315  // if !setflags && (d == 15 || m == 15 || (d == 13 && m == 13)) then
1316  // UNPREDICTABLE;
1317  if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
1318  return false;
1319  break;
1320  case eEncodingA1:
1321  Rd = Bits32(opcode, 15, 12);
1322  Rm = Bits32(opcode, 3, 0);
1323  setflags = BitIsSet(opcode, 20);
1324 
1325  // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1326  // instructions;
1327  if (Rd == 15 && setflags)
1328  return EmulateSUBSPcLrEtc(opcode, encoding);
1329  break;
1330  default:
1331  return false;
1332  }
1333  uint32_t result = ReadCoreReg(Rm, &success);
1334  if (!success)
1335  return false;
1336 
1337  // The context specifies that Rm is to be moved into Rd.
1339  if (Rd == 13)
1340  context.type = EmulateInstruction::eContextAdjustStackPointer;
1341  else if (Rd == GetFramePointerRegisterNumber() && Rm == 13)
1342  context.type = EmulateInstruction::eContextSetFramePointer;
1343  else
1344  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1345  RegisterInfo dwarf_reg;
1346  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1347  context.SetRegisterPlusOffset(dwarf_reg, 0);
1348 
1349  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
1350  return false;
1351  }
1352  return true;
1353 }
1354 
1355 // Move (immediate) writes an immediate value to the destination register. It
1356 // can optionally update the condition flags based on the value.
1357 // MOV (immediate)
1358 bool EmulateInstructionARM::EmulateMOVRdImm(const uint32_t opcode,
1359  const ARMEncoding encoding) {
1360 #if 0
1361  // ARM pseudo code...
1362  if (ConditionPassed())
1363  {
1364  EncodingSpecificOperations();
1365  result = imm32;
1366  if d == 15 then // Can only occur for ARM encoding
1367  ALUWritePC(result); // setflags is always FALSE here
1368  else
1369  R[d] = result;
1370  if setflags then
1371  APSR.N = result<31>;
1372  APSR.Z = IsZeroBit(result);
1373  APSR.C = carry;
1374  // APSR.V unchanged
1375  }
1376 #endif
1377 
1378  if (ConditionPassed(opcode)) {
1379  uint32_t Rd; // the destination register
1380  uint32_t imm32; // the immediate value to be written to Rd
1381  uint32_t carry =
1382  0; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C.
1383  // for setflags == false, this value is a don't care initialized to
1384  // 0 to silence the static analyzer
1385  bool setflags;
1386  switch (encoding) {
1387  case eEncodingT1:
1388  Rd = Bits32(opcode, 10, 8);
1389  setflags = !InITBlock();
1390  imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
1391  carry = APSR_C;
1392 
1393  break;
1394 
1395  case eEncodingT2:
1396  Rd = Bits32(opcode, 11, 8);
1397  setflags = BitIsSet(opcode, 20);
1398  imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1399  if (BadReg(Rd))
1400  return false;
1401 
1402  break;
1403 
1404  case eEncodingT3: {
1405  // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8,
1406  // 32);
1407  Rd = Bits32(opcode, 11, 8);
1408  setflags = false;
1409  uint32_t imm4 = Bits32(opcode, 19, 16);
1410  uint32_t imm3 = Bits32(opcode, 14, 12);
1411  uint32_t i = Bit32(opcode, 26);
1412  uint32_t imm8 = Bits32(opcode, 7, 0);
1413  imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
1414 
1415  // if BadReg(d) then UNPREDICTABLE;
1416  if (BadReg(Rd))
1417  return false;
1418  } break;
1419 
1420  case eEncodingA1:
1421  // d = UInt(Rd); setflags = (S == '1'); (imm32, carry) =
1422  // ARMExpandImm_C(imm12, APSR.C);
1423  Rd = Bits32(opcode, 15, 12);
1424  setflags = BitIsSet(opcode, 20);
1425  imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1426 
1427  // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1428  // instructions;
1429  if ((Rd == 15) && setflags)
1430  return EmulateSUBSPcLrEtc(opcode, encoding);
1431 
1432  break;
1433 
1434  case eEncodingA2: {
1435  // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
1436  Rd = Bits32(opcode, 15, 12);
1437  setflags = false;
1438  uint32_t imm4 = Bits32(opcode, 19, 16);
1439  uint32_t imm12 = Bits32(opcode, 11, 0);
1440  imm32 = (imm4 << 12) | imm12;
1441 
1442  // if d == 15 then UNPREDICTABLE;
1443  if (Rd == 15)
1444  return false;
1445  } break;
1446 
1447  default:
1448  return false;
1449  }
1450  uint32_t result = imm32;
1451 
1452  // The context specifies that an immediate is to be moved into Rd.
1454  context.type = EmulateInstruction::eContextImmediate;
1455  context.SetNoArgs();
1456 
1457  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1458  return false;
1459  }
1460  return true;
1461 }
1462 
1463 // MUL multiplies two register values. The least significant 32 bits of the
1464 // result are written to the destination
1465 // register. These 32 bits do not depend on whether the source register values
1466 // are considered to be signed values or unsigned values.
1467 //
1468 // Optionally, it can update the condition flags based on the result. In the
1469 // Thumb instruction set, this option is limited to only a few forms of the
1470 // instruction.
1471 bool EmulateInstructionARM::EmulateMUL(const uint32_t opcode,
1472  const ARMEncoding encoding) {
1473 #if 0
1474  if ConditionPassed() then
1475  EncodingSpecificOperations();
1476  operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
1477  operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
1478  result = operand1 * operand2;
1479  R[d] = result<31:0>;
1480  if setflags then
1481  APSR.N = result<31>;
1482  APSR.Z = IsZeroBit(result);
1483  if ArchVersion() == 4 then
1484  APSR.C = bit UNKNOWN;
1485  // else APSR.C unchanged
1486  // APSR.V always unchanged
1487 #endif
1488 
1489  if (ConditionPassed(opcode)) {
1490  uint32_t d;
1491  uint32_t n;
1492  uint32_t m;
1493  bool setflags;
1494 
1495  // EncodingSpecificOperations();
1496  switch (encoding) {
1497  case eEncodingT1:
1498  // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
1499  d = Bits32(opcode, 2, 0);
1500  n = Bits32(opcode, 5, 3);
1501  m = Bits32(opcode, 2, 0);
1502  setflags = !InITBlock();
1503 
1504  // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
1505  if ((ArchVersion() < ARMv6) && (d == n))
1506  return false;
1507 
1508  break;
1509 
1510  case eEncodingT2:
1511  // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
1512  d = Bits32(opcode, 11, 8);
1513  n = Bits32(opcode, 19, 16);
1514  m = Bits32(opcode, 3, 0);
1515  setflags = false;
1516 
1517  // if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;
1518  if (BadReg(d) || BadReg(n) || BadReg(m))
1519  return false;
1520 
1521  break;
1522 
1523  case eEncodingA1:
1524  // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1525  d = Bits32(opcode, 19, 16);
1526  n = Bits32(opcode, 3, 0);
1527  m = Bits32(opcode, 11, 8);
1528  setflags = BitIsSet(opcode, 20);
1529 
1530  // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
1531  if ((d == 15) || (n == 15) || (m == 15))
1532  return false;
1533 
1534  // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
1535  if ((ArchVersion() < ARMv6) && (d == n))
1536  return false;
1537 
1538  break;
1539 
1540  default:
1541  return false;
1542  }
1543 
1544  bool success = false;
1545 
1546  // operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final
1547  // results
1548  uint64_t operand1 =
1549  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
1550  if (!success)
1551  return false;
1552 
1553  // operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final
1554  // results
1555  uint64_t operand2 =
1556  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
1557  if (!success)
1558  return false;
1559 
1560  // result = operand1 * operand2;
1561  uint64_t result = operand1 * operand2;
1562 
1563  // R[d] = result<31:0>;
1564  RegisterInfo op1_reg;
1565  RegisterInfo op2_reg;
1566  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, op1_reg);
1567  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, op2_reg);
1568 
1570  context.type = eContextArithmetic;
1571  context.SetRegisterRegisterOperands(op1_reg, op2_reg);
1572 
1573  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d,
1574  (0x0000ffff & result)))
1575  return false;
1576 
1577  // if setflags then
1578  if (setflags) {
1579  // APSR.N = result<31>;
1580  // APSR.Z = IsZeroBit(result);
1581  m_new_inst_cpsr = m_opcode_cpsr;
1582  SetBit32(m_new_inst_cpsr, CPSR_N_POS, Bit32(result, 31));
1583  SetBit32(m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
1584  if (m_new_inst_cpsr != m_opcode_cpsr) {
1585  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
1586  LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
1587  return false;
1588  }
1589 
1590  // if ArchVersion() == 4 then
1591  // APSR.C = bit UNKNOWN;
1592  }
1593  }
1594  return true;
1595 }
1596 
1597 // Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to
1598 // the destination register. It can optionally update the condition flags based
1599 // on the value.
1600 bool EmulateInstructionARM::EmulateMVNImm(const uint32_t opcode,
1601  const ARMEncoding encoding) {
1602 #if 0
1603  // ARM pseudo code...
1604  if (ConditionPassed())
1605  {
1606  EncodingSpecificOperations();
1607  result = NOT(imm32);
1608  if d == 15 then // Can only occur for ARM encoding
1609  ALUWritePC(result); // setflags is always FALSE here
1610  else
1611  R[d] = result;
1612  if setflags then
1613  APSR.N = result<31>;
1614  APSR.Z = IsZeroBit(result);
1615  APSR.C = carry;
1616  // APSR.V unchanged
1617  }
1618 #endif
1619 
1620  if (ConditionPassed(opcode)) {
1621  uint32_t Rd; // the destination register
1622  uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C
1623  uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C
1624  bool setflags;
1625  switch (encoding) {
1626  case eEncodingT1:
1627  Rd = Bits32(opcode, 11, 8);
1628  setflags = BitIsSet(opcode, 20);
1629  imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1630  break;
1631  case eEncodingA1:
1632  Rd = Bits32(opcode, 15, 12);
1633  setflags = BitIsSet(opcode, 20);
1634  imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1635 
1636  // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1637  // instructions;
1638  if (Rd == 15 && setflags)
1639  return EmulateSUBSPcLrEtc(opcode, encoding);
1640  break;
1641  default:
1642  return false;
1643  }
1644  uint32_t result = ~imm32;
1645 
1646  // The context specifies that an immediate is to be moved into Rd.
1648  context.type = EmulateInstruction::eContextImmediate;
1649  context.SetNoArgs();
1650 
1651  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1652  return false;
1653  }
1654  return true;
1655 }
1656 
1657 // Bitwise NOT (register) writes the bitwise inverse of a register value to the
1658 // destination register. It can optionally update the condition flags based on
1659 // the result.
1660 bool EmulateInstructionARM::EmulateMVNReg(const uint32_t opcode,
1661  const ARMEncoding encoding) {
1662 #if 0
1663  // ARM pseudo code...
1664  if (ConditionPassed())
1665  {
1666  EncodingSpecificOperations();
1667  (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
1668  result = NOT(shifted);
1669  if d == 15 then // Can only occur for ARM encoding
1670  ALUWritePC(result); // setflags is always FALSE here
1671  else
1672  R[d] = result;
1673  if setflags then
1674  APSR.N = result<31>;
1675  APSR.Z = IsZeroBit(result);
1676  APSR.C = carry;
1677  // APSR.V unchanged
1678  }
1679 #endif
1680 
1681  if (ConditionPassed(opcode)) {
1682  uint32_t Rm; // the source register
1683  uint32_t Rd; // the destination register
1684  ARM_ShifterType shift_t;
1685  uint32_t shift_n; // the shift applied to the value read from Rm
1686  bool setflags;
1687  uint32_t carry; // the carry bit after the shift operation
1688  switch (encoding) {
1689  case eEncodingT1:
1690  Rd = Bits32(opcode, 2, 0);
1691  Rm = Bits32(opcode, 5, 3);
1692  setflags = !InITBlock();
1693  shift_t = SRType_LSL;
1694  shift_n = 0;
1695  if (InITBlock())
1696  return false;
1697  break;
1698  case eEncodingT2:
1699  Rd = Bits32(opcode, 11, 8);
1700  Rm = Bits32(opcode, 3, 0);
1701  setflags = BitIsSet(opcode, 20);
1702  shift_n = DecodeImmShiftThumb(opcode, shift_t);
1703  // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
1704  if (BadReg(Rd) || BadReg(Rm))
1705  return false;
1706  break;
1707  case eEncodingA1:
1708  Rd = Bits32(opcode, 15, 12);
1709  Rm = Bits32(opcode, 3, 0);
1710  setflags = BitIsSet(opcode, 20);
1711  shift_n = DecodeImmShiftARM(opcode, shift_t);
1712  break;
1713  default:
1714  return false;
1715  }
1716  bool success = false;
1717  uint32_t value = ReadCoreReg(Rm, &success);
1718  if (!success)
1719  return false;
1720 
1721  uint32_t shifted =
1722  Shift_C(value, shift_t, shift_n, APSR_C, carry, &success);
1723  if (!success)
1724  return false;
1725  uint32_t result = ~shifted;
1726 
1727  // The context specifies that an immediate is to be moved into Rd.
1729  context.type = EmulateInstruction::eContextImmediate;
1730  context.SetNoArgs();
1731 
1732  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1733  return false;
1734  }
1735  return true;
1736 }
1737 
1738 // PC relative immediate load into register, possibly followed by ADD (SP plus
1739 // register).
1740 // LDR (literal)
1741 bool EmulateInstructionARM::EmulateLDRRtPCRelative(const uint32_t opcode,
1742  const ARMEncoding encoding) {
1743 #if 0
1744  // ARM pseudo code...
1745  if (ConditionPassed())
1746  {
1747  EncodingSpecificOperations(); NullCheckIfThumbEE(15);
1748  base = Align(PC,4);
1749  address = if add then (base + imm32) else (base - imm32);
1750  data = MemU[address,4];
1751  if t == 15 then
1752  if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
1753  elsif UnalignedSupport() || address<1:0> = '00' then
1754  R[t] = data;
1755  else // Can only apply before ARMv7
1756  if CurrentInstrSet() == InstrSet_ARM then
1757  R[t] = ROR(data, 8*UInt(address<1:0>));
1758  else
1759  R[t] = bits(32) UNKNOWN;
1760  }
1761 #endif
1762 
1763  if (ConditionPassed(opcode)) {
1764  bool success = false;
1765  const uint32_t pc = ReadCoreReg(PC_REG, &success);
1766  if (!success)
1767  return false;
1768 
1769  // PC relative immediate load context
1771  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1772  RegisterInfo pc_reg;
1773  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
1774  context.SetRegisterPlusOffset(pc_reg, 0);
1775 
1776  uint32_t Rt; // the destination register
1777  uint32_t imm32; // immediate offset from the PC
1778  bool add; // +imm32 or -imm32?
1779  addr_t base; // the base address
1780  addr_t address; // the PC relative address
1781  uint32_t data; // the literal data value from the PC relative load
1782  switch (encoding) {
1783  case eEncodingT1:
1784  Rt = Bits32(opcode, 10, 8);
1785  imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
1786  add = true;
1787  break;
1788  case eEncodingT2:
1789  Rt = Bits32(opcode, 15, 12);
1790  imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
1791  add = BitIsSet(opcode, 23);
1792  if (Rt == 15 && InITBlock() && !LastInITBlock())
1793  return false;
1794  break;
1795  default:
1796  return false;
1797  }
1798 
1799  base = Align(pc, 4);
1800  if (add)
1801  address = base + imm32;
1802  else
1803  address = base - imm32;
1804 
1805  context.SetRegisterPlusOffset(pc_reg, address - base);
1806  data = MemURead(context, address, 4, 0, &success);
1807  if (!success)
1808  return false;
1809 
1810  if (Rt == 15) {
1811  if (Bits32(address, 1, 0) == 0) {
1812  // In ARMv5T and above, this is an interworking branch.
1813  if (!LoadWritePC(context, data))
1814  return false;
1815  } else
1816  return false;
1817  } else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) {
1818  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rt,
1819  data))
1820  return false;
1821  } else // We don't handle ARM for now.
1822  return false;
1823  }
1824  return true;
1825 }
1826 
1827 // An add operation to adjust the SP.
1828 // ADD (SP plus immediate)
1829 bool EmulateInstructionARM::EmulateADDSPImm(const uint32_t opcode,
1830  const ARMEncoding encoding) {
1831 #if 0
1832  // ARM pseudo code...
1833  if (ConditionPassed())
1834  {
1835  EncodingSpecificOperations();
1836  (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
1837  if d == 15 then // Can only occur for ARM encoding
1838  ALUWritePC(result); // setflags is always FALSE here
1839  else
1840  R[d] = result;
1841  if setflags then
1842  APSR.N = result<31>;
1843  APSR.Z = IsZeroBit(result);
1844  APSR.C = carry;
1845  APSR.V = overflow;
1846  }
1847 #endif
1848 
1849  bool success = false;
1850 
1851  if (ConditionPassed(opcode)) {
1852  const addr_t sp = ReadCoreReg(SP_REG, &success);
1853  if (!success)
1854  return false;
1855  uint32_t imm32; // the immediate operand
1856  uint32_t d;
1857  bool setflags;
1858  switch (encoding) {
1859  case eEncodingT1:
1860  // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
1861  d = Bits32(opcode, 10, 8);
1862  imm32 = (Bits32(opcode, 7, 0) << 2);
1863  setflags = false;
1864  break;
1865 
1866  case eEncodingT2:
1867  // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32);
1868  d = 13;
1869  imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1870  setflags = false;
1871  break;
1872 
1873  case eEncodingT3:
1874  // d = UInt(Rd); setflags = (S == "1"); imm32 =
1875  // ThumbExpandImm(i:imm3:imm8);
1876  d = Bits32(opcode, 11, 8);
1877  imm32 = ThumbExpandImm(opcode);
1878  setflags = Bit32(opcode, 20);
1879 
1880  // if Rd == "1111" && S == "1" then SEE CMN (immediate);
1881  if (d == 15 && setflags == 1)
1882  return false; // CMN (immediate) not yet supported
1883 
1884  // if d == 15 && S == "0" then UNPREDICTABLE;
1885  if (d == 15 && setflags == 0)
1886  return false;
1887  break;
1888 
1889  case eEncodingT4: {
1890  // if Rn == '1111' then SEE ADR;
1891  // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
1892  d = Bits32(opcode, 11, 8);
1893  setflags = false;
1894  uint32_t i = Bit32(opcode, 26);
1895  uint32_t imm3 = Bits32(opcode, 14, 12);
1896  uint32_t imm8 = Bits32(opcode, 7, 0);
1897  imm32 = (i << 11) | (imm3 << 8) | imm8;
1898 
1899  // if d == 15 then UNPREDICTABLE;
1900  if (d == 15)
1901  return false;
1902  } break;
1903 
1904  default:
1905  return false;
1906  }
1907  // (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
1908  AddWithCarryResult res = AddWithCarry(sp, imm32, 0);
1909 
1911  if (d == 13)
1912  context.type = EmulateInstruction::eContextAdjustStackPointer;
1913  else
1914  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1915 
1916  RegisterInfo sp_reg;
1917  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1918  context.SetRegisterPlusOffset(sp_reg, res.result - sp);
1919 
1920  if (d == 15) {
1921  if (!ALUWritePC(context, res.result))
1922  return false;
1923  } else {
1924  // R[d] = result;
1925  // if setflags then
1926  // APSR.N = result<31>;
1927  // APSR.Z = IsZeroBit(result);
1928  // APSR.C = carry;
1929  // APSR.V = overflow;
1930  if (!WriteCoreRegOptionalFlags(context, res.result, d, setflags,
1931  res.carry_out, res.overflow))
1932  return false;
1933  }
1934  }
1935  return true;
1936 }
1937 
1938 // An add operation to adjust the SP.
1939 // ADD (SP plus register)
1940 bool EmulateInstructionARM::EmulateADDSPRm(const uint32_t opcode,
1941  const ARMEncoding encoding) {
1942 #if 0
1943  // ARM pseudo code...
1944  if (ConditionPassed())
1945  {
1946  EncodingSpecificOperations();
1947  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
1948  (result, carry, overflow) = AddWithCarry(SP, shifted, '0');
1949  if d == 15 then
1950  ALUWritePC(result); // setflags is always FALSE here
1951  else
1952  R[d] = result;
1953  if setflags then
1954  APSR.N = result<31>;
1955  APSR.Z = IsZeroBit(result);
1956  APSR.C = carry;
1957  APSR.V = overflow;
1958  }
1959 #endif
1960 
1961  bool success = false;
1962 
1963  if (ConditionPassed(opcode)) {
1964  const addr_t sp = ReadCoreReg(SP_REG, &success);
1965  if (!success)
1966  return false;
1967  uint32_t Rm; // the second operand
1968  switch (encoding) {
1969  case eEncodingT2:
1970  Rm = Bits32(opcode, 6, 3);
1971  break;
1972  default:
1973  return false;
1974  }
1975  int32_t reg_value = ReadCoreReg(Rm, &success);
1976  if (!success)
1977  return false;
1978 
1979  addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value
1980 
1982  context.type = eContextArithmetic;
1983  RegisterInfo sp_reg;
1984  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1985 
1986  RegisterInfo other_reg;
1987  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, other_reg);
1988  context.SetRegisterRegisterOperands(sp_reg, other_reg);
1989 
1990  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
1991  LLDB_REGNUM_GENERIC_SP, addr))
1992  return false;
1993  }
1994  return true;
1995 }
1996 
1997 // Branch with Link and Exchange Instruction Sets (immediate) calls a
1998 // subroutine at a PC-relative address, and changes instruction set from ARM to
1999 // Thumb, or from Thumb to ARM.
2000 // BLX (immediate)
2001 bool EmulateInstructionARM::EmulateBLXImmediate(const uint32_t opcode,
2002  const ARMEncoding encoding) {
2003 #if 0
2004  // ARM pseudo code...
2005  if (ConditionPassed())
2006  {
2007  EncodingSpecificOperations();
2008  if CurrentInstrSet() == InstrSet_ARM then
2009  LR = PC - 4;
2010  else
2011  LR = PC<31:1> : '1';
2012  if targetInstrSet == InstrSet_ARM then
2013  targetAddress = Align(PC,4) + imm32;
2014  else
2015  targetAddress = PC + imm32;
2016  SelectInstrSet(targetInstrSet);
2017  BranchWritePC(targetAddress);
2018  }
2019 #endif
2020 
2021  bool success = true;
2022 
2023  if (ConditionPassed(opcode)) {
2025  context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2026  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2027  if (!success)
2028  return false;
2029  addr_t lr; // next instruction address
2030  addr_t target; // target address
2031  int32_t imm32; // PC-relative offset
2032  switch (encoding) {
2033  case eEncodingT1: {
2034  lr = pc | 1u; // return address
2035  uint32_t S = Bit32(opcode, 26);
2036  uint32_t imm10 = Bits32(opcode, 25, 16);
2037  uint32_t J1 = Bit32(opcode, 13);
2038  uint32_t J2 = Bit32(opcode, 11);
2039  uint32_t imm11 = Bits32(opcode, 10, 0);
2040  uint32_t I1 = !(J1 ^ S);
2041  uint32_t I2 = !(J2 ^ S);
2042  uint32_t imm25 =
2043  (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2044  imm32 = llvm::SignExtend32<25>(imm25);
2045  target = pc + imm32;
2046  SelectInstrSet(eModeThumb);
2047  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2048  if (InITBlock() && !LastInITBlock())
2049  return false;
2050  break;
2051  }
2052  case eEncodingT2: {
2053  lr = pc | 1u; // return address
2054  uint32_t S = Bit32(opcode, 26);
2055  uint32_t imm10H = Bits32(opcode, 25, 16);
2056  uint32_t J1 = Bit32(opcode, 13);
2057  uint32_t J2 = Bit32(opcode, 11);
2058  uint32_t imm10L = Bits32(opcode, 10, 1);
2059  uint32_t I1 = !(J1 ^ S);
2060  uint32_t I2 = !(J2 ^ S);
2061  uint32_t imm25 =
2062  (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
2063  imm32 = llvm::SignExtend32<25>(imm25);
2064  target = Align(pc, 4) + imm32;
2065  SelectInstrSet(eModeARM);
2066  context.SetISAAndImmediateSigned(eModeARM, 4 + imm32);
2067  if (InITBlock() && !LastInITBlock())
2068  return false;
2069  break;
2070  }
2071  case eEncodingA1:
2072  lr = pc - 4; // return address
2073  imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2074  target = Align(pc, 4) + imm32;
2075  SelectInstrSet(eModeARM);
2076  context.SetISAAndImmediateSigned(eModeARM, 8 + imm32);
2077  break;
2078  case eEncodingA2:
2079  lr = pc - 4; // return address
2080  imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 |
2081  Bits32(opcode, 24, 24) << 1);
2082  target = pc + imm32;
2083  SelectInstrSet(eModeThumb);
2084  context.SetISAAndImmediateSigned(eModeThumb, 8 + imm32);
2085  break;
2086  default:
2087  return false;
2088  }
2089  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2091  return false;
2092  if (!BranchWritePC(context, target))
2093  return false;
2094  if (m_opcode_cpsr != m_new_inst_cpsr)
2095  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2096  LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
2097  return false;
2098  }
2099  return true;
2100 }
2101 
2102 // Branch with Link and Exchange (register) calls a subroutine at an address
2103 // and instruction set specified by a register.
2104 // BLX (register)
2105 bool EmulateInstructionARM::EmulateBLXRm(const uint32_t opcode,
2106  const ARMEncoding encoding) {
2107 #if 0
2108  // ARM pseudo code...
2109  if (ConditionPassed())
2110  {
2111  EncodingSpecificOperations();
2112  target = R[m];
2113  if CurrentInstrSet() == InstrSet_ARM then
2114  next_instr_addr = PC - 4;
2115  LR = next_instr_addr;
2116  else
2117  next_instr_addr = PC - 2;
2118  LR = next_instr_addr<31:1> : '1';
2119  BXWritePC(target);
2120  }
2121 #endif
2122 
2123  bool success = false;
2124 
2125  if (ConditionPassed(opcode)) {
2127  context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
2128  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2129  addr_t lr; // next instruction address
2130  if (!success)
2131  return false;
2132  uint32_t Rm; // the register with the target address
2133  switch (encoding) {
2134  case eEncodingT1:
2135  lr = (pc - 2) | 1u; // return address
2136  Rm = Bits32(opcode, 6, 3);
2137  // if m == 15 then UNPREDICTABLE;
2138  if (Rm == 15)
2139  return false;
2140  if (InITBlock() && !LastInITBlock())
2141  return false;
2142  break;
2143  case eEncodingA1:
2144  lr = pc - 4; // return address
2145  Rm = Bits32(opcode, 3, 0);
2146  // if m == 15 then UNPREDICTABLE;
2147  if (Rm == 15)
2148  return false;
2149  break;
2150  default:
2151  return false;
2152  }
2153  addr_t target = ReadCoreReg(Rm, &success);
2154  if (!success)
2155  return false;
2156  RegisterInfo dwarf_reg;
2157  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
2158  context.SetRegister(dwarf_reg);
2159  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2161  return false;
2162  if (!BXWritePC(context, target))
2163  return false;
2164  }
2165  return true;
2166 }
2167 
2168 // Branch and Exchange causes a branch to an address and instruction set
2169 // specified by a register.
2170 bool EmulateInstructionARM::EmulateBXRm(const uint32_t opcode,
2171  const ARMEncoding encoding) {
2172 #if 0
2173  // ARM pseudo code...
2174  if (ConditionPassed())
2175  {
2176  EncodingSpecificOperations();
2177  BXWritePC(R[m]);
2178  }
2179 #endif
2180 
2181  if (ConditionPassed(opcode)) {
2183  context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
2184  uint32_t Rm; // the register with the target address
2185  switch (encoding) {
2186  case eEncodingT1:
2187  Rm = Bits32(opcode, 6, 3);
2188  if (InITBlock() && !LastInITBlock())
2189  return false;
2190  break;
2191  case eEncodingA1:
2192  Rm = Bits32(opcode, 3, 0);
2193  break;
2194  default:
2195  return false;
2196  }
2197  bool success = false;
2198  addr_t target = ReadCoreReg(Rm, &success);
2199  if (!success)
2200  return false;
2201 
2202  RegisterInfo dwarf_reg;
2203  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
2204  context.SetRegister(dwarf_reg);
2205  if (!BXWritePC(context, target))
2206  return false;
2207  }
2208  return true;
2209 }
2210 
2211 // Branch and Exchange Jazelle attempts to change to Jazelle state. If the
2212 // attempt fails, it branches to an address and instruction set specified by a
2213 // register as though it were a BX instruction.
2214 //
2215 // TODO: Emulate Jazelle architecture?
2216 // We currently assume that switching to Jazelle state fails, thus
2217 // treating BXJ as a BX operation.
2218 bool EmulateInstructionARM::EmulateBXJRm(const uint32_t opcode,
2219  const ARMEncoding encoding) {
2220 #if 0
2221  // ARM pseudo code...
2222  if (ConditionPassed())
2223  {
2224  EncodingSpecificOperations();
2225  if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then
2226  BXWritePC(R[m]);
2227  else
2228  if JazelleAcceptsExecution() then
2229  SwitchToJazelleExecution();
2230  else
2231  SUBARCHITECTURE_DEFINED handler call;
2232  }
2233 #endif
2234 
2235  if (ConditionPassed(opcode)) {
2237  context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
2238  uint32_t Rm; // the register with the target address
2239  switch (encoding) {
2240  case eEncodingT1:
2241  Rm = Bits32(opcode, 19, 16);
2242  if (BadReg(Rm))
2243  return false;
2244  if (InITBlock() && !LastInITBlock())
2245  return false;
2246  break;
2247  case eEncodingA1:
2248  Rm = Bits32(opcode, 3, 0);
2249  if (Rm == 15)
2250  return false;
2251  break;
2252  default:
2253  return false;
2254  }
2255  bool success = false;
2256  addr_t target = ReadCoreReg(Rm, &success);
2257  if (!success)
2258  return false;
2259 
2260  RegisterInfo dwarf_reg;
2261  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
2262  context.SetRegister(dwarf_reg);
2263  if (!BXWritePC(context, target))
2264  return false;
2265  }
2266  return true;
2267 }
2268 
2269 // Set r7 to point to some ip offset.
2270 // SUB (immediate)
2271 bool EmulateInstructionARM::EmulateSUBR7IPImm(const uint32_t opcode,
2272  const ARMEncoding encoding) {
2273 #if 0
2274  // ARM pseudo code...
2275  if (ConditionPassed())
2276  {
2277  EncodingSpecificOperations();
2278  (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
2279  if d == 15 then // Can only occur for ARM encoding
2280  ALUWritePC(result); // setflags is always FALSE here
2281  else
2282  R[d] = result;
2283  if setflags then
2284  APSR.N = result<31>;
2285  APSR.Z = IsZeroBit(result);
2286  APSR.C = carry;
2287  APSR.V = overflow;
2288  }
2289 #endif
2290 
2291  if (ConditionPassed(opcode)) {
2292  bool success = false;
2293  const addr_t ip = ReadCoreReg(12, &success);
2294  if (!success)
2295  return false;
2296  uint32_t imm32;
2297  switch (encoding) {
2298  case eEncodingA1:
2299  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2300  break;
2301  default:
2302  return false;
2303  }
2304  addr_t ip_offset = imm32;
2305  addr_t addr = ip - ip_offset; // the adjusted ip value
2306 
2308  context.type = EmulateInstruction::eContextRegisterPlusOffset;
2309  RegisterInfo dwarf_reg;
2310  GetRegisterInfo(eRegisterKindDWARF, dwarf_r12, dwarf_reg);
2311  context.SetRegisterPlusOffset(dwarf_reg, -ip_offset);
2312 
2313  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r7, addr))
2314  return false;
2315  }
2316  return true;
2317 }
2318 
2319 // Set ip to point to some stack offset.
2320 // SUB (SP minus immediate)
2321 bool EmulateInstructionARM::EmulateSUBIPSPImm(const uint32_t opcode,
2322  const ARMEncoding encoding) {
2323 #if 0
2324  // ARM pseudo code...
2325  if (ConditionPassed())
2326  {
2327  EncodingSpecificOperations();
2328  (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
2329  if d == 15 then // Can only occur for ARM encoding
2330  ALUWritePC(result); // setflags is always FALSE here
2331  else
2332  R[d] = result;
2333  if setflags then
2334  APSR.N = result<31>;
2335  APSR.Z = IsZeroBit(result);
2336  APSR.C = carry;
2337  APSR.V = overflow;
2338  }
2339 #endif
2340 
2341  if (ConditionPassed(opcode)) {
2342  bool success = false;
2343  const addr_t sp = ReadCoreReg(SP_REG, &success);
2344  if (!success)
2345  return false;
2346  uint32_t imm32;
2347  switch (encoding) {
2348  case eEncodingA1:
2349  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2350  break;
2351  default:
2352  return false;
2353  }
2354  addr_t sp_offset = imm32;
2355  addr_t addr = sp - sp_offset; // the adjusted stack pointer value
2356 
2358  context.type = EmulateInstruction::eContextRegisterPlusOffset;
2359  RegisterInfo dwarf_reg;
2360  GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, dwarf_reg);
2361  context.SetRegisterPlusOffset(dwarf_reg, -sp_offset);
2362 
2363  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r12, addr))
2364  return false;
2365  }
2366  return true;
2367 }
2368 
2369 // This instruction subtracts an immediate value from the SP value, and writes
2370 // the result to the destination register.
2371 //
2372 // If Rd == 13 => A sub operation to adjust the SP -- allocate space for local
2373 // storage.
2374 bool EmulateInstructionARM::EmulateSUBSPImm(const uint32_t opcode,
2375  const ARMEncoding encoding) {
2376 #if 0
2377  // ARM pseudo code...
2378  if (ConditionPassed())
2379  {
2380  EncodingSpecificOperations();
2381  (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
2382  if d == 15 then // Can only occur for ARM encoding
2383  ALUWritePC(result); // setflags is always FALSE here
2384  else
2385  R[d] = result;
2386  if setflags then
2387  APSR.N = result<31>;
2388  APSR.Z = IsZeroBit(result);
2389  APSR.C = carry;
2390  APSR.V = overflow;
2391  }
2392 #endif
2393 
2394  bool success = false;
2395  if (ConditionPassed(opcode)) {
2396  const addr_t sp = ReadCoreReg(SP_REG, &success);
2397  if (!success)
2398  return false;
2399 
2400  uint32_t Rd;
2401  bool setflags;
2402  uint32_t imm32;
2403  switch (encoding) {
2404  case eEncodingT1:
2405  Rd = 13;
2406  setflags = false;
2407  imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
2408  break;
2409  case eEncodingT2:
2410  Rd = Bits32(opcode, 11, 8);
2411  setflags = BitIsSet(opcode, 20);
2412  imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2413  if (Rd == 15 && setflags)
2414  return EmulateCMPImm(opcode, eEncodingT2);
2415  if (Rd == 15 && !setflags)
2416  return false;
2417  break;
2418  case eEncodingT3:
2419  Rd = Bits32(opcode, 11, 8);
2420  setflags = false;
2421  imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
2422  if (Rd == 15)
2423  return false;
2424  break;
2425  case eEncodingA1:
2426  Rd = Bits32(opcode, 15, 12);
2427  setflags = BitIsSet(opcode, 20);
2428  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2429 
2430  // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
2431  // instructions;
2432  if (Rd == 15 && setflags)
2433  return EmulateSUBSPcLrEtc(opcode, encoding);
2434  break;
2435  default:
2436  return false;
2437  }
2438  AddWithCarryResult res = AddWithCarry(sp, ~imm32, 1);
2439 
2441  if (Rd == 13) {
2442  uint64_t imm64 = imm32; // Need to expand it to 64 bits before attempting
2443  // to negate it, or the wrong
2444  // value gets passed down to context.SetImmediateSigned.
2445  context.type = EmulateInstruction::eContextAdjustStackPointer;
2446  context.SetImmediateSigned(-imm64); // the stack pointer offset
2447  } else {
2448  context.type = EmulateInstruction::eContextImmediate;
2449  context.SetNoArgs();
2450  }
2451 
2452  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
2453  res.carry_out, res.overflow))
2454  return false;
2455  }
2456  return true;
2457 }
2458 
2459 // A store operation to the stack that also updates the SP.
2460 bool EmulateInstructionARM::EmulateSTRRtSP(const uint32_t opcode,
2461  const ARMEncoding encoding) {
2462 #if 0
2463  // ARM pseudo code...
2464  if (ConditionPassed())
2465  {
2466  EncodingSpecificOperations();
2467  offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
2468  address = if index then offset_addr else R[n];
2469  MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
2470  if wback then R[n] = offset_addr;
2471  }
2472 #endif
2473 
2474  bool success = false;
2475  if (ConditionPassed(opcode)) {
2476  const uint32_t addr_byte_size = GetAddressByteSize();
2477  const addr_t sp = ReadCoreReg(SP_REG, &success);
2478  if (!success)
2479  return false;
2480  uint32_t Rt; // the source register
2481  uint32_t imm12;
2482  uint32_t
2483  Rn; // This function assumes Rn is the SP, but we should verify that.
2484 
2485  bool index;
2486  bool add;
2487  bool wback;
2488  switch (encoding) {
2489  case eEncodingA1:
2490  Rt = Bits32(opcode, 15, 12);
2491  imm12 = Bits32(opcode, 11, 0);
2492  Rn = Bits32(opcode, 19, 16);
2493 
2494  if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP.
2495  return false;
2496 
2497  index = BitIsSet(opcode, 24);
2498  add = BitIsSet(opcode, 23);
2499  wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
2500 
2501  if (wback && ((Rn == 15) || (Rn == Rt)))
2502  return false;
2503  break;
2504  default:
2505  return false;
2506  }
2507  addr_t offset_addr;
2508  if (add)
2509  offset_addr = sp + imm12;
2510  else
2511  offset_addr = sp - imm12;
2512 
2513  addr_t addr;
2514  if (index)
2515  addr = offset_addr;
2516  else
2517  addr = sp;
2518 
2520  context.type = EmulateInstruction::eContextPushRegisterOnStack;
2521  RegisterInfo sp_reg;
2522  RegisterInfo dwarf_reg;
2523 
2524  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
2525  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rt, dwarf_reg);
2526  context.SetRegisterToRegisterPlusOffset(dwarf_reg, sp_reg, addr - sp);
2527  if (Rt != 15) {
2528  uint32_t reg_value = ReadCoreReg(Rt, &success);
2529  if (!success)
2530  return false;
2531  if (!MemUWrite(context, addr, reg_value, addr_byte_size))
2532  return false;
2533  } else {
2534  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2535  if (!success)
2536  return false;
2537  if (!MemUWrite(context, addr, pc, addr_byte_size))
2538  return false;
2539  }
2540 
2541  if (wback) {
2542  context.type = EmulateInstruction::eContextAdjustStackPointer;
2543  context.SetImmediateSigned(addr - sp);
2544  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2545  LLDB_REGNUM_GENERIC_SP, offset_addr))
2546  return false;
2547  }
2548  }
2549  return true;
2550 }
2551 
2552 // Vector Push stores multiple extension registers to the stack. It also
2553 // updates SP to point to the start of the stored data.
2554 bool EmulateInstructionARM::EmulateVPUSH(const uint32_t opcode,
2555  const ARMEncoding encoding) {
2556 #if 0
2557  // ARM pseudo code...
2558  if (ConditionPassed())
2559  {
2560  EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2561  address = SP - imm32;
2562  SP = SP - imm32;
2563  if single_regs then
2564  for r = 0 to regs-1
2565  MemA[address,4] = S[d+r]; address = address+4;
2566  else
2567  for r = 0 to regs-1
2568  // Store as two word-aligned words in the correct order for
2569  // current endianness.
2570  MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
2571  MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
2572  address = address+8;
2573  }
2574 #endif
2575 
2576  bool success = false;
2577  if (ConditionPassed(opcode)) {
2578  const uint32_t addr_byte_size = GetAddressByteSize();
2579  const addr_t sp = ReadCoreReg(SP_REG, &success);
2580  if (!success)
2581  return false;
2582  bool single_regs;
2583  uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register
2584  uint32_t imm32; // stack offset
2585  uint32_t regs; // number of registers
2586  switch (encoding) {
2587  case eEncodingT1:
2588  case eEncodingA1:
2589  single_regs = false;
2590  d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2591  imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2592  // If UInt(imm8) is odd, see "FSTMX".
2593  regs = Bits32(opcode, 7, 0) / 2;
2594  // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2595  if (regs == 0 || regs > 16 || (d + regs) > 32)
2596  return false;
2597  break;
2598  case eEncodingT2:
2599  case eEncodingA2:
2600  single_regs = true;
2601  d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2602  imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2603  regs = Bits32(opcode, 7, 0);
2604  // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2605  if (regs == 0 || regs > 16 || (d + regs) > 32)
2606  return false;
2607  break;
2608  default:
2609  return false;
2610  }
2611  uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
2612  uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2613  addr_t sp_offset = imm32;
2614  addr_t addr = sp - sp_offset;
2615  uint32_t i;
2616 
2618  context.type = EmulateInstruction::eContextPushRegisterOnStack;
2619 
2620  RegisterInfo dwarf_reg;
2621  RegisterInfo sp_reg;
2622  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
2623  for (i = 0; i < regs; ++i) {
2624  GetRegisterInfo(eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
2625  context.SetRegisterToRegisterPlusOffset(dwarf_reg, sp_reg, addr - sp);
2626  // uint64_t to accommodate 64-bit registers.
2627  uint64_t reg_value = ReadRegisterUnsigned(&dwarf_reg, 0, &success);
2628  if (!success)
2629  return false;
2630  if (!MemAWrite(context, addr, reg_value, reg_byte_size))
2631  return false;
2632  addr += reg_byte_size;
2633  }
2634 
2635  context.type = EmulateInstruction::eContextAdjustStackPointer;
2636  context.SetImmediateSigned(-sp_offset);
2637 
2638  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2639  LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
2640  return false;
2641  }
2642  return true;
2643 }
2644 
2645 // Vector Pop loads multiple extension registers from the stack. It also
2646 // updates SP to point just above the loaded data.
2647 bool EmulateInstructionARM::EmulateVPOP(const uint32_t opcode,
2648  const ARMEncoding encoding) {
2649 #if 0
2650  // ARM pseudo code...
2651  if (ConditionPassed())
2652  {
2653  EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2654  address = SP;
2655  SP = SP + imm32;
2656  if single_regs then
2657  for r = 0 to regs-1
2658  S[d+r] = MemA[address,4]; address = address+4;
2659  else
2660  for r = 0 to regs-1
2661  word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
2662  // Combine the word-aligned words in the correct order for
2663  // current endianness.
2664  D[d+r] = if BigEndian() then word1:word2 else word2:word1;
2665  }
2666 #endif
2667 
2668  bool success = false;
2669  if (ConditionPassed(opcode)) {
2670  const uint32_t addr_byte_size = GetAddressByteSize();
2671  const addr_t sp = ReadCoreReg(SP_REG, &success);
2672  if (!success)
2673  return false;
2674  bool single_regs;
2675  uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register
2676  uint32_t imm32; // stack offset
2677  uint32_t regs; // number of registers
2678  switch (encoding) {
2679  case eEncodingT1:
2680  case eEncodingA1:
2681  single_regs = false;
2682  d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2683  imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2684  // If UInt(imm8) is odd, see "FLDMX".
2685  regs = Bits32(opcode, 7, 0) / 2;
2686  // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2687  if (regs == 0 || regs > 16 || (d + regs) > 32)
2688  return false;
2689  break;
2690  case eEncodingT2:
2691  case eEncodingA2:
2692  single_regs = true;
2693  d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2694  imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2695  regs = Bits32(opcode, 7, 0);
2696  // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2697  if (regs == 0 || regs > 16 || (d + regs) > 32)
2698  return false;
2699  break;
2700  default:
2701  return false;
2702  }
2703  uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
2704  uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2705  addr_t sp_offset = imm32;
2706  addr_t addr = sp;
2707  uint32_t i;
2708  uint64_t data; // uint64_t to accommodate 64-bit registers.
2709 
2711  context.type = EmulateInstruction::eContextPopRegisterOffStack;
2712 
2713  RegisterInfo dwarf_reg;
2714  RegisterInfo sp_reg;
2715  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
2716  for (i = 0; i < regs; ++i) {
2717  GetRegisterInfo(eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
2718  context.SetAddress(addr);
2719  data = MemARead(context, addr, reg_byte_size, 0, &success);
2720  if (!success)
2721  return false;
2722  if (!WriteRegisterUnsigned(context, &dwarf_reg, data))
2723  return false;
2724  addr += reg_byte_size;
2725  }
2726 
2727  context.type = EmulateInstruction::eContextAdjustStackPointer;
2728  context.SetImmediateSigned(sp_offset);
2729 
2730  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2731  LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
2732  return false;
2733  }
2734  return true;
2735 }
2736 
2737 // SVC (previously SWI)
2738 bool EmulateInstructionARM::EmulateSVC(const uint32_t opcode,
2739  const ARMEncoding encoding) {
2740 #if 0
2741  // ARM pseudo code...
2742  if (ConditionPassed())
2743  {
2744  EncodingSpecificOperations();
2745  CallSupervisor();
2746  }
2747 #endif
2748 
2749  bool success = false;
2750 
2751  if (ConditionPassed(opcode)) {
2752  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2753  addr_t lr; // next instruction address
2754  if (!success)
2755  return false;
2756  uint32_t imm32; // the immediate constant
2757  uint32_t mode; // ARM or Thumb mode
2758  switch (encoding) {
2759  case eEncodingT1:
2760  lr = (pc + 2) | 1u; // return address
2761  imm32 = Bits32(opcode, 7, 0);
2762  mode = eModeThumb;
2763  break;
2764  case eEncodingA1:
2765  lr = pc + 4; // return address
2766  imm32 = Bits32(opcode, 23, 0);
2767  mode = eModeARM;
2768  break;
2769  default:
2770  return false;
2771  }
2772 
2774  context.type = EmulateInstruction::eContextSupervisorCall;
2775  context.SetISAAndImmediate(mode, imm32);
2776  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2778  return false;
2779  }
2780  return true;
2781 }
2782 
2783 // If Then makes up to four following instructions (the IT block) conditional.
2784 bool EmulateInstructionARM::EmulateIT(const uint32_t opcode,
2785  const ARMEncoding encoding) {
2786 #if 0
2787  // ARM pseudo code...
2788  EncodingSpecificOperations();
2789  ITSTATE.IT<7:0> = firstcond:mask;
2790 #endif
2791 
2792  m_it_session.InitIT(Bits32(opcode, 7, 0));
2793  return true;
2794 }
2795 
2796 bool EmulateInstructionARM::EmulateNop(const uint32_t opcode,
2797  const ARMEncoding encoding) {
2798  // NOP, nothing to do...
2799  return true;
2800 }
2801 
2802 // Branch causes a branch to a target address.
2803 bool EmulateInstructionARM::EmulateB(const uint32_t opcode,
2804  const ARMEncoding encoding) {
2805 #if 0
2806  // ARM pseudo code...
2807  if (ConditionPassed())
2808  {
2809  EncodingSpecificOperations();
2810  BranchWritePC(PC + imm32);
2811  }
2812 #endif
2813 
2814  bool success = false;
2815 
2816  if (ConditionPassed(opcode)) {
2818  context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2819  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2820  if (!success)
2821  return false;
2822  addr_t target; // target address
2823  int32_t imm32; // PC-relative offset
2824  switch (encoding) {
2825  case eEncodingT1:
2826  // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2827  imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
2828  target = pc + imm32;
2829  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2830  break;
2831  case eEncodingT2:
2832  imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1);
2833  target = pc + imm32;
2834  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2835  break;
2836  case eEncodingT3:
2837  // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2838  {
2839  if (Bits32(opcode, 25, 23) == 7)
2840  return false; // See Branches and miscellaneous control on page
2841  // A6-235.
2842 
2843  uint32_t S = Bit32(opcode, 26);
2844  uint32_t imm6 = Bits32(opcode, 21, 16);
2845  uint32_t J1 = Bit32(opcode, 13);
2846  uint32_t J2 = Bit32(opcode, 11);
2847  uint32_t imm11 = Bits32(opcode, 10, 0);
2848  uint32_t imm21 =
2849  (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
2850  imm32 = llvm::SignExtend32<21>(imm21);
2851  target = pc + imm32;
2852  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2853  break;
2854  }
2855  case eEncodingT4: {
2856  uint32_t S = Bit32(opcode, 26);
2857  uint32_t imm10 = Bits32(opcode, 25, 16);
2858  uint32_t J1 = Bit32(opcode, 13);
2859  uint32_t J2 = Bit32(opcode, 11);
2860  uint32_t imm11 = Bits32(opcode, 10, 0);
2861  uint32_t I1 = !(J1 ^ S);
2862  uint32_t I2 = !(J2 ^ S);
2863  uint32_t imm25 =
2864  (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2865  imm32 = llvm::SignExtend32<25>(imm25);
2866  target = pc + imm32;
2867  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2868  break;
2869  }
2870  case eEncodingA1:
2871  imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2872  target = pc + imm32;
2873  context.SetISAAndImmediateSigned(eModeARM, 8 + imm32);
2874  break;
2875  default:
2876  return false;
2877  }
2878  if (!BranchWritePC(context, target))
2879  return false;
2880  }
2881  return true;
2882 }
2883 
2884 // Compare and Branch on Nonzero and Compare and Branch on Zero compare the
2885 // value in a register with zero and conditionally branch forward a constant
2886 // value. They do not affect the condition flags. CBNZ, CBZ
2887 bool EmulateInstructionARM::EmulateCB(const uint32_t opcode,
2888  const ARMEncoding encoding) {
2889 #if 0
2890  // ARM pseudo code...
2891  EncodingSpecificOperations();
2892  if nonzero ^ IsZero(R[n]) then
2893  BranchWritePC(PC + imm32);
2894 #endif
2895 
2896  bool success = false;
2897 
2898  // Read the register value from the operand register Rn.
2899  uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success);
2900  if (!success)
2901  return false;
2902 
2904  context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2905  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2906  if (!success)
2907  return false;
2908 
2909  addr_t target; // target address
2910  uint32_t imm32; // PC-relative offset to branch forward
2911  bool nonzero;
2912  switch (encoding) {
2913  case eEncodingT1:
2914  imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
2915  nonzero = BitIsSet(opcode, 11);
2916  target = pc + imm32;
2917  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2918  break;
2919  default:
2920  return false;
2921  }
2922  if (m_ignore_conditions || (nonzero ^ (reg_val == 0)))
2923  if (!BranchWritePC(context, target))
2924  return false;
2925 
2926  return true;
2927 }
2928 
2929 // Table Branch Byte causes a PC-relative forward branch using a table of
2930 // single byte offsets.
2931 // A base register provides a pointer to the table, and a second register
2932 // supplies an index into the table.
2933 // The branch length is twice the value of the byte returned from the table.
2934 //
2935 // Table Branch Halfword causes a PC-relative forward branch using a table of
2936 // single halfword offsets.
2937 // A base register provides a pointer to the table, and a second register
2938 // supplies an index into the table.
2939 // The branch length is twice the value of the halfword returned from the
2940 // table. TBB, TBH
2941 bool EmulateInstructionARM::EmulateTB(const uint32_t opcode,
2942  const ARMEncoding encoding) {
2943 #if 0
2944  // ARM pseudo code...
2945  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
2946  if is_tbh then
2947  halfwords = UInt(MemU[R[n]+LSL(R[m],1), 2]);
2948  else
2949  halfwords = UInt(MemU[R[n]+R[m], 1]);
2950  BranchWritePC(PC + 2*halfwords);
2951 #endif
2952 
2953  bool success = false;
2954 
2955  if (ConditionPassed(opcode)) {
2956  uint32_t Rn; // the base register which contains the address of the table of
2957  // branch lengths
2958  uint32_t Rm; // the index register which contains an integer pointing to a
2959  // byte/halfword in the table
2960  bool is_tbh; // true if table branch halfword
2961  switch (encoding) {
2962  case eEncodingT1:
2963  Rn = Bits32(opcode, 19, 16);
2964  Rm = Bits32(opcode, 3, 0);
2965  is_tbh = BitIsSet(opcode, 4);
2966  if (Rn == 13 || BadReg(Rm))
2967  return false;
2968  if (InITBlock() && !LastInITBlock())
2969  return false;
2970  break;
2971  default:
2972  return false;
2973  }
2974 
2975  // Read the address of the table from the operand register Rn. The PC can
2976  // be used, in which case the table immediately follows this instruction.
2977  uint32_t base = ReadCoreReg(Rn, &success);
2978  if (!success)
2979  return false;
2980 
2981  // the table index
2982  uint32_t index = ReadCoreReg(Rm, &success);
2983  if (!success)
2984  return false;
2985 
2986  // the offsetted table address
2987  addr_t addr = base + (is_tbh ? index * 2 : index);
2988 
2989  // PC-relative offset to branch forward
2991  context.type = EmulateInstruction::eContextTableBranchReadMemory;
2992  uint32_t offset = MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
2993  if (!success)
2994  return false;
2995 
2996  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2997  if (!success)
2998  return false;
2999 
3000  // target address
3001  addr_t target = pc + offset;
3002  context.type = EmulateInstruction::eContextRelativeBranchImmediate;
3003  context.SetISAAndImmediateSigned(eModeThumb, 4 + offset);
3004 
3005  if (!BranchWritePC(context, target))
3006  return false;
3007  }
3008 
3009  return true;
3010 }
3011 
3012 // This instruction adds an immediate value to a register value, and writes the
3013 // result to the destination register. It can optionally update the condition
3014 // flags based on the result.
3015 bool EmulateInstructionARM::EmulateADDImmThumb(const uint32_t opcode,
3016  const ARMEncoding encoding) {
3017 #if 0
3018  if ConditionPassed() then
3019  EncodingSpecificOperations();
3020  (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3021  R[d] = result;
3022  if setflags then
3023  APSR.N = result<31>;
3024  APSR.Z = IsZeroBit(result);
3025  APSR.C = carry;
3026  APSR.V = overflow;
3027 #endif
3028 
3029  bool success = false;
3030 
3031  if (ConditionPassed(opcode)) {
3032  uint32_t d;
3033  uint32_t n;
3034  bool setflags;
3035  uint32_t imm32;
3036  uint32_t carry_out;
3037 
3038  // EncodingSpecificOperations();
3039  switch (encoding) {
3040  case eEncodingT1:
3041  // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 =
3042  // ZeroExtend(imm3, 32);
3043  d = Bits32(opcode, 2, 0);
3044  n = Bits32(opcode, 5, 3);
3045  setflags = !InITBlock();
3046  imm32 = Bits32(opcode, 8, 6);
3047 
3048  break;
3049 
3050  case eEncodingT2:
3051  // d = UInt(Rdn); n = UInt(Rdn); setflags = !InITBlock(); imm32 =
3052  // ZeroExtend(imm8, 32);
3053  d = Bits32(opcode, 10, 8);
3054  n = Bits32(opcode, 10, 8);
3055  setflags = !InITBlock();
3056  imm32 = Bits32(opcode, 7, 0);
3057 
3058  break;
3059 
3060  case eEncodingT3:
3061  // if Rd == '1111' && S == '1' then SEE CMN (immediate);
3062  // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 =
3063  // ThumbExpandImm(i:imm3:imm8);
3064  d = Bits32(opcode, 11, 8);
3065  n = Bits32(opcode, 19, 16);
3066  setflags = BitIsSet(opcode, 20);
3067  imm32 = ThumbExpandImm_C(opcode, APSR_C, carry_out);
3068 
3069  // if Rn == '1101' then SEE ADD (SP plus immediate);
3070  if (n == 13)
3071  return EmulateADDSPImm(opcode, eEncodingT3);
3072 
3073  // if BadReg(d) || n == 15 then UNPREDICTABLE;
3074  if (BadReg(d) || (n == 15))
3075  return false;
3076 
3077  break;
3078 
3079  case eEncodingT4: {
3080  // if Rn == '1111' then SEE ADR;
3081  // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 =
3082  // ZeroExtend(i:imm3:imm8, 32);
3083  d = Bits32(opcode, 11, 8);
3084  n = Bits32(opcode, 19, 16);
3085  setflags = false;
3086  uint32_t i = Bit32(opcode, 26);
3087  uint32_t imm3 = Bits32(opcode, 14, 12);
3088  uint32_t imm8 = Bits32(opcode, 7, 0);
3089  imm32 = (i << 11) | (imm3 << 8) | imm8;
3090 
3091  // if Rn == '1101' then SEE ADD (SP plus immediate);
3092  if (n == 13)
3093  return EmulateADDSPImm(opcode, eEncodingT4);
3094 
3095  // if BadReg(d) then UNPREDICTABLE;
3096  if (BadReg(d))
3097  return false;
3098 
3099  break;
3100  }
3101 
3102  default:
3103  return false;
3104  }
3105 
3106  uint64_t Rn =
3107  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3108  if (!success)
3109  return false;
3110 
3111  //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3112  AddWithCarryResult res = AddWithCarry(Rn, imm32, 0);
3113 
3114  RegisterInfo reg_n;
3115  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, reg_n);
3116 
3118  context.type = eContextArithmetic;
3119  context.SetRegisterPlusOffset(reg_n, imm32);
3120 
3121  // R[d] = result;
3122  // if setflags then
3123  // APSR.N = result<31>;
3124  // APSR.Z = IsZeroBit(result);
3125  // APSR.C = carry;
3126  // APSR.V = overflow;
3127  if (!WriteCoreRegOptionalFlags(context, res.result, d, setflags,
3128  res.carry_out, res.overflow))
3129  return false;
3130  }
3131  return true;
3132 }
3133 
3134 // This instruction adds an immediate value to a register value, and writes the
3135 // result to the destination register. It can optionally update the condition
3136 // flags based on the result.
3137 bool EmulateInstructionARM::EmulateADDImmARM(const uint32_t opcode,
3138  const ARMEncoding encoding) {
3139 #if 0
3140  // ARM pseudo code...
3141  if ConditionPassed() then
3142  EncodingSpecificOperations();
3143  (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3144  if d == 15 then
3145  ALUWritePC(result); // setflags is always FALSE here
3146  else
3147  R[d] = result;
3148  if setflags then
3149  APSR.N = result<31>;
3150  APSR.Z = IsZeroBit(result);
3151  APSR.C = carry;
3152  APSR.V = overflow;
3153 #endif
3154 
3155  bool success = false;
3156 
3157  if (ConditionPassed(opcode)) {
3158  uint32_t Rd, Rn;
3159  uint32_t
3160  imm32; // the immediate value to be added to the value obtained from Rn
3161  bool setflags;
3162  switch (encoding) {
3163  case eEncodingA1:
3164  Rd = Bits32(opcode, 15, 12);
3165  Rn = Bits32(opcode, 19, 16);
3166  setflags = BitIsSet(opcode, 20);
3167  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3168  break;
3169  default:
3170  return false;
3171  }
3172 
3173  // Read the first operand.
3174  uint32_t val1 = ReadCoreReg(Rn, &success);
3175  if (!success)
3176  return false;
3177 
3178  AddWithCarryResult res = AddWithCarry(val1, imm32, 0);
3179 
3181  if (Rd == 13)
3182  context.type = EmulateInstruction::eContextAdjustStackPointer;
3183  else if (Rd == GetFramePointerRegisterNumber())
3184  context.type = EmulateInstruction::eContextSetFramePointer;
3185  else
3186  context.type = EmulateInstruction::eContextRegisterPlusOffset;
3187 
3188  RegisterInfo dwarf_reg;
3189  GetRegisterInfo(eRegisterKindDWARF, Rn, dwarf_reg);
3190  context.SetRegisterPlusOffset(dwarf_reg, imm32);
3191 
3192  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3193  res.carry_out, res.overflow))
3194  return false;
3195  }
3196  return true;
3197 }
3198 
3199 // This instruction adds a register value and an optionally-shifted register
3200 // value, and writes the result to the destination register. It can optionally
3201 // update the condition flags based on the result.
3202 bool EmulateInstructionARM::EmulateADDReg(const uint32_t opcode,
3203  const ARMEncoding encoding) {
3204 #if 0
3205  // ARM pseudo code...
3206  if ConditionPassed() then
3207  EncodingSpecificOperations();
3208  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
3209  (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
3210  if d == 15 then
3211  ALUWritePC(result); // setflags is always FALSE here
3212  else
3213  R[d] = result;
3214  if setflags then
3215  APSR.N = result<31>;
3216  APSR.Z = IsZeroBit(result);
3217  APSR.C = carry;
3218  APSR.V = overflow;
3219 #endif
3220 
3221  bool success = false;
3222 
3223  if (ConditionPassed(opcode)) {
3224  uint32_t Rd, Rn, Rm;
3225  ARM_ShifterType shift_t;
3226  uint32_t shift_n; // the shift applied to the value read from Rm
3227  bool setflags;
3228  switch (encoding) {
3229  case eEncodingT1:
3230  Rd = Bits32(opcode, 2, 0);
3231  Rn = Bits32(opcode, 5, 3);
3232  Rm = Bits32(opcode, 8, 6);
3233  setflags = !InITBlock();
3234  shift_t = SRType_LSL;
3235  shift_n = 0;
3236  break;
3237  case eEncodingT2:
3238  Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3239  Rm = Bits32(opcode, 6, 3);
3240  setflags = false;
3241  shift_t = SRType_LSL;
3242  shift_n = 0;
3243  if (Rn == 15 && Rm == 15)
3244  return false;
3245  if (Rd == 15 && InITBlock() && !LastInITBlock())
3246  return false;
3247  break;
3248  case eEncodingA1:
3249  Rd = Bits32(opcode, 15, 12);
3250  Rn = Bits32(opcode, 19, 16);
3251  Rm = Bits32(opcode, 3, 0);
3252  setflags = BitIsSet(opcode, 20);
3253  shift_n = DecodeImmShiftARM(opcode, shift_t);
3254  break;
3255  default:
3256  return false;
3257  }
3258 
3259  // Read the first operand.
3260  uint32_t val1 = ReadCoreReg(Rn, &success);
3261  if (!success)
3262  return false;
3263 
3264  // Read the second operand.
3265  uint32_t val2 = ReadCoreReg(Rm, &success);
3266  if (!success)
3267  return false;
3268 
3269  uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3270  if (!success)
3271  return false;
3272  AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
3273 
3275  context.type = eContextArithmetic;
3276  RegisterInfo op1_reg;
3277  RegisterInfo op2_reg;
3278  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn, op1_reg);
3279  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, op2_reg);
3280  context.SetRegisterRegisterOperands(op1_reg, op2_reg);
3281 
3282  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3283  res.carry_out, res.overflow))
3284  return false;
3285  }
3286  return true;
3287 }
3288 
3289 // Compare Negative (immediate) adds a register value and an immediate value.
3290 // It updates the condition flags based on the result, and discards the result.
3291 bool EmulateInstructionARM::EmulateCMNImm(const uint32_t opcode,
3292  const ARMEncoding encoding) {
3293 #if 0
3294  // ARM pseudo code...
3295  if ConditionPassed() then
3296  EncodingSpecificOperations();
3297  (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3298  APSR.N = result<31>;
3299  APSR.Z = IsZeroBit(result);
3300  APSR.C = carry;
3301  APSR.V = overflow;
3302 #endif
3303 
3304  bool success = false;
3305 
3306  uint32_t Rn; // the first operand
3307  uint32_t imm32; // the immediate value to be compared with
3308  switch (encoding) {
3309  case eEncodingT1:
3310  Rn = Bits32(opcode, 19, 16);
3311  imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
3312  if (Rn == 15)
3313  return false;
3314  break;
3315  case eEncodingA1:
3316  Rn = Bits32(opcode, 19, 16);
3317  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3318  break;
3319  default:
3320  return false;
3321  }
3322  // Read the register value from the operand register Rn.
3323  uint32_t reg_val = ReadCoreReg(Rn, &success);
3324  if (!success)
3325  return false;
3326 
3327  AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0);
3328 
3330  context.type = EmulateInstruction::eContextImmediate;
3331  context.SetNoArgs();
3332  return WriteFlags(context, res.result, res.carry_out, res.overflow);
3333 }
3334 
3335 // Compare Negative (register) adds a register value and an optionally-shifted
3336 // register value. It updates the condition flags based on the result, and
3337 // discards the result.
3338 bool EmulateInstructionARM::EmulateCMNReg(const uint32_t opcode,
3339  const ARMEncoding encoding) {
3340 #if 0
3341  // ARM pseudo code...
3342  if ConditionPassed() then
3343  EncodingSpecificOperations();
3344  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
3345  (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
3346  APSR.N = result<31>;
3347  APSR.Z = IsZeroBit(result);
3348  APSR.C = carry;
3349  APSR.V = overflow;
3350 #endif
3351 
3352  bool success = false;
3353 
3354  uint32_t Rn; // the first operand
3355  uint32_t Rm; // the second operand
3356  ARM_ShifterType shift_t;
3357  uint32_t shift_n; // the shift applied to the value read from Rm
3358  switch (encoding) {
3359  case eEncodingT1:
3360  Rn = Bits32(opcode, 2, 0);
3361  Rm = Bits32(opcode, 5, 3);
3362  shift_t = SRType_LSL;
3363  shift_n = 0;
3364  break;
3365  case eEncodingT2:
3366  Rn = Bits32(opcode, 19, 16);
3367  Rm = Bits32(opcode, 3, 0);
3368  shift_n = DecodeImmShiftThumb(opcode, shift_t);
3369  // if n == 15 || BadReg(m) then UNPREDICTABLE;
3370  if (Rn == 15 || BadReg(Rm))
3371  return false;
3372  break;
3373  case eEncodingA1:
3374  Rn = Bits32(opcode, 19, 16);
3375  Rm = Bits32(opcode, 3, 0);
3376  shift_n = DecodeImmShiftARM(opcode, shift_t);
3377  break;
3378  default:
3379  return false;
3380  }
3381  // Read the register value from register Rn.
3382  uint32_t val1 = ReadCoreReg(Rn, &success);
3383  if (!success)
3384  return false;
3385 
3386  // Read the register value from register Rm.
3387  uint32_t val2 = ReadCoreReg(Rm, &success);
3388  if (!success)
3389  return false;
3390 
3391  uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3392  if (!success)
3393  return false;
3394  AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
3395 
3397  context.type = EmulateInstruction::eContextImmediate;
3398  context.SetNoArgs();
3399  return WriteFlags(context, res.result, res.carry_out, res.overflow);
3400 }
3401 
3402 // Compare (immediate) subtracts an immediate value from a register value. It
3403 // updates the condition flags based on the result, and discards the result.
3404 bool EmulateInstructionARM::EmulateCMPImm(const uint32_t opcode,
3405  const ARMEncoding encoding) {
3406 #if 0
3407  // ARM pseudo code...
3408  if ConditionPassed() then
3409  EncodingSpecificOperations();
3410  (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
3411  APSR.N = result<31>;
3412  APSR.Z = IsZeroBit(result);
3413  APSR.C = carry;
3414  APSR.V = overflow;
3415 #endif
3416 
3417  bool success = false;
3418 
3419  uint32_t Rn; // the first operand
3420  uint32_t imm32; // the immediate value to be compared with
3421  switch (encoding) {
3422  case eEncodingT1:
3423  Rn = Bits32(opcode, 10, 8);
3424  imm32 = Bits32(opcode, 7, 0);
3425  break;
3426  case eEncodingT2:
3427  Rn = Bits32(opcode, 19, 16);
3428  imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
3429  if (Rn == 15)
3430  return false;
3431  break;
3432  case eEncodingA1:
3433  Rn = Bits32(opcode, 19, 16);
3434  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3435  break;
3436  default:
3437  return false;
3438  }
3439  // Read the register value from the operand register Rn.
3440  uint32_t reg_val = ReadCoreReg(Rn, &success);
3441  if (!success)
3442  return false;
3443 
3444  AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
3445 
3447  context.type = EmulateInstruction::eContextImmediate;
3448  context.SetNoArgs();
3449  return WriteFlags(context, res.result, res.carry_out, res.overflow);
3450 }
3451 
3452 // Compare (register) subtracts an optionally-shifted register value from a
3453 // register value. It updates the condition flags based on the result, and
3454 // discards the result.
3455 bool EmulateInstructionARM::EmulateCMPReg(const uint32_t opcode,
3456  const ARMEncoding encoding) {
3457 #if 0
3458  // ARM pseudo code...
3459  if ConditionPassed() then
3460  EncodingSpecificOperations();
3461  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
3462  (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1');
3463  APSR.N = result<31>;
3464  APSR.Z = IsZeroBit(result);
3465  APSR.C = carry;
3466  APSR.V = overflow;
3467 #endif
3468 
3469  bool success = false;
3470 
3471  uint32_t Rn; // the first operand
3472  uint32_t Rm; // the second operand
3473  ARM_ShifterType shift_t;
3474  uint32_t shift_n; // the shift applied to the value read from Rm
3475  switch (encoding) {
3476  case eEncodingT1:
3477  Rn = Bits32(opcode, 2, 0);
3478  Rm = Bits32(opcode, 5, 3);
3479  shift_t = SRType_LSL;
3480  shift_n = 0;
3481  break;
3482  case eEncodingT2:
3483  Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3484  Rm = Bits32(opcode, 6, 3);
3485  shift_t = SRType_LSL;
3486  shift_n = 0;
3487  if (Rn < 8 && Rm < 8)
3488  return false;
3489  if (Rn == 15 || Rm == 15)
3490  return false;
3491  break;
3492  case eEncodingT3:
3493  Rn = Bits32(opcode, 19, 16);
3494  Rm = Bits32(opcode, 3, 0);
3495  shift_n = DecodeImmShiftThumb(opcode, shift_t);
3496  if (Rn == 15 || BadReg(Rm))
3497  return false;
3498  break;
3499  case eEncodingA1:
3500  Rn = Bits32(opcode, 19, 16);
3501  Rm = Bits32(opcode, 3, 0);
3502  shift_n = DecodeImmShiftARM(opcode, shift_t);
3503  break;
3504  default:
3505  return false;
3506  }
3507  // Read the register value from register Rn.
3508  uint32_t val1 = ReadCoreReg(Rn, &success);
3509  if (!success)
3510  return false;
3511 
3512  // Read the register value from register Rm.
3513  uint32_t val2 = ReadCoreReg(Rm, &success);
3514  if (!success)
3515  return false;
3516 
3517  uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3518  if (!success)
3519  return false;
3520  AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1);
3521 
3523  context.type = EmulateInstruction::eContextImmediate;
3524  context.SetNoArgs();
3525  return WriteFlags(context, res.result, res.carry_out, res.overflow);
3526 }
3527 
3528 // Arithmetic Shift Right (immediate) shifts a register value right by an
3529 // immediate number of bits, shifting in copies of its sign bit, and writes the
3530 // result to the destination register. It can optionally update the condition
3531 // flags based on the result.
3532 bool EmulateInstructionARM::EmulateASRImm(const uint32_t opcode,
3533  const ARMEncoding encoding) {
3534 #if 0
3535  // ARM pseudo code...
3536  if ConditionPassed() then
3537  EncodingSpecificOperations();
3538  (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
3539  if d == 15 then // Can only occur for ARM encoding
3540  ALUWritePC(result); // setflags is always FALSE here
3541  else
3542  R[d] = result;
3543  if setflags then
3544  APSR.N = result<31>;
3545  APSR.Z = IsZeroBit(result);
3546  APSR.C = carry;
3547  // APSR.V unchanged
3548 #endif
3549 
3550  return EmulateShiftImm(opcode, encoding, SRType_ASR);
3551 }
3552 
3553 // Arithmetic Shift Right (register) shifts a register value right by a
3554 // variable number of bits, shifting in copies of its sign bit, and writes the
3555 // result to the destination register. The variable number of bits is read from
3556 // the bottom byte of a register. It can optionally update the condition flags
3557 // based on the result.
3558 bool EmulateInstructionARM::EmulateASRReg(const uint32_t opcode,
3559  const ARMEncoding encoding) {
3560 #if 0
3561  // ARM pseudo code...
3562  if ConditionPassed() then
3563  EncodingSpecificOperations();
3564  shift_n = UInt(R[m]<7:0>);
3565  (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
3566  R[d] = result;
3567  if setflags then
3568  APSR.N = result<31>;
3569  APSR.Z = IsZeroBit(result);
3570  APSR.C = carry;
3571  // APSR.V unchanged
3572 #endif
3573 
3574  return EmulateShiftReg(opcode, encoding, SRType_ASR);
3575 }
3576 
3577 // Logical Shift Left (immediate) shifts a register value left by an immediate
3578 // number of bits, shifting in zeros, and writes the result to the destination
3579 // register. It can optionally update the condition flags based on the result.
3580 bool EmulateInstructionARM::EmulateLSLImm(const uint32_t opcode,
3581  const ARMEncoding encoding) {
3582 #if 0
3583  // ARM pseudo code...
3584  if ConditionPassed() then
3585  EncodingSpecificOperations();
3586  (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
3587  if d == 15 then // Can only occur for ARM encoding
3588  ALUWritePC(result); // setflags is always FALSE here
3589  else
3590  R[d] = result;
3591  if setflags then
3592  APSR.N = result<31>;
3593  APSR.Z = IsZeroBit(result);
3594  APSR.C = carry;
3595  // APSR.V unchanged
3596 #endif
3597 
3598  return EmulateShiftImm(opcode, encoding, SRType_LSL);
3599 }
3600 
3601 // Logical Shift Left (register) shifts a register value left by a variable
3602 // number of bits, shifting in zeros, and writes the result to the destination
3603 // register. The variable number of bits is read from the bottom byte of a
3604 // register. It can optionally update the condition flags based on the result.
3605 bool EmulateInstructionARM::EmulateLSLReg(const uint32_t opcode,
3606  const ARMEncoding encoding) {
3607 #if 0
3608  // ARM pseudo code...
3609  if ConditionPassed() then
3610  EncodingSpecificOperations();
3611  shift_n = UInt(R[m]<7:0>);
3612  (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
3613  R[d] = result;
3614  if setflags then
3615  APSR.N = result<31>;
3616  APSR.Z = IsZeroBit(result);
3617  APSR.C = carry;
3618  // APSR.V unchanged
3619 #endif
3620 
3621  return EmulateShiftReg(opcode, encoding, SRType_LSL);
3622 }
3623 
3624 // Logical Shift Right (immediate) shifts a register value right by an
3625 // immediate number of bits, shifting in zeros, and writes the result to the
3626 // destination register. It can optionally update the condition flags based on
3627 // the result.
3628 bool EmulateInstructionARM::EmulateLSRImm(const uint32_t opcode,
3629  const ARMEncoding encoding) {
3630 #if 0
3631  // ARM pseudo code...
3632  if ConditionPassed() then
3633  EncodingSpecificOperations();
3634  (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
3635  if d == 15 then // Can only occur for ARM encoding
3636  ALUWritePC(result); // setflags is always FALSE here
3637  else
3638  R[d] = result;
3639  if setflags then
3640  APSR.N = result<31>;
3641  APSR.Z = IsZeroBit(result);
3642  APSR.C = carry;
3643  // APSR.V unchanged
3644 #endif
3645 
3646  return EmulateShiftImm(opcode, encoding, SRType_LSR);
3647 }
3648 
3649 // Logical Shift Right (register) shifts a register value right by a variable
3650 // number of bits, shifting in zeros, and writes the result to the destination
3651 // register. The variable number of bits is read from the bottom byte of a
3652 // register. It can optionally update the condition flags based on the result.
3653 bool EmulateInstructionARM::EmulateLSRReg(const uint32_t opcode,
3654  const ARMEncoding encoding) {
3655 #if 0
3656  // ARM pseudo code...
3657  if ConditionPassed() then
3658  EncodingSpecificOperations();
3659  shift_n = UInt(R[m]<7:0>);
3660  (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
3661  R[d] = result;
3662  if setflags then
3663  APSR.N = result<31>;
3664  APSR.Z = IsZeroBit(result);
3665  APSR.C = carry;
3666  // APSR.V unchanged
3667 #endif
3668 
3669  return EmulateShiftReg(opcode, encoding, SRType_LSR);
3670 }
3671 
3672 // Rotate Right (immediate) provides the value of the contents of a register
3673 // rotated by a constant value. The bits that are rotated off the right end are
3674 // inserted into the vacated bit positions on the left. It can optionally
3675 // update the condition flags based on the result.
3676 bool EmulateInstructionARM::EmulateRORImm(const uint32_t opcode,
3677  const ARMEncoding encoding) {
3678 #if 0
3679  // ARM pseudo code...
3680  if ConditionPassed() then
3681  EncodingSpecificOperations();
3682  (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
3683  if d == 15 then // Can only occur for ARM encoding
3684  ALUWritePC(result); // setflags is always FALSE here
3685  else
3686  R[d] = result;
3687  if setflags then
3688  APSR.N = result<31>;
3689  APSR.Z = IsZeroBit(result);
3690  APSR.C = carry;
3691  // APSR.V unchanged
3692 #endif
3693 
3694  return EmulateShiftImm(opcode, encoding, SRType_ROR);
3695 }
3696 
3697 // Rotate Right (register) provides the value of the contents of a register
3698 // rotated by a variable number of bits. The bits that are rotated off the
3699 // right end are inserted into the vacated bit positions on the left. The
3700 // variable number of bits is read from the bottom byte of a register. It can
3701 // optionally update the condition flags based on the result.
3702 bool EmulateInstructionARM::EmulateRORReg(const uint32_t opcode,
3703  const ARMEncoding encoding) {
3704 #if 0
3705  // ARM pseudo code...
3706  if ConditionPassed() then
3707  EncodingSpecificOperations();
3708  shift_n = UInt(R[m]<7:0>);
3709  (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
3710  R[d] = result;
3711  if setflags then
3712  APSR.N = result<31>;
3713  APSR.Z = IsZeroBit(result);
3714  APSR.C = carry;
3715  // APSR.V unchanged
3716 #endif
3717 
3718  return EmulateShiftReg(opcode, encoding, SRType_ROR);
3719 }
3720 
3721 // Rotate Right with Extend provides the value of the contents of a register
3722 // shifted right by one place, with the carry flag shifted into bit [31].
3723 //
3724 // RRX can optionally update the condition flags based on the result.
3725 // In that case, bit [0] is shifted into the carry flag.
3726 bool EmulateInstructionARM::EmulateRRX(const uint32_t opcode,
3727  const ARMEncoding encoding) {
3728 #if 0
3729  // ARM pseudo code...
3730  if ConditionPassed() then
3731  EncodingSpecificOperations();
3732  (result, carry) = Shift_C(R[m], SRType_RRX, 1, APSR.C);
3733  if d == 15 then // Can only occur for ARM encoding
3734  ALUWritePC(result); // setflags is always FALSE here
3735  else
3736  R[d] = result;
3737  if setflags then
3738  APSR.N = result<31>;
3739  APSR.Z = IsZeroBit(result);
3740  APSR.C = carry;
3741  // APSR.V unchanged
3742 #endif
3743 
3744  return EmulateShiftImm(opcode, encoding, SRType_RRX);
3745 }
3746 
3747 bool EmulateInstructionARM::EmulateShiftImm(const uint32_t opcode,
3748  const ARMEncoding encoding,
3749  ARM_ShifterType shift_type) {
3750  // assert(shift_type == SRType_ASR
3751  // || shift_type == SRType_LSL
3752  // || shift_type == SRType_LSR
3753  // || shift_type == SRType_ROR
3754  // || shift_type == SRType_RRX);
3755 
3756  bool success = false;
3757 
3758  if (ConditionPassed(opcode)) {
3759  uint32_t Rd; // the destination register
3760  uint32_t Rm; // the first operand register
3761  uint32_t imm5; // encoding for the shift amount
3762  uint32_t carry; // the carry bit after the shift operation
3763  bool setflags;
3764 
3765  // Special case handling!
3766  // A8.6.139 ROR (immediate) -- Encoding T1
3767  ARMEncoding use_encoding = encoding;
3768  if (shift_type == SRType_ROR && use_encoding == eEncodingT1) {
3769  // Morph the T1 encoding from the ARM Architecture Manual into T2
3770  // encoding to have the same decoding of bit fields as the other Thumb2
3771  // shift operations.
3772  use_encoding = eEncodingT2;
3773  }
3774 
3775  switch (use_encoding) {
3776  case eEncodingT1:
3777  // Due to the above special case handling!
3778  if (shift_type == SRType_ROR)
3779  return false;
3780 
3781  Rd = Bits32(opcode, 2, 0);
3782  Rm = Bits32(opcode, 5, 3);
3783  setflags = !InITBlock();
3784  imm5 = Bits32(opcode, 10, 6);
3785  break;
3786  case eEncodingT2:
3787  // A8.6.141 RRX
3788  // There's no imm form of RRX instructions.
3789  if (shift_type == SRType_RRX)
3790  return false;
3791 
3792  Rd = Bits32(opcode, 11, 8);
3793  Rm = Bits32(opcode, 3, 0);
3794  setflags = BitIsSet(opcode, 20);
3795  imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6);
3796  if (BadReg(Rd) || BadReg(Rm))
3797  return false;
3798  break;
3799  case eEncodingA1:
3800  Rd = Bits32(opcode, 15, 12);
3801  Rm = Bits32(opcode, 3, 0);
3802  setflags = BitIsSet(opcode, 20);
3803  imm5 = Bits32(opcode, 11, 7);
3804  break;
3805  default:
3806  return false;
3807  }
3808 
3809  // A8.6.139 ROR (immediate)
3810  if (shift_type == SRType_ROR && imm5 == 0)
3811  shift_type = SRType_RRX;
3812 
3813  // Get the first operand.
3814  uint32_t value = ReadCoreReg(Rm, &success);
3815  if (!success)
3816  return false;
3817 
3818  // Decode the shift amount if not RRX.
3819  uint32_t amt =
3820  (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5));
3821 
3822  uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3823  if (!success)
3824  return false;
3825 
3826  // The context specifies that an immediate is to be moved into Rd.
3828  context.type = EmulateInstruction::eContextImmediate;
3829  context.SetNoArgs();
3830 
3831  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3832  return false;
3833  }
3834  return true;
3835 }
3836 
3837 bool EmulateInstructionARM::EmulateShiftReg(const uint32_t opcode,
3838  const ARMEncoding encoding,
3839  ARM_ShifterType shift_type) {
3840  // assert(shift_type == SRType_ASR
3841  // || shift_type == SRType_LSL
3842  // || shift_type == SRType_LSR
3843  // || shift_type == SRType_ROR);
3844 
3845  bool success = false;
3846 
3847  if (ConditionPassed(opcode)) {
3848  uint32_t Rd; // the destination register
3849  uint32_t Rn; // the first operand register
3850  uint32_t
3851  Rm; // the register whose bottom byte contains the amount to shift by
3852  uint32_t carry; // the carry bit after the shift operation
3853  bool setflags;
3854  switch (encoding) {
3855  case eEncodingT1:
3856  Rd = Bits32(opcode, 2, 0);
3857  Rn = Rd;
3858  Rm = Bits32(opcode, 5, 3);
3859  setflags = !InITBlock();
3860  break;
3861  case eEncodingT2:
3862  Rd = Bits32(opcode, 11, 8);
3863  Rn = Bits32(opcode, 19, 16);
3864  Rm = Bits32(opcode, 3, 0);
3865  setflags = BitIsSet(opcode, 20);
3866  if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3867  return false;
3868  break;
3869  case eEncodingA1:
3870  Rd = Bits32(opcode, 15, 12);
3871  Rn = Bits32(opcode, 3, 0);
3872  Rm = Bits32(opcode, 11, 8);
3873  setflags = BitIsSet(opcode, 20);
3874  if (Rd == 15 || Rn == 15 || Rm == 15)
3875  return false;
3876  break;
3877  default:
3878  return false;
3879  }
3880 
3881  // Get the first operand.
3882  uint32_t value = ReadCoreReg(Rn, &success);
3883  if (!success)
3884  return false;
3885  // Get the Rm register content.
3886  uint32_t val = ReadCoreReg(Rm, &success);
3887  if (!success)
3888  return false;
3889 
3890  // Get the shift amount.
3891  uint32_t amt = Bits32(val, 7, 0);
3892 
3893  uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3894  if (!success)
3895  return false;
3896 
3897  // The context specifies that an immediate is to be moved into Rd.
3899  context.type = EmulateInstruction::eContextImmediate;
3900  context.SetNoArgs();
3901 
3902  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3903  return false;
3904  }
3905  return true;
3906 }
3907 
3908 // LDM loads multiple registers from consecutive memory locations, using an
3909 // address from a base register. Optionally the address just above the highest
3910 // of those locations can be written back to the base register.
3911 bool EmulateInstructionARM::EmulateLDM(const uint32_t opcode,
3912  const ARMEncoding encoding) {
3913 #if 0
3914  // ARM pseudo code...
3915  if ConditionPassed()
3916  EncodingSpecificOperations(); NullCheckIfThumbEE (n);
3917  address = R[n];
3918 
3919  for i = 0 to 14
3920  if registers<i> == '1' then
3921  R[i] = MemA[address, 4]; address = address + 4;
3922  if registers<15> == '1' then
3923  LoadWritePC (MemA[address, 4]);
3924 
3925  if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers);
3926  if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3927 
3928 #endif
3929 
3930  bool success = false;
3931  if (ConditionPassed(opcode)) {
3932  uint32_t n;
3933  uint32_t registers = 0;
3934  bool wback;
3935  const uint32_t addr_byte_size = GetAddressByteSize();
3936  switch (encoding) {
3937  case eEncodingT1:
3938  // n = UInt(Rn); registers = '00000000':register_list; wback =
3939  // (registers<n> == '0');
3940  n = Bits32(opcode, 10, 8);
3941  registers = Bits32(opcode, 7, 0);
3942  registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
3943  wback = BitIsClear(registers, n);
3944  // if BitCount(registers) < 1 then UNPREDICTABLE;
3945  if (BitCount(registers) < 1)
3946  return false;
3947  break;
3948  case eEncodingT2:
3949  // if W == '1' && Rn == '1101' then SEE POP;
3950  // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3951  n = Bits32(opcode, 19, 16);
3952  registers = Bits32(opcode, 15, 0);
3953  registers = registers & 0xdfff; // Make sure bit 13 is zero.
3954  wback = BitIsSet(opcode, 21);
3955 
3956  // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then
3957  // UNPREDICTABLE;
3958  if ((n == 15) || (BitCount(registers) < 2) ||
3959  (BitIsSet(opcode, 14) && BitIsSet(opcode, 15)))
3960  return false;
3961 
3962  // if registers<15> == '1' && InITBlock() && !LastInITBlock() then
3963  // UNPREDICTABLE;
3964  if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
3965  return false;
3966 
3967  // if wback && registers<n> == '1' then UNPREDICTABLE;
3968  if (wback && BitIsSet(registers, n))
3969  return false;
3970  break;
3971 
3972  case eEncodingA1:
3973  n = Bits32(opcode, 19, 16);
3974  registers = Bits32(opcode, 15, 0);
3975  wback = BitIsSet(opcode, 21);
3976  if ((n == 15) || (BitCount(registers) < 1))
3977  return false;
3978  break;
3979  default:
3980  return false;
3981  }
3982 
3983  int32_t offset = 0;
3984  const addr_t base_address =
3985  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3986  if (!success)
3987  return false;
3988 
3990  context.type = EmulateInstruction::eContextRegisterPlusOffset;
3991  RegisterInfo dwarf_reg;
3992  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3993  context.SetRegisterPlusOffset(dwarf_reg, offset);
3994 
3995  for (int i = 0; i < 14; ++i) {
3996  if (BitIsSet(registers, i)) {
3997  context.type = EmulateInstruction::eContextRegisterPlusOffset;
3998  context.SetRegisterPlusOffset(dwarf_reg, offset);
3999  if (wback && (n == 13)) // Pop Instruction
4000  {
4001  context.type = EmulateInstruction::eContextPopRegisterOffStack;
4002  context.SetAddress(base_address + offset);
4003  }
4004 
4005  // R[i] = MemA [address, 4]; address = address + 4;
4006  uint32_t data = MemARead(context, base_address + offset, addr_byte_size,
4007  0, &success);
4008  if (!success)
4009  return false;
4010 
4011  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
4012  data))
4013  return false;
4014 
4015  offset += addr_byte_size;
4016  }
4017  }
4018 
4019  if (BitIsSet(registers, 15)) {
4020  // LoadWritePC (MemA [address, 4]);
4021  context.type = EmulateInstruction::eContextRegisterPlusOffset;
4022  context.SetRegisterPlusOffset(dwarf_reg, offset);
4023  uint32_t data =
4024  MemARead(context, base_address + offset, addr_byte_size, 0, &success);
4025  if (!success)
4026  return false;
4027  // In ARMv5T and above, this is an interworking branch.
4028  if (!LoadWritePC(context, data))
4029  return false;
4030  }
4031 
4032  if (wback && BitIsClear(registers, n)) {
4033  // R[n] = R[n] + 4 * BitCount (registers)
4034  int32_t offset = addr_byte_size * BitCount(registers);
4035  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4036  context.SetRegisterPlusOffset(dwarf_reg, offset);
4037 
4038  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4039  base_address + offset))
4040  return false;
4041  }
4042  if (wback && BitIsSet(registers, n))
4043  // R[n] bits(32) UNKNOWN;
4044  return WriteBits32Unknown(n);
4045  }
4046  return true;
4047 }
4048 
4049 // LDMDA loads multiple registers from consecutive memory locations using an
4050 // address from a base register.
4051 // The consecutive memory locations end at this address and the address just
4052 // below the lowest of those locations can optionally be written back to the
4053 // base register.
4054 bool EmulateInstructionARM::EmulateLDMDA(const uint32_t opcode,
4055  const ARMEncoding encoding) {
4056 #if 0
4057  // ARM pseudo code...
4058  if ConditionPassed() then
4059  EncodingSpecificOperations();
4060  address = R[n] - 4*BitCount(registers) + 4;
4061 
4062  for i = 0 to 14
4063  if registers<i> == '1' then
4064  R[i] = MemA[address,4]; address = address + 4;
4065 
4066  if registers<15> == '1' then
4067  LoadWritePC(MemA[address,4]);
4068 
4069  if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4070  if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
4071 #endif
4072 
4073  bool success = false;
4074 
4075  if (ConditionPassed(opcode)) {
4076  uint32_t n;
4077  uint32_t registers = 0;
4078  bool wback;
4079  const uint32_t addr_byte_size = GetAddressByteSize();
4080 
4081  // EncodingSpecificOperations();
4082  switch (encoding) {
4083  case eEncodingA1:
4084  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4085  n = Bits32(opcode, 19, 16);
4086  registers = Bits32(opcode, 15, 0);
4087  wback = BitIsSet(opcode, 21);
4088 
4089  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4090  if ((n == 15) || (BitCount(registers) < 1))
4091  return false;
4092 
4093  break;
4094 
4095  default:
4096  return false;
4097  }
4098  // address = R[n] - 4*BitCount(registers) + 4;
4099 
4100  int32_t offset = 0;
4101  addr_t Rn = ReadCoreReg(n, &success);
4102 
4103  if (!success)
4104  return false;
4105 
4106  addr_t address =
4107  Rn - (addr_byte_size * BitCount(registers)) + addr_byte_size;
4108 
4110  context.type = EmulateInstruction::eContextRegisterPlusOffset;
4111  RegisterInfo dwarf_reg;
4112  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
4113  context.SetRegisterPlusOffset(dwarf_reg, offset);
4114 
4115  // for i = 0 to 14
4116  for (int i = 0; i < 14; ++i) {
4117  // if registers<i> == '1' then
4118  if (BitIsSet(registers, i)) {
4119  // R[i] = MemA[address,4]; address = address + 4;
4120  context.SetRegisterPlusOffset(dwarf_reg, Rn - (address + offset));
4121  uint32_t data =
4122  MemARead(context, address + offset, addr_byte_size, 0, &success);
4123  if (!success)
4124  return false;
4125  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
4126  data))
4127  return false;
4128  offset += addr_byte_size;
4129  }
4130  }
4131 
4132  // if registers<15> == '1' then
4133  // LoadWritePC(MemA[address,4]);
4134  if (BitIsSet(registers, 15)) {
4135  context.SetRegisterPlusOffset(dwarf_reg, offset);
4136  uint32_t data =
4137  MemARead(context, address + offset, addr_byte_size, 0, &success);
4138  if (!success)
4139  return false;
4140  // In ARMv5T and above, this is an interworking branch.
4141  if (!LoadWritePC(context, data))
4142  return false;
4143  }
4144 
4145  // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4146  if (wback && BitIsClear(registers, n)) {
4147  if (!success)
4148  return false;
4149 
4150  offset = (addr_byte_size * BitCount(registers)) * -1;
4151  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4152  context.SetImmediateSigned(offset);
4153  addr_t addr = Rn + offset;
4154  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4155  addr))
4156  return false;
4157  }
4158 
4159  // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
4160  if (wback && BitIsSet(registers, n))
4161  return WriteBits32Unknown(n);
4162  }
4163  return true;
4164 }
4165 
4166 // LDMDB loads multiple registers from consecutive memory locations using an
4167 // address from a base register. The
4168 // consecutive memory locations end just below this address, and the address of
4169 // the lowest of those locations can be optionally written back to the base
4170 // register.
4171 bool EmulateInstructionARM::EmulateLDMDB(const uint32_t opcode,
4172  const ARMEncoding encoding) {
4173 #if 0
4174  // ARM pseudo code...
4175  if ConditionPassed() then
4176  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4177  address = R[n] - 4*BitCount(registers);
4178 
4179  for i = 0 to 14
4180  if registers<i> == '1' then
4181  R[i] = MemA[address,4]; address = address + 4;
4182  if registers<15> == '1' then
4183  LoadWritePC(MemA[address,4]);
4184 
4185  if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4186  if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
4187 #endif
4188 
4189  bool success = false;
4190 
4191  if (ConditionPassed(opcode)) {
4192  uint32_t n;
4193  uint32_t registers = 0;
4194  bool wback;
4195  const uint32_t addr_byte_size = GetAddressByteSize();
4196  switch (encoding) {
4197  case eEncodingT1:
4198  // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
4199  n = Bits32(opcode, 19, 16);
4200  registers = Bits32(opcode, 15, 0);
4201  registers = registers & 0xdfff; // Make sure bit 13 is a zero.
4202  wback = BitIsSet(opcode, 21);
4203 
4204  // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then
4205  // UNPREDICTABLE;
4206  if ((n == 15) || (BitCount(registers) < 2) ||
4207  (BitIsSet(opcode, 14) && BitIsSet(opcode, 15)))
4208  return false;
4209 
4210  // if registers<15> == '1' && InITBlock() && !LastInITBlock() then
4211  // UNPREDICTABLE;
4212  if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
4213  return false;
4214 
4215  // if wback && registers<n> == '1' then UNPREDICTABLE;
4216  if (wback && BitIsSet(registers, n))
4217  return false;
4218 
4219  break;
4220 
4221  case eEncodingA1:
4222  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4223  n = Bits32(opcode, 19, 16);
4224  registers = Bits32(opcode, 15, 0);
4225  wback = BitIsSet(opcode, 21);
4226 
4227  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4228  if ((n == 15) || (BitCount(registers) < 1))
4229  return false;
4230 
4231  break;
4232 
4233  default:
4234  return false;
4235  }
4236 
4237  // address = R[n] - 4*BitCount(registers);
4238 
4239  int32_t offset = 0;
4240  addr_t Rn =
4241  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4242 
4243  if (!success)
4244  return false;
4245 
4246  addr_t address = Rn - (addr_byte_size * BitCount(registers));
4248  context.type = EmulateInstruction::eContextRegisterPlusOffset;
4249  RegisterInfo dwarf_reg;
4250  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
4251  context.SetRegisterPlusOffset(dwarf_reg, Rn - address);
4252 
4253  for (int i = 0; i < 14; ++i) {
4254  if (BitIsSet(registers, i)) {
4255  // R[i] = MemA[address,4]; address = address + 4;
4256  context.SetRegisterPlusOffset(dwarf_reg, Rn - (address + offset));
4257  uint32_t data =
4258  MemARead(context, address + offset, addr_byte_size, 0, &success);
4259  if (!success)
4260  return false;
4261 
4262  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
4263  data))
4264  return false;
4265 
4266  offset += addr_byte_size;
4267  }
4268  }
4269 
4270  // if registers<15> == '1' then
4271  // LoadWritePC(MemA[address,4]);
4272  if (BitIsSet(registers, 15)) {
4273  context.SetRegisterPlusOffset(dwarf_reg, offset);
4274  uint32_t data =
4275  MemARead(context, address + offset, addr_byte_size, 0, &success);
4276  if (!success)
4277  return false;
4278  // In ARMv5T and above, this is an interworking branch.
4279  if (!LoadWritePC(context, data))
4280  return false;
4281  }
4282 
4283  // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4284  if (wback && BitIsClear(registers, n)) {
4285  if (!success)
4286  return false;
4287 
4288  offset = (addr_byte_size * BitCount(registers)) * -1;
4289  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4290  context.SetImmediateSigned(offset);
4291  addr_t addr = Rn + offset;
4292  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4293  addr))
4294  return false;
4295  }
4296 
4297  // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only
4298  // possible for encoding A1
4299  if (wback && BitIsSet(registers, n))
4300  return WriteBits32Unknown(n);
4301  }
4302  return true;
4303 }
4304 
4305 // LDMIB loads multiple registers from consecutive memory locations using an
4306 // address from a base register. The
4307 // consecutive memory locations start just above this address, and thea ddress
4308 // of the last of those locations can optinoally be written back to the base
4309 // register.
4310 bool EmulateInstructionARM::EmulateLDMIB(const uint32_t opcode,
4311  const ARMEncoding encoding) {
4312 #if 0
4313  if ConditionPassed() then
4314  EncodingSpecificOperations();
4315  address = R[n] + 4;
4316 
4317  for i = 0 to 14
4318  if registers<i> == '1' then
4319  R[i] = MemA[address,4]; address = address + 4;
4320  if registers<15> == '1' then
4321  LoadWritePC(MemA[address,4]);
4322 
4323  if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
4324  if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
4325 #endif
4326 
4327  bool success = false;
4328 
4329  if (ConditionPassed(opcode)) {
4330  uint32_t n;
4331  uint32_t registers = 0;
4332  bool wback;
4333  const uint32_t addr_byte_size = GetAddressByteSize();
4334  switch (encoding) {
4335  case eEncodingA1:
4336  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4337  n = Bits32(opcode, 19, 16);
4338  registers = Bits32(opcode, 15, 0);
4339  wback = BitIsSet(opcode, 21);
4340 
4341  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4342  if ((n == 15) || (BitCount(registers) < 1))
4343  return false;
4344 
4345  break;
4346  default:
4347  return false;
4348  }
4349  // address = R[n] + 4;
4350 
4351  int32_t offset = 0;
4352  addr_t Rn =
4353  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4354 
4355  if (!success)
4356  return false;
4357 
4358  addr_t address = Rn + addr_byte_size;
4359 
4361  context.type = EmulateInstruction::eContextRegisterPlusOffset;
4362  RegisterInfo dwarf_reg;
4363  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
4364  context.SetRegisterPlusOffset(dwarf_reg, offset);
4365 
4366  for (int i = 0; i < 14; ++i) {
4367  if (BitIsSet(registers, i)) {
4368  // R[i] = MemA[address,4]; address = address + 4;
4369 
4370  context.SetRegisterPlusOffset(dwarf_reg, offset + addr_byte_size);
4371  uint32_t data =
4372  MemARead(context, address + offset, addr_byte_size, 0, &success);
4373  if (!success)
4374  return false;
4375 
4376  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
4377  data))
4378  return false;
4379 
4380  offset += addr_byte_size;
4381  }
4382  }
4383 
4384  // if registers<15> == '1' then
4385  // LoadWritePC(MemA[address,4]);
4386  if (BitIsSet(registers, 15)) {
4387  context.SetRegisterPlusOffset(dwarf_reg, offset);
4388  uint32_t data =
4389  MemARead(context, address + offset, addr_byte_size, 0, &success);
4390  if (!success)
4391  return false;
4392  // In ARMv5T and above, this is an interworking branch.
4393  if (!LoadWritePC(context, data))
4394  return false;
4395  }
4396 
4397  // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
4398  if (wback && BitIsClear(registers, n)) {
4399  if (!success)
4400  return false;
4401 
4402  offset = addr_byte_size * BitCount(registers);
4403  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4404  context.SetImmediateSigned(offset);
4405  addr_t addr = Rn + offset;
4406  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4407  addr))
4408  return false;
4409  }
4410 
4411  // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only
4412  // possible for encoding A1
4413  if (wback && BitIsSet(registers, n))
4414  return WriteBits32Unknown(n);
4415  }
4416  return true;
4417 }
4418 
4419 // Load Register (immediate) calculates an address from a base register value
4420 // and an immediate offset, loads a word from memory, and writes to a register.
4421 // LDR (immediate, Thumb)
4422 bool EmulateInstructionARM::EmulateLDRRtRnImm(const uint32_t opcode,
4423  const ARMEncoding encoding) {
4424 #if 0
4425  // ARM pseudo code...
4426  if (ConditionPassed())
4427  {
4428  EncodingSpecificOperations(); NullCheckIfThumbEE(15);
4429  offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4430  address = if index then offset_addr else R[n];
4431  data = MemU[address,4];
4432  if wback then R[n] = offset_addr;
4433  if t == 15 then
4434  if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
4435  elsif UnalignedSupport() || address<1:0> = '00' then
4436  R[t] = data;
4437  else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7
4438  }
4439 #endif
4440 
4441  bool success = false;
4442 
4443  if (ConditionPassed(opcode)) {
4444  uint32_t Rt; // the destination register
4445  uint32_t Rn; // the base register
4446  uint32_t imm32; // the immediate offset used to form the address
4447  addr_t offset_addr; // the offset address
4448  addr_t address; // the calculated address
4449  uint32_t data; // the literal data value from memory load
4450  bool add, index, wback;
4451  switch (encoding) {
4452  case eEncodingT1:
4453  Rt = Bits32(opcode, 2, 0);
4454  Rn = Bits32(opcode, 5, 3);
4455  imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32);
4456  // index = TRUE; add = TRUE; wback = FALSE
4457  add = true;
4458  index = true;
4459  wback = false;
4460 
4461  break;
4462 
4463  case eEncodingT2:
4464  // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
4465  Rt = Bits32(opcode, 10, 8);
4466  Rn = 13;
4467  imm32 = Bits32(opcode, 7, 0) << 2;
4468 
4469  // index = TRUE; add = TRUE; wback = FALSE;
4470  index = true;
4471  add = true;
4472  wback = false;
4473 
4474  break;
4475 
4476  case eEncodingT3:
4477  // if Rn == '1111' then SEE LDR (literal);
4478  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4479  Rt = Bits32(opcode, 15, 12);
4480  Rn = Bits32(opcode, 19, 16);
4481  imm32 = Bits32(opcode, 11, 0);
4482 
4483  // index = TRUE; add = TRUE; wback = FALSE;
4484  index = true;
4485  add = true;
4486  wback = false;
4487 
4488  // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
4489  if ((Rt == 15) && InITBlock() && !LastInITBlock())
4490  return false;
4491 
4492  break;
4493 
4494  case eEncodingT4:
4495  // if Rn == '1111' then SEE LDR (literal);
4496  // if P == '1' && U == '1' && W == '0' then SEE LDRT;
4497  // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 ==
4498  // '00000100' then SEE POP;
4499  // if P == '0' && W == '0' then UNDEFINED;
4500  if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))
4501  return false;
4502 
4503  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
4504  Rt = Bits32(opcode, 15, 12);
4505  Rn = Bits32(opcode, 19, 16);
4506  imm32 = Bits32(opcode, 7, 0);
4507 
4508  // index = (P == '1'); add = (U == '1'); wback = (W == '1');
4509  index = BitIsSet(opcode, 10);
4510  add = BitIsSet(opcode, 9);
4511  wback = BitIsSet(opcode, 8);
4512 
4513  // if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock())
4514  // then UNPREDICTABLE;
4515  if ((wback && (Rn == Rt)) ||
4516  ((Rt == 15) && InITBlock() && !LastInITBlock()))
4517  return false;
4518 
4519  break;
4520 
4521  default:
4522  return false;
4523  }
4524  uint32_t base = ReadCoreReg(Rn, &success);
4525  if (!success)
4526  return false;
4527  if (add)
4528  offset_addr = base + imm32;
4529  else
4530  offset_addr = base - imm32;
4531 
4532  address = (index ? offset_addr : base);
4533 
4534  RegisterInfo base_reg;
4535  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
4536  if (wback) {
4538  if (Rn == 13) {
4539  ctx.type = eContextAdjustStackPointer;
4540  ctx.SetImmediateSigned((int32_t)(offset_addr - base));
4541  } else if (Rn == GetFramePointerRegisterNumber()) {
4542  ctx.type = eContextSetFramePointer;
4543  ctx.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base));
4544  } else {
4545  ctx.type = EmulateInstruction::eContextAdjustBaseRegister;
4546  ctx.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base));
4547  }
4548 
4549  if (!WriteRegisterUnsigned(ctx, eRegisterKindDWARF, dwarf_r0 + Rn,
4550  offset_addr))
4551  return false;
4552  }
4553 
4554  // Prepare to write to the Rt register.
4556  context.type = EmulateInstruction::eContextRegisterLoad;
4557  context.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base));
4558 
4559  // Read memory from the address.
4560  data = MemURead(context, address, 4, 0, &success);
4561  if (!success)
4562  return false;
4563 
4564  if (Rt == 15) {
4565  if (Bits32(address, 1, 0) == 0) {
4566  if (!LoadWritePC(context, data))
4567  return false;
4568  } else
4569  return false;
4570  } else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) {
4571  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rt,
4572  data))
4573  return false;
4574  } else
4575  WriteBits32Unknown(Rt);
4576  }
4577  return true;
4578 }
4579 
4580 // STM (Store Multiple Increment After) stores multiple registers to consecutive
4581 // memory locations using an address
4582 // from a base register. The consecutive memory locations start at this
4583 // address, and the address just above the last of those locations can
4584 // optionally be written back to the base register.
4585 bool EmulateInstructionARM::EmulateSTM(const uint32_t opcode,
4586  const ARMEncoding encoding) {
4587 #if 0
4588  if ConditionPassed() then
4589  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4590  address = R[n];
4591 
4592  for i = 0 to 14
4593  if registers<i> == '1' then
4594  if i == n && wback && i != LowestSetBit(registers) then
4595  MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
4596  else
4597  MemA[address,4] = R[i];
4598  address = address + 4;
4599 
4600  if registers<15> == '1' then // Only possible for encoding A1
4601  MemA[address,4] = PCStoreValue();
4602  if wback then R[n] = R[n] + 4*BitCount(registers);
4603 #endif
4604 
4605  bool success = false;
4606 
4607  if (ConditionPassed(opcode)) {
4608  uint32_t n;
4609  uint32_t registers = 0;
4610  bool wback;
4611  const uint32_t addr_byte_size = GetAddressByteSize();
4612 
4613  // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4614  switch (encoding) {
4615  case eEncodingT1:
4616  // n = UInt(Rn); registers = '00000000':register_list; wback = TRUE;
4617  n = Bits32(opcode, 10, 8);
4618  registers = Bits32(opcode, 7, 0);
4619  registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
4620  wback = true;
4621 
4622  // if BitCount(registers) < 1 then UNPREDICTABLE;
4623  if (BitCount(registers) < 1)
4624  return false;
4625 
4626  break;
4627 
4628  case eEncodingT2:
4629  // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4630  n = Bits32(opcode, 19, 16);
4631  registers = Bits32(opcode, 15, 0);
4632  registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4633  wback = BitIsSet(opcode, 21);
4634 
4635  // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4636  if ((n == 15) || (BitCount(registers) < 2))
4637  return false;
4638 
4639  // if wback && registers<n> == '1' then UNPREDICTABLE;
4640  if (wback && BitIsSet(registers, n))
4641  return false;
4642 
4643  break;
4644 
4645  case eEncodingA1:
4646  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4647  n = Bits32(opcode, 19, 16);
4648  registers = Bits32(opcode, 15, 0);
4649  wback = BitIsSet(opcode, 21);
4650 
4651  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4652  if ((n == 15) || (BitCount(registers) < 1))
4653  return false;
4654 
4655  break;
4656 
4657  default:
4658  return false;
4659  }
4660 
4661  // address = R[n];
4662  int32_t offset = 0;
4663  const addr_t address =
4664  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4665  if (!success)
4666  return false;
4667 
4669  context.type = EmulateInstruction::eContextRegisterStore;
4670  RegisterInfo base_reg;
4671  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4672 
4673  // for i = 0 to 14
4674  uint32_t lowest_set_bit = 14;
4675  for (uint32_t i = 0; i < 14; ++i) {
4676  // if registers<i> == '1' then
4677  if (BitIsSet(registers, i)) {
4678  if (i < lowest_set_bit)
4679  lowest_set_bit = i;
4680  // if i == n && wback && i != LowestSetBit(registers) then
4681  if ((i == n) && wback && (i != lowest_set_bit))
4682  // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings
4683  // T1 and A1
4684  WriteBits32UnknownToMemory(address + offset);
4685  else {
4686  // MemA[address,4] = R[i];
4687  uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
4688  0, &success);
4689  if (!success)
4690  return false;
4691 
4692  RegisterInfo data_reg;
4693  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4694  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, offset);
4695  if (!MemAWrite(context, address + offset, data, addr_byte_size))
4696  return false;
4697  }
4698 
4699  // address = address + 4;
4700  offset += addr_byte_size;
4701  }
4702  }
4703 
4704  // if registers<15> == '1' then // Only possible for encoding A1
4705  // MemA[address,4] = PCStoreValue();
4706  if (BitIsSet(registers, 15)) {
4707  RegisterInfo pc_reg;
4708  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
4709  context.SetRegisterPlusOffset(pc_reg, 8);
4710  const uint32_t pc = ReadCoreReg(PC_REG, &success);
4711  if (!success)
4712  return false;
4713 
4714  if (!MemAWrite(context, address + offset, pc, addr_byte_size))
4715  return false;
4716  }
4717 
4718  // if wback then R[n] = R[n] + 4*BitCount(registers);
4719  if (wback) {
4720  offset = addr_byte_size * BitCount(registers);
4721  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4722  context.SetImmediateSigned(offset);
4723  addr_t data = address + offset;
4724  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4725  data))
4726  return false;
4727  }
4728  }
4729  return true;
4730 }
4731 
4732 // STMDA (Store Multiple Decrement After) stores multiple registers to
4733 // consecutive memory locations using an address from a base register. The
4734 // consecutive memory locations end at this address, and the address just below
4735 // the lowest of those locations can optionally be written back to the base
4736 // register.
4737 bool EmulateInstructionARM::EmulateSTMDA(const uint32_t opcode,
4738  const ARMEncoding encoding) {
4739 #if 0
4740  if ConditionPassed() then
4741  EncodingSpecificOperations();
4742  address = R[n] - 4*BitCount(registers) + 4;
4743 
4744  for i = 0 to 14
4745  if registers<i> == '1' then
4746  if i == n && wback && i != LowestSetBit(registers) then
4747  MemA[address,4] = bits(32) UNKNOWN;
4748  else
4749  MemA[address,4] = R[i];
4750  address = address + 4;
4751 
4752  if registers<15> == '1' then
4753  MemA[address,4] = PCStoreValue();
4754 
4755  if wback then R[n] = R[n] - 4*BitCount(registers);
4756 #endif
4757 
4758  bool success = false;
4759 
4760  if (ConditionPassed(opcode)) {
4761  uint32_t n;
4762  uint32_t registers = 0;
4763  bool wback;
4764  const uint32_t addr_byte_size = GetAddressByteSize();
4765 
4766  // EncodingSpecificOperations();
4767  switch (encoding) {
4768  case eEncodingA1:
4769  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4770  n = Bits32(opcode, 19, 16);
4771  registers = Bits32(opcode, 15, 0);
4772  wback = BitIsSet(opcode, 21);
4773 
4774  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4775  if ((n == 15) || (BitCount(registers) < 1))
4776  return false;
4777  break;
4778  default:
4779  return false;
4780  }
4781 
4782  // address = R[n] - 4*BitCount(registers) + 4;
4783  int32_t offset = 0;
4784  addr_t Rn = ReadCoreReg(n, &success);
4785  if (!success)
4786  return false;
4787 
4788  addr_t address = Rn - (addr_byte_size * BitCount(registers)) + 4;
4789 
4791  context.type = EmulateInstruction::eContextRegisterStore;
4792  RegisterInfo base_reg;
4793  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4794 
4795  // for i = 0 to 14
4796  uint32_t lowest_bit_set = 14;
4797  for (uint32_t i = 0; i < 14; ++i) {
4798  // if registers<i> == '1' then
4799  if (BitIsSet(registers, i)) {
4800  if (i < lowest_bit_set)
4801  lowest_bit_set = i;
4802  // if i == n && wback && i != LowestSetBit(registers) then
4803  if ((i == n) && wback && (i != lowest_bit_set))
4804  // MemA[address,4] = bits(32) UNKNOWN;
4805  WriteBits32UnknownToMemory(address + offset);
4806  else {
4807  // MemA[address,4] = R[i];
4808  uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
4809  0, &success);
4810  if (!success)
4811  return false;
4812 
4813  RegisterInfo data_reg;
4814  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4815  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
4816  Rn - (address + offset));
4817  if (!MemAWrite(context, address + offset, data, addr_byte_size))
4818  return false;
4819  }
4820 
4821  // address = address + 4;
4822  offset += addr_byte_size;
4823  }
4824  }
4825 
4826  // if registers<15> == '1' then
4827  // MemA[address,4] = PCStoreValue();
4828  if (BitIsSet(registers, 15)) {
4829  RegisterInfo pc_reg;
4830  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
4831  context.SetRegisterPlusOffset(pc_reg, 8);
4832  const uint32_t pc = ReadCoreReg(PC_REG, &success);
4833  if (!success)
4834  return false;
4835 
4836  if (!MemAWrite(context, address + offset, pc, addr_byte_size))
4837  return false;
4838  }
4839 
4840  // if wback then R[n] = R[n] - 4*BitCount(registers);
4841  if (wback) {
4842  offset = (addr_byte_size * BitCount(registers)) * -1;
4843  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4844  context.SetImmediateSigned(offset);
4845  addr_t data = Rn + offset;
4846  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4847  data))
4848  return false;
4849  }
4850  }
4851  return true;
4852 }
4853 
4854 // STMDB (Store Multiple Decrement Before) stores multiple registers to
4855 // consecutive memory locations using an address from a base register. The
4856 // consecutive memory locations end just below this address, and the address of
4857 // the first of those locations can optionally be written back to the base
4858 // register.
4859 bool EmulateInstructionARM::EmulateSTMDB(const uint32_t opcode,
4860  const ARMEncoding encoding) {
4861 #if 0
4862  if ConditionPassed() then
4863  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4864  address = R[n] - 4*BitCount(registers);
4865 
4866  for i = 0 to 14
4867  if registers<i> == '1' then
4868  if i == n && wback && i != LowestSetBit(registers) then
4869  MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
4870  else
4871  MemA[address,4] = R[i];
4872  address = address + 4;
4873 
4874  if registers<15> == '1' then // Only possible for encoding A1
4875  MemA[address,4] = PCStoreValue();
4876 
4877  if wback then R[n] = R[n] - 4*BitCount(registers);
4878 #endif
4879 
4880  bool success = false;
4881 
4882  if (ConditionPassed(opcode)) {
4883  uint32_t n;
4884  uint32_t registers = 0;
4885  bool wback;
4886  const uint32_t addr_byte_size = GetAddressByteSize();
4887 
4888  // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4889  switch (encoding) {
4890  case eEncodingT1:
4891  // if W == '1' && Rn == '1101' then SEE PUSH;
4892  if ((BitIsSet(opcode, 21)) && (Bits32(opcode, 19, 16) == 13)) {
4893  // See PUSH
4894  }
4895  // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4896  n = Bits32(opcode, 19, 16);
4897  registers = Bits32(opcode, 15, 0);
4898  registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4899  wback = BitIsSet(opcode, 21);
4900  // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4901  if ((n == 15) || BitCount(registers) < 2)
4902  return false;
4903  // if wback && registers<n> == '1' then UNPREDICTABLE;
4904  if (wback && BitIsSet(registers, n))
4905  return false;
4906  break;
4907 
4908  case eEncodingA1:
4909  // if W == '1' && Rn == '1101' && BitCount(register_list) >= 2 then SEE
4910  // PUSH;
4911  if (BitIsSet(opcode, 21) && (Bits32(opcode, 19, 16) == 13) &&
4912  BitCount(Bits32(opcode, 15, 0)) >= 2) {
4913  // See Push
4914  }
4915  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4916  n = Bits32(opcode, 19, 16);
4917  registers = Bits32(opcode, 15, 0);
4918  wback = BitIsSet(opcode, 21);
4919  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4920  if ((n == 15) || BitCount(registers) < 1)
4921  return false;
4922  break;
4923 
4924  default:
4925  return false;
4926  }
4927 
4928  // address = R[n] - 4*BitCount(registers);
4929 
4930  int32_t offset = 0;
4931  addr_t Rn =
4932  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4933  if (!success)
4934  return false;
4935 
4936  addr_t address = Rn - (addr_byte_size * BitCount(registers));
4937 
4939  context.type = EmulateInstruction::eContextRegisterStore;
4940  RegisterInfo base_reg;
4941  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4942 
4943  // for i = 0 to 14
4944  uint32_t lowest_set_bit = 14;
4945  for (uint32_t i = 0; i < 14; ++i) {
4946  // if registers<i> == '1' then
4947  if (BitIsSet(registers, i)) {
4948  if (i < lowest_set_bit)
4949  lowest_set_bit = i;
4950  // if i == n && wback && i != LowestSetBit(registers) then
4951  if ((i == n) && wback && (i != lowest_set_bit))
4952  // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding
4953  // A1
4954  WriteBits32UnknownToMemory(address + offset);
4955  else {
4956  // MemA[address,4] = R[i];
4957  uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
4958  0, &success);
4959  if (!success)
4960  return false;
4961 
4962  RegisterInfo data_reg;
4963  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4964  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
4965  Rn - (address + offset));
4966  if (!MemAWrite(context, address + offset, data, addr_byte_size))
4967  return false;
4968  }
4969 
4970  // address = address + 4;
4971  offset += addr_byte_size;
4972  }
4973  }
4974 
4975  // if registers<15> == '1' then // Only possible for encoding A1
4976  // MemA[address,4] = PCStoreValue();
4977  if (BitIsSet(registers, 15)) {
4978  RegisterInfo pc_reg;
4979  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
4980  context.SetRegisterPlusOffset(pc_reg, 8);
4981  const uint32_t pc = ReadCoreReg(PC_REG, &success);
4982  if (!success)
4983  return false;
4984 
4985  if (!MemAWrite(context, address + offset, pc, addr_byte_size))
4986  return false;
4987  }
4988 
4989  // if wback then R[n] = R[n] - 4*BitCount(registers);
4990  if (wback) {
4991  offset = (addr_byte_size * BitCount(registers)) * -1;
4992  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4993  context.SetImmediateSigned(offset);
4994  addr_t data = Rn + offset;
4995  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4996  data))
4997  return false;
4998  }
4999  }
5000  return true;
5001 }
5002 
5003 // STMIB (Store Multiple Increment Before) stores multiple registers to
5004 // consecutive memory locations using an address from a base register. The
5005 // consecutive memory locations start just above this address, and the address
5006 // of the last of those locations can optionally be written back to the base
5007 // register.
5008 bool EmulateInstructionARM::EmulateSTMIB(const uint32_t opcode,
5009  const ARMEncoding encoding) {
5010 #if 0
5011  if ConditionPassed() then
5012  EncodingSpecificOperations();
5013  address = R[n] + 4;
5014 
5015  for i = 0 to 14
5016  if registers<i> == '1' then
5017  if i == n && wback && i != LowestSetBit(registers) then
5018  MemA[address,4] = bits(32) UNKNOWN;
5019  else
5020  MemA[address,4] = R[i];
5021  address = address + 4;
5022 
5023  if registers<15> == '1' then
5024  MemA[address,4] = PCStoreValue();
5025 
5026  if wback then R[n] = R[n] + 4*BitCount(registers);
5027 #endif
5028 
5029  bool success = false;
5030 
5031  if (ConditionPassed(opcode)) {
5032  uint32_t n;
5033  uint32_t registers = 0;
5034  bool wback;
5035  const uint32_t addr_byte_size = GetAddressByteSize();
5036 
5037  // EncodingSpecificOperations();
5038  switch (encoding) {
5039  case eEncodingA1:
5040  // n = UInt(Rn); registers = register_list; wback = (W == '1');
5041  n = Bits32(opcode, 19, 16);
5042  registers = Bits32(opcode, 15, 0);
5043  wback = BitIsSet(opcode, 21);
5044 
5045  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
5046  if ((n == 15) && (BitCount(registers) < 1))
5047  return false;
5048  break;
5049  default:
5050  return false;
5051  }
5052  // address = R[n] + 4;
5053 
5054  int32_t offset = 0;
5055  addr_t Rn = ReadCoreReg(n, &success);
5056  if (!success)
5057  return false;
5058 
5059  addr_t address = Rn + addr_byte_size;
5060 
5062  context.type = EmulateInstruction::eContextRegisterStore;
5063  RegisterInfo base_reg;
5064  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5065 
5066  uint32_t lowest_set_bit = 14;
5067  // for i = 0 to 14
5068  for (uint32_t i = 0; i < 14; ++i) {
5069  // if registers<i> == '1' then
5070  if (BitIsSet(registers, i)) {
5071  if (i < lowest_set_bit)
5072  lowest_set_bit = i;
5073  // if i == n && wback && i != LowestSetBit(registers) then
5074  if ((i == n) && wback && (i != lowest_set_bit))
5075  // MemA[address,4] = bits(32) UNKNOWN;
5076  WriteBits32UnknownToMemory(address + offset);
5077  // else
5078  else {
5079  // MemA[address,4] = R[i];
5080  uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
5081  0, &success);
5082  if (!success)
5083  return false;
5084 
5085  RegisterInfo data_reg;
5086  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg);
5087  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
5088  offset + addr_byte_size);
5089  if (!MemAWrite(context, address + offset, data, addr_byte_size))
5090  return false;
5091  }
5092 
5093  // address = address + 4;
5094  offset += addr_byte_size;
5095  }
5096  }
5097 
5098  // if registers<15> == '1' then
5099  // MemA[address,4] = PCStoreValue();
5100  if (BitIsSet(registers, 15)) {
5101  RegisterInfo pc_reg;
5102  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
5103  context.SetRegisterPlusOffset(pc_reg, 8);
5104  const uint32_t pc = ReadCoreReg(PC_REG, &success);
5105  if (!success)
5106  return false;
5107 
5108  if (!MemAWrite(context, address + offset, pc, addr_byte_size))
5109  return false;
5110  }
5111 
5112  // if wback then R[n] = R[n] + 4*BitCount(registers);
5113  if (wback) {
5114  offset = addr_byte_size * BitCount(registers);
5115  context.type = EmulateInstruction::eContextAdjustBaseRegister;
5116  context.SetImmediateSigned(offset);
5117  addr_t data = Rn + offset;
5118  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5119  data))
5120  return false;
5121  }
5122  }
5123  return true;
5124 }
5125 
5126 // STR (store immediate) calculates an address from a base register value and an
5127 // immediate offset, and stores a word
5128 // from a register to memory. It can use offset, post-indexed, or pre-indexed
5129 // addressing.
5130 bool EmulateInstructionARM::EmulateSTRThumb(const uint32_t opcode,
5131  const ARMEncoding encoding) {
5132 #if 0
5133  if ConditionPassed() then
5134  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5135  offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5136  address = if index then offset_addr else R[n];
5137  if UnalignedSupport() || address<1:0> == '00' then
5138  MemU[address,4] = R[t];
5139  else // Can only occur before ARMv7
5140  MemU[address,4] = bits(32) UNKNOWN;
5141  if wback then R[n] = offset_addr;
5142 #endif
5143 
5144  bool success = false;
5145 
5146  if (ConditionPassed(opcode)) {
5147  const uint32_t addr_byte_size = GetAddressByteSize();
5148 
5149  uint32_t t;
5150  uint32_t n;
5151  uint32_t imm32;
5152  bool index;
5153  bool add;
5154  bool wback;
5155  // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
5156  switch (encoding) {
5157  case eEncodingT1:
5158  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
5159  t = Bits32(opcode, 2, 0);
5160  n = Bits32(opcode, 5, 3);
5161  imm32 = Bits32(opcode, 10, 6) << 2;
5162 
5163  // index = TRUE; add = TRUE; wback = FALSE;
5164  index = true;
5165  add = false;
5166  wback = false;
5167  break;
5168 
5169  case eEncodingT2:
5170  // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
5171  t = Bits32(opcode, 10, 8);
5172  n = 13;
5173  imm32 = Bits32(opcode, 7, 0) << 2;
5174 
5175  // index = TRUE; add = TRUE; wback = FALSE;
5176  index = true;
5177  add = true;
5178  wback = false;
5179  break;
5180 
5181  case eEncodingT3:
5182  // if Rn == '1111' then UNDEFINED;
5183  if (Bits32(opcode, 19, 16) == 15)
5184  return false;
5185 
5186  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5187  t = Bits32(opcode, 15, 12);
5188  n = Bits32(opcode, 19, 16);
5189  imm32 = Bits32(opcode, 11, 0);
5190 
5191  // index = TRUE; add = TRUE; wback = FALSE;
5192  index = true;
5193  add = true;
5194  wback = false;
5195 
5196  // if t == 15 then UNPREDICTABLE;
5197  if (t == 15)
5198  return false;
5199  break;
5200 
5201  case eEncodingT4:
5202  // if P == '1' && U == '1' && W == '0' then SEE STRT;
5203  // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 ==
5204  // '00000100' then SEE PUSH;
5205  // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
5206  if ((Bits32(opcode, 19, 16) == 15) ||
5207  (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)))
5208  return false;
5209 
5210  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5211  t = Bits32(opcode, 15, 12);
5212  n = Bits32(opcode, 19, 16);
5213  imm32 = Bits32(opcode, 7, 0);
5214 
5215  // index = (P == '1'); add = (U == '1'); wback = (W == '1');
5216  index = BitIsSet(opcode, 10);
5217  add = BitIsSet(opcode, 9);
5218  wback = BitIsSet(opcode, 8);
5219 
5220  // if t == 15 || (wback && n == t) then UNPREDICTABLE;
5221  if ((t == 15) || (wback && (n == t)))
5222  return false;
5223  break;
5224 
5225  default:
5226  return false;
5227  }
5228 
5229  addr_t offset_addr;
5230  addr_t address;
5231 
5232  // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5233  uint32_t base_address = ReadCoreReg(n, &success);
5234  if (!success)
5235  return false;
5236 
5237  if (add)
5238  offset_addr = base_address + imm32;
5239  else
5240  offset_addr = base_address - imm32;
5241 
5242  // address = if index then offset_addr else R[n];
5243  if (index)
5244  address = offset_addr;
5245  else
5246  address = base_address;
5247 
5249  if (n == 13)
5250  context.type = eContextPushRegisterOnStack;
5251  else
5252  context.type = eContextRegisterStore;
5253 
5254  RegisterInfo base_reg;
5255  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5256 
5257  // if UnalignedSupport() || address<1:0> == '00' then
5258  if (UnalignedSupport() ||
5259  (BitIsClear(address, 1) && BitIsClear(address, 0))) {
5260  // MemU[address,4] = R[t];
5261  uint32_t data =
5262  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5263  if (!success)
5264  return false;
5265 
5266  RegisterInfo data_reg;
5267  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5268  int32_t offset = address - base_address;
5269  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, offset);
5270  if (!MemUWrite(context, address, data, addr_byte_size))
5271  return false;
5272  } else {
5273  // MemU[address,4] = bits(32) UNKNOWN;
5274  WriteBits32UnknownToMemory(address);
5275  }
5276 
5277  // if wback then R[n] = offset_addr;
5278  if (wback) {
5279  if (n == 13)
5280  context.type = eContextAdjustStackPointer;
5281  else
5282  context.type = eContextAdjustBaseRegister;
5283  context.SetAddress(offset_addr);
5284 
5285  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5286  offset_addr))
5287  return false;
5288  }
5289  }
5290  return true;
5291 }
5292 
5293 // STR (Store Register) calculates an address from a base register value and an
5294 // offset register value, stores a
5295 // word from a register to memory. The offset register value can optionally
5296 // be shifted.
5297 bool EmulateInstructionARM::EmulateSTRRegister(const uint32_t opcode,
5298  const ARMEncoding encoding) {
5299 #if 0
5300  if ConditionPassed() then
5301  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5302  offset = Shift(R[m], shift_t, shift_n, APSR.C);
5303  offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5304  address = if index then offset_addr else R[n];
5305  if t == 15 then // Only possible for encoding A1
5306  data = PCStoreValue();
5307  else
5308  data = R[t];
5309  if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
5310  MemU[address,4] = data;
5311  else // Can only occur before ARMv7
5312  MemU[address,4] = bits(32) UNKNOWN;
5313  if wback then R[n] = offset_addr;
5314 #endif
5315 
5316  bool success = false;
5317 
5318  if (ConditionPassed(opcode)) {
5319  const uint32_t addr_byte_size = GetAddressByteSize();
5320 
5321  uint32_t t;
5322  uint32_t n;
5323  uint32_t m;
5324  ARM_ShifterType shift_t;
5325  uint32_t shift_n;
5326  bool index;
5327  bool add;
5328  bool wback;
5329 
5330  // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
5331  switch (encoding) {
5332  case eEncodingT1:
5333  // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation
5334  // in ThumbEE";
5335  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5336  t = Bits32(opcode, 2, 0);
5337  n = Bits32(opcode, 5, 3);
5338  m = Bits32(opcode, 8, 6);
5339 
5340  // index = TRUE; add = TRUE; wback = FALSE;
5341  index = true;
5342  add = true;
5343  wback = false;
5344 
5345  // (shift_t, shift_n) = (SRType_LSL, 0);
5346  shift_t = SRType_LSL;
5347  shift_n = 0;
5348  break;
5349 
5350  case eEncodingT2:
5351  // if Rn == '1111' then UNDEFINED;
5352  if (Bits32(opcode, 19, 16) == 15)
5353  return false;
5354 
5355  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5356  t = Bits32(opcode, 15, 12);
5357  n = Bits32(opcode, 19, 16);
5358  m = Bits32(opcode, 3, 0);
5359 
5360  // index = TRUE; add = TRUE; wback = FALSE;
5361  index = true;
5362  add = true;
5363  wback = false;
5364 
5365  // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
5366  shift_t = SRType_LSL;
5367  shift_n = Bits32(opcode, 5, 4);
5368 
5369  // if t == 15 || BadReg(m) then UNPREDICTABLE;
5370  if ((t == 15) || (BadReg(m)))
5371  return false;
5372  break;
5373 
5374  case eEncodingA1: {
5375  // if P == '0' && W == '1' then SEE STRT;
5376  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5377  t = Bits32(opcode, 15, 12);
5378  n = Bits32(opcode, 19, 16);
5379  m = Bits32(opcode, 3, 0);
5380 
5381  // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
5382  // (W == '1');
5383  index = BitIsSet(opcode, 24);
5384  add = BitIsSet(opcode, 23);
5385  wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
5386 
5387  // (shift_t, shift_n) = DecodeImmShift(type, imm5);
5388  uint32_t typ = Bits32(opcode, 6, 5);
5389  uint32_t imm5 = Bits32(opcode, 11, 7);
5390  shift_n = DecodeImmShift(typ, imm5, shift_t);
5391 
5392  // if m == 15 then UNPREDICTABLE;
5393  if (m == 15)
5394  return false;
5395 
5396  // if wback && (n == 15 || n == t) then UNPREDICTABLE;
5397  if (wback && ((n == 15) || (n == t)))
5398  return false;
5399 
5400  break;
5401  }
5402  default:
5403  return false;
5404  }
5405 
5406  addr_t offset_addr;
5407  addr_t address;
5408  int32_t offset = 0;
5409 
5410  addr_t base_address =
5411  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
5412  if (!success)
5413  return false;
5414 
5415  uint32_t Rm_data =
5416  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
5417  if (!success)
5418  return false;
5419 
5420  // offset = Shift(R[m], shift_t, shift_n, APSR.C);
5421  offset = Shift(Rm_data, shift_t, shift_n, APSR_C, &success);
5422  if (!success)
5423  return false;
5424 
5425  // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5426  if (add)
5427  offset_addr = base_address + offset;
5428  else
5429  offset_addr = base_address - offset;
5430 
5431  // address = if index then offset_addr else R[n];
5432  if (index)
5433  address = offset_addr;
5434  else
5435  address = base_address;
5436 
5437  uint32_t data;
5438  // if t == 15 then // Only possible for encoding A1
5439  if (t == 15)
5440  // data = PCStoreValue();
5441  data = ReadCoreReg(PC_REG, &success);
5442  else
5443  // data = R[t];
5444  data =
5445  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5446 
5447  if (!success)
5448  return false;
5449 
5451  context.type = eContextRegisterStore;
5452 
5453  // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() ==
5454  // InstrSet_ARM then
5455  if (UnalignedSupport() ||
5456  (BitIsClear(address, 1) && BitIsClear(address, 0)) ||
5457  CurrentInstrSet() == eModeARM) {
5458  // MemU[address,4] = data;
5459 
5460  RegisterInfo base_reg;
5461  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5462 
5463  RegisterInfo data_reg;
5464  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5465 
5466  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
5467  address - base_address);
5468  if (!MemUWrite(context, address, data, addr_byte_size))
5469  return false;
5470 
5471  } else
5472  // MemU[address,4] = bits(32) UNKNOWN;
5473  WriteBits32UnknownToMemory(address);
5474 
5475  // if wback then R[n] = offset_addr;
5476  if (wback) {
5477  context.type = eContextRegisterLoad;
5478  context.SetAddress(offset_addr);
5479  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5480  offset_addr))
5481  return false;
5482  }
5483  }
5484  return true;
5485 }
5486 
5487 bool EmulateInstructionARM::EmulateSTRBThumb(const uint32_t opcode,
5488  const ARMEncoding encoding) {
5489 #if 0
5490  if ConditionPassed() then
5491  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5492  offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5493  address = if index then offset_addr else R[n];
5494  MemU[address,1] = R[t]<7:0>;
5495  if wback then R[n] = offset_addr;
5496 #endif
5497 
5498  bool success = false;
5499 
5500  if (ConditionPassed(opcode)) {
5501  uint32_t t;
5502  uint32_t n;
5503  uint32_t imm32;
5504  bool index;
5505  bool add;
5506  bool wback;
5507  // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5508  switch (encoding) {
5509  case eEncodingT1:
5510  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
5511  t = Bits32(opcode, 2, 0);
5512  n = Bits32(opcode, 5, 3);
5513  imm32 = Bits32(opcode, 10, 6);
5514 
5515  // index = TRUE; add = TRUE; wback = FALSE;
5516  index = true;
5517  add = true;
5518  wback = false;
5519  break;
5520 
5521  case eEncodingT2:
5522  // if Rn == '1111' then UNDEFINED;
5523  if (Bits32(opcode, 19, 16) == 15)
5524  return false;
5525 
5526  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5527  t = Bits32(opcode, 15, 12);
5528  n = Bits32(opcode, 19, 16);
5529  imm32 = Bits32(opcode, 11, 0);
5530 
5531  // index = TRUE; add = TRUE; wback = FALSE;
5532  index = true;
5533  add = true;
5534  wback = false;
5535 
5536  // if BadReg(t) then UNPREDICTABLE;
5537  if (BadReg(t))
5538  return false;
5539  break;
5540 
5541  case eEncodingT3:
5542  // if P == '1' && U == '1' && W == '0' then SEE STRBT;
5543  // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
5544  if (Bits32(opcode, 19, 16) == 15)
5545  return false;
5546 
5547  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5548  t = Bits32(opcode, 15, 12);
5549  n = Bits32(opcode, 19, 16);
5550  imm32 = Bits32(opcode, 7, 0);
5551 
5552  // index = (P == '1'); add = (U == '1'); wback = (W == '1');
5553  index = BitIsSet(opcode, 10);
5554  add = BitIsSet(opcode, 9);
5555  wback = BitIsSet(opcode, 8);
5556 
5557  // if BadReg(t) || (wback && n == t) then UNPREDICTABLE
5558  if ((BadReg(t)) || (wback && (n == t)))
5559  return false;
5560  break;
5561 
5562  default:
5563  return false;
5564  }
5565 
5566  addr_t offset_addr;
5567  addr_t address;
5568  addr_t base_address =
5569  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
5570  if (!success)
5571  return false;
5572 
5573  // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5574  if (add)
5575  offset_addr = base_address + imm32;
5576  else
5577  offset_addr = base_address - imm32;
5578 
5579  // address = if index then offset_addr else R[n];
5580  if (index)
5581  address = offset_addr;
5582  else
5583  address = base_address;
5584 
5585  // MemU[address,1] = R[t]<7:0>
5586  RegisterInfo base_reg;
5587  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5588 
5589  RegisterInfo data_reg;
5590  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5591 
5593  context.type = eContextRegisterStore;
5594  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
5595  address - base_address);
5596 
5597  uint32_t data =
5598  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5599  if (!success)
5600  return false;
5601 
5602  data = Bits32(data, 7, 0);
5603 
5604  if (!MemUWrite(context, address, data, 1))
5605  return false;
5606 
5607  // if wback then R[n] = offset_addr;
5608  if (wback) {
5609  context.type = eContextRegisterLoad;
5610  context.SetAddress(offset_addr);
5611  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5612  offset_addr))
5613  return false;
5614  }
5615  }
5616 
5617  return true;
5618 }
5619 
5620 // STRH (register) calculates an address from a base register value and an
5621 // offset register value, and stores a
5622 // halfword from a register to memory. The offset register value can be
5623 // shifted left by 0, 1, 2, or 3 bits.
5624 bool EmulateInstructionARM::EmulateSTRHRegister(const uint32_t opcode,
5625  const ARMEncoding encoding) {
5626 #if 0
5627  if ConditionPassed() then
5628  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5629  offset = Shift(R[m], shift_t, shift_n, APSR.C);
5630  offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5631  address = if index then offset_addr else R[n];
5632  if UnalignedSupport() || address<0> == '0' then
5633  MemU[address,2] = R[t]<15:0>;
5634  else // Can only occur before ARMv7
5635  MemU[address,2] = bits(16) UNKNOWN;
5636  if wback then R[n] = offset_addr;
5637 #endif
5638 
5639  bool success = false;
5640 
5641  if (ConditionPassed(opcode)) {
5642  uint32_t t;
5643  uint32_t n;
5644  uint32_t m;
5645  bool index;
5646  bool add;
5647  bool wback;
5648  ARM_ShifterType shift_t;
5649  uint32_t shift_n;
5650 
5651  // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5652  switch (encoding) {
5653  case eEncodingT1:
5654  // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation
5655  // in ThumbEE";
5656  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5657  t = Bits32(opcode, 2, 0);
5658  n = Bits32(opcode, 5, 3);
5659  m = Bits32(opcode, 8, 6);
5660 
5661  // index = TRUE; add = TRUE; wback = FALSE;
5662  index = true;
5663  add = true;
5664  wback = false;
5665 
5666  // (shift_t, shift_n) = (SRType_LSL, 0);
5667  shift_t = SRType_LSL;
5668  shift_n = 0;
5669 
5670  break;
5671 
5672  case eEncodingT2:
5673  // if Rn == '1111' then UNDEFINED;
5674  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5675  t = Bits32(opcode, 15, 12);
5676  n = Bits32(opcode, 19, 16);
5677  m = Bits32(opcode, 3, 0);
5678  if (n == 15)
5679  return false;
5680 
5681  // index = TRUE; add = TRUE; wback = FALSE;
5682  index = true;
5683  add = true;
5684  wback = false;
5685 
5686  // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
5687  shift_t = SRType_LSL;
5688  shift_n = Bits32(opcode, 5, 4);
5689 
5690  // if BadReg(t) || BadReg(m) then UNPREDICTABLE;
5691  if (BadReg(t) || BadReg(m))
5692  return false;
5693 
5694  break;
5695 
5696  case eEncodingA1:
5697  // if P == '0' && W == '1' then SEE STRHT;
5698  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5699  t = Bits32(opcode, 15, 12);
5700  n = Bits32(opcode, 19, 16);
5701  m = Bits32(opcode, 3, 0);
5702 
5703  // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
5704  // (W == '1');
5705  index = BitIsSet(opcode, 24);
5706  add = BitIsSet(opcode, 23);
5707  wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
5708 
5709  // (shift_t, shift_n) = (SRType_LSL, 0);
5710  shift_t = SRType_LSL;
5711  shift_n = 0;
5712 
5713  // if t == 15 || m == 15 then UNPREDICTABLE;
5714  if ((t == 15) || (m == 15))
5715  return false;
5716 
5717  // if wback && (n == 15 || n == t) then UNPREDICTABLE;
5718  if (wback && ((n == 15) || (n == t)))
5719  return false;
5720 
5721  break;
5722 
5723  default:
5724  return false;
5725  }
5726 
5727  uint32_t Rm = ReadCoreReg(m, &success);
5728  if (!success)
5729  return false;
5730 
5731  uint32_t Rn = ReadCoreReg(n, &success);
5732  if (!success)
5733  return false;
5734 
5735  // offset = Shift(R[m], shift_t, shift_n, APSR.C);
5736  uint32_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
5737  if (!success)
5738  return false;
5739 
5740  // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5741  addr_t offset_addr;
5742  if (add)
5743  offset_addr = Rn + offset;
5744  else
5745  offset_addr = Rn - offset;
5746 
5747  // address = if index then offset_addr else R[n];
5748  addr_t address;
5749  if (index)
5750  address = offset_addr;
5751  else
5752  address = Rn;
5753 
5755  context.type = eContextRegisterStore;
5756  RegisterInfo base_reg;
5757  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5758  RegisterInfo offset_reg;
5759  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
5760 
5761  // if UnalignedSupport() || address<0> == '0' then
5762  if (UnalignedSupport() || BitIsClear(address, 0)) {
5763  // MemU[address,2] = R[t]<15:0>;
5764  uint32_t Rt = ReadCoreReg(t, &success);
5765  if (!success)
5766  return false;
5767 
5769  context.type = eContextRegisterStore;
5770  RegisterInfo base_reg;
5771  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5772  RegisterInfo offset_reg;
5773  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
5774  RegisterInfo data_reg;
5775  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5776  context.SetRegisterToRegisterPlusIndirectOffset(base_reg, offset_reg,
5777  data_reg);
5778 
5779  if (!MemUWrite(context, address, Bits32(Rt, 15, 0), 2))
5780  return false;
5781  } else // Can only occur before ARMv7
5782  {
5783  // MemU[address,2] = bits(16) UNKNOWN;
5784  }
5785 
5786  // if wback then R[n] = offset_addr;
5787  if (wback) {
5788  context.type = eContextAdjustBaseRegister;
5789  context.SetAddress(offset_addr);
5790  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5791  offset_addr))
5792  return false;
5793  }
5794  }
5795 
5796  return true;
5797 }
5798 
5799 // Add with Carry (immediate) adds an immediate value and the carry flag value
5800 // to a register value, and writes the result to the destination register. It
5801 // can optionally update the condition flags based on the result.
5802 bool EmulateInstructionARM::EmulateADCImm(const uint32_t opcode,
5803  const ARMEncoding encoding) {
5804 #if 0
5805  // ARM pseudo code...
5806  if ConditionPassed() then
5807  EncodingSpecificOperations();
5808  (result, carry, overflow) = AddWithCarry(R[n], imm32, APSR.C);
5809  if d == 15 then // Can only occur for ARM encoding
5810  ALUWritePC(result); // setflags is always FALSE here
5811  else
5812  R[d] = result;
5813  if setflags then
5814  APSR.N = result<31>;
5815  APSR.Z = IsZeroBit(result);
5816  APSR.C = carry;
5817  APSR.V = overflow;
5818 #endif
5819 
5820  bool success = false;
5821 
5822  if (ConditionPassed(opcode)) {
5823  uint32_t Rd, Rn;
5824  uint32_t
5825  imm32; // the immediate value to be added to the value obtained from Rn
5826  bool setflags;
5827  switch (encoding) {
5828  case eEncodingT1:
5829  Rd = Bits32(opcode, 11, 8);
5830  Rn = Bits32(opcode, 19, 16);
5831  setflags = BitIsSet(opcode, 20);
5832  imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
5833  if (BadReg(Rd) || BadReg(Rn))
5834  return false;
5835  break;
5836  case eEncodingA1:
5837  Rd = Bits32(opcode, 15, 12);
5838  Rn = Bits32(opcode, 19, 16);
5839  setflags = BitIsSet(opcode, 20);
5840  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5841 
5842  if (Rd == 15 && setflags)
5843  return EmulateSUBSPcLrEtc(opcode, encoding);
5844  break;
5845  default:
5846  return false;
5847  }
5848 
5849  // Read the first operand.
5850  int32_t val1 = ReadCoreReg(Rn, &success);
5851  if (!success)
5852  return false;
5853 
5854  AddWithCarryResult res = AddWithCarry(val1, imm32, APSR_C);
5855 
5857  context.type = EmulateInstruction::eContextImmediate;
5858  context.SetNoArgs();
5859 
5860  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
5861  res.carry_out, res.overflow))
5862  return false;
5863  }
5864  return true;
5865 }
5866 
5867 // Add with Carry (register) adds a register value, the carry flag value, and
5868 // an optionally-shifted register value, and writes the result to the
5869 // destination register. It can optionally update the condition flags based on
5870 // the result.
5871 bool EmulateInstructionARM::EmulateADCReg(const uint32_t opcode,
5872  const ARMEncoding encoding) {
5873 #if 0
5874  // ARM pseudo code...
5875  if ConditionPassed() then
5876  EncodingSpecificOperations();
5877  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
5878  (result, carry, overflow) = AddWithCarry(R[n], shifted, APSR.C);
5879  if d == 15 then // Can only occur for ARM encoding
5880  ALUWritePC(result); // setflags is always FALSE here
5881  else
5882  R[d] = result;
5883  if setflags then
5884  APSR.N = result<31>;
5885  APSR.Z = IsZeroBit(result);
5886  APSR.C = carry;
5887  APSR.V = overflow;
5888 #endif
5889 
5890  bool success = false;
5891 
5892  if (ConditionPassed(opcode)) {
5893  uint32_t Rd, Rn, Rm;
5894  ARM_ShifterType shift_t;
5895  uint32_t shift_n; // the shift applied to the value read from Rm
5896  bool setflags;
5897  switch (encoding) {
5898  case eEncodingT1:
5899  Rd = Rn = Bits32(opcode, 2, 0);
5900  Rm = Bits32(opcode, 5, 3);
5901  setflags = !InITBlock();
5902  shift_t = SRType_LSL;
5903  shift_n = 0;
5904  break;
5905  case eEncodingT2:
5906  Rd = Bits32(opcode, 11, 8);
5907  Rn = Bits32(opcode, 19, 16);
5908  Rm = Bits32(opcode, 3, 0);
5909  setflags = BitIsSet(opcode, 20);
5910  shift_n = DecodeImmShiftThumb(opcode, shift_t);
5911  if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5912  return false;
5913  break;
5914  case eEncodingA1:
5915  Rd = Bits32(opcode, 15, 12);
5916  Rn = Bits32(opcode, 19, 16);
5917  Rm = Bits32(opcode, 3, 0);
5918  setflags = BitIsSet(opcode, 20);
5919  shift_n = DecodeImmShiftARM(opcode, shift_t);
5920 
5921  if (Rd == 15 && setflags)
5922  return EmulateSUBSPcLrEtc(opcode, encoding);
5923  break;
5924  default:
5925  return false;
5926  }
5927 
5928  // Read the first operand.
5929  int32_t val1 = ReadCoreReg(Rn, &success);
5930  if (!success)
5931  return false;
5932 
5933  // Read the second operand.
5934  int32_t val2 = ReadCoreReg(Rm, &success);
5935  if (!success)
5936  return false;
5937 
5938  uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
5939  if (!success)
5940  return false;
5941  AddWithCarryResult res = AddWithCarry(val1, shifted, APSR_C);
5942 
5944  context.type = EmulateInstruction::eContextImmediate;
5945  context.SetNoArgs();
5946 
5947  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
5948  res.carry_out, res.overflow))
5949  return false;
5950  }
5951  return true;
5952 }
5953 
5954 // This instruction adds an immediate value to the PC value to form a PC-
5955 // relative address, and writes the result to the destination register.
5956 bool EmulateInstructionARM::EmulateADR(const uint32_t opcode,
5957  const ARMEncoding encoding) {
5958 #if 0
5959  // ARM pseudo code...
5960  if ConditionPassed() then
5961  EncodingSpecificOperations();
5962  result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
5963  if d == 15 then // Can only occur for ARM encodings
5964  ALUWritePC(result);
5965  else
5966  R[d] = result;
5967 #endif
5968 
5969  bool success = false;
5970 
5971  if (ConditionPassed(opcode)) {
5972  uint32_t Rd;
5973  uint32_t imm32; // the immediate value to be added/subtracted to/from the PC
5974  bool add;
5975  switch (encoding) {
5976  case eEncodingT1:
5977  Rd = Bits32(opcode, 10, 8);
5978  imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32)
5979  add = true;
5980  break;
5981  case eEncodingT2:
5982  case eEncodingT3:
5983  Rd = Bits32(opcode, 11, 8);
5984  imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
5985  add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB
5986  if (BadReg(Rd))
5987  return false;
5988  break;
5989  case eEncodingA1:
5990  case eEncodingA2:
5991  Rd = Bits32(opcode, 15, 12);
5992  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5993  add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB
5994  break;
5995  default:
5996  return false;
5997  }
5998 
5999  // Read the PC value.
6000  uint32_t pc = ReadCoreReg(PC_REG, &success);
6001  if (!success)
6002  return false;
6003 
6004  uint32_t result = (add ? Align(pc, 4) + imm32 : Align(pc, 4) - imm32);
6005 
6007  context.type = EmulateInstruction::eContextImmediate;
6008  context.SetNoArgs();
6009 
6010  if (!WriteCoreReg(context, result, Rd))
6011  return false;
6012  }
6013  return true;
6014 }
6015 
6016 // This instruction performs a bitwise AND of a register value and an immediate
6017 // value, and writes the result to the destination register. It can optionally
6018 // update the condition flags based on the result.
6019 bool EmulateInstructionARM::EmulateANDImm(const uint32_t opcode,
6020  const ARMEncoding encoding) {
6021 #if 0
6022  // ARM pseudo code...
6023  if ConditionPassed() then
6024  EncodingSpecificOperations();
6025  result = R[n] AND imm32;
6026  if d == 15 then // Can only occur for ARM encoding
6027  ALUWritePC(result); // setflags is always FALSE here
6028  else
6029  R[d] = result;
6030  if setflags then
6031  APSR.N = result<31>;
6032  APSR.Z = IsZeroBit(result);
6033  APSR.C = carry;
6034  // APSR.V unchanged
6035 #endif
6036 
6037  bool success = false;
6038 
6039  if (ConditionPassed(opcode)) {
6040  uint32_t Rd, Rn;
6041  uint32_t
6042  imm32; // the immediate value to be ANDed to the value obtained from Rn
6043  bool setflags;
6044  uint32_t carry; // the carry bit after ARM/Thumb Expand operation
6045  switch (encoding) {
6046  case eEncodingT1:
6047  Rd = Bits32(opcode, 11, 8);
6048  Rn = Bits32(opcode, 19, 16);
6049  setflags = BitIsSet(opcode, 20);
6050  imm32 = ThumbExpandImm_C(
6051  opcode, APSR_C,
6052  carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
6053  // if Rd == '1111' && S == '1' then SEE TST (immediate);
6054  if (Rd == 15 && setflags)
6055  return EmulateTSTImm(opcode, eEncodingT1);
6056  if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
6057  return false;
6058  break;
6059  case eEncodingA1:
6060  Rd = Bits32(opcode, 15, 12);
6061  Rn = Bits32(opcode, 19, 16);
6062  setflags = BitIsSet(opcode, 20);
6063  imm32 =
6064  ARMExpandImm_C(opcode, APSR_C,
6065  carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
6066 
6067  if (Rd == 15 && setflags)
6068  return EmulateSUBSPcLrEtc(opcode, encoding);
6069  break;
6070  default:
6071  return false;
6072  }
6073 
6074  // Read the first operand.
6075  uint32_t val1 = ReadCoreReg(Rn, &success);
6076  if (!success)
6077  return false;
6078 
6079  uint32_t result = val1 & imm32;
6080 
6082  context.type = EmulateInstruction::eContextImmediate;
6083  context.SetNoArgs();
6084 
6085  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
6086  return false;
6087  }
6088  return true;
6089 }
6090 
6091 // This instruction performs a bitwise AND of a register value and an
6092 // optionally-shifted register value, and writes the result to the destination
6093 // register. It can optionally update the condition flags based on the result.
6094 bool EmulateInstructionARM::EmulateANDReg(const uint32_t opcode,
6095  const ARMEncoding encoding) {
6096 #if 0
6097  // ARM pseudo code...
6098  if ConditionPassed() then
6099  EncodingSpecificOperations();
6100  (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
6101  result = R[n] AND shifted;
6102  if d == 15 then // Can only occur for ARM encoding
6103  ALUWritePC(result); // setflags is always FALSE here
6104  else
6105  R[d] = re