28#include "llvm/ADT/STLExtras.h"
29#include "llvm/Support/MathExtras.h"
37#define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS)
38#define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)
40#define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
47 RegisterInfo reg_info;
48 ::memset(®_info, 0,
sizeof(RegisterInfo));
52 reg_info.byte_size = 16;
58 reg_info.byte_size = 8;
62 reg_info.byte_size = 4;
66 reg_info.byte_size = 12;
70 reg_info.byte_size = 4;
100 reg_info.name =
"r7";
104 reg_info.name =
"r8";
107 reg_info.name =
"r9";
110 reg_info.name =
"r10";
113 reg_info.name =
"r11";
116 reg_info.name =
"r12";
119 reg_info.name =
"sp";
120 reg_info.alt_name =
"r13";
124 reg_info.name =
"lr";
125 reg_info.alt_name =
"r14";
129 reg_info.name =
"pc";
130 reg_info.alt_name =
"r15";
134 reg_info.name =
"cpsr";
139 reg_info.name =
"s0";
142 reg_info.name =
"s1";
145 reg_info.name =
"s2";
148 reg_info.name =
"s3";
151 reg_info.name =
"s4";
154 reg_info.name =
"s5";
157 reg_info.name =
"s6";
160 reg_info.name =
"s7";
163 reg_info.name =
"s8";
166 reg_info.name =
"s9";
169 reg_info.name =
"s10";
172 reg_info.name =
"s11";
175 reg_info.name =
"s12";
178 reg_info.name =
"s13";
181 reg_info.name =
"s14";
184 reg_info.name =
"s15";
187 reg_info.name =
"s16";
190 reg_info.name =
"s17";
193 reg_info.name =
"s18";
196 reg_info.name =
"s19";
199 reg_info.name =
"s20";
202 reg_info.name =
"s21";
205 reg_info.name =
"s22";
208 reg_info.name =
"s23";
211 reg_info.name =
"s24";
214 reg_info.name =
"s25";
217 reg_info.name =
"s26";
220 reg_info.name =
"s27";
223 reg_info.name =
"s28";
226 reg_info.name =
"s29";
229 reg_info.name =
"s30";
232 reg_info.name =
"s31";
237 reg_info.name =
"f0";
240 reg_info.name =
"f1";
243 reg_info.name =
"f2";
246 reg_info.name =
"f3";
249 reg_info.name =
"f4";
252 reg_info.name =
"f5";
255 reg_info.name =
"f6";
258 reg_info.name =
"f7";
264 reg_info.name =
"wCGR0/ACC0";
267 reg_info.name =
"wCGR1/ACC1";
270 reg_info.name =
"wCGR2/ACC2";
273 reg_info.name =
"wCGR3/ACC3";
276 reg_info.name =
"wCGR4/ACC4";
279 reg_info.name =
"wCGR5/ACC5";
282 reg_info.name =
"wCGR6/ACC6";
285 reg_info.name =
"wCGR7/ACC7";
290 reg_info.name =
"wR0";
293 reg_info.name =
"wR1";
296 reg_info.name =
"wR2";
299 reg_info.name =
"wR3";
302 reg_info.name =
"wR4";
305 reg_info.name =
"wR5";
308 reg_info.name =
"wR6";
311 reg_info.name =
"wR7";
314 reg_info.name =
"wR8";
317 reg_info.name =
"wR9";
320 reg_info.name =
"wR10";
323 reg_info.name =
"wR11";
326 reg_info.name =
"wR12";
329 reg_info.name =
"wR13";
332 reg_info.name =
"wR14";
335 reg_info.name =
"wR15";
339 reg_info.name =
"spsr";
342 reg_info.name =
"spsr_fiq";
345 reg_info.name =
"spsr_irq";
348 reg_info.name =
"spsr_abt";
351 reg_info.name =
"spsr_und";
354 reg_info.name =
"spsr_svc";
358 reg_info.name =
"r8_usr";
361 reg_info.name =
"r9_usr";
364 reg_info.name =
"r10_usr";
367 reg_info.name =
"r11_usr";
370 reg_info.name =
"r12_usr";
373 reg_info.name =
"r13_usr";
376 reg_info.name =
"r14_usr";
379 reg_info.name =
"r8_fiq";
382 reg_info.name =
"r9_fiq";
385 reg_info.name =
"r10_fiq";
388 reg_info.name =
"r11_fiq";
391 reg_info.name =
"r12_fiq";
394 reg_info.name =
"r13_fiq";
397 reg_info.name =
"r14_fiq";
400 reg_info.name =
"r13_irq";
403 reg_info.name =
"r14_irq";
406 reg_info.name =
"r13_abt";
409 reg_info.name =
"r14_abt";
412 reg_info.name =
"r13_und";
415 reg_info.name =
"r14_und";
418 reg_info.name =
"r13_svc";
421 reg_info.name =
"r14_svc";
426 reg_info.name =
"wC0";
429 reg_info.name =
"wC1";
432 reg_info.name =
"wC2";
435 reg_info.name =
"wC3";
438 reg_info.name =
"wC4";
441 reg_info.name =
"wC5";
444 reg_info.name =
"wC6";
447 reg_info.name =
"wC7";
452 reg_info.name =
"d0";
455 reg_info.name =
"d1";
458 reg_info.name =
"d2";
461 reg_info.name =
"d3";
464 reg_info.name =
"d4";
467 reg_info.name =
"d5";
470 reg_info.name =
"d6";
473 reg_info.name =
"d7";
476 reg_info.name =
"d8";
479 reg_info.name =
"d9";
482 reg_info.name =
"d10";
485 reg_info.name =
"d11";
488 reg_info.name =
"d12";
491 reg_info.name =
"d13";
494 reg_info.name =
"d14";
497 reg_info.name =
"d15";
500 reg_info.name =
"d16";
503 reg_info.name =
"d17";
506 reg_info.name =
"d18";
509 reg_info.name =
"d19";
512 reg_info.name =
"d20";
515 reg_info.name =
"d21";
518 reg_info.name =
"d22";
521 reg_info.name =
"d23";
524 reg_info.name =
"d24";
527 reg_info.name =
"d25";
530 reg_info.name =
"d26";
533 reg_info.name =
"d27";
536 reg_info.name =
"d28";
539 reg_info.name =
"d29";
542 reg_info.name =
"d30";
545 reg_info.name =
"d31";
550 reg_info.name =
"q0";
553 reg_info.name =
"q1";
556 reg_info.name =
"q2";
559 reg_info.name =
"q3";
562 reg_info.name =
"q4";
565 reg_info.name =
"q5";
568 reg_info.name =
"q6";
571 reg_info.name =
"q7";
574 reg_info.name =
"q8";
577 reg_info.name =
"q9";
580 reg_info.name =
"q10";
583 reg_info.name =
"q11";
586 reg_info.name =
"q12";
589 reg_info.name =
"q13";
592 reg_info.name =
"q14";
595 reg_info.name =
"q15";
608 uint32_t TZ = llvm::countr_zero(ITMask);
622 unsigned short FirstCond =
Bits32(bits7_0, 7, 4);
623 if (FirstCond == 0xF) {
626 if (FirstCond == 0xE &&
ITCounter != 1) {
666#define PC_REGLIST_BIT 0x8000
668#define ARMv4 (1u << 0)
669#define ARMv4T (1u << 1)
670#define ARMv5T (1u << 2)
671#define ARMv5TE (1u << 3)
672#define ARMv5TEJ (1u << 4)
673#define ARMv6 (1u << 5)
674#define ARMv6K (1u << 6)
675#define ARMv6T2 (1u << 7)
676#define ARMv7 (1u << 8)
677#define ARMv7S (1u << 9)
678#define ARMv8 (1u << 10)
679#define ARMvAll (0xffffffffu)
681#define ARMV4T_ABOVE \
682 (ARMv4T | ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | \
685 (ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | \
687#define ARMV5TE_ABOVE \
688 (ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
689#define ARMV5J_ABOVE \
690 (ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
691#define ARMV6_ABOVE (ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
692#define ARMV6T2_ABOVE (ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
693#define ARMV7_ABOVE (ARMv7 | ARMv7S | ARMv8)
696#define VFPv1 (1u << 1)
697#define VFPv2 (1u << 2)
698#define VFPv3 (1u << 3)
699#define AdvancedSIMD (1u << 4)
701#define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
702#define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
703#define VFPv2v3 (VFPv2 | VFPv3)
719 return "Emulate instructions for the ARM architecture.";
727 if (arch.
GetTriple().getArch() == llvm::Triple::arm) {
728 std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
732 return emulate_insn_up.release();
733 }
else if (arch.
GetTriple().getArch() == llvm::Triple::thumb) {
734 std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
738 return emulate_insn_up.release();
746 if (arch.
GetTriple().getArch() == llvm::Triple::arm)
748 else if (arch.
GetTriple().getArch() == llvm::Triple::thumb)
764 return MemAWrite(context, address, random_data, addr_byte_size);
787std::optional<RegisterInfo>
825 bool is_apple =
false;
829 case llvm::Triple::Darwin:
830 case llvm::Triple::MacOSX:
831 case llvm::Triple::IOS:
832 case llvm::Triple::TvOS:
833 case llvm::Triple::WatchOS:
858 bool is_apple =
false;
862 case llvm::Triple::Darwin:
863 case llvm::Triple::MacOSX:
864 case llvm::Triple::IOS:
897 EncodingSpecificOperations();
898 NullCheckIfThumbEE(13);
899 address = SP - 4*
BitCount(registers);
903 if (registers<i> ==
'1')
905 if i == 13 && i != LowestSetBit(registers)
906 MemA[address,4] =
bits(32) UNKNOWN;
908 MemA[address,4] = R[i];
909 address = address + 4;
913 if (registers<15> ==
'1')
914 MemA[address,4] = PCStoreValue();
920 bool success =
false;
930 registers =
Bits32(opcode, 7, 0);
932 if (
Bit32(opcode, 8))
933 registers |= (1u << 14);
940 registers =
Bits32(opcode, 15, 0) & ~0xa000;
946 Rt =
Bits32(opcode, 15, 12);
950 registers = (1u << Rt);
953 registers =
Bits32(opcode, 15, 0);
959 Rt =
Bits32(opcode, 15, 12);
963 registers = (1u << Rt);
974 std::optional<RegisterInfo> sp_reg =
976 for (i = 0; i < 15; ++i) {
978 std::optional<RegisterInfo> reg_info =
984 if (!
MemAWrite(context, addr, reg_value, addr_byte_size))
986 addr += addr_byte_size;
991 std::optional<RegisterInfo> reg_info =
1020 EncodingSpecificOperations(); NullCheckIfThumbEE(13);
1023 if registers<i> ==
'1' then
1024 R[i] =
if UnalignedAllowed then MemU[address,4]
else MemA[address,4]; address = address + 4;
1025 if registers<15> ==
'1' then
1026 if UnalignedAllowed then
1030 if registers<13> ==
'0' then SP = SP + 4*
BitCount(registers);
1031 if registers<13> ==
'1' then SP =
bits(32) UNKNOWN;
1035 bool success =
false;
1046 registers =
Bits32(opcode, 7, 0);
1048 if (
Bit32(opcode, 8))
1049 registers |= (1u << 15);
1056 registers =
Bits32(opcode, 15, 0) & ~0x2000;
1067 Rt =
Bits32(opcode, 15, 12);
1074 registers = (1u << Rt);
1077 registers =
Bits32(opcode, 15, 0);
1087 Rt =
Bits32(opcode, 15, 12);
1091 registers = (1u << Rt);
1103 std::optional<RegisterInfo> sp_reg =
1106 for (i = 0; i < 15; ++i) {
1109 data =
MemARead(context, addr, 4, 0, &success);
1115 addr += addr_byte_size;
1121 data =
MemARead(context, addr, 4, 0, &success);
1148 EncodingSpecificOperations();
1149 (result, carry, overflow) =
AddWithCarry(SP, imm32,
'0');
1155 APSR.N = result<31>;
1156 APSR.Z = IsZeroBit(result);
1162 bool success =
false;
1173 imm32 =
Bits32(opcode, 7, 0) << 2;
1182 addr_t sp_offset = imm32;
1190 std::optional<RegisterInfo> sp_reg =
1209 EncodingSpecificOperations();
1216 APSR.N = result<31>;
1217 APSR.Z = IsZeroBit(result);
1223 bool success =
false;
1246 std::optional<RegisterInfo> sp_reg =
1271 EncodingSpecificOperations();
1278 APSR.N = result<31>;
1279 APSR.Z = IsZeroBit(result);
1285 bool success =
false;
1294 Rm =
Bits32(opcode, 6, 3);
1301 Rm =
Bits32(opcode, 5, 3);
1308 Rm =
Bits32(opcode, 3, 0);
1315 if (!setflags && (
Rd == 15 || Rm == 15 || (
Rd == 13 && Rm == 13)))
1320 Rm =
Bits32(opcode, 3, 0);
1325 if (
Rd == 15 && setflags)
1343 std::optional<RegisterInfo> dwarf_reg =
1362 EncodingSpecificOperations();
1369 APSR.N = result<31>;
1370 APSR.Z = IsZeroBit(result);
1388 imm32 =
Bits32(opcode, 7, 0);
1411 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
1427 if ((
Rd == 15) && setflags)
1438 imm32 = (imm4 << 12) | imm12;
1473 EncodingSpecificOperations();
1474 operand1 =
SInt(R[n]);
1475 operand2 =
SInt(R[m]);
1476 result = operand1 * operand2;
1477 R[d] = result<31:0>;
1479 APSR.N = result<31>;
1480 APSR.Z = IsZeroBit(result);
1482 APSR.C =
bit UNKNOWN;
1497 d =
Bits32(opcode, 2, 0);
1498 n =
Bits32(opcode, 5, 3);
1499 m =
Bits32(opcode, 2, 0);
1510 d =
Bits32(opcode, 11, 8);
1511 n =
Bits32(opcode, 19, 16);
1512 m =
Bits32(opcode, 3, 0);
1523 d =
Bits32(opcode, 19, 16);
1524 n =
Bits32(opcode, 3, 0);
1525 m =
Bits32(opcode, 11, 8);
1529 if ((d == 15) || (n == 15) || (m == 15))
1542 bool success =
false;
1559 uint64_t result = operand1 * operand2;
1562 std::optional<RegisterInfo> op1_reg =
1564 std::optional<RegisterInfo> op2_reg =
1572 (0x0000ffff & result)))
1604 EncodingSpecificOperations();
1605 result =
NOT(imm32);
1611 APSR.N = result<31>;
1612 APSR.Z = IsZeroBit(result);
1636 if (
Rd == 15 && setflags)
1664 EncodingSpecificOperations();
1665 (shifted, carry) =
Shift_C(R[m], shift_t, shift_n, APSR.C);
1666 result =
NOT(shifted);
1672 APSR.N = result<31>;
1673 APSR.Z = IsZeroBit(result);
1689 Rm =
Bits32(opcode, 5, 3);
1698 Rm =
Bits32(opcode, 3, 0);
1707 Rm =
Bits32(opcode, 3, 0);
1714 bool success =
false;
1745 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
1747 address =
if add then (base + imm32)
else (base - imm32);
1748 data = MemU[address,4];
1750 if address<1:0> ==
'00' then
LoadWritePC(data);
else UNPREDICTABLE;
1755 R[t] =
ROR(data, 8*
UInt(address<1:0>));
1757 R[t] =
bits(32) UNKNOWN;
1762 bool success =
false;
1770 std::optional<RegisterInfo> pc_reg =
1782 Rt =
Bits32(opcode, 10, 8);
1783 imm32 =
Bits32(opcode, 7, 0) << 2;
1787 Rt =
Bits32(opcode, 15, 12);
1788 imm32 =
Bits32(opcode, 11, 0) << 2;
1799 address = base + imm32;
1801 address = base - imm32;
1804 data =
MemURead(context, address, 4, 0, &success);
1809 if (
Bits32(address, 1, 0) == 0) {
1833 EncodingSpecificOperations();
1834 (result, carry, overflow) =
AddWithCarry(SP, imm32,
'0');
1840 APSR.N = result<31>;
1841 APSR.Z = IsZeroBit(result);
1847 bool success =
false;
1859 d =
Bits32(opcode, 10, 8);
1860 imm32 = (
Bits32(opcode, 7, 0) << 2);
1874 d =
Bits32(opcode, 11, 8);
1876 setflags =
Bit32(opcode, 20);
1879 if (d == 15 && setflags == 1)
1883 if (d == 15 && setflags == 0)
1890 d =
Bits32(opcode, 11, 8);
1895 imm32 = (i << 11) | (imm3 << 8) | imm8;
1914 std::optional<RegisterInfo> sp_reg =
1944 EncodingSpecificOperations();
1945 shifted =
Shift(R[m], shift_t, shift_n, APSR.C);
1946 (result, carry, overflow) =
AddWithCarry(SP, shifted,
'0');
1952 APSR.N = result<31>;
1953 APSR.Z = IsZeroBit(result);
1959 bool success =
false;
1968 Rm =
Bits32(opcode, 6, 3);
1977 addr_t addr = (int32_t)
sp + reg_value;
1981 std::optional<RegisterInfo> sp_reg =
1983 std::optional<RegisterInfo> other_reg =
2004 EncodingSpecificOperations();
2008 LR = PC<31:1> :
'1';
2009 if targetInstrSet == InstrSet_ARM then
2010 targetAddress =
Align(PC,4) + imm32;
2012 targetAddress = PC + imm32;
2018 bool success =
true;
2040 (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2041 imm32 = llvm::SignExtend32<25>(imm25);
2042 target =
pc + imm32;
2059 (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
2060 imm32 = llvm::SignExtend32<25>(imm25);
2061 target =
Align(
pc, 4) + imm32;
2070 imm32 = llvm::SignExtend32<26>(
Bits32(opcode, 23, 0) << 2);
2071 target =
Align(
pc, 4) + imm32;
2077 imm32 = llvm::SignExtend32<26>(
Bits32(opcode, 23, 0) << 2 |
2078 Bits32(opcode, 24, 24) << 1);
2079 target =
pc + imm32;
2108 EncodingSpecificOperations();
2111 next_instr_addr = PC - 4;
2112 LR = next_instr_addr;
2114 next_instr_addr = PC - 2;
2115 LR = next_instr_addr<31:1> :
'1';
2120 bool success =
false;
2133 Rm =
Bits32(opcode, 6, 3);
2142 Rm =
Bits32(opcode, 3, 0);
2153 std::optional<RegisterInfo> dwarf_reg =
2173 EncodingSpecificOperations();
2184 Rm =
Bits32(opcode, 6, 3);
2189 Rm =
Bits32(opcode, 3, 0);
2194 bool success =
false;
2199 std::optional<RegisterInfo> dwarf_reg =
2221 EncodingSpecificOperations();
2225 if JazelleAcceptsExecution() then
2226 SwitchToJazelleExecution();
2228 SUBARCHITECTURE_DEFINED handler call;
2238 Rm =
Bits32(opcode, 19, 16);
2245 Rm =
Bits32(opcode, 3, 0);
2252 bool success =
false;
2257 std::optional<RegisterInfo> dwarf_reg =
2274 EncodingSpecificOperations();
2281 APSR.N = result<31>;
2282 APSR.Z = IsZeroBit(result);
2289 bool success =
false;
2301 addr_t ip_offset = imm32;
2302 addr_t addr = ip - ip_offset;
2306 std::optional<RegisterInfo> dwarf_reg =
2324 EncodingSpecificOperations();
2331 APSR.N = result<31>;
2332 APSR.Z = IsZeroBit(result);
2339 bool success =
false;
2351 addr_t sp_offset = imm32;
2356 std::optional<RegisterInfo> dwarf_reg =
2377 EncodingSpecificOperations();
2384 APSR.N = result<31>;
2385 APSR.Z = IsZeroBit(result);
2391 bool success =
false;
2410 if (
Rd == 15 && setflags)
2412 if (
Rd == 15 && !setflags)
2429 if (
Rd == 15 && setflags)
2439 uint64_t imm64 = imm32;
2463 EncodingSpecificOperations();
2464 offset_addr =
if add then (R[n] + imm32)
else (R[n] - imm32);
2465 address =
if index then offset_addr
else R[n];
2466 MemU[address,4] =
if t == 15 then PCStoreValue()
else R[t];
2467 if wback then R[n] = offset_addr;
2471 bool success =
false;
2487 Rt =
Bits32(opcode, 15, 12);
2488 imm12 =
Bits32(opcode, 11, 0);
2489 Rn =
Bits32(opcode, 19, 16);
2498 if (wback && ((Rn == 15) || (Rn == Rt)))
2506 offset_addr =
sp + imm12;
2508 offset_addr =
sp - imm12;
2518 std::optional<RegisterInfo> sp_reg =
2520 std::optional<RegisterInfo> dwarf_reg =
2528 if (!
MemUWrite(context, addr, reg_value, addr_byte_size))
2534 if (!
MemUWrite(context, addr,
pc, addr_byte_size))
2557 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2558 address = SP - imm32;
2562 MemA[address,4] = S[d+r]; address = address+4;
2567 MemA[address,4] =
if BigEndian() then D[d+r]<63:32>
else D[d+r]<31:0>;
2568 MemA[address+4,4] =
if BigEndian() then D[d+r]<31:0>
else D[d+r]<63:32>;
2569 address = address+8;
2573 bool success =
false;
2586 single_regs =
false;
2587 d =
Bit32(opcode, 22) << 4 |
Bits32(opcode, 15, 12);
2588 imm32 =
Bits32(opcode, 7, 0) * addr_byte_size;
2590 regs =
Bits32(opcode, 7, 0) / 2;
2592 if (regs == 0 || regs > 16 || (d + regs) > 32)
2598 d =
Bits32(opcode, 15, 12) << 1 |
Bit32(opcode, 22);
2599 imm32 =
Bits32(opcode, 7, 0) * addr_byte_size;
2600 regs =
Bits32(opcode, 7, 0);
2602 if (regs == 0 || regs > 16 || (d + regs) > 32)
2609 uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2610 addr_t sp_offset = imm32;
2617 std::optional<RegisterInfo> sp_reg =
2619 for (i = 0; i < regs; ++i) {
2620 std::optional<RegisterInfo> dwarf_reg =
2627 if (!
MemAWrite(context, addr, reg_value, reg_byte_size))
2629 addr += reg_byte_size;
2650 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2655 S[d+r] = MemA[address,4]; address = address+4;
2658 word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
2661 D[d+r] =
if BigEndian() then word1:word2
else word2:word1;
2665 bool success =
false;
2678 single_regs =
false;
2679 d =
Bit32(opcode, 22) << 4 |
Bits32(opcode, 15, 12);
2680 imm32 =
Bits32(opcode, 7, 0) * addr_byte_size;
2682 regs =
Bits32(opcode, 7, 0) / 2;
2684 if (regs == 0 || regs > 16 || (d + regs) > 32)
2690 d =
Bits32(opcode, 15, 12) << 1 |
Bit32(opcode, 22);
2691 imm32 =
Bits32(opcode, 7, 0) * addr_byte_size;
2692 regs =
Bits32(opcode, 7, 0);
2694 if (regs == 0 || regs > 16 || (d + regs) > 32)
2701 uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2702 addr_t sp_offset = imm32;
2710 for (i = 0; i < regs; ++i) {
2711 std::optional<RegisterInfo> dwarf_reg =
2714 data =
MemARead(context, addr, reg_byte_size, 0, &success);
2719 addr += reg_byte_size;
2739 EncodingSpecificOperations();
2744 bool success =
false;
2756 imm32 =
Bits32(opcode, 7, 0);
2761 imm32 =
Bits32(opcode, 23, 0);
2783 EncodingSpecificOperations();
2784 ITSTATE.IT<7:0> = firstcond:mask;
2804 EncodingSpecificOperations();
2809 bool success =
false;
2822 imm32 = llvm::SignExtend32<9>(
Bits32(opcode, 7, 0) << 1);
2823 target =
pc + imm32;
2827 imm32 = llvm::SignExtend32<12>(
Bits32(opcode, 10, 0) << 1);
2828 target =
pc + imm32;
2834 if (
Bits32(opcode, 25, 23) == 7)
2844 (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
2845 imm32 = llvm::SignExtend32<21>(imm21);
2846 target =
pc + imm32;
2859 (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2860 imm32 = llvm::SignExtend32<25>(imm25);
2861 target =
pc + imm32;
2866 imm32 = llvm::SignExtend32<26>(
Bits32(opcode, 23, 0) << 2);
2867 target =
pc + imm32;
2886 EncodingSpecificOperations();
2887 if nonzero ^
IsZero(R[n]) then
2891 bool success =
false;
2909 imm32 =
Bit32(opcode, 9) << 6 |
Bits32(opcode, 7, 3) << 1;
2911 target =
pc + imm32;
2940 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
2942 halfwords =
UInt(MemU[R[n]+
LSL(R[m],1), 2]);
2944 halfwords =
UInt(MemU[R[n]+R[m], 1]);
2948 bool success =
false;
2958 Rn =
Bits32(opcode, 19, 16);
2959 Rm =
Bits32(opcode, 3, 0);
2961 if (Rn == 13 ||
BadReg(Rm))
2982 addr_t addr = base + (is_tbh ? index * 2 : index);
2987 uint32_t offset =
MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
2998 context.SetISAAndImmediateSigned(
eModeThumb, 4 + offset);
3014 EncodingSpecificOperations();
3015 (result, carry, overflow) =
AddWithCarry(R[n], imm32,
'0');
3018 APSR.N = result<31>;
3019 APSR.Z = IsZeroBit(result);
3024 bool success =
false;
3038 d =
Bits32(opcode, 2, 0);
3039 n =
Bits32(opcode, 5, 3);
3041 imm32 =
Bits32(opcode, 8, 6);
3048 d =
Bits32(opcode, 10, 8);
3049 n =
Bits32(opcode, 10, 8);
3051 imm32 =
Bits32(opcode, 7, 0);
3059 d =
Bits32(opcode, 11, 8);
3060 n =
Bits32(opcode, 19, 16);
3069 if (
BadReg(d) || (n == 15))
3078 d =
Bits32(opcode, 11, 8);
3079 n =
Bits32(opcode, 19, 16);
3084 imm32 = (i << 11) | (imm3 << 8) | imm8;
3109 std::optional<RegisterInfo> reg_n =
3136 EncodingSpecificOperations();
3137 (result, carry, overflow) =
AddWithCarry(R[n], imm32,
'0');
3143 APSR.N = result<31>;
3144 APSR.Z = IsZeroBit(result);
3149 bool success =
false;
3159 Rn =
Bits32(opcode, 19, 16);
3182 std::optional<RegisterInfo> dwarf_reg =
3201 EncodingSpecificOperations();
3202 shifted =
Shift(R[m], shift_t, shift_n, APSR.C);
3203 (result, carry, overflow) =
AddWithCarry(R[n], shifted,
'0');
3209 APSR.N = result<31>;
3210 APSR.Z = IsZeroBit(result);
3215 bool success =
false;
3225 Rn =
Bits32(opcode, 5, 3);
3226 Rm =
Bits32(opcode, 8, 6);
3233 Rm =
Bits32(opcode, 6, 3);
3237 if (Rn == 15 && Rm == 15)
3244 Rn =
Bits32(opcode, 19, 16);
3245 Rm =
Bits32(opcode, 3, 0);
3270 std::optional<RegisterInfo> op1_reg =
3272 std::optional<RegisterInfo> op2_reg =
3290 EncodingSpecificOperations();
3291 (result, carry, overflow) =
AddWithCarry(R[n], imm32,
'0');
3292 APSR.N = result<31>;
3293 APSR.Z = IsZeroBit(result);
3298 bool success =
false;
3304 Rn =
Bits32(opcode, 19, 16);
3310 Rn =
Bits32(opcode, 19, 16);
3337 EncodingSpecificOperations();
3338 shifted =
Shift(R[m], shift_t, shift_n, APSR.C);
3339 (result, carry, overflow) =
AddWithCarry(R[n], shifted,
'0');
3340 APSR.N = result<31>;
3341 APSR.Z = IsZeroBit(result);
3346 bool success =
false;
3354 Rn =
Bits32(opcode, 2, 0);
3355 Rm =
Bits32(opcode, 5, 3);
3360 Rn =
Bits32(opcode, 19, 16);
3361 Rm =
Bits32(opcode, 3, 0);
3364 if (Rn == 15 ||
BadReg(Rm))
3368 Rn =
Bits32(opcode, 19, 16);
3369 Rm =
Bits32(opcode, 3, 0);
3403 EncodingSpecificOperations();
3405 APSR.N = result<31>;
3406 APSR.Z = IsZeroBit(result);
3411 bool success =
false;
3417 Rn =
Bits32(opcode, 10, 8);
3418 imm32 =
Bits32(opcode, 7, 0);
3421 Rn =
Bits32(opcode, 19, 16);
3427 Rn =
Bits32(opcode, 19, 16);
3454 EncodingSpecificOperations();
3455 shifted =
Shift(R[m], shift_t, shift_n, APSR.C);
3457 APSR.N = result<31>;
3458 APSR.Z = IsZeroBit(result);
3463 bool success =
false;
3471 Rn =
Bits32(opcode, 2, 0);
3472 Rm =
Bits32(opcode, 5, 3);
3477 Rn =
Bit32(opcode, 7) << 3 |
Bits32(opcode, 2, 0);
3478 Rm =
Bits32(opcode, 6, 3);
3481 if (Rn < 8 && Rm < 8)
3483 if (Rn == 15 || Rm == 15)
3487 Rn =
Bits32(opcode, 19, 16);
3488 Rm =
Bits32(opcode, 3, 0);
3490 if (Rn == 15 ||
BadReg(Rm))
3494 Rn =
Bits32(opcode, 19, 16);
3495 Rm =
Bits32(opcode, 3, 0);
3531 EncodingSpecificOperations();
3538 APSR.N = result<31>;
3539 APSR.Z = IsZeroBit(result);
3557 EncodingSpecificOperations();
3558 shift_n =
UInt(R[m]<7:0>);
3562 APSR.N = result<31>;
3563 APSR.Z = IsZeroBit(result);
3579 EncodingSpecificOperations();
3586 APSR.N = result<31>;
3587 APSR.Z = IsZeroBit(result);
3604 EncodingSpecificOperations();
3605 shift_n =
UInt(R[m]<7:0>);
3609 APSR.N = result<31>;
3610 APSR.Z = IsZeroBit(result);
3627 EncodingSpecificOperations();
3634 APSR.N = result<31>;
3635 APSR.Z = IsZeroBit(result);
3652 EncodingSpecificOperations();
3653 shift_n =
UInt(R[m]<7:0>);
3657 APSR.N = result<31>;
3658 APSR.Z = IsZeroBit(result);
3675 EncodingSpecificOperations();
3682 APSR.N = result<31>;
3683 APSR.Z = IsZeroBit(result);
3701 EncodingSpecificOperations();
3702 shift_n =
UInt(R[m]<7:0>);
3706 APSR.N = result<31>;
3707 APSR.Z = IsZeroBit(result);
3725 EncodingSpecificOperations();
3732 APSR.N = result<31>;
3733 APSR.Z = IsZeroBit(result);
3750 bool success =
false;
3769 switch (use_encoding) {
3772 Rm =
Bits32(opcode, 5, 3);
3774 imm5 =
Bits32(opcode, 10, 6);
3783 Rm =
Bits32(opcode, 3, 0);
3785 imm5 =
Bits32(opcode, 14, 12) << 2 |
Bits32(opcode, 7, 6);
3791 Rm =
Bits32(opcode, 3, 0);
3793 imm5 =
Bits32(opcode, 11, 7);
3835 bool success =
false;
3848 Rm =
Bits32(opcode, 5, 3);
3853 Rn =
Bits32(opcode, 19, 16);
3854 Rm =
Bits32(opcode, 3, 0);
3861 Rn =
Bits32(opcode, 3, 0);
3862 Rm =
Bits32(opcode, 11, 8);
3864 if (
Rd == 15 || Rn == 15 || Rm == 15)
3906 EncodingSpecificOperations(); NullCheckIfThumbEE (n);
3910 if registers<i> ==
'1' then
3911 R[i] = MemA[address, 4]; address = address + 4;
3912 if registers<15> ==
'1' then
3915 if wback && registers<n> ==
'0' then R[n] = R[n] + 4 *
BitCount (registers);
3916 if wback && registers<n> ==
'1' then R[n] =
bits(32) UNKNOWN;
3920 bool success =
false;
3930 n =
Bits32(opcode, 10, 8);
3931 registers =
Bits32(opcode, 7, 0);
3932 registers = registers & 0x00ff;
3941 n =
Bits32(opcode, 19, 16);
3942 registers =
Bits32(opcode, 15, 0);
3943 registers = registers & 0xdfff;
3948 if ((n == 15) || (
BitCount(registers) < 2) ||
3958 if (wback &&
BitIsSet(registers, n))
3963 n =
Bits32(opcode, 19, 16);
3964 registers =
Bits32(opcode, 15, 0);
3966 if ((n == 15) || (
BitCount(registers) < 1))
3974 const addr_t base_address =
3981 std::optional<RegisterInfo> dwarf_reg =
3985 for (
int i = 0; i < 14; ++i) {
3989 if (wback && (n == 13))
4005 offset += addr_byte_size;
4014 MemARead(context, base_address + offset, addr_byte_size, 0, &success);
4024 int32_t offset = addr_byte_size *
BitCount(registers);
4029 base_address + offset))
4032 if (wback &&
BitIsSet(registers, n))
4049 EncodingSpecificOperations();
4050 address = R[n] - 4*
BitCount(registers) + 4;
4053 if registers<i> ==
'1' then
4054 R[i] = MemA[address,4]; address = address + 4;
4056 if registers<15> ==
'1' then
4059 if wback && registers<n> ==
'0' then R[n] = R[n] - 4*
BitCount(registers);
4060 if wback && registers<n> ==
'1' then R[n] =
bits(32) UNKNOWN;
4063 bool success =
false;
4075 n =
Bits32(opcode, 19, 16);
4076 registers =
Bits32(opcode, 15, 0);
4080 if ((n == 15) || (
BitCount(registers) < 1))
4097 Rn - (addr_byte_size *
BitCount(registers)) + addr_byte_size;
4101 std::optional<RegisterInfo> dwarf_reg =
4103 context.SetRegisterPlusOffset(*dwarf_reg, offset);
4106 for (
int i = 0; i < 14; ++i) {
4110 context.SetRegisterPlusOffset(*dwarf_reg, Rn - (address + offset));
4112 MemARead(context, address + offset, addr_byte_size, 0, &success);
4118 offset += addr_byte_size;
4125 context.SetRegisterPlusOffset(*dwarf_reg, offset);
4127 MemARead(context, address + offset, addr_byte_size, 0, &success);
4138 offset = (addr_byte_size *
BitCount(registers)) * -1;
4140 context.SetImmediateSigned(offset);
4141 addr_t addr = Rn + offset;
4148 if (wback &&
BitIsSet(registers, n))
4164 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4165 address = R[n] - 4*
BitCount(registers);
4168 if registers<i> ==
'1' then
4169 R[i] = MemA[address,4]; address = address + 4;
4170 if registers<15> ==
'1' then
4173 if wback && registers<n> ==
'0' then R[n] = R[n] - 4*
BitCount(registers);
4174 if wback && registers<n> ==
'1' then R[n] =
bits(32) UNKNOWN;
4177 bool success =
false;
4187 n =
Bits32(opcode, 19, 16);
4188 registers =
Bits32(opcode, 15, 0);
4189 registers = registers & 0xdfff;
4194 if ((n == 15) || (
BitCount(registers) < 2) ||
4204 if (wback &&
BitIsSet(registers, n))
4211 n =
Bits32(opcode, 19, 16);
4212 registers =
Bits32(opcode, 15, 0);
4216 if ((n == 15) || (
BitCount(registers) < 1))
4237 std::optional<RegisterInfo> dwarf_reg =
4239 context.SetRegisterPlusOffset(*dwarf_reg, Rn - address);
4241 for (
int i = 0; i < 14; ++i) {
4244 context.SetRegisterPlusOffset(*dwarf_reg, Rn - (address + offset));
4246 MemARead(context, address + offset, addr_byte_size, 0, &success);
4254 offset += addr_byte_size;
4261 context.SetRegisterPlusOffset(*dwarf_reg, offset);
4263 MemARead(context, address + offset, addr_byte_size, 0, &success);
4274 offset = (addr_byte_size *
BitCount(registers)) * -1;
4276 context.SetImmediateSigned(offset);
4277 addr_t addr = Rn + offset;
4285 if (wback &&
BitIsSet(registers, n))
4300 EncodingSpecificOperations();
4304 if registers<i> ==
'1' then
4305 R[i] = MemA[address,4]; address = address + 4;
4306 if registers<15> ==
'1' then
4309 if wback && registers<n> ==
'0' then R[n] = R[n] + 4*
BitCount(registers);
4310 if wback && registers<n> ==
'1' then R[n] =
bits(32) UNKNOWN;
4313 bool success =
false;
4323 n =
Bits32(opcode, 19, 16);
4324 registers =
Bits32(opcode, 15, 0);
4328 if ((n == 15) || (
BitCount(registers) < 1))
4344 addr_t address = Rn + addr_byte_size;
4348 std::optional<RegisterInfo> dwarf_reg =
4352 for (
int i = 0; i < 14; ++i) {
4358 MemARead(context, address + offset, addr_byte_size, 0, &success);
4366 offset += addr_byte_size;
4375 MemARead(context, address + offset, addr_byte_size, 0, &success);
4386 offset = addr_byte_size *
BitCount(registers);
4389 addr_t addr = Rn + offset;
4397 if (wback &&
BitIsSet(registers, n))
4412 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
4413 offset_addr =
if add then (R[n] + imm32)
else (R[n] - imm32);
4414 address =
if index then offset_addr
else R[n];
4415 data = MemU[address,4];
4416 if wback then R[n] = offset_addr;
4418 if address<1:0> ==
'00' then
LoadWritePC(data);
else UNPREDICTABLE;
4421 else R[t] =
bits(32) UNKNOWN;
4425 bool success =
false;
4434 bool add, index, wback;
4437 Rt =
Bits32(opcode, 2, 0);
4438 Rn =
Bits32(opcode, 5, 3);
4439 imm32 =
Bits32(opcode, 10, 6) << 2;
4449 Rt =
Bits32(opcode, 10, 8);
4451 imm32 =
Bits32(opcode, 7, 0) << 2;
4463 Rt =
Bits32(opcode, 15, 12);
4464 Rn =
Bits32(opcode, 19, 16);
4465 imm32 =
Bits32(opcode, 11, 0);
4488 Rt =
Bits32(opcode, 15, 12);
4489 Rn =
Bits32(opcode, 19, 16);
4490 imm32 =
Bits32(opcode, 7, 0);
4499 if ((wback && (Rn == Rt)) ||
4512 offset_addr = base + imm32;
4514 offset_addr = base - imm32;
4516 address = (index ? offset_addr : base);
4518 std::optional<RegisterInfo> base_reg =
4544 data =
MemURead(context, address, 4, 0, &success);
4549 if (
Bits32(address, 1, 0) == 0) {
4573 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4577 if registers<i> ==
'1' then
4578 if i == n && wback && i != LowestSetBit(registers) then
4579 MemA[address,4] =
bits(32) UNKNOWN;
4581 MemA[address,4] = R[i];
4582 address = address + 4;
4584 if registers<15> ==
'1' then
4585 MemA[address,4] = PCStoreValue();
4586 if wback then R[n] = R[n] + 4*
BitCount(registers);
4589 bool success =
false;
4601 n =
Bits32(opcode, 10, 8);
4602 registers =
Bits32(opcode, 7, 0);
4603 registers = registers & 0x00ff;
4614 n =
Bits32(opcode, 19, 16);
4615 registers =
Bits32(opcode, 15, 0);
4616 registers = registers & 0x5fff;
4620 if ((n == 15) || (
BitCount(registers) < 2))
4624 if (wback &&
BitIsSet(registers, n))
4631 n =
Bits32(opcode, 19, 16);
4632 registers =
Bits32(opcode, 15, 0);
4636 if ((n == 15) || (
BitCount(registers) < 1))
4654 std::optional<RegisterInfo> base_reg =
4659 for (
uint32_t i = 0; i < 14; ++i) {
4662 if (i < lowest_set_bit)
4665 if ((i == n) && wback && (i != lowest_set_bit))
4676 std::optional<RegisterInfo> data_reg =
4679 if (!
MemAWrite(context, address + offset, data, addr_byte_size))
4684 offset += addr_byte_size;
4691 std::optional<RegisterInfo> pc_reg =
4698 if (!
MemAWrite(context, address + offset,
pc, addr_byte_size))
4704 offset = addr_byte_size *
BitCount(registers);
4707 addr_t data = address + offset;
4725 EncodingSpecificOperations();
4726 address = R[n] - 4*
BitCount(registers) + 4;
4729 if registers<i> ==
'1' then
4730 if i == n && wback && i != LowestSetBit(registers) then
4731 MemA[address,4] =
bits(32) UNKNOWN;
4733 MemA[address,4] = R[i];
4734 address = address + 4;
4736 if registers<15> ==
'1' then
4737 MemA[address,4] = PCStoreValue();
4739 if wback then R[n] = R[n] - 4*
BitCount(registers);
4742 bool success =
false;
4754 n =
Bits32(opcode, 19, 16);
4755 registers =
Bits32(opcode, 15, 0);
4759 if ((n == 15) || (
BitCount(registers) < 1))
4772 addr_t address = Rn - (addr_byte_size *
BitCount(registers)) + 4;
4776 std::optional<RegisterInfo> base_reg =
4781 for (
uint32_t i = 0; i < 14; ++i) {
4784 if (i < lowest_bit_set)
4787 if ((i == n) && wback && (i != lowest_bit_set))
4797 std::optional<RegisterInfo> data_reg =
4799 context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
4800 Rn - (address + offset));
4801 if (!
MemAWrite(context, address + offset, data, addr_byte_size))
4806 offset += addr_byte_size;
4813 std::optional<RegisterInfo> pc_reg =
4815 context.SetRegisterPlusOffset(*pc_reg, 8);
4820 if (!
MemAWrite(context, address + offset,
pc, addr_byte_size))
4826 offset = (addr_byte_size *
BitCount(registers)) * -1;
4828 context.SetImmediateSigned(offset);
4829 addr_t data = Rn + offset;
4847 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4848 address = R[n] - 4*
BitCount(registers);
4851 if registers<i> ==
'1' then
4852 if i == n && wback && i != LowestSetBit(registers) then
4853 MemA[address,4] =
bits(32) UNKNOWN;
4855 MemA[address,4] = R[i];
4856 address = address + 4;
4858 if registers<15> ==
'1' then
4859 MemA[address,4] = PCStoreValue();
4861 if wback then R[n] = R[n] - 4*
BitCount(registers);
4864 bool success =
false;
4880 n =
Bits32(opcode, 19, 16);
4881 registers =
Bits32(opcode, 15, 0);
4882 registers = registers & 0x5fff;
4885 if ((n == 15) ||
BitCount(registers) < 2)
4888 if (wback &&
BitIsSet(registers, n))
4900 n =
Bits32(opcode, 19, 16);
4901 registers =
Bits32(opcode, 15, 0);
4904 if ((n == 15) ||
BitCount(registers) < 1)
4924 std::optional<RegisterInfo> base_reg =
4929 for (
uint32_t i = 0; i < 14; ++i) {
4932 if (i < lowest_set_bit)
4935 if ((i == n) && wback && (i != lowest_set_bit))
4946 std::optional<RegisterInfo> data_reg =
4948 context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
4949 Rn - (address + offset));
4950 if (!
MemAWrite(context, address + offset, data, addr_byte_size))
4955 offset += addr_byte_size;
4962 std::optional<RegisterInfo> pc_reg =
4964 context.SetRegisterPlusOffset(*pc_reg, 8);
4969 if (!
MemAWrite(context, address + offset,
pc, addr_byte_size))
4975 offset = (addr_byte_size *
BitCount(registers)) * -1;
4977 context.SetImmediateSigned(offset);
4978 addr_t data = Rn + offset;
4996 EncodingSpecificOperations();
5000 if registers<i> ==
'1' then
5001 if i == n && wback && i != LowestSetBit(registers) then
5002 MemA[address,4] =
bits(32) UNKNOWN;
5004 MemA[address,4] = R[i];
5005 address = address + 4;
5007 if registers<15> ==
'1' then
5008 MemA[address,4] = PCStoreValue();
5010 if wback then R[n] = R[n] + 4*
BitCount(registers);
5013 bool success =
false;
5025 n =
Bits32(opcode, 19, 16);
5026 registers =
Bits32(opcode, 15, 0);
5030 if ((n == 15) && (
BitCount(registers) < 1))
5043 addr_t address = Rn + addr_byte_size;
5047 std::optional<RegisterInfo> base_reg =
5052 for (
uint32_t i = 0; i < 14; ++i) {
5055 if (i < lowest_set_bit)
5058 if ((i == n) && wback && (i != lowest_set_bit))
5069 std::optional<RegisterInfo> data_reg =
5072 offset + addr_byte_size);
5073 if (!
MemAWrite(context, address + offset, data, addr_byte_size))
5078 offset += addr_byte_size;
5085 std::optional<RegisterInfo> pc_reg =
5092 if (!
MemAWrite(context, address + offset,
pc, addr_byte_size))
5098 offset = addr_byte_size *
BitCount(registers);
5101 addr_t data = Rn + offset;
5118 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5119 offset_addr =
if add then (R[n] + imm32)
else (R[n] - imm32);
5120 address =
if index then offset_addr
else R[n];
5122 MemU[address,4] = R[t];
5124 MemU[address,4] =
bits(32) UNKNOWN;
5125 if wback then R[n] = offset_addr;
5128 bool success =
false;
5143 t =
Bits32(opcode, 2, 0);
5144 n =
Bits32(opcode, 5, 3);
5145 imm32 =
Bits32(opcode, 10, 6) << 2;