27#include "llvm/ADT/STLExtras.h"
28#include "llvm/Support/MathExtras.h"
36#define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS)
37#define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)
39#define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
103 reg_info.
name =
"r8";
106 reg_info.
name =
"r9";
109 reg_info.
name =
"r10";
112 reg_info.
name =
"r11";
115 reg_info.
name =
"r12";
118 reg_info.
name =
"sp";
123 reg_info.
name =
"lr";
128 reg_info.
name =
"pc";
133 reg_info.
name =
"cpsr";
138 reg_info.
name =
"s0";
141 reg_info.
name =
"s1";
144 reg_info.
name =
"s2";
147 reg_info.
name =
"s3";
150 reg_info.
name =
"s4";
153 reg_info.
name =
"s5";
156 reg_info.
name =
"s6";
159 reg_info.
name =
"s7";
162 reg_info.
name =
"s8";
165 reg_info.
name =
"s9";
168 reg_info.
name =
"s10";
171 reg_info.
name =
"s11";
174 reg_info.
name =
"s12";
177 reg_info.
name =
"s13";
180 reg_info.
name =
"s14";
183 reg_info.
name =
"s15";
186 reg_info.
name =
"s16";
189 reg_info.
name =
"s17";
192 reg_info.
name =
"s18";
195 reg_info.
name =
"s19";
198 reg_info.
name =
"s20";
201 reg_info.
name =
"s21";
204 reg_info.
name =
"s22";
207 reg_info.
name =
"s23";
210 reg_info.
name =
"s24";
213 reg_info.
name =
"s25";
216 reg_info.
name =
"s26";
219 reg_info.
name =
"s27";
222 reg_info.
name =
"s28";
225 reg_info.
name =
"s29";
228 reg_info.
name =
"s30";
231 reg_info.
name =
"s31";
236 reg_info.
name =
"f0";
239 reg_info.
name =
"f1";
242 reg_info.
name =
"f2";
245 reg_info.
name =
"f3";
248 reg_info.
name =
"f4";
251 reg_info.
name =
"f5";
254 reg_info.
name =
"f6";
257 reg_info.
name =
"f7";
263 reg_info.
name =
"wCGR0/ACC0";
266 reg_info.
name =
"wCGR1/ACC1";
269 reg_info.
name =
"wCGR2/ACC2";
272 reg_info.
name =
"wCGR3/ACC3";
275 reg_info.
name =
"wCGR4/ACC4";
278 reg_info.
name =
"wCGR5/ACC5";
281 reg_info.
name =
"wCGR6/ACC6";
284 reg_info.
name =
"wCGR7/ACC7";
289 reg_info.
name =
"wR0";
292 reg_info.
name =
"wR1";
295 reg_info.
name =
"wR2";
298 reg_info.
name =
"wR3";
301 reg_info.
name =
"wR4";
304 reg_info.
name =
"wR5";
307 reg_info.
name =
"wR6";
310 reg_info.
name =
"wR7";
313 reg_info.
name =
"wR8";
316 reg_info.
name =
"wR9";
319 reg_info.
name =
"wR10";
322 reg_info.
name =
"wR11";
325 reg_info.
name =
"wR12";
328 reg_info.
name =
"wR13";
331 reg_info.
name =
"wR14";
334 reg_info.
name =
"wR15";
338 reg_info.
name =
"spsr";
341 reg_info.
name =
"spsr_fiq";
344 reg_info.
name =
"spsr_irq";
347 reg_info.
name =
"spsr_abt";
350 reg_info.
name =
"spsr_und";
353 reg_info.
name =
"spsr_svc";
357 reg_info.
name =
"r8_usr";
360 reg_info.
name =
"r9_usr";
363 reg_info.
name =
"r10_usr";
366 reg_info.
name =
"r11_usr";
369 reg_info.
name =
"r12_usr";
372 reg_info.
name =
"r13_usr";
375 reg_info.
name =
"r14_usr";
378 reg_info.
name =
"r8_fiq";
381 reg_info.
name =
"r9_fiq";
384 reg_info.
name =
"r10_fiq";
387 reg_info.
name =
"r11_fiq";
390 reg_info.
name =
"r12_fiq";
393 reg_info.
name =
"r13_fiq";
396 reg_info.
name =
"r14_fiq";
399 reg_info.
name =
"r13_irq";
402 reg_info.
name =
"r14_irq";
405 reg_info.
name =
"r13_abt";
408 reg_info.
name =
"r14_abt";
411 reg_info.
name =
"r13_und";
414 reg_info.
name =
"r14_und";
417 reg_info.
name =
"r13_svc";
420 reg_info.
name =
"r14_svc";
425 reg_info.
name =
"wC0";
428 reg_info.
name =
"wC1";
431 reg_info.
name =
"wC2";
434 reg_info.
name =
"wC3";
437 reg_info.
name =
"wC4";
440 reg_info.
name =
"wC5";
443 reg_info.
name =
"wC6";
446 reg_info.
name =
"wC7";
451 reg_info.
name =
"d0";
454 reg_info.
name =
"d1";
457 reg_info.
name =
"d2";
460 reg_info.
name =
"d3";
463 reg_info.
name =
"d4";
466 reg_info.
name =
"d5";
469 reg_info.
name =
"d6";
472 reg_info.
name =
"d7";
475 reg_info.
name =
"d8";
478 reg_info.
name =
"d9";
481 reg_info.
name =
"d10";
484 reg_info.
name =
"d11";
487 reg_info.
name =
"d12";
490 reg_info.
name =
"d13";
493 reg_info.
name =
"d14";
496 reg_info.
name =
"d15";
499 reg_info.
name =
"d16";
502 reg_info.
name =
"d17";
505 reg_info.
name =
"d18";
508 reg_info.
name =
"d19";
511 reg_info.
name =
"d20";
514 reg_info.
name =
"d21";
517 reg_info.
name =
"d22";
520 reg_info.
name =
"d23";
523 reg_info.
name =
"d24";
526 reg_info.
name =
"d25";
529 reg_info.
name =
"d26";
532 reg_info.
name =
"d27";
535 reg_info.
name =
"d28";
538 reg_info.
name =
"d29";
541 reg_info.
name =
"d30";
544 reg_info.
name =
"d31";
549 reg_info.
name =
"q0";
552 reg_info.
name =
"q1";
555 reg_info.
name =
"q2";
558 reg_info.
name =
"q3";
561 reg_info.
name =
"q4";
564 reg_info.
name =
"q5";
567 reg_info.
name =
"q6";
570 reg_info.
name =
"q7";
573 reg_info.
name =
"q8";
576 reg_info.
name =
"q9";
579 reg_info.
name =
"q10";
582 reg_info.
name =
"q11";
585 reg_info.
name =
"q12";
588 reg_info.
name =
"q13";
591 reg_info.
name =
"q14";
594 reg_info.
name =
"q15";
607 uint32_t TZ = llvm::countr_zero(ITMask);
621 unsigned short FirstCond =
Bits32(bits7_0, 7, 4);
622 if (FirstCond == 0xF) {
625 if (FirstCond == 0xE &&
ITCounter != 1) {
665#define PC_REGLIST_BIT 0x8000
667#define ARMv4 (1u << 0)
668#define ARMv4T (1u << 1)
669#define ARMv5T (1u << 2)
670#define ARMv5TE (1u << 3)
671#define ARMv5TEJ (1u << 4)
672#define ARMv6 (1u << 5)
673#define ARMv6K (1u << 6)
674#define ARMv6T2 (1u << 7)
675#define ARMv7 (1u << 8)
676#define ARMv7S (1u << 9)
677#define ARMv8 (1u << 10)
678#define ARMvAll (0xffffffffu)
680#define ARMV4T_ABOVE \
681 (ARMv4T | ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | \
684 (ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | \
686#define ARMV5TE_ABOVE \
687 (ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
688#define ARMV5J_ABOVE \
689 (ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
690#define ARMV6_ABOVE (ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
691#define ARMV6T2_ABOVE (ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
692#define ARMV7_ABOVE (ARMv7 | ARMv7S | ARMv8)
695#define VFPv1 (1u << 1)
696#define VFPv2 (1u << 2)
697#define VFPv3 (1u << 3)
698#define AdvancedSIMD (1u << 4)
700#define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
701#define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
702#define VFPv2v3 (VFPv2 | VFPv3)
718 return "Emulate instructions for the ARM architecture.";
726 if (arch.
GetTriple().getArch() == llvm::Triple::arm) {
727 std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
731 return emulate_insn_up.release();
732 }
else if (arch.
GetTriple().getArch() == llvm::Triple::thumb) {
733 std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
737 return emulate_insn_up.release();
745 if (arch.
GetTriple().getArch() == llvm::Triple::arm)
747 else if (arch.
GetTriple().getArch() == llvm::Triple::thumb)
760 uint32_t random_data = rand();
763 return MemAWrite(context, address, random_data, addr_byte_size);
786std::optional<RegisterInfo>
824 bool is_apple =
false;
828 case llvm::Triple::Darwin:
829 case llvm::Triple::MacOSX:
830 case llvm::Triple::IOS:
831 case llvm::Triple::TvOS:
832 case llvm::Triple::WatchOS:
845 uint32_t fp_regnum = 11;
857 bool is_apple =
false;
861 case llvm::Triple::Darwin:
862 case llvm::Triple::MacOSX:
863 case llvm::Triple::IOS:
896 EncodingSpecificOperations();
897 NullCheckIfThumbEE(13);
898 address = SP - 4*
BitCount(registers);
902 if (registers<i> ==
'1')
904 if i == 13 && i != LowestSetBit(registers)
905 MemA[address,4] =
bits(32) UNKNOWN;
907 MemA[address,4] = R[i];
908 address = address + 4;
912 if (registers<15> ==
'1')
913 MemA[address,4] = PCStoreValue();
919 bool success =
false;
925 uint32_t registers = 0;
929 registers =
Bits32(opcode, 7, 0);
931 if (
Bit32(opcode, 8))
932 registers |= (1u << 14);
939 registers =
Bits32(opcode, 15, 0) & ~0xa000;
945 Rt =
Bits32(opcode, 15, 12);
949 registers = (1u << Rt);
952 registers =
Bits32(opcode, 15, 0);
958 Rt =
Bits32(opcode, 15, 12);
962 registers = (1u << Rt);
973 std::optional<RegisterInfo> sp_reg =
975 for (i = 0; i < 15; ++i) {
977 std::optional<RegisterInfo> reg_info =
983 if (!
MemAWrite(context, addr, reg_value, addr_byte_size))
985 addr += addr_byte_size;
990 std::optional<RegisterInfo> reg_info =
1019 EncodingSpecificOperations(); NullCheckIfThumbEE(13);
1022 if registers<i> ==
'1' then
1023 R[i] =
if UnalignedAllowed then MemU[address,4]
else MemA[address,4]; address = address + 4;
1024 if registers<15> ==
'1' then
1025 if UnalignedAllowed then
1029 if registers<13> ==
'0' then SP = SP + 4*
BitCount(registers);
1030 if registers<13> ==
'1' then SP =
bits(32) UNKNOWN;
1034 bool success =
false;
1041 uint32_t registers = 0;
1045 registers =
Bits32(opcode, 7, 0);
1047 if (
Bit32(opcode, 8))
1048 registers |= (1u << 15);
1055 registers =
Bits32(opcode, 15, 0) & ~0x2000;
1066 Rt =
Bits32(opcode, 15, 12);
1073 registers = (1u << Rt);
1076 registers =
Bits32(opcode, 15, 0);
1086 Rt =
Bits32(opcode, 15, 12);
1090 registers = (1u << Rt);
1102 std::optional<RegisterInfo> sp_reg =
1105 for (i = 0; i < 15; ++i) {
1108 data =
MemARead(context, addr, 4, 0, &success);
1114 addr += addr_byte_size;
1120 data =
MemARead(context, addr, 4, 0, &success);
1147 EncodingSpecificOperations();
1148 (result, carry, overflow) =
AddWithCarry(SP, imm32,
'0');
1154 APSR.N = result<31>;
1155 APSR.Z = IsZeroBit(result);
1161 bool success =
false;
1172 imm32 =
Bits32(opcode, 7, 0) << 2;
1181 addr_t sp_offset = imm32;
1189 std::optional<RegisterInfo> sp_reg =
1208 EncodingSpecificOperations();
1215 APSR.N = result<31>;
1216 APSR.Z = IsZeroBit(result);
1222 bool success =
false;
1245 std::optional<RegisterInfo> sp_reg =
1270 EncodingSpecificOperations();
1277 APSR.N = result<31>;
1278 APSR.Z = IsZeroBit(result);
1284 bool success =
false;
1293 Rm =
Bits32(opcode, 6, 3);
1300 Rm =
Bits32(opcode, 5, 3);
1307 Rm =
Bits32(opcode, 3, 0);
1314 if (!setflags && (
Rd == 15 || Rm == 15 || (
Rd == 13 && Rm == 13)))
1319 Rm =
Bits32(opcode, 3, 0);
1324 if (
Rd == 15 && setflags)
1342 std::optional<RegisterInfo> dwarf_reg =
1361 EncodingSpecificOperations();
1368 APSR.N = result<31>;
1369 APSR.Z = IsZeroBit(result);
1387 imm32 =
Bits32(opcode, 7, 0);
1406 uint32_t imm4 =
Bits32(opcode, 19, 16);
1407 uint32_t imm3 =
Bits32(opcode, 14, 12);
1408 uint32_t i =
Bit32(opcode, 26);
1409 uint32_t imm8 =
Bits32(opcode, 7, 0);
1410 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
1426 if ((
Rd == 15) && setflags)
1435 uint32_t imm4 =
Bits32(opcode, 19, 16);
1436 uint32_t imm12 =
Bits32(opcode, 11, 0);
1437 imm32 = (imm4 << 12) | imm12;
1447 uint32_t result = imm32;
1472 EncodingSpecificOperations();
1473 operand1 =
SInt(R[n]);
1474 operand2 =
SInt(R[m]);
1475 result = operand1 * operand2;
1476 R[d] = result<31:0>;
1478 APSR.N = result<31>;
1479 APSR.Z = IsZeroBit(result);
1481 APSR.C =
bit UNKNOWN;
1496 d =
Bits32(opcode, 2, 0);
1497 n =
Bits32(opcode, 5, 3);
1498 m =
Bits32(opcode, 2, 0);
1509 d =
Bits32(opcode, 11, 8);
1510 n =
Bits32(opcode, 19, 16);
1511 m =
Bits32(opcode, 3, 0);
1522 d =
Bits32(opcode, 19, 16);
1523 n =
Bits32(opcode, 3, 0);
1524 m =
Bits32(opcode, 11, 8);
1528 if ((d == 15) || (n == 15) || (m == 15))
1541 bool success =
false;
1558 uint64_t result = operand1 * operand2;
1561 std::optional<RegisterInfo> op1_reg =
1563 std::optional<RegisterInfo> op2_reg =
1571 (0x0000ffff & result)))
1603 EncodingSpecificOperations();
1604 result =
NOT(imm32);
1610 APSR.N = result<31>;
1611 APSR.Z = IsZeroBit(result);
1635 if (
Rd == 15 && setflags)
1641 uint32_t result = ~imm32;
1663 EncodingSpecificOperations();
1664 (shifted, carry) =
Shift_C(R[m], shift_t, shift_n, APSR.C);
1665 result =
NOT(shifted);
1671 APSR.N = result<31>;
1672 APSR.Z = IsZeroBit(result);
1688 Rm =
Bits32(opcode, 5, 3);
1697 Rm =
Bits32(opcode, 3, 0);
1706 Rm =
Bits32(opcode, 3, 0);
1713 bool success =
false;
1722 uint32_t result = ~shifted;
1744 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
1746 address =
if add then (base + imm32)
else (base - imm32);
1747 data = MemU[address,4];
1749 if address<1:0> ==
'00' then
LoadWritePC(data);
else UNPREDICTABLE;
1754 R[t] =
ROR(data, 8*
UInt(address<1:0>));
1756 R[t] =
bits(32) UNKNOWN;
1761 bool success =
false;
1769 std::optional<RegisterInfo> pc_reg =
1781 Rt =
Bits32(opcode, 10, 8);
1782 imm32 =
Bits32(opcode, 7, 0) << 2;
1786 Rt =
Bits32(opcode, 15, 12);
1787 imm32 =
Bits32(opcode, 11, 0) << 2;
1798 address = base + imm32;
1800 address = base - imm32;
1803 data =
MemURead(context, address, 4, 0, &success);
1808 if (
Bits32(address, 1, 0) == 0) {
1832 EncodingSpecificOperations();
1833 (result, carry, overflow) =
AddWithCarry(SP, imm32,
'0');
1839 APSR.N = result<31>;
1840 APSR.Z = IsZeroBit(result);
1846 bool success =
false;
1858 d =
Bits32(opcode, 10, 8);
1859 imm32 = (
Bits32(opcode, 7, 0) << 2);
1873 d =
Bits32(opcode, 11, 8);
1875 setflags =
Bit32(opcode, 20);
1878 if (d == 15 && setflags == 1)
1882 if (d == 15 && setflags == 0)
1889 d =
Bits32(opcode, 11, 8);
1891 uint32_t i =
Bit32(opcode, 26);
1892 uint32_t imm3 =
Bits32(opcode, 14, 12);
1893 uint32_t imm8 =
Bits32(opcode, 7, 0);
1894 imm32 = (i << 11) | (imm3 << 8) | imm8;
1913 std::optional<RegisterInfo> sp_reg =
1943 EncodingSpecificOperations();
1944 shifted =
Shift(R[m], shift_t, shift_n, APSR.C);
1945 (result, carry, overflow) =
AddWithCarry(SP, shifted,
'0');
1951 APSR.N = result<31>;
1952 APSR.Z = IsZeroBit(result);
1958 bool success =
false;
1967 Rm =
Bits32(opcode, 6, 3);
1976 addr_t addr = (int32_t)
sp + reg_value;
1980 std::optional<RegisterInfo> sp_reg =
1982 std::optional<RegisterInfo> other_reg =
2003 EncodingSpecificOperations();
2007 LR = PC<31:1> :
'1';
2008 if targetInstrSet == InstrSet_ARM then
2009 targetAddress =
Align(PC,4) + imm32;
2011 targetAddress = PC + imm32;
2017 bool success =
true;
2031 uint32_t S =
Bit32(opcode, 26);
2032 uint32_t imm10 =
Bits32(opcode, 25, 16);
2033 uint32_t J1 =
Bit32(opcode, 13);
2034 uint32_t J2 =
Bit32(opcode, 11);
2035 uint32_t imm11 =
Bits32(opcode, 10, 0);
2036 uint32_t I1 = !(J1 ^ S);
2037 uint32_t I2 = !(J2 ^ S);
2039 (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2040 imm32 = llvm::SignExtend32<25>(imm25);
2041 target =
pc + imm32;
2050 uint32_t S =
Bit32(opcode, 26);
2051 uint32_t imm10H =
Bits32(opcode, 25, 16);
2052 uint32_t J1 =
Bit32(opcode, 13);
2053 uint32_t J2 =
Bit32(opcode, 11);
2054 uint32_t imm10L =
Bits32(opcode, 10, 1);
2055 uint32_t I1 = !(J1 ^ S);
2056 uint32_t I2 = !(J2 ^ S);
2058 (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
2059 imm32 = llvm::SignExtend32<25>(imm25);
2060 target =
Align(
pc, 4) + imm32;
2069 imm32 = llvm::SignExtend32<26>(
Bits32(opcode, 23, 0) << 2);
2070 target =
Align(
pc, 4) + imm32;
2076 imm32 = llvm::SignExtend32<26>(
Bits32(opcode, 23, 0) << 2 |
2077 Bits32(opcode, 24, 24) << 1);
2078 target =
pc + imm32;
2107 EncodingSpecificOperations();
2110 next_instr_addr = PC - 4;
2111 LR = next_instr_addr;
2113 next_instr_addr = PC - 2;
2114 LR = next_instr_addr<31:1> :
'1';
2119 bool success =
false;
2132 Rm =
Bits32(opcode, 6, 3);
2141 Rm =
Bits32(opcode, 3, 0);
2152 std::optional<RegisterInfo> dwarf_reg =
2172 EncodingSpecificOperations();
2183 Rm =
Bits32(opcode, 6, 3);
2188 Rm =
Bits32(opcode, 3, 0);
2193 bool success =
false;
2198 std::optional<RegisterInfo> dwarf_reg =
2220 EncodingSpecificOperations();
2224 if JazelleAcceptsExecution() then
2225 SwitchToJazelleExecution();
2227 SUBARCHITECTURE_DEFINED handler call;
2237 Rm =
Bits32(opcode, 19, 16);
2244 Rm =
Bits32(opcode, 3, 0);
2251 bool success =
false;
2256 std::optional<RegisterInfo> dwarf_reg =
2273 EncodingSpecificOperations();
2280 APSR.N = result<31>;
2281 APSR.Z = IsZeroBit(result);
2288 bool success =
false;
2300 addr_t ip_offset = imm32;
2301 addr_t addr = ip - ip_offset;
2305 std::optional<RegisterInfo> dwarf_reg =
2323 EncodingSpecificOperations();
2330 APSR.N = result<31>;
2331 APSR.Z = IsZeroBit(result);
2338 bool success =
false;
2350 addr_t sp_offset = imm32;
2355 std::optional<RegisterInfo> dwarf_reg =
2376 EncodingSpecificOperations();
2383 APSR.N = result<31>;
2384 APSR.Z = IsZeroBit(result);
2390 bool success =
false;
2409 if (
Rd == 15 && setflags)
2411 if (
Rd == 15 && !setflags)
2428 if (
Rd == 15 && setflags)
2438 uint64_t imm64 = imm32;
2462 EncodingSpecificOperations();
2463 offset_addr =
if add then (R[n] + imm32)
else (R[n] - imm32);
2464 address =
if index then offset_addr
else R[n];
2465 MemU[address,4] =
if t == 15 then PCStoreValue()
else R[t];
2466 if wback then R[n] = offset_addr;
2470 bool success =
false;
2486 Rt =
Bits32(opcode, 15, 12);
2487 imm12 =
Bits32(opcode, 11, 0);
2488 Rn =
Bits32(opcode, 19, 16);
2497 if (wback && ((Rn == 15) || (Rn == Rt)))
2505 offset_addr =
sp + imm12;
2507 offset_addr =
sp - imm12;
2517 std::optional<RegisterInfo> sp_reg =
2519 std::optional<RegisterInfo> dwarf_reg =
2527 if (!
MemUWrite(context, addr, reg_value, addr_byte_size))
2533 if (!
MemUWrite(context, addr,
pc, addr_byte_size))
2556 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2557 address = SP - imm32;
2561 MemA[address,4] = S[d+r]; address = address+4;
2566 MemA[address,4] =
if BigEndian() then D[d+r]<63:32>
else D[d+r]<31:0>;
2567 MemA[address+4,4] =
if BigEndian() then D[d+r]<31:0>
else D[d+r]<63:32>;
2568 address = address+8;
2572 bool success =
false;
2585 single_regs =
false;
2586 d =
Bit32(opcode, 22) << 4 |
Bits32(opcode, 15, 12);
2587 imm32 =
Bits32(opcode, 7, 0) * addr_byte_size;
2589 regs =
Bits32(opcode, 7, 0) / 2;
2591 if (regs == 0 || regs > 16 || (d + regs) > 32)
2597 d =
Bits32(opcode, 15, 12) << 1 |
Bit32(opcode, 22);
2598 imm32 =
Bits32(opcode, 7, 0) * addr_byte_size;
2599 regs =
Bits32(opcode, 7, 0);
2601 if (regs == 0 || regs > 16 || (d + regs) > 32)
2608 uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2609 addr_t sp_offset = imm32;
2616 std::optional<RegisterInfo> sp_reg =
2618 for (i = 0; i < regs; ++i) {
2619 std::optional<RegisterInfo> dwarf_reg =
2626 if (!
MemAWrite(context, addr, reg_value, reg_byte_size))
2628 addr += reg_byte_size;
2649 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2654 S[d+r] = MemA[address,4]; address = address+4;
2657 word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
2660 D[d+r] =
if BigEndian() then word1:word2
else word2:word1;
2664 bool success =
false;
2677 single_regs =
false;
2678 d =
Bit32(opcode, 22) << 4 |
Bits32(opcode, 15, 12);
2679 imm32 =
Bits32(opcode, 7, 0) * addr_byte_size;
2681 regs =
Bits32(opcode, 7, 0) / 2;
2683 if (regs == 0 || regs > 16 || (d + regs) > 32)
2689 d =
Bits32(opcode, 15, 12) << 1 |
Bit32(opcode, 22);
2690 imm32 =
Bits32(opcode, 7, 0) * addr_byte_size;
2691 regs =
Bits32(opcode, 7, 0);
2693 if (regs == 0 || regs > 16 || (d + regs) > 32)
2700 uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2701 addr_t sp_offset = imm32;
2709 for (i = 0; i < regs; ++i) {
2710 std::optional<RegisterInfo> dwarf_reg =
2713 data =
MemARead(context, addr, reg_byte_size, 0, &success);
2718 addr += reg_byte_size;
2738 EncodingSpecificOperations();
2743 bool success =
false;
2755 imm32 =
Bits32(opcode, 7, 0);
2760 imm32 =
Bits32(opcode, 23, 0);
2782 EncodingSpecificOperations();
2783 ITSTATE.IT<7:0> = firstcond:mask;
2803 EncodingSpecificOperations();
2808 bool success =
false;
2821 imm32 = llvm::SignExtend32<9>(
Bits32(opcode, 7, 0) << 1);
2822 target =
pc + imm32;
2826 imm32 = llvm::SignExtend32<12>(
Bits32(opcode, 10, 0) << 1);
2827 target =
pc + imm32;
2833 if (
Bits32(opcode, 25, 23) == 7)
2837 uint32_t S =
Bit32(opcode, 26);
2838 uint32_t imm6 =
Bits32(opcode, 21, 16);
2839 uint32_t J1 =
Bit32(opcode, 13);
2840 uint32_t J2 =
Bit32(opcode, 11);
2841 uint32_t imm11 =
Bits32(opcode, 10, 0);
2843 (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
2844 imm32 = llvm::SignExtend32<21>(imm21);
2845 target =
pc + imm32;
2850 uint32_t S =
Bit32(opcode, 26);
2851 uint32_t imm10 =
Bits32(opcode, 25, 16);
2852 uint32_t J1 =
Bit32(opcode, 13);
2853 uint32_t J2 =
Bit32(opcode, 11);
2854 uint32_t imm11 =
Bits32(opcode, 10, 0);
2855 uint32_t I1 = !(J1 ^ S);
2856 uint32_t I2 = !(J2 ^ S);
2858 (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2859 imm32 = llvm::SignExtend32<25>(imm25);
2860 target =
pc + imm32;
2865 imm32 = llvm::SignExtend32<26>(
Bits32(opcode, 23, 0) << 2);
2866 target =
pc + imm32;
2885 EncodingSpecificOperations();
2886 if nonzero ^
IsZero(R[n]) then
2890 bool success =
false;
2908 imm32 =
Bit32(opcode, 9) << 6 |
Bits32(opcode, 7, 3) << 1;
2910 target =
pc + imm32;
2939 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
2941 halfwords =
UInt(MemU[R[n]+
LSL(R[m],1), 2]);
2943 halfwords =
UInt(MemU[R[n]+R[m], 1]);
2947 bool success =
false;
2957 Rn =
Bits32(opcode, 19, 16);
2958 Rm =
Bits32(opcode, 3, 0);
2960 if (Rn == 13 ||
BadReg(Rm))
2981 addr_t addr = base + (is_tbh ? index * 2 : index);
2986 uint32_t offset =
MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
2997 context.SetISAAndImmediateSigned(
eModeThumb, 4 + offset);
3013 EncodingSpecificOperations();
3014 (result, carry, overflow) =
AddWithCarry(R[n], imm32,
'0');
3017 APSR.N = result<31>;
3018 APSR.Z = IsZeroBit(result);
3023 bool success =
false;
3037 d =
Bits32(opcode, 2, 0);
3038 n =
Bits32(opcode, 5, 3);
3040 imm32 =
Bits32(opcode, 8, 6);
3047 d =
Bits32(opcode, 10, 8);
3048 n =
Bits32(opcode, 10, 8);
3050 imm32 =
Bits32(opcode, 7, 0);
3058 d =
Bits32(opcode, 11, 8);
3059 n =
Bits32(opcode, 19, 16);
3068 if (
BadReg(d) || (n == 15))
3077 d =
Bits32(opcode, 11, 8);
3078 n =
Bits32(opcode, 19, 16);
3080 uint32_t i =
Bit32(opcode, 26);
3081 uint32_t imm3 =
Bits32(opcode, 14, 12);
3082 uint32_t imm8 =
Bits32(opcode, 7, 0);
3083 imm32 = (i << 11) | (imm3 << 8) | imm8;
3108 std::optional<RegisterInfo> reg_n =
3135 EncodingSpecificOperations();
3136 (result, carry, overflow) =
AddWithCarry(R[n], imm32,
'0');
3142 APSR.N = result<31>;
3143 APSR.Z = IsZeroBit(result);
3148 bool success =
false;
3158 Rn =
Bits32(opcode, 19, 16);
3181 std::optional<RegisterInfo> dwarf_reg =
3200 EncodingSpecificOperations();
3201 shifted =
Shift(R[m], shift_t, shift_n, APSR.C);
3202 (result, carry, overflow) =
AddWithCarry(R[n], shifted,
'0');
3208 APSR.N = result<31>;
3209 APSR.Z = IsZeroBit(result);
3214 bool success =
false;
3217 uint32_t
Rd, Rn, Rm;
3224 Rn =
Bits32(opcode, 5, 3);
3225 Rm =
Bits32(opcode, 8, 6);
3232 Rm =
Bits32(opcode, 6, 3);
3236 if (Rn == 15 && Rm == 15)
3243 Rn =
Bits32(opcode, 19, 16);
3244 Rm =
Bits32(opcode, 3, 0);
3262 uint32_t shifted =
Shift(val2, shift_t, shift_n,
APSR_C, &success);
3269 std::optional<RegisterInfo> op1_reg =
3271 std::optional<RegisterInfo> op2_reg =
3289 EncodingSpecificOperations();
3290 (result, carry, overflow) =
AddWithCarry(R[n], imm32,
'0');
3291 APSR.N = result<31>;
3292 APSR.Z = IsZeroBit(result);
3297 bool success =
false;
3303 Rn =
Bits32(opcode, 19, 16);
3309 Rn =
Bits32(opcode, 19, 16);
3336 EncodingSpecificOperations();
3337 shifted =
Shift(R[m], shift_t, shift_n, APSR.C);
3338 (result, carry, overflow) =
AddWithCarry(R[n], shifted,
'0');
3339 APSR.N = result<31>;
3340 APSR.Z = IsZeroBit(result);
3345 bool success =
false;
3353 Rn =
Bits32(opcode, 2, 0);
3354 Rm =
Bits32(opcode, 5, 3);
3359 Rn =
Bits32(opcode, 19, 16);
3360 Rm =
Bits32(opcode, 3, 0);
3363 if (Rn == 15 ||
BadReg(Rm))
3367 Rn =
Bits32(opcode, 19, 16);
3368 Rm =
Bits32(opcode, 3, 0);
3384 uint32_t shifted =
Shift(val2, shift_t, shift_n,
APSR_C, &success);
3402 EncodingSpecificOperations();
3404 APSR.N = result<31>;
3405 APSR.Z = IsZeroBit(result);
3410 bool success =
false;
3416 Rn =
Bits32(opcode, 10, 8);
3417 imm32 =
Bits32(opcode, 7, 0);
3420 Rn =
Bits32(opcode, 19, 16);
3426 Rn =
Bits32(opcode, 19, 16);
3453 EncodingSpecificOperations();
3454 shifted =
Shift(R[m], shift_t, shift_n, APSR.C);
3456 APSR.N = result<31>;
3457 APSR.Z = IsZeroBit(result);
3462 bool success =
false;
3470 Rn =
Bits32(opcode, 2, 0);
3471 Rm =
Bits32(opcode, 5, 3);
3476 Rn =
Bit32(opcode, 7) << 3 |
Bits32(opcode, 2, 0);
3477 Rm =
Bits32(opcode, 6, 3);
3480 if (Rn < 8 && Rm < 8)
3482 if (Rn == 15 || Rm == 15)
3486 Rn =
Bits32(opcode, 19, 16);
3487 Rm =
Bits32(opcode, 3, 0);
3489 if (Rn == 15 ||
BadReg(Rm))
3493 Rn =
Bits32(opcode, 19, 16);
3494 Rm =
Bits32(opcode, 3, 0);
3510 uint32_t shifted =
Shift(val2, shift_t, shift_n,
APSR_C, &success);
3530 EncodingSpecificOperations();
3537 APSR.N = result<31>;
3538 APSR.Z = IsZeroBit(result);
3556 EncodingSpecificOperations();
3557 shift_n =
UInt(R[m]<7:0>);
3561 APSR.N = result<31>;
3562 APSR.Z = IsZeroBit(result);
3578 EncodingSpecificOperations();
3585 APSR.N = result<31>;
3586 APSR.Z = IsZeroBit(result);
3603 EncodingSpecificOperations();
3604 shift_n =
UInt(R[m]<7:0>);
3608 APSR.N = result<31>;
3609 APSR.Z = IsZeroBit(result);
3626 EncodingSpecificOperations();
3633 APSR.N = result<31>;
3634 APSR.Z = IsZeroBit(result);
3651 EncodingSpecificOperations();
3652 shift_n =
UInt(R[m]<7:0>);
3656 APSR.N = result<31>;
3657 APSR.Z = IsZeroBit(result);
3674 EncodingSpecificOperations();
3681 APSR.N = result<31>;
3682 APSR.Z = IsZeroBit(result);
3700 EncodingSpecificOperations();
3701 shift_n =
UInt(R[m]<7:0>);
3705 APSR.N = result<31>;
3706 APSR.Z = IsZeroBit(result);
3724 EncodingSpecificOperations();
3731 APSR.N = result<31>;
3732 APSR.Z = IsZeroBit(result);
3749 bool success =
false;
3768 switch (use_encoding) {
3771 Rm =
Bits32(opcode, 5, 3);
3773 imm5 =
Bits32(opcode, 10, 6);
3782 Rm =
Bits32(opcode, 3, 0);
3784 imm5 =
Bits32(opcode, 14, 12) << 2 |
Bits32(opcode, 7, 6);
3790 Rm =
Bits32(opcode, 3, 0);
3792 imm5 =
Bits32(opcode, 11, 7);
3811 uint32_t result =
Shift_C(value, shift_type, amt,
APSR_C, carry, &success);
3834 bool success =
false;
3847 Rm =
Bits32(opcode, 5, 3);
3852 Rn =
Bits32(opcode, 19, 16);
3853 Rm =
Bits32(opcode, 3, 0);
3860 Rn =
Bits32(opcode, 3, 0);
3861 Rm =
Bits32(opcode, 11, 8);
3863 if (
Rd == 15 || Rn == 15 || Rm == 15)
3880 uint32_t amt =
Bits32(val, 7, 0);
3882 uint32_t result =
Shift_C(value, shift_type, amt,
APSR_C, carry, &success);
3905 EncodingSpecificOperations(); NullCheckIfThumbEE (n);
3909 if registers<i> ==
'1' then
3910 R[i] = MemA[address, 4]; address = address + 4;
3911 if registers<15> ==
'1' then
3914 if wback && registers<n> ==
'0' then R[n] = R[n] + 4 *
BitCount (registers);
3915 if wback && registers<n> ==
'1' then R[n] =
bits(32) UNKNOWN;
3919 bool success =
false;
3922 uint32_t registers = 0;
3929 n =
Bits32(opcode, 10, 8);
3930 registers =
Bits32(opcode, 7, 0);
3931 registers = registers & 0x00ff;
3940 n =
Bits32(opcode, 19, 16);
3941 registers =
Bits32(opcode, 15, 0);
3942 registers = registers & 0xdfff;
3947 if ((n == 15) || (
BitCount(registers) < 2) ||
3957 if (wback &&
BitIsSet(registers, n))
3962 n =
Bits32(opcode, 19, 16);
3963 registers =
Bits32(opcode, 15, 0);
3965 if ((n == 15) || (
BitCount(registers) < 1))
3973 const addr_t base_address =
3980 std::optional<RegisterInfo> dwarf_reg =
3984 for (
int i = 0; i < 14; ++i) {
3988 if (wback && (n == 13))
3995 uint32_t data =
MemARead(context, base_address + offset, addr_byte_size,
4004 offset += addr_byte_size;
4013 MemARead(context, base_address + offset, addr_byte_size, 0, &success);
4023 int32_t offset = addr_byte_size *
BitCount(registers);
4028 base_address + offset))
4031 if (wback &&
BitIsSet(registers, n))
4048 EncodingSpecificOperations();
4049 address = R[n] - 4*
BitCount(registers) + 4;
4052 if registers<i> ==
'1' then
4053 R[i] = MemA[address,4]; address = address + 4;
4055 if registers<15> ==
'1' then
4058 if wback && registers<n> ==
'0' then R[n] = R[n] - 4*
BitCount(registers);
4059 if wback && registers<n> ==
'1' then R[n] =
bits(32) UNKNOWN;
4062 bool success =
false;
4066 uint32_t registers = 0;
4074 n =
Bits32(opcode, 19, 16);
4075 registers =
Bits32(opcode, 15, 0);
4079 if ((n == 15) || (
BitCount(registers) < 1))
4096 Rn - (addr_byte_size *
BitCount(registers)) + addr_byte_size;
4100 std::optional<RegisterInfo> dwarf_reg =
4102 context.SetRegisterPlusOffset(*dwarf_reg, offset);
4105 for (
int i = 0; i < 14; ++i) {
4109 context.SetRegisterPlusOffset(*dwarf_reg, Rn - (address + offset));
4111 MemARead(context, address + offset, addr_byte_size, 0, &success);
4117 offset += addr_byte_size;
4124 context.SetRegisterPlusOffset(*dwarf_reg, offset);
4126 MemARead(context, address + offset, addr_byte_size, 0, &success);
4137 offset = (addr_byte_size *
BitCount(registers)) * -1;
4139 context.SetImmediateSigned(offset);
4140 addr_t addr = Rn + offset;
4147 if (wback &&
BitIsSet(registers, n))
4163 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4164 address = R[n] - 4*
BitCount(registers);
4167 if registers<i> ==
'1' then
4168 R[i] = MemA[address,4]; address = address + 4;
4169 if registers<15> ==
'1' then
4172 if wback && registers<n> ==
'0' then R[n] = R[n] - 4*
BitCount(registers);
4173 if wback && registers<n> ==
'1' then R[n] =
bits(32) UNKNOWN;
4176 bool success =
false;
4180 uint32_t registers = 0;
4186 n =
Bits32(opcode, 19, 16);
4187 registers =
Bits32(opcode, 15, 0);
4188 registers = registers & 0xdfff;
4193 if ((n == 15) || (
BitCount(registers) < 2) ||
4203 if (wback &&
BitIsSet(registers, n))
4210 n =
Bits32(opcode, 19, 16);
4211 registers =
Bits32(opcode, 15, 0);
4215 if ((n == 15) || (
BitCount(registers) < 1))
4236 std::optional<RegisterInfo> dwarf_reg =
4238 context.SetRegisterPlusOffset(*dwarf_reg, Rn - address);
4240 for (
int i = 0; i < 14; ++i) {
4243 context.SetRegisterPlusOffset(*dwarf_reg, Rn - (address + offset));
4245 MemARead(context, address + offset, addr_byte_size, 0, &success);
4253 offset += addr_byte_size;
4260 context.SetRegisterPlusOffset(*dwarf_reg, offset);
4262 MemARead(context, address + offset, addr_byte_size, 0, &success);
4273 offset = (addr_byte_size *
BitCount(registers)) * -1;
4275 context.SetImmediateSigned(offset);
4276 addr_t addr = Rn + offset;
4284 if (wback &&
BitIsSet(registers, n))
4299 EncodingSpecificOperations();
4303 if registers<i> ==
'1' then
4304 R[i] = MemA[address,4]; address = address + 4;
4305 if registers<15> ==
'1' then
4308 if wback && registers<n> ==
'0' then R[n] = R[n] + 4*
BitCount(registers);
4309 if wback && registers<n> ==
'1' then R[n] =
bits(32) UNKNOWN;
4312 bool success =
false;
4316 uint32_t registers = 0;
4322 n =
Bits32(opcode, 19, 16);
4323 registers =
Bits32(opcode, 15, 0);
4327 if ((n == 15) || (
BitCount(registers) < 1))
4343 addr_t address = Rn + addr_byte_size;
4347 std::optional<RegisterInfo> dwarf_reg =
4351 for (
int i = 0; i < 14; ++i) {
4357 MemARead(context, address + offset, addr_byte_size, 0, &success);
4365 offset += addr_byte_size;
4374 MemARead(context, address + offset, addr_byte_size, 0, &success);
4385 offset = addr_byte_size *
BitCount(registers);
4388 addr_t addr = Rn + offset;
4396 if (wback &&
BitIsSet(registers, n))
4411 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
4412 offset_addr =
if add then (R[n] + imm32)
else (R[n] - imm32);
4413 address =
if index then offset_addr
else R[n];
4414 data = MemU[address,4];
4415 if wback then R[n] = offset_addr;
4417 if address<1:0> ==
'00' then
LoadWritePC(data);
else UNPREDICTABLE;
4420 else R[t] =
bits(32) UNKNOWN;
4424 bool success =
false;
4433 bool add, index, wback;
4436 Rt =
Bits32(opcode, 2, 0);
4437 Rn =
Bits32(opcode, 5, 3);
4438 imm32 =
Bits32(opcode, 10, 6) << 2;
4448 Rt =
Bits32(opcode, 10, 8);
4450 imm32 =
Bits32(opcode, 7, 0) << 2;
4462 Rt =
Bits32(opcode, 15, 12);
4463 Rn =
Bits32(opcode, 19, 16);
4464 imm32 =
Bits32(opcode, 11, 0);
4487 Rt =
Bits32(opcode, 15, 12);
4488 Rn =
Bits32(opcode, 19, 16);
4489 imm32 =
Bits32(opcode, 7, 0);
4498 if ((wback && (Rn == Rt)) ||
4511 offset_addr = base + imm32;
4513 offset_addr = base - imm32;
4515 address = (index ? offset_addr : base);
4517 std::optional<RegisterInfo> base_reg =
4543 data =
MemURead(context, address, 4, 0, &success);
4548 if (
Bits32(address, 1, 0) == 0) {
4572 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4576 if registers<i> ==
'1' then
4577 if i == n && wback && i != LowestSetBit(registers) then
4578 MemA[address,4] =
bits(32) UNKNOWN;
4580 MemA[address,4] = R[i];
4581 address = address + 4;
4583 if registers<15> ==
'1' then
4584 MemA[address,4] = PCStoreValue();
4585 if wback then R[n] = R[n] + 4*
BitCount(registers);
4588 bool success =
false;
4592 uint32_t registers = 0;
4600 n =
Bits32(opcode, 10, 8);
4601 registers =
Bits32(opcode, 7, 0);
4602 registers = registers & 0x00ff;
4613 n =
Bits32(opcode, 19, 16);
4614 registers =
Bits32(opcode, 15, 0);
4615 registers = registers & 0x5fff;
4619 if ((n == 15) || (
BitCount(registers) < 2))
4623 if (wback &&
BitIsSet(registers, n))
4630 n =
Bits32(opcode, 19, 16);
4631 registers =
Bits32(opcode, 15, 0);
4635 if ((n == 15) || (
BitCount(registers) < 1))
4653 std::optional<RegisterInfo> base_reg =
4657 uint32_t lowest_set_bit = 14;
4658 for (uint32_t i = 0; i < 14; ++i) {
4661 if (i < lowest_set_bit)
4664 if ((i == n) && wback && (i != lowest_set_bit))
4675 std::optional<RegisterInfo> data_reg =
4678 if (!
MemAWrite(context, address + offset, data, addr_byte_size))
4683 offset += addr_byte_size;
4690 std::optional<RegisterInfo> pc_reg =
4697 if (!
MemAWrite(context, address + offset,
pc, addr_byte_size))
4703 offset = addr_byte_size *
BitCount(registers);
4706 addr_t data = address + offset;
4724 EncodingSpecificOperations();
4725 address = R[n] - 4*
BitCount(registers) + 4;
4728 if registers<i> ==
'1' then
4729 if i == n && wback && i != LowestSetBit(registers) then
4730 MemA[address,4] =
bits(32) UNKNOWN;
4732 MemA[address,4] = R[i];
4733 address = address + 4;
4735 if registers<15> ==
'1' then
4736 MemA[address,4] = PCStoreValue();
4738 if wback then R[n] = R[n] - 4*
BitCount(registers);
4741 bool success =
false;
4745 uint32_t registers = 0;
4753 n =
Bits32(opcode, 19, 16);
4754 registers =
Bits32(opcode, 15, 0);
4758 if ((n == 15) || (
BitCount(registers) < 1))
4771 addr_t address = Rn - (addr_byte_size *
BitCount(registers)) + 4;
4775 std::optional<RegisterInfo> base_reg =
4779 uint32_t lowest_bit_set = 14;
4780 for (uint32_t i = 0; i < 14; ++i) {
4783 if (i < lowest_bit_set)
4786 if ((i == n) && wback && (i != lowest_bit_set))
4796 std::optional<RegisterInfo> data_reg =
4798 context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
4799 Rn - (address + offset));
4800 if (!
MemAWrite(context, address + offset, data, addr_byte_size))
4805 offset += addr_byte_size;
4812 std::optional<RegisterInfo> pc_reg =
4814 context.SetRegisterPlusOffset(*pc_reg, 8);
4819 if (!
MemAWrite(context, address + offset,
pc, addr_byte_size))
4825 offset = (addr_byte_size *
BitCount(registers)) * -1;
4827 context.SetImmediateSigned(offset);
4828 addr_t data = Rn + offset;
4846 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4847 address = R[n] - 4*
BitCount(registers);
4850 if registers<i> ==
'1' then
4851 if i == n && wback && i != LowestSetBit(registers) then
4852 MemA[address,4] =
bits(32) UNKNOWN;
4854 MemA[address,4] = R[i];
4855 address = address + 4;
4857 if registers<15> ==
'1' then
4858 MemA[address,4] = PCStoreValue();
4860 if wback then R[n] = R[n] - 4*
BitCount(registers);
4863 bool success =
false;
4867 uint32_t registers = 0;
4879 n =
Bits32(opcode, 19, 16);
4880 registers =
Bits32(opcode, 15, 0);
4881 registers = registers & 0x5fff;
4884 if ((n == 15) ||
BitCount(registers) < 2)
4887 if (wback &&
BitIsSet(registers, n))
4899 n =
Bits32(opcode, 19, 16);
4900 registers =
Bits32(opcode, 15, 0);
4903 if ((n == 15) ||
BitCount(registers) < 1)
4923 std::optional<RegisterInfo> base_reg =
4927 uint32_t lowest_set_bit = 14;
4928 for (uint32_t i = 0; i < 14; ++i) {
4931 if (i < lowest_set_bit)
4934 if ((i == n) && wback && (i != lowest_set_bit))
4945 std::optional<RegisterInfo> data_reg =
4947 context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
4948 Rn - (address + offset));
4949 if (!
MemAWrite(context, address + offset, data, addr_byte_size))
4954 offset += addr_byte_size;
4961 std::optional<RegisterInfo> pc_reg =
4963 context.SetRegisterPlusOffset(*pc_reg, 8);
4968 if (!
MemAWrite(context, address + offset,
pc, addr_byte_size))
4974 offset = (addr_byte_size *
BitCount(registers)) * -1;
4976 context.SetImmediateSigned(offset);
4977 addr_t data = Rn + offset;
4995 EncodingSpecificOperations();
4999 if registers<i> ==
'1' then
5000 if i == n && wback && i != LowestSetBit(registers) then
5001 MemA[address,4] =
bits(32) UNKNOWN;
5003 MemA[address,4] = R[i];
5004 address = address + 4;
5006 if registers<15> ==
'1' then
5007 MemA[address,4] = PCStoreValue();
5009 if wback then R[n] = R[n] + 4*
BitCount(registers);
5012 bool success =
false;
5016 uint32_t registers = 0;
5024 n =
Bits32(opcode, 19, 16);
5025 registers =
Bits32(opcode, 15, 0);
5029 if ((n == 15) && (
BitCount(registers) < 1))
5042 addr_t address = Rn + addr_byte_size;
5046 std::optional<RegisterInfo> base_reg =
5049 uint32_t lowest_set_bit = 14;
5051 for (uint32_t i = 0; i < 14; ++i) {
5054 if (i < lowest_set_bit)
5057 if ((i == n) && wback && (i != lowest_set_bit))
5068 std::optional<RegisterInfo> data_reg =
5071 offset + addr_byte_size);
5072 if (!
MemAWrite(context, address + offset, data, addr_byte_size))
5077 offset += addr_byte_size;
5084 std::optional<RegisterInfo> pc_reg =
5091 if (!
MemAWrite(context, address + offset,
pc, addr_byte_size))
5097 offset = addr_byte_size *
BitCount(registers);
5100 addr_t data = Rn + offset;
5117 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5118 offset_addr =
if add then (R[n] + imm32)
else (R[n] - imm32);