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EmulateInstructionARM.cpp
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1 //===-- EmulateInstructionARM.cpp -----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include <cstdlib>
10 
11 #include "EmulateInstructionARM.h"
12 #include "EmulationStateARM.h"
13 #include "lldb/Core/Address.h"
15 #include "lldb/Host/PosixApi.h"
18 #include "lldb/Symbol/UnwindPlan.h"
19 #include "lldb/Utility/ArchSpec.h"
21 #include "lldb/Utility/Stream.h"
22 
26 
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/Support/MathExtras.h"
29 
30 using namespace lldb;
31 using namespace lldb_private;
32 
34 
35 // Convenient macro definitions.
36 #define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS)
37 #define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)
38 
39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
40 
41 //
42 // ITSession implementation
43 //
44 
45 static bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo &reg_info) {
46  ::memset(&reg_info, 0, sizeof(RegisterInfo));
47  ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
48 
49  if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
50  reg_info.byte_size = 16;
51  reg_info.format = eFormatVectorOfUInt8;
52  reg_info.encoding = eEncodingVector;
53  }
54 
55  if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) {
56  reg_info.byte_size = 8;
57  reg_info.format = eFormatFloat;
58  reg_info.encoding = eEncodingIEEE754;
59  } else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31) {
60  reg_info.byte_size = 4;
61  reg_info.format = eFormatFloat;
62  reg_info.encoding = eEncodingIEEE754;
63  } else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7) {
64  reg_info.byte_size = 12;
65  reg_info.format = eFormatFloat;
66  reg_info.encoding = eEncodingIEEE754;
67  } else {
68  reg_info.byte_size = 4;
69  reg_info.format = eFormatHex;
70  reg_info.encoding = eEncodingUint;
71  }
72 
73  reg_info.kinds[eRegisterKindDWARF] = reg_num;
74 
75  switch (reg_num) {
76  case dwarf_r0:
77  reg_info.name = "r0";
78  break;
79  case dwarf_r1:
80  reg_info.name = "r1";
81  break;
82  case dwarf_r2:
83  reg_info.name = "r2";
84  break;
85  case dwarf_r3:
86  reg_info.name = "r3";
87  break;
88  case dwarf_r4:
89  reg_info.name = "r4";
90  break;
91  case dwarf_r5:
92  reg_info.name = "r5";
93  break;
94  case dwarf_r6:
95  reg_info.name = "r6";
96  break;
97  case dwarf_r7:
98  reg_info.name = "r7";
100  break;
101  case dwarf_r8:
102  reg_info.name = "r8";
103  break;
104  case dwarf_r9:
105  reg_info.name = "r9";
106  break;
107  case dwarf_r10:
108  reg_info.name = "r10";
109  break;
110  case dwarf_r11:
111  reg_info.name = "r11";
112  break;
113  case dwarf_r12:
114  reg_info.name = "r12";
115  break;
116  case dwarf_sp:
117  reg_info.name = "sp";
118  reg_info.alt_name = "r13";
120  break;
121  case dwarf_lr:
122  reg_info.name = "lr";
123  reg_info.alt_name = "r14";
125  break;
126  case dwarf_pc:
127  reg_info.name = "pc";
128  reg_info.alt_name = "r15";
130  break;
131  case dwarf_cpsr:
132  reg_info.name = "cpsr";
134  break;
135 
136  case dwarf_s0:
137  reg_info.name = "s0";
138  break;
139  case dwarf_s1:
140  reg_info.name = "s1";
141  break;
142  case dwarf_s2:
143  reg_info.name = "s2";
144  break;
145  case dwarf_s3:
146  reg_info.name = "s3";
147  break;
148  case dwarf_s4:
149  reg_info.name = "s4";
150  break;
151  case dwarf_s5:
152  reg_info.name = "s5";
153  break;
154  case dwarf_s6:
155  reg_info.name = "s6";
156  break;
157  case dwarf_s7:
158  reg_info.name = "s7";
159  break;
160  case dwarf_s8:
161  reg_info.name = "s8";
162  break;
163  case dwarf_s9:
164  reg_info.name = "s9";
165  break;
166  case dwarf_s10:
167  reg_info.name = "s10";
168  break;
169  case dwarf_s11:
170  reg_info.name = "s11";
171  break;
172  case dwarf_s12:
173  reg_info.name = "s12";
174  break;
175  case dwarf_s13:
176  reg_info.name = "s13";
177  break;
178  case dwarf_s14:
179  reg_info.name = "s14";
180  break;
181  case dwarf_s15:
182  reg_info.name = "s15";
183  break;
184  case dwarf_s16:
185  reg_info.name = "s16";
186  break;
187  case dwarf_s17:
188  reg_info.name = "s17";
189  break;
190  case dwarf_s18:
191  reg_info.name = "s18";
192  break;
193  case dwarf_s19:
194  reg_info.name = "s19";
195  break;
196  case dwarf_s20:
197  reg_info.name = "s20";
198  break;
199  case dwarf_s21:
200  reg_info.name = "s21";
201  break;
202  case dwarf_s22:
203  reg_info.name = "s22";
204  break;
205  case dwarf_s23:
206  reg_info.name = "s23";
207  break;
208  case dwarf_s24:
209  reg_info.name = "s24";
210  break;
211  case dwarf_s25:
212  reg_info.name = "s25";
213  break;
214  case dwarf_s26:
215  reg_info.name = "s26";
216  break;
217  case dwarf_s27:
218  reg_info.name = "s27";
219  break;
220  case dwarf_s28:
221  reg_info.name = "s28";
222  break;
223  case dwarf_s29:
224  reg_info.name = "s29";
225  break;
226  case dwarf_s30:
227  reg_info.name = "s30";
228  break;
229  case dwarf_s31:
230  reg_info.name = "s31";
231  break;
232 
233  // FPA Registers 0-7
234  case dwarf_f0:
235  reg_info.name = "f0";
236  break;
237  case dwarf_f1:
238  reg_info.name = "f1";
239  break;
240  case dwarf_f2:
241  reg_info.name = "f2";
242  break;
243  case dwarf_f3:
244  reg_info.name = "f3";
245  break;
246  case dwarf_f4:
247  reg_info.name = "f4";
248  break;
249  case dwarf_f5:
250  reg_info.name = "f5";
251  break;
252  case dwarf_f6:
253  reg_info.name = "f6";
254  break;
255  case dwarf_f7:
256  reg_info.name = "f7";
257  break;
258 
259  // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator
260  // register 0 - 7 (they do overlap with wCGR0 - wCGR7)
261  case dwarf_wCGR0:
262  reg_info.name = "wCGR0/ACC0";
263  break;
264  case dwarf_wCGR1:
265  reg_info.name = "wCGR1/ACC1";
266  break;
267  case dwarf_wCGR2:
268  reg_info.name = "wCGR2/ACC2";
269  break;
270  case dwarf_wCGR3:
271  reg_info.name = "wCGR3/ACC3";
272  break;
273  case dwarf_wCGR4:
274  reg_info.name = "wCGR4/ACC4";
275  break;
276  case dwarf_wCGR5:
277  reg_info.name = "wCGR5/ACC5";
278  break;
279  case dwarf_wCGR6:
280  reg_info.name = "wCGR6/ACC6";
281  break;
282  case dwarf_wCGR7:
283  reg_info.name = "wCGR7/ACC7";
284  break;
285 
286  // Intel wireless MMX data registers 0 - 15
287  case dwarf_wR0:
288  reg_info.name = "wR0";
289  break;
290  case dwarf_wR1:
291  reg_info.name = "wR1";
292  break;
293  case dwarf_wR2:
294  reg_info.name = "wR2";
295  break;
296  case dwarf_wR3:
297  reg_info.name = "wR3";
298  break;
299  case dwarf_wR4:
300  reg_info.name = "wR4";
301  break;
302  case dwarf_wR5:
303  reg_info.name = "wR5";
304  break;
305  case dwarf_wR6:
306  reg_info.name = "wR6";
307  break;
308  case dwarf_wR7:
309  reg_info.name = "wR7";
310  break;
311  case dwarf_wR8:
312  reg_info.name = "wR8";
313  break;
314  case dwarf_wR9:
315  reg_info.name = "wR9";
316  break;
317  case dwarf_wR10:
318  reg_info.name = "wR10";
319  break;
320  case dwarf_wR11:
321  reg_info.name = "wR11";
322  break;
323  case dwarf_wR12:
324  reg_info.name = "wR12";
325  break;
326  case dwarf_wR13:
327  reg_info.name = "wR13";
328  break;
329  case dwarf_wR14:
330  reg_info.name = "wR14";
331  break;
332  case dwarf_wR15:
333  reg_info.name = "wR15";
334  break;
335 
336  case dwarf_spsr:
337  reg_info.name = "spsr";
338  break;
339  case dwarf_spsr_fiq:
340  reg_info.name = "spsr_fiq";
341  break;
342  case dwarf_spsr_irq:
343  reg_info.name = "spsr_irq";
344  break;
345  case dwarf_spsr_abt:
346  reg_info.name = "spsr_abt";
347  break;
348  case dwarf_spsr_und:
349  reg_info.name = "spsr_und";
350  break;
351  case dwarf_spsr_svc:
352  reg_info.name = "spsr_svc";
353  break;
354 
355  case dwarf_r8_usr:
356  reg_info.name = "r8_usr";
357  break;
358  case dwarf_r9_usr:
359  reg_info.name = "r9_usr";
360  break;
361  case dwarf_r10_usr:
362  reg_info.name = "r10_usr";
363  break;
364  case dwarf_r11_usr:
365  reg_info.name = "r11_usr";
366  break;
367  case dwarf_r12_usr:
368  reg_info.name = "r12_usr";
369  break;
370  case dwarf_r13_usr:
371  reg_info.name = "r13_usr";
372  break;
373  case dwarf_r14_usr:
374  reg_info.name = "r14_usr";
375  break;
376  case dwarf_r8_fiq:
377  reg_info.name = "r8_fiq";
378  break;
379  case dwarf_r9_fiq:
380  reg_info.name = "r9_fiq";
381  break;
382  case dwarf_r10_fiq:
383  reg_info.name = "r10_fiq";
384  break;
385  case dwarf_r11_fiq:
386  reg_info.name = "r11_fiq";
387  break;
388  case dwarf_r12_fiq:
389  reg_info.name = "r12_fiq";
390  break;
391  case dwarf_r13_fiq:
392  reg_info.name = "r13_fiq";
393  break;
394  case dwarf_r14_fiq:
395  reg_info.name = "r14_fiq";
396  break;
397  case dwarf_r13_irq:
398  reg_info.name = "r13_irq";
399  break;
400  case dwarf_r14_irq:
401  reg_info.name = "r14_irq";
402  break;
403  case dwarf_r13_abt:
404  reg_info.name = "r13_abt";
405  break;
406  case dwarf_r14_abt:
407  reg_info.name = "r14_abt";
408  break;
409  case dwarf_r13_und:
410  reg_info.name = "r13_und";
411  break;
412  case dwarf_r14_und:
413  reg_info.name = "r14_und";
414  break;
415  case dwarf_r13_svc:
416  reg_info.name = "r13_svc";
417  break;
418  case dwarf_r14_svc:
419  reg_info.name = "r14_svc";
420  break;
421 
422  // Intel wireless MMX control register in co-processor 0 - 7
423  case dwarf_wC0:
424  reg_info.name = "wC0";
425  break;
426  case dwarf_wC1:
427  reg_info.name = "wC1";
428  break;
429  case dwarf_wC2:
430  reg_info.name = "wC2";
431  break;
432  case dwarf_wC3:
433  reg_info.name = "wC3";
434  break;
435  case dwarf_wC4:
436  reg_info.name = "wC4";
437  break;
438  case dwarf_wC5:
439  reg_info.name = "wC5";
440  break;
441  case dwarf_wC6:
442  reg_info.name = "wC6";
443  break;
444  case dwarf_wC7:
445  reg_info.name = "wC7";
446  break;
447 
448  // VFP-v3/Neon
449  case dwarf_d0:
450  reg_info.name = "d0";
451  break;
452  case dwarf_d1:
453  reg_info.name = "d1";
454  break;
455  case dwarf_d2:
456  reg_info.name = "d2";
457  break;
458  case dwarf_d3:
459  reg_info.name = "d3";
460  break;
461  case dwarf_d4:
462  reg_info.name = "d4";
463  break;
464  case dwarf_d5:
465  reg_info.name = "d5";
466  break;
467  case dwarf_d6:
468  reg_info.name = "d6";
469  break;
470  case dwarf_d7:
471  reg_info.name = "d7";
472  break;
473  case dwarf_d8:
474  reg_info.name = "d8";
475  break;
476  case dwarf_d9:
477  reg_info.name = "d9";
478  break;
479  case dwarf_d10:
480  reg_info.name = "d10";
481  break;
482  case dwarf_d11:
483  reg_info.name = "d11";
484  break;
485  case dwarf_d12:
486  reg_info.name = "d12";
487  break;
488  case dwarf_d13:
489  reg_info.name = "d13";
490  break;
491  case dwarf_d14:
492  reg_info.name = "d14";
493  break;
494  case dwarf_d15:
495  reg_info.name = "d15";
496  break;
497  case dwarf_d16:
498  reg_info.name = "d16";
499  break;
500  case dwarf_d17:
501  reg_info.name = "d17";
502  break;
503  case dwarf_d18:
504  reg_info.name = "d18";
505  break;
506  case dwarf_d19:
507  reg_info.name = "d19";
508  break;
509  case dwarf_d20:
510  reg_info.name = "d20";
511  break;
512  case dwarf_d21:
513  reg_info.name = "d21";
514  break;
515  case dwarf_d22:
516  reg_info.name = "d22";
517  break;
518  case dwarf_d23:
519  reg_info.name = "d23";
520  break;
521  case dwarf_d24:
522  reg_info.name = "d24";
523  break;
524  case dwarf_d25:
525  reg_info.name = "d25";
526  break;
527  case dwarf_d26:
528  reg_info.name = "d26";
529  break;
530  case dwarf_d27:
531  reg_info.name = "d27";
532  break;
533  case dwarf_d28:
534  reg_info.name = "d28";
535  break;
536  case dwarf_d29:
537  reg_info.name = "d29";
538  break;
539  case dwarf_d30:
540  reg_info.name = "d30";
541  break;
542  case dwarf_d31:
543  reg_info.name = "d31";
544  break;
545 
546  // NEON 128-bit vector registers (overlays the d registers)
547  case dwarf_q0:
548  reg_info.name = "q0";
549  break;
550  case dwarf_q1:
551  reg_info.name = "q1";
552  break;
553  case dwarf_q2:
554  reg_info.name = "q2";
555  break;
556  case dwarf_q3:
557  reg_info.name = "q3";
558  break;
559  case dwarf_q4:
560  reg_info.name = "q4";
561  break;
562  case dwarf_q5:
563  reg_info.name = "q5";
564  break;
565  case dwarf_q6:
566  reg_info.name = "q6";
567  break;
568  case dwarf_q7:
569  reg_info.name = "q7";
570  break;
571  case dwarf_q8:
572  reg_info.name = "q8";
573  break;
574  case dwarf_q9:
575  reg_info.name = "q9";
576  break;
577  case dwarf_q10:
578  reg_info.name = "q10";
579  break;
580  case dwarf_q11:
581  reg_info.name = "q11";
582  break;
583  case dwarf_q12:
584  reg_info.name = "q12";
585  break;
586  case dwarf_q13:
587  reg_info.name = "q13";
588  break;
589  case dwarf_q14:
590  reg_info.name = "q14";
591  break;
592  case dwarf_q15:
593  reg_info.name = "q15";
594  break;
595 
596  default:
597  return false;
598  }
599  return true;
600 }
601 
602 // A8.6.50
603 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
604 static uint32_t CountITSize(uint32_t ITMask) {
605  // First count the trailing zeros of the IT mask.
606  uint32_t TZ = llvm::countTrailingZeros(ITMask);
607  if (TZ > 3) {
608  return 0;
609  }
610  return (4 - TZ);
611 }
612 
613 // Init ITState. Note that at least one bit is always 1 in mask.
614 bool ITSession::InitIT(uint32_t bits7_0) {
615  ITCounter = CountITSize(Bits32(bits7_0, 3, 0));
616  if (ITCounter == 0)
617  return false;
618 
619  // A8.6.50 IT
620  unsigned short FirstCond = Bits32(bits7_0, 7, 4);
621  if (FirstCond == 0xF) {
622  return false;
623  }
624  if (FirstCond == 0xE && ITCounter != 1) {
625  return false;
626  }
627 
628  ITState = bits7_0;
629  return true;
630 }
631 
632 // Update ITState if necessary.
633 void ITSession::ITAdvance() {
634  // assert(ITCounter);
635  --ITCounter;
636  if (ITCounter == 0)
637  ITState = 0;
638  else {
639  unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1;
640  SetBits32(ITState, 4, 0, NewITState4_0);
641  }
642 }
643 
644 // Return true if we're inside an IT Block.
645 bool ITSession::InITBlock() { return ITCounter != 0; }
646 
647 // Return true if we're the last instruction inside an IT Block.
648 bool ITSession::LastInITBlock() { return ITCounter == 1; }
649 
650 // Get condition bits for the current thumb instruction.
651 uint32_t ITSession::GetCond() {
652  if (InITBlock())
653  return Bits32(ITState, 7, 4);
654  else
655  return COND_AL;
656 }
657 
658 // ARM constants used during decoding
659 #define REG_RD 0
660 #define LDM_REGLIST 1
661 #define SP_REG 13
662 #define LR_REG 14
663 #define PC_REG 15
664 #define PC_REGLIST_BIT 0x8000
665 
666 #define ARMv4 (1u << 0)
667 #define ARMv4T (1u << 1)
668 #define ARMv5T (1u << 2)
669 #define ARMv5TE (1u << 3)
670 #define ARMv5TEJ (1u << 4)
671 #define ARMv6 (1u << 5)
672 #define ARMv6K (1u << 6)
673 #define ARMv6T2 (1u << 7)
674 #define ARMv7 (1u << 8)
675 #define ARMv7S (1u << 9)
676 #define ARMv8 (1u << 10)
677 #define ARMvAll (0xffffffffu)
678 
679 #define ARMV4T_ABOVE \
680  (ARMv4T | ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | \
681  ARMv7S | ARMv8)
682 #define ARMV5_ABOVE \
683  (ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | \
684  ARMv8)
685 #define ARMV5TE_ABOVE \
686  (ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
687 #define ARMV5J_ABOVE \
688  (ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
689 #define ARMV6_ABOVE (ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
690 #define ARMV6T2_ABOVE (ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
691 #define ARMV7_ABOVE (ARMv7 | ARMv7S | ARMv8)
692 
693 #define No_VFP 0
694 #define VFPv1 (1u << 1)
695 #define VFPv2 (1u << 2)
696 #define VFPv3 (1u << 3)
697 #define AdvancedSIMD (1u << 4)
698 
699 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
700 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
701 #define VFPv2v3 (VFPv2 | VFPv3)
702 
703 //
704 // EmulateInstructionARM implementation
705 //
706 
707 void EmulateInstructionARM::Initialize() {
708  PluginManager::RegisterPlugin(GetPluginNameStatic(),
709  GetPluginDescriptionStatic(), CreateInstance);
710 }
711 
712 void EmulateInstructionARM::Terminate() {
713  PluginManager::UnregisterPlugin(CreateInstance);
714 }
715 
716 llvm::StringRef EmulateInstructionARM::GetPluginDescriptionStatic() {
717  return "Emulate instructions for the ARM architecture.";
718 }
719 
721 EmulateInstructionARM::CreateInstance(const ArchSpec &arch,
722  InstructionType inst_type) {
723  if (EmulateInstructionARM::SupportsEmulatingInstructionsOfTypeStatic(
724  inst_type)) {
725  if (arch.GetTriple().getArch() == llvm::Triple::arm) {
726  std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
727  new EmulateInstructionARM(arch));
728 
729  if (emulate_insn_up)
730  return emulate_insn_up.release();
731  } else if (arch.GetTriple().getArch() == llvm::Triple::thumb) {
732  std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
733  new EmulateInstructionARM(arch));
734 
735  if (emulate_insn_up)
736  return emulate_insn_up.release();
737  }
738  }
739 
740  return nullptr;
741 }
742 
743 bool EmulateInstructionARM::SetTargetTriple(const ArchSpec &arch) {
744  if (arch.GetTriple().getArch() == llvm::Triple::arm)
745  return true;
746  else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
747  return true;
748 
749  return false;
750 }
751 
752 // Write "bits (32) UNKNOWN" to memory address "address". Helper function for
753 // many ARM instructions.
754 bool EmulateInstructionARM::WriteBits32UnknownToMemory(addr_t address) {
756  context.type = EmulateInstruction::eContextWriteMemoryRandomBits;
757  context.SetNoArgs();
758 
759  uint32_t random_data = rand();
760  const uint32_t addr_byte_size = GetAddressByteSize();
761 
762  return MemAWrite(context, address, random_data, addr_byte_size);
763 }
764 
765 // Write "bits (32) UNKNOWN" to register n. Helper function for many ARM
766 // instructions.
767 bool EmulateInstructionARM::WriteBits32Unknown(int n) {
769  context.type = EmulateInstruction::eContextWriteRegisterRandomBits;
770  context.SetNoArgs();
771 
772  bool success;
773  uint32_t data =
774  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
775 
776  if (!success)
777  return false;
778 
779  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, data))
780  return false;
781 
782  return true;
783 }
784 
785 bool EmulateInstructionARM::GetRegisterInfo(lldb::RegisterKind reg_kind,
786  uint32_t reg_num,
787  RegisterInfo &reg_info) {
788  if (reg_kind == eRegisterKindGeneric) {
789  switch (reg_num) {
791  reg_kind = eRegisterKindDWARF;
792  reg_num = dwarf_pc;
793  break;
795  reg_kind = eRegisterKindDWARF;
796  reg_num = dwarf_sp;
797  break;
799  reg_kind = eRegisterKindDWARF;
800  reg_num = dwarf_r7;
801  break;
803  reg_kind = eRegisterKindDWARF;
804  reg_num = dwarf_lr;
805  break;
807  reg_kind = eRegisterKindDWARF;
808  reg_num = dwarf_cpsr;
809  break;
810  default:
811  return false;
812  }
813  }
814 
815  if (reg_kind == eRegisterKindDWARF)
816  return GetARMDWARFRegisterInfo(reg_num, reg_info);
817  return false;
818 }
819 
820 uint32_t EmulateInstructionARM::GetFramePointerRegisterNumber() const {
821  if (m_arch.GetTriple().isAndroid())
822  return LLDB_INVALID_REGNUM; // Don't use frame pointer on android
823  bool is_apple = false;
824  if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple)
825  is_apple = true;
826  switch (m_arch.GetTriple().getOS()) {
827  case llvm::Triple::Darwin:
828  case llvm::Triple::MacOSX:
829  case llvm::Triple::IOS:
830  case llvm::Triple::TvOS:
831  case llvm::Triple::WatchOS:
832  // NEED_BRIDGEOS_TRIPLE case llvm::Triple::BridgeOS:
833  is_apple = true;
834  break;
835  default:
836  break;
837  }
838 
839  /* On Apple iOS et al, the frame pointer register is always r7.
840  * Typically on other ARM systems, thumb code uses r7; arm code uses r11.
841  * Windows on ARM, which is in thumb mode, uses r11 though.
842  */
843 
844  uint32_t fp_regnum = 11;
845 
846  if (is_apple)
847  fp_regnum = 7;
848 
849  if (m_opcode_mode == eModeThumb && !m_arch.GetTriple().isOSWindows())
850  fp_regnum = 7;
851 
852  return fp_regnum;
853 }
854 
855 uint32_t EmulateInstructionARM::GetFramePointerDWARFRegisterNumber() const {
856  bool is_apple = false;
857  if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple)
858  is_apple = true;
859  switch (m_arch.GetTriple().getOS()) {
860  case llvm::Triple::Darwin:
861  case llvm::Triple::MacOSX:
862  case llvm::Triple::IOS:
863  is_apple = true;
864  break;
865  default:
866  break;
867  }
868 
869  /* On Apple iOS et al, the frame pointer register is always r7.
870  * Typically on other ARM systems, thumb code uses r7; arm code uses r11.
871  * Windows on ARM, which is in thumb mode, uses r11 though.
872  */
873 
874  uint32_t fp_regnum = dwarf_r11;
875 
876  if (is_apple)
877  fp_regnum = dwarf_r7;
878 
879  if (m_opcode_mode == eModeThumb && !m_arch.GetTriple().isOSWindows())
880  fp_regnum = dwarf_r7;
881 
882  return fp_regnum;
883 }
884 
885 // Push Multiple Registers stores multiple registers to the stack, storing to
886 // consecutive memory locations ending just below the address in SP, and
887 // updates
888 // SP to point to the start of the stored data.
889 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode,
890  const ARMEncoding encoding) {
891 #if 0
892  // ARM pseudo code...
893  if (ConditionPassed())
894  {
895  EncodingSpecificOperations();
896  NullCheckIfThumbEE(13);
897  address = SP - 4*BitCount(registers);
898 
899  for (i = 0 to 14)
900  {
901  if (registers<i> == '1')
902  {
903  if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1
904  MemA[address,4] = bits(32) UNKNOWN;
905  else
906  MemA[address,4] = R[i];
907  address = address + 4;
908  }
909  }
910 
911  if (registers<15> == '1') // Only possible for encoding A1 or A2
912  MemA[address,4] = PCStoreValue();
913 
914  SP = SP - 4*BitCount(registers);
915  }
916 #endif
917 
918  bool success = false;
919  if (ConditionPassed(opcode)) {
920  const uint32_t addr_byte_size = GetAddressByteSize();
921  const addr_t sp = ReadCoreReg(SP_REG, &success);
922  if (!success)
923  return false;
924  uint32_t registers = 0;
925  uint32_t Rt; // the source register
926  switch (encoding) {
927  case eEncodingT1:
928  registers = Bits32(opcode, 7, 0);
929  // The M bit represents LR.
930  if (Bit32(opcode, 8))
931  registers |= (1u << 14);
932  // if BitCount(registers) < 1 then UNPREDICTABLE;
933  if (BitCount(registers) < 1)
934  return false;
935  break;
936  case eEncodingT2:
937  // Ignore bits 15 & 13.
938  registers = Bits32(opcode, 15, 0) & ~0xa000;
939  // if BitCount(registers) < 2 then UNPREDICTABLE;
940  if (BitCount(registers) < 2)
941  return false;
942  break;
943  case eEncodingT3:
944  Rt = Bits32(opcode, 15, 12);
945  // if BadReg(t) then UNPREDICTABLE;
946  if (BadReg(Rt))
947  return false;
948  registers = (1u << Rt);
949  break;
950  case eEncodingA1:
951  registers = Bits32(opcode, 15, 0);
952  // Instead of return false, let's handle the following case as well,
953  // which amounts to pushing one reg onto the full descending stacks.
954  // if BitCount(register_list) < 2 then SEE STMDB / STMFD;
955  break;
956  case eEncodingA2:
957  Rt = Bits32(opcode, 15, 12);
958  // if t == 13 then UNPREDICTABLE;
959  if (Rt == dwarf_sp)
960  return false;
961  registers = (1u << Rt);
962  break;
963  default:
964  return false;
965  }
966  addr_t sp_offset = addr_byte_size * BitCount(registers);
967  addr_t addr = sp - sp_offset;
968  uint32_t i;
969 
971  context.type = EmulateInstruction::eContextPushRegisterOnStack;
972  RegisterInfo reg_info;
973  RegisterInfo sp_reg;
974  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
975  for (i = 0; i < 15; ++i) {
976  if (BitIsSet(registers, i)) {
977  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, reg_info);
978  context.SetRegisterToRegisterPlusOffset(reg_info, sp_reg, addr - sp);
979  uint32_t reg_value = ReadCoreReg(i, &success);
980  if (!success)
981  return false;
982  if (!MemAWrite(context, addr, reg_value, addr_byte_size))
983  return false;
984  addr += addr_byte_size;
985  }
986  }
987 
988  if (BitIsSet(registers, 15)) {
989  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, reg_info);
990  context.SetRegisterToRegisterPlusOffset(reg_info, sp_reg, addr - sp);
991  const uint32_t pc = ReadCoreReg(PC_REG, &success);
992  if (!success)
993  return false;
994  if (!MemAWrite(context, addr, pc, addr_byte_size))
995  return false;
996  }
997 
998  context.type = EmulateInstruction::eContextAdjustStackPointer;
999  context.SetImmediateSigned(-sp_offset);
1000 
1001  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
1002  LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
1003  return false;
1004  }
1005  return true;
1006 }
1007 
1008 // Pop Multiple Registers loads multiple registers from the stack, loading from
1009 // consecutive memory locations staring at the address in SP, and updates
1010 // SP to point just above the loaded data.
1011 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode,
1012  const ARMEncoding encoding) {
1013 #if 0
1014  // ARM pseudo code...
1015  if (ConditionPassed())
1016  {
1017  EncodingSpecificOperations(); NullCheckIfThumbEE(13);
1018  address = SP;
1019  for i = 0 to 14
1020  if registers<i> == '1' then
1021  R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
1022  if registers<15> == '1' then
1023  if UnalignedAllowed then
1024  LoadWritePC(MemU[address,4]);
1025  else
1026  LoadWritePC(MemA[address,4]);
1027  if registers<13> == '0' then SP = SP + 4*BitCount(registers);
1028  if registers<13> == '1' then SP = bits(32) UNKNOWN;
1029  }
1030 #endif
1031 
1032  bool success = false;
1033 
1034  if (ConditionPassed(opcode)) {
1035  const uint32_t addr_byte_size = GetAddressByteSize();
1036  const addr_t sp = ReadCoreReg(SP_REG, &success);
1037  if (!success)
1038  return false;
1039  uint32_t registers = 0;
1040  uint32_t Rt; // the destination register
1041  switch (encoding) {
1042  case eEncodingT1:
1043  registers = Bits32(opcode, 7, 0);
1044  // The P bit represents PC.
1045  if (Bit32(opcode, 8))
1046  registers |= (1u << 15);
1047  // if BitCount(registers) < 1 then UNPREDICTABLE;
1048  if (BitCount(registers) < 1)
1049  return false;
1050  break;
1051  case eEncodingT2:
1052  // Ignore bit 13.
1053  registers = Bits32(opcode, 15, 0) & ~0x2000;
1054  // if BitCount(registers) < 2 || (P == '1' && M == '1') then
1055  // UNPREDICTABLE;
1056  if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14)))
1057  return false;
1058  // if registers<15> == '1' && InITBlock() && !LastInITBlock() then
1059  // UNPREDICTABLE;
1060  if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
1061  return false;
1062  break;
1063  case eEncodingT3:
1064  Rt = Bits32(opcode, 15, 12);
1065  // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then
1066  // UNPREDICTABLE;
1067  if (Rt == 13)
1068  return false;
1069  if (Rt == 15 && InITBlock() && !LastInITBlock())
1070  return false;
1071  registers = (1u << Rt);
1072  break;
1073  case eEncodingA1:
1074  registers = Bits32(opcode, 15, 0);
1075  // Instead of return false, let's handle the following case as well,
1076  // which amounts to popping one reg from the full descending stacks.
1077  // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD;
1078 
1079  // if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE;
1080  if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7)
1081  return false;
1082  break;
1083  case eEncodingA2:
1084  Rt = Bits32(opcode, 15, 12);
1085  // if t == 13 then UNPREDICTABLE;
1086  if (Rt == dwarf_sp)
1087  return false;
1088  registers = (1u << Rt);
1089  break;
1090  default:
1091  return false;
1092  }
1093  addr_t sp_offset = addr_byte_size * BitCount(registers);
1094  addr_t addr = sp;
1095  uint32_t i, data;
1096 
1098  context.type = EmulateInstruction::eContextPopRegisterOffStack;
1099 
1100  RegisterInfo sp_reg;
1101  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1102 
1103  for (i = 0; i < 15; ++i) {
1104  if (BitIsSet(registers, i)) {
1105  context.SetAddress(addr);
1106  data = MemARead(context, addr, 4, 0, &success);
1107  if (!success)
1108  return false;
1109  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
1110  data))
1111  return false;
1112  addr += addr_byte_size;
1113  }
1114  }
1115 
1116  if (BitIsSet(registers, 15)) {
1117  context.SetRegisterPlusOffset(sp_reg, addr - sp);
1118  data = MemARead(context, addr, 4, 0, &success);
1119  if (!success)
1120  return false;
1121  // In ARMv5T and above, this is an interworking branch.
1122  if (!LoadWritePC(context, data))
1123  return false;
1124  // addr += addr_byte_size;
1125  }
1126 
1127  context.type = EmulateInstruction::eContextAdjustStackPointer;
1128  context.SetImmediateSigned(sp_offset);
1129 
1130  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
1131  LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
1132  return false;
1133  }
1134  return true;
1135 }
1136 
1137 // Set r7 or ip to point to saved value residing within the stack.
1138 // ADD (SP plus immediate)
1139 bool EmulateInstructionARM::EmulateADDRdSPImm(const uint32_t opcode,
1140  const ARMEncoding encoding) {
1141 #if 0
1142  // ARM pseudo code...
1143  if (ConditionPassed())
1144  {
1145  EncodingSpecificOperations();
1146  (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
1147  if d == 15 then
1148  ALUWritePC(result); // setflags is always FALSE here
1149  else
1150  R[d] = result;
1151  if setflags then
1152  APSR.N = result<31>;
1153  APSR.Z = IsZeroBit(result);
1154  APSR.C = carry;
1155  APSR.V = overflow;
1156  }
1157 #endif
1158 
1159  bool success = false;
1160 
1161  if (ConditionPassed(opcode)) {
1162  const addr_t sp = ReadCoreReg(SP_REG, &success);
1163  if (!success)
1164  return false;
1165  uint32_t Rd; // the destination register
1166  uint32_t imm32;
1167  switch (encoding) {
1168  case eEncodingT1:
1169  Rd = 7;
1170  imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
1171  break;
1172  case eEncodingA1:
1173  Rd = Bits32(opcode, 15, 12);
1174  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1175  break;
1176  default:
1177  return false;
1178  }
1179  addr_t sp_offset = imm32;
1180  addr_t addr = sp + sp_offset; // a pointer to the stack area
1181 
1183  if (Rd == GetFramePointerRegisterNumber())
1184  context.type = eContextSetFramePointer;
1185  else
1186  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1187  RegisterInfo sp_reg;
1188  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1189  context.SetRegisterPlusOffset(sp_reg, sp_offset);
1190 
1191  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd,
1192  addr))
1193  return false;
1194  }
1195  return true;
1196 }
1197 
1198 // Set r7 or ip to the current stack pointer.
1199 // MOV (register)
1200 bool EmulateInstructionARM::EmulateMOVRdSP(const uint32_t opcode,
1201  const ARMEncoding encoding) {
1202 #if 0
1203  // ARM pseudo code...
1204  if (ConditionPassed())
1205  {
1206  EncodingSpecificOperations();
1207  result = R[m];
1208  if d == 15 then
1209  ALUWritePC(result); // setflags is always FALSE here
1210  else
1211  R[d] = result;
1212  if setflags then
1213  APSR.N = result<31>;
1214  APSR.Z = IsZeroBit(result);
1215  // APSR.C unchanged
1216  // APSR.V unchanged
1217  }
1218 #endif
1219 
1220  bool success = false;
1221 
1222  if (ConditionPassed(opcode)) {
1223  const addr_t sp = ReadCoreReg(SP_REG, &success);
1224  if (!success)
1225  return false;
1226  uint32_t Rd; // the destination register
1227  switch (encoding) {
1228  case eEncodingT1:
1229  Rd = 7;
1230  break;
1231  case eEncodingA1:
1232  Rd = 12;
1233  break;
1234  default:
1235  return false;
1236  }
1237 
1239  if (Rd == GetFramePointerRegisterNumber())
1240  context.type = EmulateInstruction::eContextSetFramePointer;
1241  else
1242  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1243  RegisterInfo sp_reg;
1244  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1245  context.SetRegisterPlusOffset(sp_reg, 0);
1246 
1247  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
1248  return false;
1249  }
1250  return true;
1251 }
1252 
1253 // Move from high register (r8-r15) to low register (r0-r7).
1254 // MOV (register)
1255 bool EmulateInstructionARM::EmulateMOVLowHigh(const uint32_t opcode,
1256  const ARMEncoding encoding) {
1257  return EmulateMOVRdRm(opcode, encoding);
1258 }
1259 
1260 // Move from register to register.
1261 // MOV (register)
1262 bool EmulateInstructionARM::EmulateMOVRdRm(const uint32_t opcode,
1263  const ARMEncoding encoding) {
1264 #if 0
1265  // ARM pseudo code...
1266  if (ConditionPassed())
1267  {
1268  EncodingSpecificOperations();
1269  result = R[m];
1270  if d == 15 then
1271  ALUWritePC(result); // setflags is always FALSE here
1272  else
1273  R[d] = result;
1274  if setflags then
1275  APSR.N = result<31>;
1276  APSR.Z = IsZeroBit(result);
1277  // APSR.C unchanged
1278  // APSR.V unchanged
1279  }
1280 #endif
1281 
1282  bool success = false;
1283 
1284  if (ConditionPassed(opcode)) {
1285  uint32_t Rm; // the source register
1286  uint32_t Rd; // the destination register
1287  bool setflags;
1288  switch (encoding) {
1289  case eEncodingT1:
1290  Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
1291  Rm = Bits32(opcode, 6, 3);
1292  setflags = false;
1293  if (Rd == 15 && InITBlock() && !LastInITBlock())
1294  return false;
1295  break;
1296  case eEncodingT2:
1297  Rd = Bits32(opcode, 2, 0);
1298  Rm = Bits32(opcode, 5, 3);
1299  setflags = true;
1300  if (InITBlock())
1301  return false;
1302  break;
1303  case eEncodingT3:
1304  Rd = Bits32(opcode, 11, 8);
1305  Rm = Bits32(opcode, 3, 0);
1306  setflags = BitIsSet(opcode, 20);
1307  // if setflags && (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
1308  if (setflags && (BadReg(Rd) || BadReg(Rm)))
1309  return false;
1310  // if !setflags && (d == 15 || m == 15 || (d == 13 && m == 13)) then
1311  // UNPREDICTABLE;
1312  if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
1313  return false;
1314  break;
1315  case eEncodingA1:
1316  Rd = Bits32(opcode, 15, 12);
1317  Rm = Bits32(opcode, 3, 0);
1318  setflags = BitIsSet(opcode, 20);
1319 
1320  // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1321  // instructions;
1322  if (Rd == 15 && setflags)
1323  return EmulateSUBSPcLrEtc(opcode, encoding);
1324  break;
1325  default:
1326  return false;
1327  }
1328  uint32_t result = ReadCoreReg(Rm, &success);
1329  if (!success)
1330  return false;
1331 
1332  // The context specifies that Rm is to be moved into Rd.
1334  if (Rd == 13)
1335  context.type = EmulateInstruction::eContextAdjustStackPointer;
1336  else if (Rd == GetFramePointerRegisterNumber() && Rm == 13)
1337  context.type = EmulateInstruction::eContextSetFramePointer;
1338  else
1339  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1340  RegisterInfo dwarf_reg;
1341  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1342  context.SetRegisterPlusOffset(dwarf_reg, 0);
1343 
1344  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
1345  return false;
1346  }
1347  return true;
1348 }
1349 
1350 // Move (immediate) writes an immediate value to the destination register. It
1351 // can optionally update the condition flags based on the value.
1352 // MOV (immediate)
1353 bool EmulateInstructionARM::EmulateMOVRdImm(const uint32_t opcode,
1354  const ARMEncoding encoding) {
1355 #if 0
1356  // ARM pseudo code...
1357  if (ConditionPassed())
1358  {
1359  EncodingSpecificOperations();
1360  result = imm32;
1361  if d == 15 then // Can only occur for ARM encoding
1362  ALUWritePC(result); // setflags is always FALSE here
1363  else
1364  R[d] = result;
1365  if setflags then
1366  APSR.N = result<31>;
1367  APSR.Z = IsZeroBit(result);
1368  APSR.C = carry;
1369  // APSR.V unchanged
1370  }
1371 #endif
1372 
1373  if (ConditionPassed(opcode)) {
1374  uint32_t Rd; // the destination register
1375  uint32_t imm32; // the immediate value to be written to Rd
1376  uint32_t carry =
1377  0; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C.
1378  // for setflags == false, this value is a don't care initialized to
1379  // 0 to silence the static analyzer
1380  bool setflags;
1381  switch (encoding) {
1382  case eEncodingT1:
1383  Rd = Bits32(opcode, 10, 8);
1384  setflags = !InITBlock();
1385  imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
1386  carry = APSR_C;
1387 
1388  break;
1389 
1390  case eEncodingT2:
1391  Rd = Bits32(opcode, 11, 8);
1392  setflags = BitIsSet(opcode, 20);
1393  imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1394  if (BadReg(Rd))
1395  return false;
1396 
1397  break;
1398 
1399  case eEncodingT3: {
1400  // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8,
1401  // 32);
1402  Rd = Bits32(opcode, 11, 8);
1403  setflags = false;
1404  uint32_t imm4 = Bits32(opcode, 19, 16);
1405  uint32_t imm3 = Bits32(opcode, 14, 12);
1406  uint32_t i = Bit32(opcode, 26);
1407  uint32_t imm8 = Bits32(opcode, 7, 0);
1408  imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
1409 
1410  // if BadReg(d) then UNPREDICTABLE;
1411  if (BadReg(Rd))
1412  return false;
1413  } break;
1414 
1415  case eEncodingA1:
1416  // d = UInt(Rd); setflags = (S == '1'); (imm32, carry) =
1417  // ARMExpandImm_C(imm12, APSR.C);
1418  Rd = Bits32(opcode, 15, 12);
1419  setflags = BitIsSet(opcode, 20);
1420  imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1421 
1422  // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1423  // instructions;
1424  if ((Rd == 15) && setflags)
1425  return EmulateSUBSPcLrEtc(opcode, encoding);
1426 
1427  break;
1428 
1429  case eEncodingA2: {
1430  // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
1431  Rd = Bits32(opcode, 15, 12);
1432  setflags = false;
1433  uint32_t imm4 = Bits32(opcode, 19, 16);
1434  uint32_t imm12 = Bits32(opcode, 11, 0);
1435  imm32 = (imm4 << 12) | imm12;
1436 
1437  // if d == 15 then UNPREDICTABLE;
1438  if (Rd == 15)
1439  return false;
1440  } break;
1441 
1442  default:
1443  return false;
1444  }
1445  uint32_t result = imm32;
1446 
1447  // The context specifies that an immediate is to be moved into Rd.
1449  context.type = EmulateInstruction::eContextImmediate;
1450  context.SetNoArgs();
1451 
1452  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1453  return false;
1454  }
1455  return true;
1456 }
1457 
1458 // MUL multiplies two register values. The least significant 32 bits of the
1459 // result are written to the destination
1460 // register. These 32 bits do not depend on whether the source register values
1461 // are considered to be signed values or unsigned values.
1462 //
1463 // Optionally, it can update the condition flags based on the result. In the
1464 // Thumb instruction set, this option is limited to only a few forms of the
1465 // instruction.
1466 bool EmulateInstructionARM::EmulateMUL(const uint32_t opcode,
1467  const ARMEncoding encoding) {
1468 #if 0
1469  if ConditionPassed() then
1470  EncodingSpecificOperations();
1471  operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
1472  operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
1473  result = operand1 * operand2;
1474  R[d] = result<31:0>;
1475  if setflags then
1476  APSR.N = result<31>;
1477  APSR.Z = IsZeroBit(result);
1478  if ArchVersion() == 4 then
1479  APSR.C = bit UNKNOWN;
1480  // else APSR.C unchanged
1481  // APSR.V always unchanged
1482 #endif
1483 
1484  if (ConditionPassed(opcode)) {
1485  uint32_t d;
1486  uint32_t n;
1487  uint32_t m;
1488  bool setflags;
1489 
1490  // EncodingSpecificOperations();
1491  switch (encoding) {
1492  case eEncodingT1:
1493  // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
1494  d = Bits32(opcode, 2, 0);
1495  n = Bits32(opcode, 5, 3);
1496  m = Bits32(opcode, 2, 0);
1497  setflags = !InITBlock();
1498 
1499  // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
1500  if ((ArchVersion() < ARMv6) && (d == n))
1501  return false;
1502 
1503  break;
1504 
1505  case eEncodingT2:
1506  // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
1507  d = Bits32(opcode, 11, 8);
1508  n = Bits32(opcode, 19, 16);
1509  m = Bits32(opcode, 3, 0);
1510  setflags = false;
1511 
1512  // if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;
1513  if (BadReg(d) || BadReg(n) || BadReg(m))
1514  return false;
1515 
1516  break;
1517 
1518  case eEncodingA1:
1519  // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1520  d = Bits32(opcode, 19, 16);
1521  n = Bits32(opcode, 3, 0);
1522  m = Bits32(opcode, 11, 8);
1523  setflags = BitIsSet(opcode, 20);
1524 
1525  // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
1526  if ((d == 15) || (n == 15) || (m == 15))
1527  return false;
1528 
1529  // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
1530  if ((ArchVersion() < ARMv6) && (d == n))
1531  return false;
1532 
1533  break;
1534 
1535  default:
1536  return false;
1537  }
1538 
1539  bool success = false;
1540 
1541  // operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final
1542  // results
1543  uint64_t operand1 =
1544  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
1545  if (!success)
1546  return false;
1547 
1548  // operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final
1549  // results
1550  uint64_t operand2 =
1551  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
1552  if (!success)
1553  return false;
1554 
1555  // result = operand1 * operand2;
1556  uint64_t result = operand1 * operand2;
1557 
1558  // R[d] = result<31:0>;
1559  RegisterInfo op1_reg;
1560  RegisterInfo op2_reg;
1561  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, op1_reg);
1562  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, op2_reg);
1563 
1565  context.type = eContextArithmetic;
1566  context.SetRegisterRegisterOperands(op1_reg, op2_reg);
1567 
1568  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d,
1569  (0x0000ffff & result)))
1570  return false;
1571 
1572  // if setflags then
1573  if (setflags) {
1574  // APSR.N = result<31>;
1575  // APSR.Z = IsZeroBit(result);
1576  m_new_inst_cpsr = m_opcode_cpsr;
1577  SetBit32(m_new_inst_cpsr, CPSR_N_POS, Bit32(result, 31));
1578  SetBit32(m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
1579  if (m_new_inst_cpsr != m_opcode_cpsr) {
1580  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
1581  LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
1582  return false;
1583  }
1584 
1585  // if ArchVersion() == 4 then
1586  // APSR.C = bit UNKNOWN;
1587  }
1588  }
1589  return true;
1590 }
1591 
1592 // Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to
1593 // the destination register. It can optionally update the condition flags based
1594 // on the value.
1595 bool EmulateInstructionARM::EmulateMVNImm(const uint32_t opcode,
1596  const ARMEncoding encoding) {
1597 #if 0
1598  // ARM pseudo code...
1599  if (ConditionPassed())
1600  {
1601  EncodingSpecificOperations();
1602  result = NOT(imm32);
1603  if d == 15 then // Can only occur for ARM encoding
1604  ALUWritePC(result); // setflags is always FALSE here
1605  else
1606  R[d] = result;
1607  if setflags then
1608  APSR.N = result<31>;
1609  APSR.Z = IsZeroBit(result);
1610  APSR.C = carry;
1611  // APSR.V unchanged
1612  }
1613 #endif
1614 
1615  if (ConditionPassed(opcode)) {
1616  uint32_t Rd; // the destination register
1617  uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C
1618  uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C
1619  bool setflags;
1620  switch (encoding) {
1621  case eEncodingT1:
1622  Rd = Bits32(opcode, 11, 8);
1623  setflags = BitIsSet(opcode, 20);
1624  imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1625  break;
1626  case eEncodingA1:
1627  Rd = Bits32(opcode, 15, 12);
1628  setflags = BitIsSet(opcode, 20);
1629  imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1630 
1631  // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1632  // instructions;
1633  if (Rd == 15 && setflags)
1634  return EmulateSUBSPcLrEtc(opcode, encoding);
1635  break;
1636  default:
1637  return false;
1638  }
1639  uint32_t result = ~imm32;
1640 
1641  // The context specifies that an immediate is to be moved into Rd.
1643  context.type = EmulateInstruction::eContextImmediate;
1644  context.SetNoArgs();
1645 
1646  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1647  return false;
1648  }
1649  return true;
1650 }
1651 
1652 // Bitwise NOT (register) writes the bitwise inverse of a register value to the
1653 // destination register. It can optionally update the condition flags based on
1654 // the result.
1655 bool EmulateInstructionARM::EmulateMVNReg(const uint32_t opcode,
1656  const ARMEncoding encoding) {
1657 #if 0
1658  // ARM pseudo code...
1659  if (ConditionPassed())
1660  {
1661  EncodingSpecificOperations();
1662  (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
1663  result = NOT(shifted);
1664  if d == 15 then // Can only occur for ARM encoding
1665  ALUWritePC(result); // setflags is always FALSE here
1666  else
1667  R[d] = result;
1668  if setflags then
1669  APSR.N = result<31>;
1670  APSR.Z = IsZeroBit(result);
1671  APSR.C = carry;
1672  // APSR.V unchanged
1673  }
1674 #endif
1675 
1676  if (ConditionPassed(opcode)) {
1677  uint32_t Rm; // the source register
1678  uint32_t Rd; // the destination register
1679  ARM_ShifterType shift_t;
1680  uint32_t shift_n; // the shift applied to the value read from Rm
1681  bool setflags;
1682  uint32_t carry; // the carry bit after the shift operation
1683  switch (encoding) {
1684  case eEncodingT1:
1685  Rd = Bits32(opcode, 2, 0);
1686  Rm = Bits32(opcode, 5, 3);
1687  setflags = !InITBlock();
1688  shift_t = SRType_LSL;
1689  shift_n = 0;
1690  if (InITBlock())
1691  return false;
1692  break;
1693  case eEncodingT2:
1694  Rd = Bits32(opcode, 11, 8);
1695  Rm = Bits32(opcode, 3, 0);
1696  setflags = BitIsSet(opcode, 20);
1697  shift_n = DecodeImmShiftThumb(opcode, shift_t);
1698  // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
1699  if (BadReg(Rd) || BadReg(Rm))
1700  return false;
1701  break;
1702  case eEncodingA1:
1703  Rd = Bits32(opcode, 15, 12);
1704  Rm = Bits32(opcode, 3, 0);
1705  setflags = BitIsSet(opcode, 20);
1706  shift_n = DecodeImmShiftARM(opcode, shift_t);
1707  break;
1708  default:
1709  return false;
1710  }
1711  bool success = false;
1712  uint32_t value = ReadCoreReg(Rm, &success);
1713  if (!success)
1714  return false;
1715 
1716  uint32_t shifted =
1717  Shift_C(value, shift_t, shift_n, APSR_C, carry, &success);
1718  if (!success)
1719  return false;
1720  uint32_t result = ~shifted;
1721 
1722  // The context specifies that an immediate is to be moved into Rd.
1724  context.type = EmulateInstruction::eContextImmediate;
1725  context.SetNoArgs();
1726 
1727  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1728  return false;
1729  }
1730  return true;
1731 }
1732 
1733 // PC relative immediate load into register, possibly followed by ADD (SP plus
1734 // register).
1735 // LDR (literal)
1736 bool EmulateInstructionARM::EmulateLDRRtPCRelative(const uint32_t opcode,
1737  const ARMEncoding encoding) {
1738 #if 0
1739  // ARM pseudo code...
1740  if (ConditionPassed())
1741  {
1742  EncodingSpecificOperations(); NullCheckIfThumbEE(15);
1743  base = Align(PC,4);
1744  address = if add then (base + imm32) else (base - imm32);
1745  data = MemU[address,4];
1746  if t == 15 then
1747  if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
1748  elsif UnalignedSupport() || address<1:0> = '00' then
1749  R[t] = data;
1750  else // Can only apply before ARMv7
1751  if CurrentInstrSet() == InstrSet_ARM then
1752  R[t] = ROR(data, 8*UInt(address<1:0>));
1753  else
1754  R[t] = bits(32) UNKNOWN;
1755  }
1756 #endif
1757 
1758  if (ConditionPassed(opcode)) {
1759  bool success = false;
1760  const uint32_t pc = ReadCoreReg(PC_REG, &success);
1761  if (!success)
1762  return false;
1763 
1764  // PC relative immediate load context
1766  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1767  RegisterInfo pc_reg;
1768  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
1769  context.SetRegisterPlusOffset(pc_reg, 0);
1770 
1771  uint32_t Rt; // the destination register
1772  uint32_t imm32; // immediate offset from the PC
1773  bool add; // +imm32 or -imm32?
1774  addr_t base; // the base address
1775  addr_t address; // the PC relative address
1776  uint32_t data; // the literal data value from the PC relative load
1777  switch (encoding) {
1778  case eEncodingT1:
1779  Rt = Bits32(opcode, 10, 8);
1780  imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
1781  add = true;
1782  break;
1783  case eEncodingT2:
1784  Rt = Bits32(opcode, 15, 12);
1785  imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
1786  add = BitIsSet(opcode, 23);
1787  if (Rt == 15 && InITBlock() && !LastInITBlock())
1788  return false;
1789  break;
1790  default:
1791  return false;
1792  }
1793 
1794  base = Align(pc, 4);
1795  if (add)
1796  address = base + imm32;
1797  else
1798  address = base - imm32;
1799 
1800  context.SetRegisterPlusOffset(pc_reg, address - base);
1801  data = MemURead(context, address, 4, 0, &success);
1802  if (!success)
1803  return false;
1804 
1805  if (Rt == 15) {
1806  if (Bits32(address, 1, 0) == 0) {
1807  // In ARMv5T and above, this is an interworking branch.
1808  if (!LoadWritePC(context, data))
1809  return false;
1810  } else
1811  return false;
1812  } else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) {
1813  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rt,
1814  data))
1815  return false;
1816  } else // We don't handle ARM for now.
1817  return false;
1818  }
1819  return true;
1820 }
1821 
1822 // An add operation to adjust the SP.
1823 // ADD (SP plus immediate)
1824 bool EmulateInstructionARM::EmulateADDSPImm(const uint32_t opcode,
1825  const ARMEncoding encoding) {
1826 #if 0
1827  // ARM pseudo code...
1828  if (ConditionPassed())
1829  {
1830  EncodingSpecificOperations();
1831  (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
1832  if d == 15 then // Can only occur for ARM encoding
1833  ALUWritePC(result); // setflags is always FALSE here
1834  else
1835  R[d] = result;
1836  if setflags then
1837  APSR.N = result<31>;
1838  APSR.Z = IsZeroBit(result);
1839  APSR.C = carry;
1840  APSR.V = overflow;
1841  }
1842 #endif
1843 
1844  bool success = false;
1845 
1846  if (ConditionPassed(opcode)) {
1847  const addr_t sp = ReadCoreReg(SP_REG, &success);
1848  if (!success)
1849  return false;
1850  uint32_t imm32; // the immediate operand
1851  uint32_t d;
1852  bool setflags;
1853  switch (encoding) {
1854  case eEncodingT1:
1855  // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
1856  d = Bits32(opcode, 10, 8);
1857  imm32 = (Bits32(opcode, 7, 0) << 2);
1858  setflags = false;
1859  break;
1860 
1861  case eEncodingT2:
1862  // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32);
1863  d = 13;
1864  imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1865  setflags = false;
1866  break;
1867 
1868  case eEncodingT3:
1869  // d = UInt(Rd); setflags = (S == "1"); imm32 =
1870  // ThumbExpandImm(i:imm3:imm8);
1871  d = Bits32(opcode, 11, 8);
1872  imm32 = ThumbExpandImm(opcode);
1873  setflags = Bit32(opcode, 20);
1874 
1875  // if Rd == "1111" && S == "1" then SEE CMN (immediate);
1876  if (d == 15 && setflags == 1)
1877  return false; // CMN (immediate) not yet supported
1878 
1879  // if d == 15 && S == "0" then UNPREDICTABLE;
1880  if (d == 15 && setflags == 0)
1881  return false;
1882  break;
1883 
1884  case eEncodingT4: {
1885  // if Rn == '1111' then SEE ADR;
1886  // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
1887  d = Bits32(opcode, 11, 8);
1888  setflags = false;
1889  uint32_t i = Bit32(opcode, 26);
1890  uint32_t imm3 = Bits32(opcode, 14, 12);
1891  uint32_t imm8 = Bits32(opcode, 7, 0);
1892  imm32 = (i << 11) | (imm3 << 8) | imm8;
1893 
1894  // if d == 15 then UNPREDICTABLE;
1895  if (d == 15)
1896  return false;
1897  } break;
1898 
1899  default:
1900  return false;
1901  }
1902  // (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
1903  AddWithCarryResult res = AddWithCarry(sp, imm32, 0);
1904 
1906  if (d == 13)
1907  context.type = EmulateInstruction::eContextAdjustStackPointer;
1908  else
1909  context.type = EmulateInstruction::eContextRegisterPlusOffset;
1910 
1911  RegisterInfo sp_reg;
1912  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1913  context.SetRegisterPlusOffset(sp_reg, res.result - sp);
1914 
1915  if (d == 15) {
1916  if (!ALUWritePC(context, res.result))
1917  return false;
1918  } else {
1919  // R[d] = result;
1920  // if setflags then
1921  // APSR.N = result<31>;
1922  // APSR.Z = IsZeroBit(result);
1923  // APSR.C = carry;
1924  // APSR.V = overflow;
1925  if (!WriteCoreRegOptionalFlags(context, res.result, d, setflags,
1926  res.carry_out, res.overflow))
1927  return false;
1928  }
1929  }
1930  return true;
1931 }
1932 
1933 // An add operation to adjust the SP.
1934 // ADD (SP plus register)
1935 bool EmulateInstructionARM::EmulateADDSPRm(const uint32_t opcode,
1936  const ARMEncoding encoding) {
1937 #if 0
1938  // ARM pseudo code...
1939  if (ConditionPassed())
1940  {
1941  EncodingSpecificOperations();
1942  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
1943  (result, carry, overflow) = AddWithCarry(SP, shifted, '0');
1944  if d == 15 then
1945  ALUWritePC(result); // setflags is always FALSE here
1946  else
1947  R[d] = result;
1948  if setflags then
1949  APSR.N = result<31>;
1950  APSR.Z = IsZeroBit(result);
1951  APSR.C = carry;
1952  APSR.V = overflow;
1953  }
1954 #endif
1955 
1956  bool success = false;
1957 
1958  if (ConditionPassed(opcode)) {
1959  const addr_t sp = ReadCoreReg(SP_REG, &success);
1960  if (!success)
1961  return false;
1962  uint32_t Rm; // the second operand
1963  switch (encoding) {
1964  case eEncodingT2:
1965  Rm = Bits32(opcode, 6, 3);
1966  break;
1967  default:
1968  return false;
1969  }
1970  int32_t reg_value = ReadCoreReg(Rm, &success);
1971  if (!success)
1972  return false;
1973 
1974  addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value
1975 
1977  context.type = eContextArithmetic;
1978  RegisterInfo sp_reg;
1979  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
1980 
1981  RegisterInfo other_reg;
1982  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, other_reg);
1983  context.SetRegisterRegisterOperands(sp_reg, other_reg);
1984 
1985  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
1986  LLDB_REGNUM_GENERIC_SP, addr))
1987  return false;
1988  }
1989  return true;
1990 }
1991 
1992 // Branch with Link and Exchange Instruction Sets (immediate) calls a
1993 // subroutine at a PC-relative address, and changes instruction set from ARM to
1994 // Thumb, or from Thumb to ARM.
1995 // BLX (immediate)
1996 bool EmulateInstructionARM::EmulateBLXImmediate(const uint32_t opcode,
1997  const ARMEncoding encoding) {
1998 #if 0
1999  // ARM pseudo code...
2000  if (ConditionPassed())
2001  {
2002  EncodingSpecificOperations();
2003  if CurrentInstrSet() == InstrSet_ARM then
2004  LR = PC - 4;
2005  else
2006  LR = PC<31:1> : '1';
2007  if targetInstrSet == InstrSet_ARM then
2008  targetAddress = Align(PC,4) + imm32;
2009  else
2010  targetAddress = PC + imm32;
2011  SelectInstrSet(targetInstrSet);
2012  BranchWritePC(targetAddress);
2013  }
2014 #endif
2015 
2016  bool success = true;
2017 
2018  if (ConditionPassed(opcode)) {
2020  context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2021  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2022  if (!success)
2023  return false;
2024  addr_t lr; // next instruction address
2025  addr_t target; // target address
2026  int32_t imm32; // PC-relative offset
2027  switch (encoding) {
2028  case eEncodingT1: {
2029  lr = pc | 1u; // return address
2030  uint32_t S = Bit32(opcode, 26);
2031  uint32_t imm10 = Bits32(opcode, 25, 16);
2032  uint32_t J1 = Bit32(opcode, 13);
2033  uint32_t J2 = Bit32(opcode, 11);
2034  uint32_t imm11 = Bits32(opcode, 10, 0);
2035  uint32_t I1 = !(J1 ^ S);
2036  uint32_t I2 = !(J2 ^ S);
2037  uint32_t imm25 =
2038  (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2039  imm32 = llvm::SignExtend32<25>(imm25);
2040  target = pc + imm32;
2041  SelectInstrSet(eModeThumb);
2042  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2043  if (InITBlock() && !LastInITBlock())
2044  return false;
2045  break;
2046  }
2047  case eEncodingT2: {
2048  lr = pc | 1u; // return address
2049  uint32_t S = Bit32(opcode, 26);
2050  uint32_t imm10H = Bits32(opcode, 25, 16);
2051  uint32_t J1 = Bit32(opcode, 13);
2052  uint32_t J2 = Bit32(opcode, 11);
2053  uint32_t imm10L = Bits32(opcode, 10, 1);
2054  uint32_t I1 = !(J1 ^ S);
2055  uint32_t I2 = !(J2 ^ S);
2056  uint32_t imm25 =
2057  (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
2058  imm32 = llvm::SignExtend32<25>(imm25);
2059  target = Align(pc, 4) + imm32;
2060  SelectInstrSet(eModeARM);
2061  context.SetISAAndImmediateSigned(eModeARM, 4 + imm32);
2062  if (InITBlock() && !LastInITBlock())
2063  return false;
2064  break;
2065  }
2066  case eEncodingA1:
2067  lr = pc - 4; // return address
2068  imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2069  target = Align(pc, 4) + imm32;
2070  SelectInstrSet(eModeARM);
2071  context.SetISAAndImmediateSigned(eModeARM, 8 + imm32);
2072  break;
2073  case eEncodingA2:
2074  lr = pc - 4; // return address
2075  imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 |
2076  Bits32(opcode, 24, 24) << 1);
2077  target = pc + imm32;
2078  SelectInstrSet(eModeThumb);
2079  context.SetISAAndImmediateSigned(eModeThumb, 8 + imm32);
2080  break;
2081  default:
2082  return false;
2083  }
2084  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2086  return false;
2087  if (!BranchWritePC(context, target))
2088  return false;
2089  if (m_opcode_cpsr != m_new_inst_cpsr)
2090  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2091  LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
2092  return false;
2093  }
2094  return true;
2095 }
2096 
2097 // Branch with Link and Exchange (register) calls a subroutine at an address
2098 // and instruction set specified by a register.
2099 // BLX (register)
2100 bool EmulateInstructionARM::EmulateBLXRm(const uint32_t opcode,
2101  const ARMEncoding encoding) {
2102 #if 0
2103  // ARM pseudo code...
2104  if (ConditionPassed())
2105  {
2106  EncodingSpecificOperations();
2107  target = R[m];
2108  if CurrentInstrSet() == InstrSet_ARM then
2109  next_instr_addr = PC - 4;
2110  LR = next_instr_addr;
2111  else
2112  next_instr_addr = PC - 2;
2113  LR = next_instr_addr<31:1> : '1';
2114  BXWritePC(target);
2115  }
2116 #endif
2117 
2118  bool success = false;
2119 
2120  if (ConditionPassed(opcode)) {
2122  context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
2123  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2124  addr_t lr; // next instruction address
2125  if (!success)
2126  return false;
2127  uint32_t Rm; // the register with the target address
2128  switch (encoding) {
2129  case eEncodingT1:
2130  lr = (pc - 2) | 1u; // return address
2131  Rm = Bits32(opcode, 6, 3);
2132  // if m == 15 then UNPREDICTABLE;
2133  if (Rm == 15)
2134  return false;
2135  if (InITBlock() && !LastInITBlock())
2136  return false;
2137  break;
2138  case eEncodingA1:
2139  lr = pc - 4; // return address
2140  Rm = Bits32(opcode, 3, 0);
2141  // if m == 15 then UNPREDICTABLE;
2142  if (Rm == 15)
2143  return false;
2144  break;
2145  default:
2146  return false;
2147  }
2148  addr_t target = ReadCoreReg(Rm, &success);
2149  if (!success)
2150  return false;
2151  RegisterInfo dwarf_reg;
2152  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
2153  context.SetRegister(dwarf_reg);
2154  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2156  return false;
2157  if (!BXWritePC(context, target))
2158  return false;
2159  }
2160  return true;
2161 }
2162 
2163 // Branch and Exchange causes a branch to an address and instruction set
2164 // specified by a register.
2165 bool EmulateInstructionARM::EmulateBXRm(const uint32_t opcode,
2166  const ARMEncoding encoding) {
2167 #if 0
2168  // ARM pseudo code...
2169  if (ConditionPassed())
2170  {
2171  EncodingSpecificOperations();
2172  BXWritePC(R[m]);
2173  }
2174 #endif
2175 
2176  if (ConditionPassed(opcode)) {
2178  context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
2179  uint32_t Rm; // the register with the target address
2180  switch (encoding) {
2181  case eEncodingT1:
2182  Rm = Bits32(opcode, 6, 3);
2183  if (InITBlock() && !LastInITBlock())
2184  return false;
2185  break;
2186  case eEncodingA1:
2187  Rm = Bits32(opcode, 3, 0);
2188  break;
2189  default:
2190  return false;
2191  }
2192  bool success = false;
2193  addr_t target = ReadCoreReg(Rm, &success);
2194  if (!success)
2195  return false;
2196 
2197  RegisterInfo dwarf_reg;
2198  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
2199  context.SetRegister(dwarf_reg);
2200  if (!BXWritePC(context, target))
2201  return false;
2202  }
2203  return true;
2204 }
2205 
2206 // Branch and Exchange Jazelle attempts to change to Jazelle state. If the
2207 // attempt fails, it branches to an address and instruction set specified by a
2208 // register as though it were a BX instruction.
2209 //
2210 // TODO: Emulate Jazelle architecture?
2211 // We currently assume that switching to Jazelle state fails, thus
2212 // treating BXJ as a BX operation.
2213 bool EmulateInstructionARM::EmulateBXJRm(const uint32_t opcode,
2214  const ARMEncoding encoding) {
2215 #if 0
2216  // ARM pseudo code...
2217  if (ConditionPassed())
2218  {
2219  EncodingSpecificOperations();
2220  if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then
2221  BXWritePC(R[m]);
2222  else
2223  if JazelleAcceptsExecution() then
2224  SwitchToJazelleExecution();
2225  else
2226  SUBARCHITECTURE_DEFINED handler call;
2227  }
2228 #endif
2229 
2230  if (ConditionPassed(opcode)) {
2232  context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
2233  uint32_t Rm; // the register with the target address
2234  switch (encoding) {
2235  case eEncodingT1:
2236  Rm = Bits32(opcode, 19, 16);
2237  if (BadReg(Rm))
2238  return false;
2239  if (InITBlock() && !LastInITBlock())
2240  return false;
2241  break;
2242  case eEncodingA1:
2243  Rm = Bits32(opcode, 3, 0);
2244  if (Rm == 15)
2245  return false;
2246  break;
2247  default:
2248  return false;
2249  }
2250  bool success = false;
2251  addr_t target = ReadCoreReg(Rm, &success);
2252  if (!success)
2253  return false;
2254 
2255  RegisterInfo dwarf_reg;
2256  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
2257  context.SetRegister(dwarf_reg);
2258  if (!BXWritePC(context, target))
2259  return false;
2260  }
2261  return true;
2262 }
2263 
2264 // Set r7 to point to some ip offset.
2265 // SUB (immediate)
2266 bool EmulateInstructionARM::EmulateSUBR7IPImm(const uint32_t opcode,
2267  const ARMEncoding encoding) {
2268 #if 0
2269  // ARM pseudo code...
2270  if (ConditionPassed())
2271  {
2272  EncodingSpecificOperations();
2273  (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
2274  if d == 15 then // Can only occur for ARM encoding
2275  ALUWritePC(result); // setflags is always FALSE here
2276  else
2277  R[d] = result;
2278  if setflags then
2279  APSR.N = result<31>;
2280  APSR.Z = IsZeroBit(result);
2281  APSR.C = carry;
2282  APSR.V = overflow;
2283  }
2284 #endif
2285 
2286  if (ConditionPassed(opcode)) {
2287  bool success = false;
2288  const addr_t ip = ReadCoreReg(12, &success);
2289  if (!success)
2290  return false;
2291  uint32_t imm32;
2292  switch (encoding) {
2293  case eEncodingA1:
2294  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2295  break;
2296  default:
2297  return false;
2298  }
2299  addr_t ip_offset = imm32;
2300  addr_t addr = ip - ip_offset; // the adjusted ip value
2301 
2303  context.type = EmulateInstruction::eContextRegisterPlusOffset;
2304  RegisterInfo dwarf_reg;
2305  GetRegisterInfo(eRegisterKindDWARF, dwarf_r12, dwarf_reg);
2306  context.SetRegisterPlusOffset(dwarf_reg, -ip_offset);
2307 
2308  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r7, addr))
2309  return false;
2310  }
2311  return true;
2312 }
2313 
2314 // Set ip to point to some stack offset.
2315 // SUB (SP minus immediate)
2316 bool EmulateInstructionARM::EmulateSUBIPSPImm(const uint32_t opcode,
2317  const ARMEncoding encoding) {
2318 #if 0
2319  // ARM pseudo code...
2320  if (ConditionPassed())
2321  {
2322  EncodingSpecificOperations();
2323  (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
2324  if d == 15 then // Can only occur for ARM encoding
2325  ALUWritePC(result); // setflags is always FALSE here
2326  else
2327  R[d] = result;
2328  if setflags then
2329  APSR.N = result<31>;
2330  APSR.Z = IsZeroBit(result);
2331  APSR.C = carry;
2332  APSR.V = overflow;
2333  }
2334 #endif
2335 
2336  if (ConditionPassed(opcode)) {
2337  bool success = false;
2338  const addr_t sp = ReadCoreReg(SP_REG, &success);
2339  if (!success)
2340  return false;
2341  uint32_t imm32;
2342  switch (encoding) {
2343  case eEncodingA1:
2344  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2345  break;
2346  default:
2347  return false;
2348  }
2349  addr_t sp_offset = imm32;
2350  addr_t addr = sp - sp_offset; // the adjusted stack pointer value
2351 
2353  context.type = EmulateInstruction::eContextRegisterPlusOffset;
2354  RegisterInfo dwarf_reg;
2355  GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, dwarf_reg);
2356  context.SetRegisterPlusOffset(dwarf_reg, -sp_offset);
2357 
2358  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r12, addr))
2359  return false;
2360  }
2361  return true;
2362 }
2363 
2364 // This instruction subtracts an immediate value from the SP value, and writes
2365 // the result to the destination register.
2366 //
2367 // If Rd == 13 => A sub operation to adjust the SP -- allocate space for local
2368 // storage.
2369 bool EmulateInstructionARM::EmulateSUBSPImm(const uint32_t opcode,
2370  const ARMEncoding encoding) {
2371 #if 0
2372  // ARM pseudo code...
2373  if (ConditionPassed())
2374  {
2375  EncodingSpecificOperations();
2376  (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
2377  if d == 15 then // Can only occur for ARM encoding
2378  ALUWritePC(result); // setflags is always FALSE here
2379  else
2380  R[d] = result;
2381  if setflags then
2382  APSR.N = result<31>;
2383  APSR.Z = IsZeroBit(result);
2384  APSR.C = carry;
2385  APSR.V = overflow;
2386  }
2387 #endif
2388 
2389  bool success = false;
2390  if (ConditionPassed(opcode)) {
2391  const addr_t sp = ReadCoreReg(SP_REG, &success);
2392  if (!success)
2393  return false;
2394 
2395  uint32_t Rd;
2396  bool setflags;
2397  uint32_t imm32;
2398  switch (encoding) {
2399  case eEncodingT1:
2400  Rd = 13;
2401  setflags = false;
2402  imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
2403  break;
2404  case eEncodingT2:
2405  Rd = Bits32(opcode, 11, 8);
2406  setflags = BitIsSet(opcode, 20);
2407  imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2408  if (Rd == 15 && setflags)
2409  return EmulateCMPImm(opcode, eEncodingT2);
2410  if (Rd == 15 && !setflags)
2411  return false;
2412  break;
2413  case eEncodingT3:
2414  Rd = Bits32(opcode, 11, 8);
2415  setflags = false;
2416  imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
2417  if (Rd == 15)
2418  return false;
2419  break;
2420  case eEncodingA1:
2421  Rd = Bits32(opcode, 15, 12);
2422  setflags = BitIsSet(opcode, 20);
2423  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2424 
2425  // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
2426  // instructions;
2427  if (Rd == 15 && setflags)
2428  return EmulateSUBSPcLrEtc(opcode, encoding);
2429  break;
2430  default:
2431  return false;
2432  }
2433  AddWithCarryResult res = AddWithCarry(sp, ~imm32, 1);
2434 
2436  if (Rd == 13) {
2437  uint64_t imm64 = imm32; // Need to expand it to 64 bits before attempting
2438  // to negate it, or the wrong
2439  // value gets passed down to context.SetImmediateSigned.
2440  context.type = EmulateInstruction::eContextAdjustStackPointer;
2441  context.SetImmediateSigned(-imm64); // the stack pointer offset
2442  } else {
2443  context.type = EmulateInstruction::eContextImmediate;
2444  context.SetNoArgs();
2445  }
2446 
2447  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
2448  res.carry_out, res.overflow))
2449  return false;
2450  }
2451  return true;
2452 }
2453 
2454 // A store operation to the stack that also updates the SP.
2455 bool EmulateInstructionARM::EmulateSTRRtSP(const uint32_t opcode,
2456  const ARMEncoding encoding) {
2457 #if 0
2458  // ARM pseudo code...
2459  if (ConditionPassed())
2460  {
2461  EncodingSpecificOperations();
2462  offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
2463  address = if index then offset_addr else R[n];
2464  MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
2465  if wback then R[n] = offset_addr;
2466  }
2467 #endif
2468 
2469  bool success = false;
2470  if (ConditionPassed(opcode)) {
2471  const uint32_t addr_byte_size = GetAddressByteSize();
2472  const addr_t sp = ReadCoreReg(SP_REG, &success);
2473  if (!success)
2474  return false;
2475  uint32_t Rt; // the source register
2476  uint32_t imm12;
2477  uint32_t
2478  Rn; // This function assumes Rn is the SP, but we should verify that.
2479 
2480  bool index;
2481  bool add;
2482  bool wback;
2483  switch (encoding) {
2484  case eEncodingA1:
2485  Rt = Bits32(opcode, 15, 12);
2486  imm12 = Bits32(opcode, 11, 0);
2487  Rn = Bits32(opcode, 19, 16);
2488 
2489  if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP.
2490  return false;
2491 
2492  index = BitIsSet(opcode, 24);
2493  add = BitIsSet(opcode, 23);
2494  wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
2495 
2496  if (wback && ((Rn == 15) || (Rn == Rt)))
2497  return false;
2498  break;
2499  default:
2500  return false;
2501  }
2502  addr_t offset_addr;
2503  if (add)
2504  offset_addr = sp + imm12;
2505  else
2506  offset_addr = sp - imm12;
2507 
2508  addr_t addr;
2509  if (index)
2510  addr = offset_addr;
2511  else
2512  addr = sp;
2513 
2515  context.type = EmulateInstruction::eContextPushRegisterOnStack;
2516  RegisterInfo sp_reg;
2517  RegisterInfo dwarf_reg;
2518 
2519  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
2520  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rt, dwarf_reg);
2521  context.SetRegisterToRegisterPlusOffset(dwarf_reg, sp_reg, addr - sp);
2522  if (Rt != 15) {
2523  uint32_t reg_value = ReadCoreReg(Rt, &success);
2524  if (!success)
2525  return false;
2526  if (!MemUWrite(context, addr, reg_value, addr_byte_size))
2527  return false;
2528  } else {
2529  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2530  if (!success)
2531  return false;
2532  if (!MemUWrite(context, addr, pc, addr_byte_size))
2533  return false;
2534  }
2535 
2536  if (wback) {
2537  context.type = EmulateInstruction::eContextAdjustStackPointer;
2538  context.SetImmediateSigned(addr - sp);
2539  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2540  LLDB_REGNUM_GENERIC_SP, offset_addr))
2541  return false;
2542  }
2543  }
2544  return true;
2545 }
2546 
2547 // Vector Push stores multiple extension registers to the stack. It also
2548 // updates SP to point to the start of the stored data.
2549 bool EmulateInstructionARM::EmulateVPUSH(const uint32_t opcode,
2550  const ARMEncoding encoding) {
2551 #if 0
2552  // ARM pseudo code...
2553  if (ConditionPassed())
2554  {
2555  EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2556  address = SP - imm32;
2557  SP = SP - imm32;
2558  if single_regs then
2559  for r = 0 to regs-1
2560  MemA[address,4] = S[d+r]; address = address+4;
2561  else
2562  for r = 0 to regs-1
2563  // Store as two word-aligned words in the correct order for
2564  // current endianness.
2565  MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
2566  MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
2567  address = address+8;
2568  }
2569 #endif
2570 
2571  bool success = false;
2572  if (ConditionPassed(opcode)) {
2573  const uint32_t addr_byte_size = GetAddressByteSize();
2574  const addr_t sp = ReadCoreReg(SP_REG, &success);
2575  if (!success)
2576  return false;
2577  bool single_regs;
2578  uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register
2579  uint32_t imm32; // stack offset
2580  uint32_t regs; // number of registers
2581  switch (encoding) {
2582  case eEncodingT1:
2583  case eEncodingA1:
2584  single_regs = false;
2585  d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2586  imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2587  // If UInt(imm8) is odd, see "FSTMX".
2588  regs = Bits32(opcode, 7, 0) / 2;
2589  // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2590  if (regs == 0 || regs > 16 || (d + regs) > 32)
2591  return false;
2592  break;
2593  case eEncodingT2:
2594  case eEncodingA2:
2595  single_regs = true;
2596  d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2597  imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2598  regs = Bits32(opcode, 7, 0);
2599  // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2600  if (regs == 0 || regs > 16 || (d + regs) > 32)
2601  return false;
2602  break;
2603  default:
2604  return false;
2605  }
2606  uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
2607  uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2608  addr_t sp_offset = imm32;
2609  addr_t addr = sp - sp_offset;
2610  uint32_t i;
2611 
2613  context.type = EmulateInstruction::eContextPushRegisterOnStack;
2614 
2615  RegisterInfo dwarf_reg;
2616  RegisterInfo sp_reg;
2617  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
2618  for (i = 0; i < regs; ++i) {
2619  GetRegisterInfo(eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
2620  context.SetRegisterToRegisterPlusOffset(dwarf_reg, sp_reg, addr - sp);
2621  // uint64_t to accommodate 64-bit registers.
2622  uint64_t reg_value = ReadRegisterUnsigned(&dwarf_reg, 0, &success);
2623  if (!success)
2624  return false;
2625  if (!MemAWrite(context, addr, reg_value, reg_byte_size))
2626  return false;
2627  addr += reg_byte_size;
2628  }
2629 
2630  context.type = EmulateInstruction::eContextAdjustStackPointer;
2631  context.SetImmediateSigned(-sp_offset);
2632 
2633  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2634  LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
2635  return false;
2636  }
2637  return true;
2638 }
2639 
2640 // Vector Pop loads multiple extension registers from the stack. It also
2641 // updates SP to point just above the loaded data.
2642 bool EmulateInstructionARM::EmulateVPOP(const uint32_t opcode,
2643  const ARMEncoding encoding) {
2644 #if 0
2645  // ARM pseudo code...
2646  if (ConditionPassed())
2647  {
2648  EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2649  address = SP;
2650  SP = SP + imm32;
2651  if single_regs then
2652  for r = 0 to regs-1
2653  S[d+r] = MemA[address,4]; address = address+4;
2654  else
2655  for r = 0 to regs-1
2656  word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
2657  // Combine the word-aligned words in the correct order for
2658  // current endianness.
2659  D[d+r] = if BigEndian() then word1:word2 else word2:word1;
2660  }
2661 #endif
2662 
2663  bool success = false;
2664  if (ConditionPassed(opcode)) {
2665  const uint32_t addr_byte_size = GetAddressByteSize();
2666  const addr_t sp = ReadCoreReg(SP_REG, &success);
2667  if (!success)
2668  return false;
2669  bool single_regs;
2670  uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register
2671  uint32_t imm32; // stack offset
2672  uint32_t regs; // number of registers
2673  switch (encoding) {
2674  case eEncodingT1:
2675  case eEncodingA1:
2676  single_regs = false;
2677  d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2678  imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2679  // If UInt(imm8) is odd, see "FLDMX".
2680  regs = Bits32(opcode, 7, 0) / 2;
2681  // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2682  if (regs == 0 || regs > 16 || (d + regs) > 32)
2683  return false;
2684  break;
2685  case eEncodingT2:
2686  case eEncodingA2:
2687  single_regs = true;
2688  d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2689  imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2690  regs = Bits32(opcode, 7, 0);
2691  // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2692  if (regs == 0 || regs > 16 || (d + regs) > 32)
2693  return false;
2694  break;
2695  default:
2696  return false;
2697  }
2698  uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
2699  uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2700  addr_t sp_offset = imm32;
2701  addr_t addr = sp;
2702  uint32_t i;
2703  uint64_t data; // uint64_t to accommodate 64-bit registers.
2704 
2706  context.type = EmulateInstruction::eContextPopRegisterOffStack;
2707 
2708  RegisterInfo dwarf_reg;
2709  RegisterInfo sp_reg;
2710  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
2711  for (i = 0; i < regs; ++i) {
2712  GetRegisterInfo(eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
2713  context.SetAddress(addr);
2714  data = MemARead(context, addr, reg_byte_size, 0, &success);
2715  if (!success)
2716  return false;
2717  if (!WriteRegisterUnsigned(context, &dwarf_reg, data))
2718  return false;
2719  addr += reg_byte_size;
2720  }
2721 
2722  context.type = EmulateInstruction::eContextAdjustStackPointer;
2723  context.SetImmediateSigned(sp_offset);
2724 
2725  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2726  LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
2727  return false;
2728  }
2729  return true;
2730 }
2731 
2732 // SVC (previously SWI)
2733 bool EmulateInstructionARM::EmulateSVC(const uint32_t opcode,
2734  const ARMEncoding encoding) {
2735 #if 0
2736  // ARM pseudo code...
2737  if (ConditionPassed())
2738  {
2739  EncodingSpecificOperations();
2740  CallSupervisor();
2741  }
2742 #endif
2743 
2744  bool success = false;
2745 
2746  if (ConditionPassed(opcode)) {
2747  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2748  addr_t lr; // next instruction address
2749  if (!success)
2750  return false;
2751  uint32_t imm32; // the immediate constant
2752  uint32_t mode; // ARM or Thumb mode
2753  switch (encoding) {
2754  case eEncodingT1:
2755  lr = (pc + 2) | 1u; // return address
2756  imm32 = Bits32(opcode, 7, 0);
2757  mode = eModeThumb;
2758  break;
2759  case eEncodingA1:
2760  lr = pc + 4; // return address
2761  imm32 = Bits32(opcode, 23, 0);
2762  mode = eModeARM;
2763  break;
2764  default:
2765  return false;
2766  }
2767 
2769  context.type = EmulateInstruction::eContextSupervisorCall;
2770  context.SetISAAndImmediate(mode, imm32);
2771  if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
2773  return false;
2774  }
2775  return true;
2776 }
2777 
2778 // If Then makes up to four following instructions (the IT block) conditional.
2779 bool EmulateInstructionARM::EmulateIT(const uint32_t opcode,
2780  const ARMEncoding encoding) {
2781 #if 0
2782  // ARM pseudo code...
2783  EncodingSpecificOperations();
2784  ITSTATE.IT<7:0> = firstcond:mask;
2785 #endif
2786 
2787  m_it_session.InitIT(Bits32(opcode, 7, 0));
2788  return true;
2789 }
2790 
2791 bool EmulateInstructionARM::EmulateNop(const uint32_t opcode,
2792  const ARMEncoding encoding) {
2793  // NOP, nothing to do...
2794  return true;
2795 }
2796 
2797 // Branch causes a branch to a target address.
2798 bool EmulateInstructionARM::EmulateB(const uint32_t opcode,
2799  const ARMEncoding encoding) {
2800 #if 0
2801  // ARM pseudo code...
2802  if (ConditionPassed())
2803  {
2804  EncodingSpecificOperations();
2805  BranchWritePC(PC + imm32);
2806  }
2807 #endif
2808 
2809  bool success = false;
2810 
2811  if (ConditionPassed(opcode)) {
2813  context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2814  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2815  if (!success)
2816  return false;
2817  addr_t target; // target address
2818  int32_t imm32; // PC-relative offset
2819  switch (encoding) {
2820  case eEncodingT1:
2821  // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2822  imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
2823  target = pc + imm32;
2824  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2825  break;
2826  case eEncodingT2:
2827  imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1);
2828  target = pc + imm32;
2829  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2830  break;
2831  case eEncodingT3:
2832  // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2833  {
2834  if (Bits32(opcode, 25, 23) == 7)
2835  return false; // See Branches and miscellaneous control on page
2836  // A6-235.
2837 
2838  uint32_t S = Bit32(opcode, 26);
2839  uint32_t imm6 = Bits32(opcode, 21, 16);
2840  uint32_t J1 = Bit32(opcode, 13);
2841  uint32_t J2 = Bit32(opcode, 11);
2842  uint32_t imm11 = Bits32(opcode, 10, 0);
2843  uint32_t imm21 =
2844  (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
2845  imm32 = llvm::SignExtend32<21>(imm21);
2846  target = pc + imm32;
2847  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2848  break;
2849  }
2850  case eEncodingT4: {
2851  uint32_t S = Bit32(opcode, 26);
2852  uint32_t imm10 = Bits32(opcode, 25, 16);
2853  uint32_t J1 = Bit32(opcode, 13);
2854  uint32_t J2 = Bit32(opcode, 11);
2855  uint32_t imm11 = Bits32(opcode, 10, 0);
2856  uint32_t I1 = !(J1 ^ S);
2857  uint32_t I2 = !(J2 ^ S);
2858  uint32_t imm25 =
2859  (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2860  imm32 = llvm::SignExtend32<25>(imm25);
2861  target = pc + imm32;
2862  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2863  break;
2864  }
2865  case eEncodingA1:
2866  imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2867  target = pc + imm32;
2868  context.SetISAAndImmediateSigned(eModeARM, 8 + imm32);
2869  break;
2870  default:
2871  return false;
2872  }
2873  if (!BranchWritePC(context, target))
2874  return false;
2875  }
2876  return true;
2877 }
2878 
2879 // Compare and Branch on Nonzero and Compare and Branch on Zero compare the
2880 // value in a register with zero and conditionally branch forward a constant
2881 // value. They do not affect the condition flags. CBNZ, CBZ
2882 bool EmulateInstructionARM::EmulateCB(const uint32_t opcode,
2883  const ARMEncoding encoding) {
2884 #if 0
2885  // ARM pseudo code...
2886  EncodingSpecificOperations();
2887  if nonzero ^ IsZero(R[n]) then
2888  BranchWritePC(PC + imm32);
2889 #endif
2890 
2891  bool success = false;
2892 
2893  // Read the register value from the operand register Rn.
2894  uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success);
2895  if (!success)
2896  return false;
2897 
2899  context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2900  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2901  if (!success)
2902  return false;
2903 
2904  addr_t target; // target address
2905  uint32_t imm32; // PC-relative offset to branch forward
2906  bool nonzero;
2907  switch (encoding) {
2908  case eEncodingT1:
2909  imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
2910  nonzero = BitIsSet(opcode, 11);
2911  target = pc + imm32;
2912  context.SetISAAndImmediateSigned(eModeThumb, 4 + imm32);
2913  break;
2914  default:
2915  return false;
2916  }
2917  if (m_ignore_conditions || (nonzero ^ (reg_val == 0)))
2918  if (!BranchWritePC(context, target))
2919  return false;
2920 
2921  return true;
2922 }
2923 
2924 // Table Branch Byte causes a PC-relative forward branch using a table of
2925 // single byte offsets.
2926 // A base register provides a pointer to the table, and a second register
2927 // supplies an index into the table.
2928 // The branch length is twice the value of the byte returned from the table.
2929 //
2930 // Table Branch Halfword causes a PC-relative forward branch using a table of
2931 // single halfword offsets.
2932 // A base register provides a pointer to the table, and a second register
2933 // supplies an index into the table.
2934 // The branch length is twice the value of the halfword returned from the
2935 // table. TBB, TBH
2936 bool EmulateInstructionARM::EmulateTB(const uint32_t opcode,
2937  const ARMEncoding encoding) {
2938 #if 0
2939  // ARM pseudo code...
2940  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
2941  if is_tbh then
2942  halfwords = UInt(MemU[R[n]+LSL(R[m],1), 2]);
2943  else
2944  halfwords = UInt(MemU[R[n]+R[m], 1]);
2945  BranchWritePC(PC + 2*halfwords);
2946 #endif
2947 
2948  bool success = false;
2949 
2950  if (ConditionPassed(opcode)) {
2951  uint32_t Rn; // the base register which contains the address of the table of
2952  // branch lengths
2953  uint32_t Rm; // the index register which contains an integer pointing to a
2954  // byte/halfword in the table
2955  bool is_tbh; // true if table branch halfword
2956  switch (encoding) {
2957  case eEncodingT1:
2958  Rn = Bits32(opcode, 19, 16);
2959  Rm = Bits32(opcode, 3, 0);
2960  is_tbh = BitIsSet(opcode, 4);
2961  if (Rn == 13 || BadReg(Rm))
2962  return false;
2963  if (InITBlock() && !LastInITBlock())
2964  return false;
2965  break;
2966  default:
2967  return false;
2968  }
2969 
2970  // Read the address of the table from the operand register Rn. The PC can
2971  // be used, in which case the table immediately follows this instruction.
2972  uint32_t base = ReadCoreReg(Rn, &success);
2973  if (!success)
2974  return false;
2975 
2976  // the table index
2977  uint32_t index = ReadCoreReg(Rm, &success);
2978  if (!success)
2979  return false;
2980 
2981  // the offsetted table address
2982  addr_t addr = base + (is_tbh ? index * 2 : index);
2983 
2984  // PC-relative offset to branch forward
2986  context.type = EmulateInstruction::eContextTableBranchReadMemory;
2987  uint32_t offset = MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
2988  if (!success)
2989  return false;
2990 
2991  const uint32_t pc = ReadCoreReg(PC_REG, &success);
2992  if (!success)
2993  return false;
2994 
2995  // target address
2996  addr_t target = pc + offset;
2997  context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2998  context.SetISAAndImmediateSigned(eModeThumb, 4 + offset);
2999 
3000  if (!BranchWritePC(context, target))
3001  return false;
3002  }
3003 
3004  return true;
3005 }
3006 
3007 // This instruction adds an immediate value to a register value, and writes the
3008 // result to the destination register. It can optionally update the condition
3009 // flags based on the result.
3010 bool EmulateInstructionARM::EmulateADDImmThumb(const uint32_t opcode,
3011  const ARMEncoding encoding) {
3012 #if 0
3013  if ConditionPassed() then
3014  EncodingSpecificOperations();
3015  (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3016  R[d] = result;
3017  if setflags then
3018  APSR.N = result<31>;
3019  APSR.Z = IsZeroBit(result);
3020  APSR.C = carry;
3021  APSR.V = overflow;
3022 #endif
3023 
3024  bool success = false;
3025 
3026  if (ConditionPassed(opcode)) {
3027  uint32_t d;
3028  uint32_t n;
3029  bool setflags;
3030  uint32_t imm32;
3031  uint32_t carry_out;
3032 
3033  // EncodingSpecificOperations();
3034  switch (encoding) {
3035  case eEncodingT1:
3036  // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 =
3037  // ZeroExtend(imm3, 32);
3038  d = Bits32(opcode, 2, 0);
3039  n = Bits32(opcode, 5, 3);
3040  setflags = !InITBlock();
3041  imm32 = Bits32(opcode, 8, 6);
3042 
3043  break;
3044 
3045  case eEncodingT2:
3046  // d = UInt(Rdn); n = UInt(Rdn); setflags = !InITBlock(); imm32 =
3047  // ZeroExtend(imm8, 32);
3048  d = Bits32(opcode, 10, 8);
3049  n = Bits32(opcode, 10, 8);
3050  setflags = !InITBlock();
3051  imm32 = Bits32(opcode, 7, 0);
3052 
3053  break;
3054 
3055  case eEncodingT3:
3056  // if Rd == '1111' && S == '1' then SEE CMN (immediate);
3057  // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 =
3058  // ThumbExpandImm(i:imm3:imm8);
3059  d = Bits32(opcode, 11, 8);
3060  n = Bits32(opcode, 19, 16);
3061  setflags = BitIsSet(opcode, 20);
3062  imm32 = ThumbExpandImm_C(opcode, APSR_C, carry_out);
3063 
3064  // if Rn == '1101' then SEE ADD (SP plus immediate);
3065  if (n == 13)
3066  return EmulateADDSPImm(opcode, eEncodingT3);
3067 
3068  // if BadReg(d) || n == 15 then UNPREDICTABLE;
3069  if (BadReg(d) || (n == 15))
3070  return false;
3071 
3072  break;
3073 
3074  case eEncodingT4: {
3075  // if Rn == '1111' then SEE ADR;
3076  // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 =
3077  // ZeroExtend(i:imm3:imm8, 32);
3078  d = Bits32(opcode, 11, 8);
3079  n = Bits32(opcode, 19, 16);
3080  setflags = false;
3081  uint32_t i = Bit32(opcode, 26);
3082  uint32_t imm3 = Bits32(opcode, 14, 12);
3083  uint32_t imm8 = Bits32(opcode, 7, 0);
3084  imm32 = (i << 11) | (imm3 << 8) | imm8;
3085 
3086  // if Rn == '1101' then SEE ADD (SP plus immediate);
3087  if (n == 13)
3088  return EmulateADDSPImm(opcode, eEncodingT4);
3089 
3090  // if BadReg(d) then UNPREDICTABLE;
3091  if (BadReg(d))
3092  return false;
3093 
3094  break;
3095  }
3096 
3097  default:
3098  return false;
3099  }
3100 
3101  uint64_t Rn =
3102  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3103  if (!success)
3104  return false;
3105 
3106  //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3107  AddWithCarryResult res = AddWithCarry(Rn, imm32, 0);
3108 
3109  RegisterInfo reg_n;
3110  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, reg_n);
3111 
3113  context.type = eContextArithmetic;
3114  context.SetRegisterPlusOffset(reg_n, imm32);
3115 
3116  // R[d] = result;
3117  // if setflags then
3118  // APSR.N = result<31>;
3119  // APSR.Z = IsZeroBit(result);
3120  // APSR.C = carry;
3121  // APSR.V = overflow;
3122  if (!WriteCoreRegOptionalFlags(context, res.result, d, setflags,
3123  res.carry_out, res.overflow))
3124  return false;
3125  }
3126  return true;
3127 }
3128 
3129 // This instruction adds an immediate value to a register value, and writes the
3130 // result to the destination register. It can optionally update the condition
3131 // flags based on the result.
3132 bool EmulateInstructionARM::EmulateADDImmARM(const uint32_t opcode,
3133  const ARMEncoding encoding) {
3134 #if 0
3135  // ARM pseudo code...
3136  if ConditionPassed() then
3137  EncodingSpecificOperations();
3138  (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3139  if d == 15 then
3140  ALUWritePC(result); // setflags is always FALSE here
3141  else
3142  R[d] = result;
3143  if setflags then
3144  APSR.N = result<31>;
3145  APSR.Z = IsZeroBit(result);
3146  APSR.C = carry;
3147  APSR.V = overflow;
3148 #endif
3149 
3150  bool success = false;
3151 
3152  if (ConditionPassed(opcode)) {
3153  uint32_t Rd, Rn;
3154  uint32_t
3155  imm32; // the immediate value to be added to the value obtained from Rn
3156  bool setflags;
3157  switch (encoding) {
3158  case eEncodingA1:
3159  Rd = Bits32(opcode, 15, 12);
3160  Rn = Bits32(opcode, 19, 16);
3161  setflags = BitIsSet(opcode, 20);
3162  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3163  break;
3164  default:
3165  return false;
3166  }
3167 
3168  // Read the first operand.
3169  uint32_t val1 = ReadCoreReg(Rn, &success);
3170  if (!success)
3171  return false;
3172 
3173  AddWithCarryResult res = AddWithCarry(val1, imm32, 0);
3174 
3176  if (Rd == 13)
3177  context.type = EmulateInstruction::eContextAdjustStackPointer;
3178  else if (Rd == GetFramePointerRegisterNumber())
3179  context.type = EmulateInstruction::eContextSetFramePointer;
3180  else
3181  context.type = EmulateInstruction::eContextRegisterPlusOffset;
3182 
3183  RegisterInfo dwarf_reg;
3184  GetRegisterInfo(eRegisterKindDWARF, Rn, dwarf_reg);
3185  context.SetRegisterPlusOffset(dwarf_reg, imm32);
3186 
3187  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3188  res.carry_out, res.overflow))
3189  return false;
3190  }
3191  return true;
3192 }
3193 
3194 // This instruction adds a register value and an optionally-shifted register
3195 // value, and writes the result to the destination register. It can optionally
3196 // update the condition flags based on the result.
3197 bool EmulateInstructionARM::EmulateADDReg(const uint32_t opcode,
3198  const ARMEncoding encoding) {
3199 #if 0
3200  // ARM pseudo code...
3201  if ConditionPassed() then
3202  EncodingSpecificOperations();
3203  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
3204  (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
3205  if d == 15 then
3206  ALUWritePC(result); // setflags is always FALSE here
3207  else
3208  R[d] = result;
3209  if setflags then
3210  APSR.N = result<31>;
3211  APSR.Z = IsZeroBit(result);
3212  APSR.C = carry;
3213  APSR.V = overflow;
3214 #endif
3215 
3216  bool success = false;
3217 
3218  if (ConditionPassed(opcode)) {
3219  uint32_t Rd, Rn, Rm;
3220  ARM_ShifterType shift_t;
3221  uint32_t shift_n; // the shift applied to the value read from Rm
3222  bool setflags;
3223  switch (encoding) {
3224  case eEncodingT1:
3225  Rd = Bits32(opcode, 2, 0);
3226  Rn = Bits32(opcode, 5, 3);
3227  Rm = Bits32(opcode, 8, 6);
3228  setflags = !InITBlock();
3229  shift_t = SRType_LSL;
3230  shift_n = 0;
3231  break;
3232  case eEncodingT2:
3233  Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3234  Rm = Bits32(opcode, 6, 3);
3235  setflags = false;
3236  shift_t = SRType_LSL;
3237  shift_n = 0;
3238  if (Rn == 15 && Rm == 15)
3239  return false;
3240  if (Rd == 15 && InITBlock() && !LastInITBlock())
3241  return false;
3242  break;
3243  case eEncodingA1:
3244  Rd = Bits32(opcode, 15, 12);
3245  Rn = Bits32(opcode, 19, 16);
3246  Rm = Bits32(opcode, 3, 0);
3247  setflags = BitIsSet(opcode, 20);
3248  shift_n = DecodeImmShiftARM(opcode, shift_t);
3249  break;
3250  default:
3251  return false;
3252  }
3253 
3254  // Read the first operand.
3255  uint32_t val1 = ReadCoreReg(Rn, &success);
3256  if (!success)
3257  return false;
3258 
3259  // Read the second operand.
3260  uint32_t val2 = ReadCoreReg(Rm, &success);
3261  if (!success)
3262  return false;
3263 
3264  uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3265  if (!success)
3266  return false;
3267  AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
3268 
3270  context.type = eContextArithmetic;
3271  RegisterInfo op1_reg;
3272  RegisterInfo op2_reg;
3273  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn, op1_reg);
3274  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, op2_reg);
3275  context.SetRegisterRegisterOperands(op1_reg, op2_reg);
3276 
3277  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3278  res.carry_out, res.overflow))
3279  return false;
3280  }
3281  return true;
3282 }
3283 
3284 // Compare Negative (immediate) adds a register value and an immediate value.
3285 // It updates the condition flags based on the result, and discards the result.
3286 bool EmulateInstructionARM::EmulateCMNImm(const uint32_t opcode,
3287  const ARMEncoding encoding) {
3288 #if 0
3289  // ARM pseudo code...
3290  if ConditionPassed() then
3291  EncodingSpecificOperations();
3292  (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3293  APSR.N = result<31>;
3294  APSR.Z = IsZeroBit(result);
3295  APSR.C = carry;
3296  APSR.V = overflow;
3297 #endif
3298 
3299  bool success = false;
3300 
3301  uint32_t Rn; // the first operand
3302  uint32_t imm32; // the immediate value to be compared with
3303  switch (encoding) {
3304  case eEncodingT1:
3305  Rn = Bits32(opcode, 19, 16);
3306  imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
3307  if (Rn == 15)
3308  return false;
3309  break;
3310  case eEncodingA1:
3311  Rn = Bits32(opcode, 19, 16);
3312  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3313  break;
3314  default:
3315  return false;
3316  }
3317  // Read the register value from the operand register Rn.
3318  uint32_t reg_val = ReadCoreReg(Rn, &success);
3319  if (!success)
3320  return false;
3321 
3322  AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0);
3323 
3325  context.type = EmulateInstruction::eContextImmediate;
3326  context.SetNoArgs();
3327  return WriteFlags(context, res.result, res.carry_out, res.overflow);
3328 }
3329 
3330 // Compare Negative (register) adds a register value and an optionally-shifted
3331 // register value. It updates the condition flags based on the result, and
3332 // discards the result.
3333 bool EmulateInstructionARM::EmulateCMNReg(const uint32_t opcode,
3334  const ARMEncoding encoding) {
3335 #if 0
3336  // ARM pseudo code...
3337  if ConditionPassed() then
3338  EncodingSpecificOperations();
3339  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
3340  (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
3341  APSR.N = result<31>;
3342  APSR.Z = IsZeroBit(result);
3343  APSR.C = carry;
3344  APSR.V = overflow;
3345 #endif
3346 
3347  bool success = false;
3348 
3349  uint32_t Rn; // the first operand
3350  uint32_t Rm; // the second operand
3351  ARM_ShifterType shift_t;
3352  uint32_t shift_n; // the shift applied to the value read from Rm
3353  switch (encoding) {
3354  case eEncodingT1:
3355  Rn = Bits32(opcode, 2, 0);
3356  Rm = Bits32(opcode, 5, 3);
3357  shift_t = SRType_LSL;
3358  shift_n = 0;
3359  break;
3360  case eEncodingT2:
3361  Rn = Bits32(opcode, 19, 16);
3362  Rm = Bits32(opcode, 3, 0);
3363  shift_n = DecodeImmShiftThumb(opcode, shift_t);
3364  // if n == 15 || BadReg(m) then UNPREDICTABLE;
3365  if (Rn == 15 || BadReg(Rm))
3366  return false;
3367  break;
3368  case eEncodingA1:
3369  Rn = Bits32(opcode, 19, 16);
3370  Rm = Bits32(opcode, 3, 0);
3371  shift_n = DecodeImmShiftARM(opcode, shift_t);
3372  break;
3373  default:
3374  return false;
3375  }
3376  // Read the register value from register Rn.
3377  uint32_t val1 = ReadCoreReg(Rn, &success);
3378  if (!success)
3379  return false;
3380 
3381  // Read the register value from register Rm.
3382  uint32_t val2 = ReadCoreReg(Rm, &success);
3383  if (!success)
3384  return false;
3385 
3386  uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3387  if (!success)
3388  return false;
3389  AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
3390 
3392  context.type = EmulateInstruction::eContextImmediate;
3393  context.SetNoArgs();
3394  return WriteFlags(context, res.result, res.carry_out, res.overflow);
3395 }
3396 
3397 // Compare (immediate) subtracts an immediate value from a register value. It
3398 // updates the condition flags based on the result, and discards the result.
3399 bool EmulateInstructionARM::EmulateCMPImm(const uint32_t opcode,
3400  const ARMEncoding encoding) {
3401 #if 0
3402  // ARM pseudo code...
3403  if ConditionPassed() then
3404  EncodingSpecificOperations();
3405  (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
3406  APSR.N = result<31>;
3407  APSR.Z = IsZeroBit(result);
3408  APSR.C = carry;
3409  APSR.V = overflow;
3410 #endif
3411 
3412  bool success = false;
3413 
3414  uint32_t Rn; // the first operand
3415  uint32_t imm32; // the immediate value to be compared with
3416  switch (encoding) {
3417  case eEncodingT1:
3418  Rn = Bits32(opcode, 10, 8);
3419  imm32 = Bits32(opcode, 7, 0);
3420  break;
3421  case eEncodingT2:
3422  Rn = Bits32(opcode, 19, 16);
3423  imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
3424  if (Rn == 15)
3425  return false;
3426  break;
3427  case eEncodingA1:
3428  Rn = Bits32(opcode, 19, 16);
3429  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3430  break;
3431  default:
3432  return false;
3433  }
3434  // Read the register value from the operand register Rn.
3435  uint32_t reg_val = ReadCoreReg(Rn, &success);
3436  if (!success)
3437  return false;
3438 
3439  AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
3440 
3442  context.type = EmulateInstruction::eContextImmediate;
3443  context.SetNoArgs();
3444  return WriteFlags(context, res.result, res.carry_out, res.overflow);
3445 }
3446 
3447 // Compare (register) subtracts an optionally-shifted register value from a
3448 // register value. It updates the condition flags based on the result, and
3449 // discards the result.
3450 bool EmulateInstructionARM::EmulateCMPReg(const uint32_t opcode,
3451  const ARMEncoding encoding) {
3452 #if 0
3453  // ARM pseudo code...
3454  if ConditionPassed() then
3455  EncodingSpecificOperations();
3456  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
3457  (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1');
3458  APSR.N = result<31>;
3459  APSR.Z = IsZeroBit(result);
3460  APSR.C = carry;
3461  APSR.V = overflow;
3462 #endif
3463 
3464  bool success = false;
3465 
3466  uint32_t Rn; // the first operand
3467  uint32_t Rm; // the second operand
3468  ARM_ShifterType shift_t;
3469  uint32_t shift_n; // the shift applied to the value read from Rm
3470  switch (encoding) {
3471  case eEncodingT1:
3472  Rn = Bits32(opcode, 2, 0);
3473  Rm = Bits32(opcode, 5, 3);
3474  shift_t = SRType_LSL;
3475  shift_n = 0;
3476  break;
3477  case eEncodingT2:
3478  Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3479  Rm = Bits32(opcode, 6, 3);
3480  shift_t = SRType_LSL;
3481  shift_n = 0;
3482  if (Rn < 8 && Rm < 8)
3483  return false;
3484  if (Rn == 15 || Rm == 15)
3485  return false;
3486  break;
3487  case eEncodingT3:
3488  Rn = Bits32(opcode, 19, 16);
3489  Rm = Bits32(opcode, 3, 0);
3490  shift_n = DecodeImmShiftThumb(opcode, shift_t);
3491  if (Rn == 15 || BadReg(Rm))
3492  return false;
3493  break;
3494  case eEncodingA1:
3495  Rn = Bits32(opcode, 19, 16);
3496  Rm = Bits32(opcode, 3, 0);
3497  shift_n = DecodeImmShiftARM(opcode, shift_t);
3498  break;
3499  default:
3500  return false;
3501  }
3502  // Read the register value from register Rn.
3503  uint32_t val1 = ReadCoreReg(Rn, &success);
3504  if (!success)
3505  return false;
3506 
3507  // Read the register value from register Rm.
3508  uint32_t val2 = ReadCoreReg(Rm, &success);
3509  if (!success)
3510  return false;
3511 
3512  uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3513  if (!success)
3514  return false;
3515  AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1);
3516 
3518  context.type = EmulateInstruction::eContextImmediate;
3519  context.SetNoArgs();
3520  return WriteFlags(context, res.result, res.carry_out, res.overflow);
3521 }
3522 
3523 // Arithmetic Shift Right (immediate) shifts a register value right by an
3524 // immediate number of bits, shifting in copies of its sign bit, and writes the
3525 // result to the destination register. It can optionally update the condition
3526 // flags based on the result.
3527 bool EmulateInstructionARM::EmulateASRImm(const uint32_t opcode,
3528  const ARMEncoding encoding) {
3529 #if 0
3530  // ARM pseudo code...
3531  if ConditionPassed() then
3532  EncodingSpecificOperations();
3533  (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
3534  if d == 15 then // Can only occur for ARM encoding
3535  ALUWritePC(result); // setflags is always FALSE here
3536  else
3537  R[d] = result;
3538  if setflags then
3539  APSR.N = result<31>;
3540  APSR.Z = IsZeroBit(result);
3541  APSR.C = carry;
3542  // APSR.V unchanged
3543 #endif
3544 
3545  return EmulateShiftImm(opcode, encoding, SRType_ASR);
3546 }
3547 
3548 // Arithmetic Shift Right (register) shifts a register value right by a
3549 // variable number of bits, shifting in copies of its sign bit, and writes the
3550 // result to the destination register. The variable number of bits is read from
3551 // the bottom byte of a register. It can optionally update the condition flags
3552 // based on the result.
3553 bool EmulateInstructionARM::EmulateASRReg(const uint32_t opcode,
3554  const ARMEncoding encoding) {
3555 #if 0
3556  // ARM pseudo code...
3557  if ConditionPassed() then
3558  EncodingSpecificOperations();
3559  shift_n = UInt(R[m]<7:0>);
3560  (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
3561  R[d] = result;
3562  if setflags then
3563  APSR.N = result<31>;
3564  APSR.Z = IsZeroBit(result);
3565  APSR.C = carry;
3566  // APSR.V unchanged
3567 #endif
3568 
3569  return EmulateShiftReg(opcode, encoding, SRType_ASR);
3570 }
3571 
3572 // Logical Shift Left (immediate) shifts a register value left by an immediate
3573 // number of bits, shifting in zeros, and writes the result to the destination
3574 // register. It can optionally update the condition flags based on the result.
3575 bool EmulateInstructionARM::EmulateLSLImm(const uint32_t opcode,
3576  const ARMEncoding encoding) {
3577 #if 0
3578  // ARM pseudo code...
3579  if ConditionPassed() then
3580  EncodingSpecificOperations();
3581  (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
3582  if d == 15 then // Can only occur for ARM encoding
3583  ALUWritePC(result); // setflags is always FALSE here
3584  else
3585  R[d] = result;
3586  if setflags then
3587  APSR.N = result<31>;
3588  APSR.Z = IsZeroBit(result);
3589  APSR.C = carry;
3590  // APSR.V unchanged
3591 #endif
3592 
3593  return EmulateShiftImm(opcode, encoding, SRType_LSL);
3594 }
3595 
3596 // Logical Shift Left (register) shifts a register value left by a variable
3597 // number of bits, shifting in zeros, and writes the result to the destination
3598 // register. The variable number of bits is read from the bottom byte of a
3599 // register. It can optionally update the condition flags based on the result.
3600 bool EmulateInstructionARM::EmulateLSLReg(const uint32_t opcode,
3601  const ARMEncoding encoding) {
3602 #if 0
3603  // ARM pseudo code...
3604  if ConditionPassed() then
3605  EncodingSpecificOperations();
3606  shift_n = UInt(R[m]<7:0>);
3607  (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
3608  R[d] = result;
3609  if setflags then
3610  APSR.N = result<31>;
3611  APSR.Z = IsZeroBit(result);
3612  APSR.C = carry;
3613  // APSR.V unchanged
3614 #endif
3615 
3616  return EmulateShiftReg(opcode, encoding, SRType_LSL);
3617 }
3618 
3619 // Logical Shift Right (immediate) shifts a register value right by an
3620 // immediate number of bits, shifting in zeros, and writes the result to the
3621 // destination register. It can optionally update the condition flags based on
3622 // the result.
3623 bool EmulateInstructionARM::EmulateLSRImm(const uint32_t opcode,
3624  const ARMEncoding encoding) {
3625 #if 0
3626  // ARM pseudo code...
3627  if ConditionPassed() then
3628  EncodingSpecificOperations();
3629  (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
3630  if d == 15 then // Can only occur for ARM encoding
3631  ALUWritePC(result); // setflags is always FALSE here
3632  else
3633  R[d] = result;
3634  if setflags then
3635  APSR.N = result<31>;
3636  APSR.Z = IsZeroBit(result);
3637  APSR.C = carry;
3638  // APSR.V unchanged
3639 #endif
3640 
3641  return EmulateShiftImm(opcode, encoding, SRType_LSR);
3642 }
3643 
3644 // Logical Shift Right (register) shifts a register value right by a variable
3645 // number of bits, shifting in zeros, and writes the result to the destination
3646 // register. The variable number of bits is read from the bottom byte of a
3647 // register. It can optionally update the condition flags based on the result.
3648 bool EmulateInstructionARM::EmulateLSRReg(const uint32_t opcode,
3649  const ARMEncoding encoding) {
3650 #if 0
3651  // ARM pseudo code...
3652  if ConditionPassed() then
3653  EncodingSpecificOperations();
3654  shift_n = UInt(R[m]<7:0>);
3655  (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
3656  R[d] = result;
3657  if setflags then
3658  APSR.N = result<31>;
3659  APSR.Z = IsZeroBit(result);
3660  APSR.C = carry;
3661  // APSR.V unchanged
3662 #endif
3663 
3664  return EmulateShiftReg(opcode, encoding, SRType_LSR);
3665 }
3666 
3667 // Rotate Right (immediate) provides the value of the contents of a register
3668 // rotated by a constant value. The bits that are rotated off the right end are
3669 // inserted into the vacated bit positions on the left. It can optionally
3670 // update the condition flags based on the result.
3671 bool EmulateInstructionARM::EmulateRORImm(const uint32_t opcode,
3672  const ARMEncoding encoding) {
3673 #if 0
3674  // ARM pseudo code...
3675  if ConditionPassed() then
3676  EncodingSpecificOperations();
3677  (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
3678  if d == 15 then // Can only occur for ARM encoding
3679  ALUWritePC(result); // setflags is always FALSE here
3680  else
3681  R[d] = result;
3682  if setflags then
3683  APSR.N = result<31>;
3684  APSR.Z = IsZeroBit(result);
3685  APSR.C = carry;
3686  // APSR.V unchanged
3687 #endif
3688 
3689  return EmulateShiftImm(opcode, encoding, SRType_ROR);
3690 }
3691 
3692 // Rotate Right (register) provides the value of the contents of a register
3693 // rotated by a variable number of bits. The bits that are rotated off the
3694 // right end are inserted into the vacated bit positions on the left. The
3695 // variable number of bits is read from the bottom byte of a register. It can
3696 // optionally update the condition flags based on the result.
3697 bool EmulateInstructionARM::EmulateRORReg(const uint32_t opcode,
3698  const ARMEncoding encoding) {
3699 #if 0
3700  // ARM pseudo code...
3701  if ConditionPassed() then
3702  EncodingSpecificOperations();
3703  shift_n = UInt(R[m]<7:0>);
3704  (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
3705  R[d] = result;
3706  if setflags then
3707  APSR.N = result<31>;
3708  APSR.Z = IsZeroBit(result);
3709  APSR.C = carry;
3710  // APSR.V unchanged
3711 #endif
3712 
3713  return EmulateShiftReg(opcode, encoding, SRType_ROR);
3714 }
3715 
3716 // Rotate Right with Extend provides the value of the contents of a register
3717 // shifted right by one place, with the carry flag shifted into bit [31].
3718 //
3719 // RRX can optionally update the condition flags based on the result.
3720 // In that case, bit [0] is shifted into the carry flag.
3721 bool EmulateInstructionARM::EmulateRRX(const uint32_t opcode,
3722  const ARMEncoding encoding) {
3723 #if 0
3724  // ARM pseudo code...
3725  if ConditionPassed() then
3726  EncodingSpecificOperations();
3727  (result, carry) = Shift_C(R[m], SRType_RRX, 1, APSR.C);
3728  if d == 15 then // Can only occur for ARM encoding
3729  ALUWritePC(result); // setflags is always FALSE here
3730  else
3731  R[d] = result;
3732  if setflags then
3733  APSR.N = result<31>;
3734  APSR.Z = IsZeroBit(result);
3735  APSR.C = carry;
3736  // APSR.V unchanged
3737 #endif
3738 
3739  return EmulateShiftImm(opcode, encoding, SRType_RRX);
3740 }
3741 
3742 bool EmulateInstructionARM::EmulateShiftImm(const uint32_t opcode,
3743  const ARMEncoding encoding,
3744  ARM_ShifterType shift_type) {
3745  // assert(shift_type == SRType_ASR
3746  // || shift_type == SRType_LSL
3747  // || shift_type == SRType_LSR
3748  // || shift_type == SRType_ROR
3749  // || shift_type == SRType_RRX);
3750 
3751  bool success = false;
3752 
3753  if (ConditionPassed(opcode)) {
3754  uint32_t Rd; // the destination register
3755  uint32_t Rm; // the first operand register
3756  uint32_t imm5; // encoding for the shift amount
3757  uint32_t carry; // the carry bit after the shift operation
3758  bool setflags;
3759 
3760  // Special case handling!
3761  // A8.6.139 ROR (immediate) -- Encoding T1
3762  ARMEncoding use_encoding = encoding;
3763  if (shift_type == SRType_ROR && use_encoding == eEncodingT1) {
3764  // Morph the T1 encoding from the ARM Architecture Manual into T2
3765  // encoding to have the same decoding of bit fields as the other Thumb2
3766  // shift operations.
3767  use_encoding = eEncodingT2;
3768  }
3769 
3770  switch (use_encoding) {
3771  case eEncodingT1:
3772  // Due to the above special case handling!
3773  if (shift_type == SRType_ROR)
3774  return false;
3775 
3776  Rd = Bits32(opcode, 2, 0);
3777  Rm = Bits32(opcode, 5, 3);
3778  setflags = !InITBlock();
3779  imm5 = Bits32(opcode, 10, 6);
3780  break;
3781  case eEncodingT2:
3782  // A8.6.141 RRX
3783  // There's no imm form of RRX instructions.
3784  if (shift_type == SRType_RRX)
3785  return false;
3786 
3787  Rd = Bits32(opcode, 11, 8);
3788  Rm = Bits32(opcode, 3, 0);
3789  setflags = BitIsSet(opcode, 20);
3790  imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6);
3791  if (BadReg(Rd) || BadReg(Rm))
3792  return false;
3793  break;
3794  case eEncodingA1:
3795  Rd = Bits32(opcode, 15, 12);
3796  Rm = Bits32(opcode, 3, 0);
3797  setflags = BitIsSet(opcode, 20);
3798  imm5 = Bits32(opcode, 11, 7);
3799  break;
3800  default:
3801  return false;
3802  }
3803 
3804  // A8.6.139 ROR (immediate)
3805  if (shift_type == SRType_ROR && imm5 == 0)
3806  shift_type = SRType_RRX;
3807 
3808  // Get the first operand.
3809  uint32_t value = ReadCoreReg(Rm, &success);
3810  if (!success)
3811  return false;
3812 
3813  // Decode the shift amount if not RRX.
3814  uint32_t amt =
3815  (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5));
3816 
3817  uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3818  if (!success)
3819  return false;
3820 
3821  // The context specifies that an immediate is to be moved into Rd.
3823  context.type = EmulateInstruction::eContextImmediate;
3824  context.SetNoArgs();
3825 
3826  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3827  return false;
3828  }
3829  return true;
3830 }
3831 
3832 bool EmulateInstructionARM::EmulateShiftReg(const uint32_t opcode,
3833  const ARMEncoding encoding,
3834  ARM_ShifterType shift_type) {
3835  // assert(shift_type == SRType_ASR
3836  // || shift_type == SRType_LSL
3837  // || shift_type == SRType_LSR
3838  // || shift_type == SRType_ROR);
3839 
3840  bool success = false;
3841 
3842  if (ConditionPassed(opcode)) {
3843  uint32_t Rd; // the destination register
3844  uint32_t Rn; // the first operand register
3845  uint32_t
3846  Rm; // the register whose bottom byte contains the amount to shift by
3847  uint32_t carry; // the carry bit after the shift operation
3848  bool setflags;
3849  switch (encoding) {
3850  case eEncodingT1:
3851  Rd = Bits32(opcode, 2, 0);
3852  Rn = Rd;
3853  Rm = Bits32(opcode, 5, 3);
3854  setflags = !InITBlock();
3855  break;
3856  case eEncodingT2:
3857  Rd = Bits32(opcode, 11, 8);
3858  Rn = Bits32(opcode, 19, 16);
3859  Rm = Bits32(opcode, 3, 0);
3860  setflags = BitIsSet(opcode, 20);
3861  if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3862  return false;
3863  break;
3864  case eEncodingA1:
3865  Rd = Bits32(opcode, 15, 12);
3866  Rn = Bits32(opcode, 3, 0);
3867  Rm = Bits32(opcode, 11, 8);
3868  setflags = BitIsSet(opcode, 20);
3869  if (Rd == 15 || Rn == 15 || Rm == 15)
3870  return false;
3871  break;
3872  default:
3873  return false;
3874  }
3875 
3876  // Get the first operand.
3877  uint32_t value = ReadCoreReg(Rn, &success);
3878  if (!success)
3879  return false;
3880  // Get the Rm register content.
3881  uint32_t val = ReadCoreReg(Rm, &success);
3882  if (!success)
3883  return false;
3884 
3885  // Get the shift amount.
3886  uint32_t amt = Bits32(val, 7, 0);
3887 
3888  uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3889  if (!success)
3890  return false;
3891 
3892  // The context specifies that an immediate is to be moved into Rd.
3894  context.type = EmulateInstruction::eContextImmediate;
3895  context.SetNoArgs();
3896 
3897  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3898  return false;
3899  }
3900  return true;
3901 }
3902 
3903 // LDM loads multiple registers from consecutive memory locations, using an
3904 // address from a base register. Optionally the address just above the highest
3905 // of those locations can be written back to the base register.
3906 bool EmulateInstructionARM::EmulateLDM(const uint32_t opcode,
3907  const ARMEncoding encoding) {
3908 #if 0
3909  // ARM pseudo code...
3910  if ConditionPassed()
3911  EncodingSpecificOperations(); NullCheckIfThumbEE (n);
3912  address = R[n];
3913 
3914  for i = 0 to 14
3915  if registers<i> == '1' then
3916  R[i] = MemA[address, 4]; address = address + 4;
3917  if registers<15> == '1' then
3918  LoadWritePC (MemA[address, 4]);
3919 
3920  if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers);
3921  if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3922 
3923 #endif
3924 
3925  bool success = false;
3926  if (ConditionPassed(opcode)) {
3927  uint32_t n;
3928  uint32_t registers = 0;
3929  bool wback;
3930  const uint32_t addr_byte_size = GetAddressByteSize();
3931  switch (encoding) {
3932  case eEncodingT1:
3933  // n = UInt(Rn); registers = '00000000':register_list; wback =
3934  // (registers<n> == '0');
3935  n = Bits32(opcode, 10, 8);
3936  registers = Bits32(opcode, 7, 0);
3937  registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
3938  wback = BitIsClear(registers, n);
3939  // if BitCount(registers) < 1 then UNPREDICTABLE;
3940  if (BitCount(registers) < 1)
3941  return false;
3942  break;
3943  case eEncodingT2:
3944  // if W == '1' && Rn == '1101' then SEE POP;
3945  // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3946  n = Bits32(opcode, 19, 16);
3947  registers = Bits32(opcode, 15, 0);
3948  registers = registers & 0xdfff; // Make sure bit 13 is zero.
3949  wback = BitIsSet(opcode, 21);
3950 
3951  // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then
3952  // UNPREDICTABLE;
3953  if ((n == 15) || (BitCount(registers) < 2) ||
3954  (BitIsSet(opcode, 14) && BitIsSet(opcode, 15)))
3955  return false;
3956 
3957  // if registers<15> == '1' && InITBlock() && !LastInITBlock() then
3958  // UNPREDICTABLE;
3959  if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
3960  return false;
3961 
3962  // if wback && registers<n> == '1' then UNPREDICTABLE;
3963  if (wback && BitIsSet(registers, n))
3964  return false;
3965  break;
3966 
3967  case eEncodingA1:
3968  n = Bits32(opcode, 19, 16);
3969  registers = Bits32(opcode, 15, 0);
3970  wback = BitIsSet(opcode, 21);
3971  if ((n == 15) || (BitCount(registers) < 1))
3972  return false;
3973  break;
3974  default:
3975  return false;
3976  }
3977 
3978  int32_t offset = 0;
3979  const addr_t base_address =
3980  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3981  if (!success)
3982  return false;
3983 
3985  context.type = EmulateInstruction::eContextRegisterPlusOffset;
3986  RegisterInfo dwarf_reg;
3987  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3988  context.SetRegisterPlusOffset(dwarf_reg, offset);
3989 
3990  for (int i = 0; i < 14; ++i) {
3991  if (BitIsSet(registers, i)) {
3992  context.type = EmulateInstruction::eContextRegisterPlusOffset;
3993  context.SetRegisterPlusOffset(dwarf_reg, offset);
3994  if (wback && (n == 13)) // Pop Instruction
3995  {
3996  context.type = EmulateInstruction::eContextPopRegisterOffStack;
3997  context.SetAddress(base_address + offset);
3998  }
3999 
4000  // R[i] = MemA [address, 4]; address = address + 4;
4001  uint32_t data = MemARead(context, base_address + offset, addr_byte_size,
4002  0, &success);
4003  if (!success)
4004  return false;
4005 
4006  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
4007  data))
4008  return false;
4009 
4010  offset += addr_byte_size;
4011  }
4012  }
4013 
4014  if (BitIsSet(registers, 15)) {
4015  // LoadWritePC (MemA [address, 4]);
4016  context.type = EmulateInstruction::eContextRegisterPlusOffset;
4017  context.SetRegisterPlusOffset(dwarf_reg, offset);
4018  uint32_t data =
4019  MemARead(context, base_address + offset, addr_byte_size, 0, &success);
4020  if (!success)
4021  return false;
4022  // In ARMv5T and above, this is an interworking branch.
4023  if (!LoadWritePC(context, data))
4024  return false;
4025  }
4026 
4027  if (wback && BitIsClear(registers, n)) {
4028  // R[n] = R[n] + 4 * BitCount (registers)
4029  int32_t offset = addr_byte_size * BitCount(registers);
4030  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4031  context.SetRegisterPlusOffset(dwarf_reg, offset);
4032 
4033  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4034  base_address + offset))
4035  return false;
4036  }
4037  if (wback && BitIsSet(registers, n))
4038  // R[n] bits(32) UNKNOWN;
4039  return WriteBits32Unknown(n);
4040  }
4041  return true;
4042 }
4043 
4044 // LDMDA loads multiple registers from consecutive memory locations using an
4045 // address from a base register.
4046 // The consecutive memory locations end at this address and the address just
4047 // below the lowest of those locations can optionally be written back to the
4048 // base register.
4049 bool EmulateInstructionARM::EmulateLDMDA(const uint32_t opcode,
4050  const ARMEncoding encoding) {
4051 #if 0
4052  // ARM pseudo code...
4053  if ConditionPassed() then
4054  EncodingSpecificOperations();
4055  address = R[n] - 4*BitCount(registers) + 4;
4056 
4057  for i = 0 to 14
4058  if registers<i> == '1' then
4059  R[i] = MemA[address,4]; address = address + 4;
4060 
4061  if registers<15> == '1' then
4062  LoadWritePC(MemA[address,4]);
4063 
4064  if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4065  if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
4066 #endif
4067 
4068  bool success = false;
4069 
4070  if (ConditionPassed(opcode)) {
4071  uint32_t n;
4072  uint32_t registers = 0;
4073  bool wback;
4074  const uint32_t addr_byte_size = GetAddressByteSize();
4075 
4076  // EncodingSpecificOperations();
4077  switch (encoding) {
4078  case eEncodingA1:
4079  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4080  n = Bits32(opcode, 19, 16);
4081  registers = Bits32(opcode, 15, 0);
4082  wback = BitIsSet(opcode, 21);
4083 
4084  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4085  if ((n == 15) || (BitCount(registers) < 1))
4086  return false;
4087 
4088  break;
4089 
4090  default:
4091  return false;
4092  }
4093  // address = R[n] - 4*BitCount(registers) + 4;
4094 
4095  int32_t offset = 0;
4096  addr_t Rn = ReadCoreReg(n, &success);
4097 
4098  if (!success)
4099  return false;
4100 
4101  addr_t address =
4102  Rn - (addr_byte_size * BitCount(registers)) + addr_byte_size;
4103 
4105  context.type = EmulateInstruction::eContextRegisterPlusOffset;
4106  RegisterInfo dwarf_reg;
4107  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
4108  context.SetRegisterPlusOffset(dwarf_reg, offset);
4109 
4110  // for i = 0 to 14
4111  for (int i = 0; i < 14; ++i) {
4112  // if registers<i> == '1' then
4113  if (BitIsSet(registers, i)) {
4114  // R[i] = MemA[address,4]; address = address + 4;
4115  context.SetRegisterPlusOffset(dwarf_reg, Rn - (address + offset));
4116  uint32_t data =
4117  MemARead(context, address + offset, addr_byte_size, 0, &success);
4118  if (!success)
4119  return false;
4120  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
4121  data))
4122  return false;
4123  offset += addr_byte_size;
4124  }
4125  }
4126 
4127  // if registers<15> == '1' then
4128  // LoadWritePC(MemA[address,4]);
4129  if (BitIsSet(registers, 15)) {
4130  context.SetRegisterPlusOffset(dwarf_reg, offset);
4131  uint32_t data =
4132  MemARead(context, address + offset, addr_byte_size, 0, &success);
4133  if (!success)
4134  return false;
4135  // In ARMv5T and above, this is an interworking branch.
4136  if (!LoadWritePC(context, data))
4137  return false;
4138  }
4139 
4140  // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4141  if (wback && BitIsClear(registers, n)) {
4142  if (!success)
4143  return false;
4144 
4145  offset = (addr_byte_size * BitCount(registers)) * -1;
4146  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4147  context.SetImmediateSigned(offset);
4148  addr_t addr = Rn + offset;
4149  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4150  addr))
4151  return false;
4152  }
4153 
4154  // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
4155  if (wback && BitIsSet(registers, n))
4156  return WriteBits32Unknown(n);
4157  }
4158  return true;
4159 }
4160 
4161 // LDMDB loads multiple registers from consecutive memory locations using an
4162 // address from a base register. The
4163 // consecutive memory locations end just below this address, and the address of
4164 // the lowest of those locations can be optionally written back to the base
4165 // register.
4166 bool EmulateInstructionARM::EmulateLDMDB(const uint32_t opcode,
4167  const ARMEncoding encoding) {
4168 #if 0
4169  // ARM pseudo code...
4170  if ConditionPassed() then
4171  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4172  address = R[n] - 4*BitCount(registers);
4173 
4174  for i = 0 to 14
4175  if registers<i> == '1' then
4176  R[i] = MemA[address,4]; address = address + 4;
4177  if registers<15> == '1' then
4178  LoadWritePC(MemA[address,4]);
4179 
4180  if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4181  if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
4182 #endif
4183 
4184  bool success = false;
4185 
4186  if (ConditionPassed(opcode)) {
4187  uint32_t n;
4188  uint32_t registers = 0;
4189  bool wback;
4190  const uint32_t addr_byte_size = GetAddressByteSize();
4191  switch (encoding) {
4192  case eEncodingT1:
4193  // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
4194  n = Bits32(opcode, 19, 16);
4195  registers = Bits32(opcode, 15, 0);
4196  registers = registers & 0xdfff; // Make sure bit 13 is a zero.
4197  wback = BitIsSet(opcode, 21);
4198 
4199  // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then
4200  // UNPREDICTABLE;
4201  if ((n == 15) || (BitCount(registers) < 2) ||
4202  (BitIsSet(opcode, 14) && BitIsSet(opcode, 15)))
4203  return false;
4204 
4205  // if registers<15> == '1' && InITBlock() && !LastInITBlock() then
4206  // UNPREDICTABLE;
4207  if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
4208  return false;
4209 
4210  // if wback && registers<n> == '1' then UNPREDICTABLE;
4211  if (wback && BitIsSet(registers, n))
4212  return false;
4213 
4214  break;
4215 
4216  case eEncodingA1:
4217  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4218  n = Bits32(opcode, 19, 16);
4219  registers = Bits32(opcode, 15, 0);
4220  wback = BitIsSet(opcode, 21);
4221 
4222  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4223  if ((n == 15) || (BitCount(registers) < 1))
4224  return false;
4225 
4226  break;
4227 
4228  default:
4229  return false;
4230  }
4231 
4232  // address = R[n] - 4*BitCount(registers);
4233 
4234  int32_t offset = 0;
4235  addr_t Rn =
4236  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4237 
4238  if (!success)
4239  return false;
4240 
4241  addr_t address = Rn - (addr_byte_size * BitCount(registers));
4243  context.type = EmulateInstruction::eContextRegisterPlusOffset;
4244  RegisterInfo dwarf_reg;
4245  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
4246  context.SetRegisterPlusOffset(dwarf_reg, Rn - address);
4247 
4248  for (int i = 0; i < 14; ++i) {
4249  if (BitIsSet(registers, i)) {
4250  // R[i] = MemA[address,4]; address = address + 4;
4251  context.SetRegisterPlusOffset(dwarf_reg, Rn - (address + offset));
4252  uint32_t data =
4253  MemARead(context, address + offset, addr_byte_size, 0, &success);
4254  if (!success)
4255  return false;
4256 
4257  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
4258  data))
4259  return false;
4260 
4261  offset += addr_byte_size;
4262  }
4263  }
4264 
4265  // if registers<15> == '1' then
4266  // LoadWritePC(MemA[address,4]);
4267  if (BitIsSet(registers, 15)) {
4268  context.SetRegisterPlusOffset(dwarf_reg, offset);
4269  uint32_t data =
4270  MemARead(context, address + offset, addr_byte_size, 0, &success);
4271  if (!success)
4272  return false;
4273  // In ARMv5T and above, this is an interworking branch.
4274  if (!LoadWritePC(context, data))
4275  return false;
4276  }
4277 
4278  // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4279  if (wback && BitIsClear(registers, n)) {
4280  if (!success)
4281  return false;
4282 
4283  offset = (addr_byte_size * BitCount(registers)) * -1;
4284  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4285  context.SetImmediateSigned(offset);
4286  addr_t addr = Rn + offset;
4287  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4288  addr))
4289  return false;
4290  }
4291 
4292  // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only
4293  // possible for encoding A1
4294  if (wback && BitIsSet(registers, n))
4295  return WriteBits32Unknown(n);
4296  }
4297  return true;
4298 }
4299 
4300 // LDMIB loads multiple registers from consecutive memory locations using an
4301 // address from a base register. The
4302 // consecutive memory locations start just above this address, and thea ddress
4303 // of the last of those locations can optinoally be written back to the base
4304 // register.
4305 bool EmulateInstructionARM::EmulateLDMIB(const uint32_t opcode,
4306  const ARMEncoding encoding) {
4307 #if 0
4308  if ConditionPassed() then
4309  EncodingSpecificOperations();
4310  address = R[n] + 4;
4311 
4312  for i = 0 to 14
4313  if registers<i> == '1' then
4314  R[i] = MemA[address,4]; address = address + 4;
4315  if registers<15> == '1' then
4316  LoadWritePC(MemA[address,4]);
4317 
4318  if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
4319  if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
4320 #endif
4321 
4322  bool success = false;
4323 
4324  if (ConditionPassed(opcode)) {
4325  uint32_t n;
4326  uint32_t registers = 0;
4327  bool wback;
4328  const uint32_t addr_byte_size = GetAddressByteSize();
4329  switch (encoding) {
4330  case eEncodingA1:
4331  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4332  n = Bits32(opcode, 19, 16);
4333  registers = Bits32(opcode, 15, 0);
4334  wback = BitIsSet(opcode, 21);
4335 
4336  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4337  if ((n == 15) || (BitCount(registers) < 1))
4338  return false;
4339 
4340  break;
4341  default:
4342  return false;
4343  }
4344  // address = R[n] + 4;
4345 
4346  int32_t offset = 0;
4347  addr_t Rn =
4348  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4349 
4350  if (!success)
4351  return false;
4352 
4353  addr_t address = Rn + addr_byte_size;
4354 
4356  context.type = EmulateInstruction::eContextRegisterPlusOffset;
4357  RegisterInfo dwarf_reg;
4358  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
4359  context.SetRegisterPlusOffset(dwarf_reg, offset);
4360 
4361  for (int i = 0; i < 14; ++i) {
4362  if (BitIsSet(registers, i)) {
4363  // R[i] = MemA[address,4]; address = address + 4;
4364 
4365  context.SetRegisterPlusOffset(dwarf_reg, offset + addr_byte_size);
4366  uint32_t data =
4367  MemARead(context, address + offset, addr_byte_size, 0, &success);
4368  if (!success)
4369  return false;
4370 
4371  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
4372  data))
4373  return false;
4374 
4375  offset += addr_byte_size;
4376  }
4377  }
4378 
4379  // if registers<15> == '1' then
4380  // LoadWritePC(MemA[address,4]);
4381  if (BitIsSet(registers, 15)) {
4382  context.SetRegisterPlusOffset(dwarf_reg, offset);
4383  uint32_t data =
4384  MemARead(context, address + offset, addr_byte_size, 0, &success);
4385  if (!success)
4386  return false;
4387  // In ARMv5T and above, this is an interworking branch.
4388  if (!LoadWritePC(context, data))
4389  return false;
4390  }
4391 
4392  // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
4393  if (wback && BitIsClear(registers, n)) {
4394  if (!success)
4395  return false;
4396 
4397  offset = addr_byte_size * BitCount(registers);
4398  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4399  context.SetImmediateSigned(offset);
4400  addr_t addr = Rn + offset;
4401  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4402  addr))
4403  return false;
4404  }
4405 
4406  // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only
4407  // possible for encoding A1
4408  if (wback && BitIsSet(registers, n))
4409  return WriteBits32Unknown(n);
4410  }
4411  return true;
4412 }
4413 
4414 // Load Register (immediate) calculates an address from a base register value
4415 // and an immediate offset, loads a word from memory, and writes to a register.
4416 // LDR (immediate, Thumb)
4417 bool EmulateInstructionARM::EmulateLDRRtRnImm(const uint32_t opcode,
4418  const ARMEncoding encoding) {
4419 #if 0
4420  // ARM pseudo code...
4421  if (ConditionPassed())
4422  {
4423  EncodingSpecificOperations(); NullCheckIfThumbEE(15);
4424  offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4425  address = if index then offset_addr else R[n];
4426  data = MemU[address,4];
4427  if wback then R[n] = offset_addr;
4428  if t == 15 then
4429  if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
4430  elsif UnalignedSupport() || address<1:0> = '00' then
4431  R[t] = data;
4432  else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7
4433  }
4434 #endif
4435 
4436  bool success = false;
4437 
4438  if (ConditionPassed(opcode)) {
4439  uint32_t Rt; // the destination register
4440  uint32_t Rn; // the base register
4441  uint32_t imm32; // the immediate offset used to form the address
4442  addr_t offset_addr; // the offset address
4443  addr_t address; // the calculated address
4444  uint32_t data; // the literal data value from memory load
4445  bool add, index, wback;
4446  switch (encoding) {
4447  case eEncodingT1:
4448  Rt = Bits32(opcode, 2, 0);
4449  Rn = Bits32(opcode, 5, 3);
4450  imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32);
4451  // index = TRUE; add = TRUE; wback = FALSE
4452  add = true;
4453  index = true;
4454  wback = false;
4455 
4456  break;
4457 
4458  case eEncodingT2:
4459  // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
4460  Rt = Bits32(opcode, 10, 8);
4461  Rn = 13;
4462  imm32 = Bits32(opcode, 7, 0) << 2;
4463 
4464  // index = TRUE; add = TRUE; wback = FALSE;
4465  index = true;
4466  add = true;
4467  wback = false;
4468 
4469  break;
4470 
4471  case eEncodingT3:
4472  // if Rn == '1111' then SEE LDR (literal);
4473  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4474  Rt = Bits32(opcode, 15, 12);
4475  Rn = Bits32(opcode, 19, 16);
4476  imm32 = Bits32(opcode, 11, 0);
4477 
4478  // index = TRUE; add = TRUE; wback = FALSE;
4479  index = true;
4480  add = true;
4481  wback = false;
4482 
4483  // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
4484  if ((Rt == 15) && InITBlock() && !LastInITBlock())
4485  return false;
4486 
4487  break;
4488 
4489  case eEncodingT4:
4490  // if Rn == '1111' then SEE LDR (literal);
4491  // if P == '1' && U == '1' && W == '0' then SEE LDRT;
4492  // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 ==
4493  // '00000100' then SEE POP;
4494  // if P == '0' && W == '0' then UNDEFINED;
4495  if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))
4496  return false;
4497 
4498  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
4499  Rt = Bits32(opcode, 15, 12);
4500  Rn = Bits32(opcode, 19, 16);
4501  imm32 = Bits32(opcode, 7, 0);
4502 
4503  // index = (P == '1'); add = (U == '1'); wback = (W == '1');
4504  index = BitIsSet(opcode, 10);
4505  add = BitIsSet(opcode, 9);
4506  wback = BitIsSet(opcode, 8);
4507 
4508  // if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock())
4509  // then UNPREDICTABLE;
4510  if ((wback && (Rn == Rt)) ||
4511  ((Rt == 15) && InITBlock() && !LastInITBlock()))
4512  return false;
4513 
4514  break;
4515 
4516  default:
4517  return false;
4518  }
4519  uint32_t base = ReadCoreReg(Rn, &success);
4520  if (!success)
4521  return false;
4522  if (add)
4523  offset_addr = base + imm32;
4524  else
4525  offset_addr = base - imm32;
4526 
4527  address = (index ? offset_addr : base);
4528 
4529  RegisterInfo base_reg;
4530  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
4531  if (wback) {
4533  if (Rn == 13) {
4534  ctx.type = eContextAdjustStackPointer;
4535  ctx.SetImmediateSigned((int32_t)(offset_addr - base));
4536  } else if (Rn == GetFramePointerRegisterNumber()) {
4537  ctx.type = eContextSetFramePointer;
4538  ctx.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base));
4539  } else {
4540  ctx.type = EmulateInstruction::eContextAdjustBaseRegister;
4541  ctx.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base));
4542  }
4543 
4544  if (!WriteRegisterUnsigned(ctx, eRegisterKindDWARF, dwarf_r0 + Rn,
4545  offset_addr))
4546  return false;
4547  }
4548 
4549  // Prepare to write to the Rt register.
4551  context.type = EmulateInstruction::eContextRegisterLoad;
4552  context.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base));
4553 
4554  // Read memory from the address.
4555  data = MemURead(context, address, 4, 0, &success);
4556  if (!success)
4557  return false;
4558 
4559  if (Rt == 15) {
4560  if (Bits32(address, 1, 0) == 0) {
4561  if (!LoadWritePC(context, data))
4562  return false;
4563  } else
4564  return false;
4565  } else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) {
4566  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rt,
4567  data))
4568  return false;
4569  } else
4570  WriteBits32Unknown(Rt);
4571  }
4572  return true;
4573 }
4574 
4575 // STM (Store Multiple Increment After) stores multiple registers to consecutive
4576 // memory locations using an address
4577 // from a base register. The consecutive memory locations start at this
4578 // address, and the address just above the last of those locations can
4579 // optionally be written back to the base register.
4580 bool EmulateInstructionARM::EmulateSTM(const uint32_t opcode,
4581  const ARMEncoding encoding) {
4582 #if 0
4583  if ConditionPassed() then
4584  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4585  address = R[n];
4586 
4587  for i = 0 to 14
4588  if registers<i> == '1' then
4589  if i == n && wback && i != LowestSetBit(registers) then
4590  MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
4591  else
4592  MemA[address,4] = R[i];
4593  address = address + 4;
4594 
4595  if registers<15> == '1' then // Only possible for encoding A1
4596  MemA[address,4] = PCStoreValue();
4597  if wback then R[n] = R[n] + 4*BitCount(registers);
4598 #endif
4599 
4600  bool success = false;
4601 
4602  if (ConditionPassed(opcode)) {
4603  uint32_t n;
4604  uint32_t registers = 0;
4605  bool wback;
4606  const uint32_t addr_byte_size = GetAddressByteSize();
4607 
4608  // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4609  switch (encoding) {
4610  case eEncodingT1:
4611  // n = UInt(Rn); registers = '00000000':register_list; wback = TRUE;
4612  n = Bits32(opcode, 10, 8);
4613  registers = Bits32(opcode, 7, 0);
4614  registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
4615  wback = true;
4616 
4617  // if BitCount(registers) < 1 then UNPREDICTABLE;
4618  if (BitCount(registers) < 1)
4619  return false;
4620 
4621  break;
4622 
4623  case eEncodingT2:
4624  // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4625  n = Bits32(opcode, 19, 16);
4626  registers = Bits32(opcode, 15, 0);
4627  registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4628  wback = BitIsSet(opcode, 21);
4629 
4630  // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4631  if ((n == 15) || (BitCount(registers) < 2))
4632  return false;
4633 
4634  // if wback && registers<n> == '1' then UNPREDICTABLE;
4635  if (wback && BitIsSet(registers, n))
4636  return false;
4637 
4638  break;
4639 
4640  case eEncodingA1:
4641  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4642  n = Bits32(opcode, 19, 16);
4643  registers = Bits32(opcode, 15, 0);
4644  wback = BitIsSet(opcode, 21);
4645 
4646  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4647  if ((n == 15) || (BitCount(registers) < 1))
4648  return false;
4649 
4650  break;
4651 
4652  default:
4653  return false;
4654  }
4655 
4656  // address = R[n];
4657  int32_t offset = 0;
4658  const addr_t address =
4659  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4660  if (!success)
4661  return false;
4662 
4664  context.type = EmulateInstruction::eContextRegisterStore;
4665  RegisterInfo base_reg;
4666  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4667 
4668  // for i = 0 to 14
4669  uint32_t lowest_set_bit = 14;
4670  for (uint32_t i = 0; i < 14; ++i) {
4671  // if registers<i> == '1' then
4672  if (BitIsSet(registers, i)) {
4673  if (i < lowest_set_bit)
4674  lowest_set_bit = i;
4675  // if i == n && wback && i != LowestSetBit(registers) then
4676  if ((i == n) && wback && (i != lowest_set_bit))
4677  // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings
4678  // T1 and A1
4679  WriteBits32UnknownToMemory(address + offset);
4680  else {
4681  // MemA[address,4] = R[i];
4682  uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
4683  0, &success);
4684  if (!success)
4685  return false;
4686 
4687  RegisterInfo data_reg;
4688  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4689  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, offset);
4690  if (!MemAWrite(context, address + offset, data, addr_byte_size))
4691  return false;
4692  }
4693 
4694  // address = address + 4;
4695  offset += addr_byte_size;
4696  }
4697  }
4698 
4699  // if registers<15> == '1' then // Only possible for encoding A1
4700  // MemA[address,4] = PCStoreValue();
4701  if (BitIsSet(registers, 15)) {
4702  RegisterInfo pc_reg;
4703  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
4704  context.SetRegisterPlusOffset(pc_reg, 8);
4705  const uint32_t pc = ReadCoreReg(PC_REG, &success);
4706  if (!success)
4707  return false;
4708 
4709  if (!MemAWrite(context, address + offset, pc, addr_byte_size))
4710  return false;
4711  }
4712 
4713  // if wback then R[n] = R[n] + 4*BitCount(registers);
4714  if (wback) {
4715  offset = addr_byte_size * BitCount(registers);
4716  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4717  context.SetImmediateSigned(offset);
4718  addr_t data = address + offset;
4719  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4720  data))
4721  return false;
4722  }
4723  }
4724  return true;
4725 }
4726 
4727 // STMDA (Store Multiple Decrement After) stores multiple registers to
4728 // consecutive memory locations using an address from a base register. The
4729 // consecutive memory locations end at this address, and the address just below
4730 // the lowest of those locations can optionally be written back to the base
4731 // register.
4732 bool EmulateInstructionARM::EmulateSTMDA(const uint32_t opcode,
4733  const ARMEncoding encoding) {
4734 #if 0
4735  if ConditionPassed() then
4736  EncodingSpecificOperations();
4737  address = R[n] - 4*BitCount(registers) + 4;
4738 
4739  for i = 0 to 14
4740  if registers<i> == '1' then
4741  if i == n && wback && i != LowestSetBit(registers) then
4742  MemA[address,4] = bits(32) UNKNOWN;
4743  else
4744  MemA[address,4] = R[i];
4745  address = address + 4;
4746 
4747  if registers<15> == '1' then
4748  MemA[address,4] = PCStoreValue();
4749 
4750  if wback then R[n] = R[n] - 4*BitCount(registers);
4751 #endif
4752 
4753  bool success = false;
4754 
4755  if (ConditionPassed(opcode)) {
4756  uint32_t n;
4757  uint32_t registers = 0;
4758  bool wback;
4759  const uint32_t addr_byte_size = GetAddressByteSize();
4760 
4761  // EncodingSpecificOperations();
4762  switch (encoding) {
4763  case eEncodingA1:
4764  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4765  n = Bits32(opcode, 19, 16);
4766  registers = Bits32(opcode, 15, 0);
4767  wback = BitIsSet(opcode, 21);
4768 
4769  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4770  if ((n == 15) || (BitCount(registers) < 1))
4771  return false;
4772  break;
4773  default:
4774  return false;
4775  }
4776 
4777  // address = R[n] - 4*BitCount(registers) + 4;
4778  int32_t offset = 0;
4779  addr_t Rn = ReadCoreReg(n, &success);
4780  if (!success)
4781  return false;
4782 
4783  addr_t address = Rn - (addr_byte_size * BitCount(registers)) + 4;
4784 
4786  context.type = EmulateInstruction::eContextRegisterStore;
4787  RegisterInfo base_reg;
4788  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4789 
4790  // for i = 0 to 14
4791  uint32_t lowest_bit_set = 14;
4792  for (uint32_t i = 0; i < 14; ++i) {
4793  // if registers<i> == '1' then
4794  if (BitIsSet(registers, i)) {
4795  if (i < lowest_bit_set)
4796  lowest_bit_set = i;
4797  // if i == n && wback && i != LowestSetBit(registers) then
4798  if ((i == n) && wback && (i != lowest_bit_set))
4799  // MemA[address,4] = bits(32) UNKNOWN;
4800  WriteBits32UnknownToMemory(address + offset);
4801  else {
4802  // MemA[address,4] = R[i];
4803  uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
4804  0, &success);
4805  if (!success)
4806  return false;
4807 
4808  RegisterInfo data_reg;
4809  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4810  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
4811  Rn - (address + offset));
4812  if (!MemAWrite(context, address + offset, data, addr_byte_size))
4813  return false;
4814  }
4815 
4816  // address = address + 4;
4817  offset += addr_byte_size;
4818  }
4819  }
4820 
4821  // if registers<15> == '1' then
4822  // MemA[address,4] = PCStoreValue();
4823  if (BitIsSet(registers, 15)) {
4824  RegisterInfo pc_reg;
4825  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
4826  context.SetRegisterPlusOffset(pc_reg, 8);
4827  const uint32_t pc = ReadCoreReg(PC_REG, &success);
4828  if (!success)
4829  return false;
4830 
4831  if (!MemAWrite(context, address + offset, pc, addr_byte_size))
4832  return false;
4833  }
4834 
4835  // if wback then R[n] = R[n] - 4*BitCount(registers);
4836  if (wback) {
4837  offset = (addr_byte_size * BitCount(registers)) * -1;
4838  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4839  context.SetImmediateSigned(offset);
4840  addr_t data = Rn + offset;
4841  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4842  data))
4843  return false;
4844  }
4845  }
4846  return true;
4847 }
4848 
4849 // STMDB (Store Multiple Decrement Before) stores multiple registers to
4850 // consecutive memory locations using an address from a base register. The
4851 // consecutive memory locations end just below this address, and the address of
4852 // the first of those locations can optionally be written back to the base
4853 // register.
4854 bool EmulateInstructionARM::EmulateSTMDB(const uint32_t opcode,
4855  const ARMEncoding encoding) {
4856 #if 0
4857  if ConditionPassed() then
4858  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4859  address = R[n] - 4*BitCount(registers);
4860 
4861  for i = 0 to 14
4862  if registers<i> == '1' then
4863  if i == n && wback && i != LowestSetBit(registers) then
4864  MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
4865  else
4866  MemA[address,4] = R[i];
4867  address = address + 4;
4868 
4869  if registers<15> == '1' then // Only possible for encoding A1
4870  MemA[address,4] = PCStoreValue();
4871 
4872  if wback then R[n] = R[n] - 4*BitCount(registers);
4873 #endif
4874 
4875  bool success = false;
4876 
4877  if (ConditionPassed(opcode)) {
4878  uint32_t n;
4879  uint32_t registers = 0;
4880  bool wback;
4881  const uint32_t addr_byte_size = GetAddressByteSize();
4882 
4883  // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4884  switch (encoding) {
4885  case eEncodingT1:
4886  // if W == '1' && Rn == '1101' then SEE PUSH;
4887  if ((BitIsSet(opcode, 21)) && (Bits32(opcode, 19, 16) == 13)) {
4888  // See PUSH
4889  }
4890  // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4891  n = Bits32(opcode, 19, 16);
4892  registers = Bits32(opcode, 15, 0);
4893  registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4894  wback = BitIsSet(opcode, 21);
4895  // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4896  if ((n == 15) || BitCount(registers) < 2)
4897  return false;
4898  // if wback && registers<n> == '1' then UNPREDICTABLE;
4899  if (wback && BitIsSet(registers, n))
4900  return false;
4901  break;
4902 
4903  case eEncodingA1:
4904  // if W == '1' && Rn == '1101' && BitCount(register_list) >= 2 then SEE
4905  // PUSH;
4906  if (BitIsSet(opcode, 21) && (Bits32(opcode, 19, 16) == 13) &&
4907  BitCount(Bits32(opcode, 15, 0)) >= 2) {
4908  // See Push
4909  }
4910  // n = UInt(Rn); registers = register_list; wback = (W == '1');
4911  n = Bits32(opcode, 19, 16);
4912  registers = Bits32(opcode, 15, 0);
4913  wback = BitIsSet(opcode, 21);
4914  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4915  if ((n == 15) || BitCount(registers) < 1)
4916  return false;
4917  break;
4918 
4919  default:
4920  return false;
4921  }
4922 
4923  // address = R[n] - 4*BitCount(registers);
4924 
4925  int32_t offset = 0;
4926  addr_t Rn =
4927  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4928  if (!success)
4929  return false;
4930 
4931  addr_t address = Rn - (addr_byte_size * BitCount(registers));
4932 
4934  context.type = EmulateInstruction::eContextRegisterStore;
4935  RegisterInfo base_reg;
4936  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4937 
4938  // for i = 0 to 14
4939  uint32_t lowest_set_bit = 14;
4940  for (uint32_t i = 0; i < 14; ++i) {
4941  // if registers<i> == '1' then
4942  if (BitIsSet(registers, i)) {
4943  if (i < lowest_set_bit)
4944  lowest_set_bit = i;
4945  // if i == n && wback && i != LowestSetBit(registers) then
4946  if ((i == n) && wback && (i != lowest_set_bit))
4947  // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding
4948  // A1
4949  WriteBits32UnknownToMemory(address + offset);
4950  else {
4951  // MemA[address,4] = R[i];
4952  uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
4953  0, &success);
4954  if (!success)
4955  return false;
4956 
4957  RegisterInfo data_reg;
4958  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4959  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
4960  Rn - (address + offset));
4961  if (!MemAWrite(context, address + offset, data, addr_byte_size))
4962  return false;
4963  }
4964 
4965  // address = address + 4;
4966  offset += addr_byte_size;
4967  }
4968  }
4969 
4970  // if registers<15> == '1' then // Only possible for encoding A1
4971  // MemA[address,4] = PCStoreValue();
4972  if (BitIsSet(registers, 15)) {
4973  RegisterInfo pc_reg;
4974  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
4975  context.SetRegisterPlusOffset(pc_reg, 8);
4976  const uint32_t pc = ReadCoreReg(PC_REG, &success);
4977  if (!success)
4978  return false;
4979 
4980  if (!MemAWrite(context, address + offset, pc, addr_byte_size))
4981  return false;
4982  }
4983 
4984  // if wback then R[n] = R[n] - 4*BitCount(registers);
4985  if (wback) {
4986  offset = (addr_byte_size * BitCount(registers)) * -1;
4987  context.type = EmulateInstruction::eContextAdjustBaseRegister;
4988  context.SetImmediateSigned(offset);
4989  addr_t data = Rn + offset;
4990  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
4991  data))
4992  return false;
4993  }
4994  }
4995  return true;
4996 }
4997 
4998 // STMIB (Store Multiple Increment Before) stores multiple registers to
4999 // consecutive memory locations using an address from a base register. The
5000 // consecutive memory locations start just above this address, and the address
5001 // of the last of those locations can optionally be written back to the base
5002 // register.
5003 bool EmulateInstructionARM::EmulateSTMIB(const uint32_t opcode,
5004  const ARMEncoding encoding) {
5005 #if 0
5006  if ConditionPassed() then
5007  EncodingSpecificOperations();
5008  address = R[n] + 4;
5009 
5010  for i = 0 to 14
5011  if registers<i> == '1' then
5012  if i == n && wback && i != LowestSetBit(registers) then
5013  MemA[address,4] = bits(32) UNKNOWN;
5014  else
5015  MemA[address,4] = R[i];
5016  address = address + 4;
5017 
5018  if registers<15> == '1' then
5019  MemA[address,4] = PCStoreValue();
5020 
5021  if wback then R[n] = R[n] + 4*BitCount(registers);
5022 #endif
5023 
5024  bool success = false;
5025 
5026  if (ConditionPassed(opcode)) {
5027  uint32_t n;
5028  uint32_t registers = 0;
5029  bool wback;
5030  const uint32_t addr_byte_size = GetAddressByteSize();
5031 
5032  // EncodingSpecificOperations();
5033  switch (encoding) {
5034  case eEncodingA1:
5035  // n = UInt(Rn); registers = register_list; wback = (W == '1');
5036  n = Bits32(opcode, 19, 16);
5037  registers = Bits32(opcode, 15, 0);
5038  wback = BitIsSet(opcode, 21);
5039 
5040  // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
5041  if ((n == 15) && (BitCount(registers) < 1))
5042  return false;
5043  break;
5044  default:
5045  return false;
5046  }
5047  // address = R[n] + 4;
5048 
5049  int32_t offset = 0;
5050  addr_t Rn = ReadCoreReg(n, &success);
5051  if (!success)
5052  return false;
5053 
5054  addr_t address = Rn + addr_byte_size;
5055 
5057  context.type = EmulateInstruction::eContextRegisterStore;
5058  RegisterInfo base_reg;
5059  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5060 
5061  uint32_t lowest_set_bit = 14;
5062  // for i = 0 to 14
5063  for (uint32_t i = 0; i < 14; ++i) {
5064  // if registers<i> == '1' then
5065  if (BitIsSet(registers, i)) {
5066  if (i < lowest_set_bit)
5067  lowest_set_bit = i;
5068  // if i == n && wback && i != LowestSetBit(registers) then
5069  if ((i == n) && wback && (i != lowest_set_bit))
5070  // MemA[address,4] = bits(32) UNKNOWN;
5071  WriteBits32UnknownToMemory(address + offset);
5072  // else
5073  else {
5074  // MemA[address,4] = R[i];
5075  uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
5076  0, &success);
5077  if (!success)
5078  return false;
5079 
5080  RegisterInfo data_reg;
5081  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg);
5082  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
5083  offset + addr_byte_size);
5084  if (!MemAWrite(context, address + offset, data, addr_byte_size))
5085  return false;
5086  }
5087 
5088  // address = address + 4;
5089  offset += addr_byte_size;
5090  }
5091  }
5092 
5093  // if registers<15> == '1' then
5094  // MemA[address,4] = PCStoreValue();
5095  if (BitIsSet(registers, 15)) {
5096  RegisterInfo pc_reg;
5097  GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg);
5098  context.SetRegisterPlusOffset(pc_reg, 8);
5099  const uint32_t pc = ReadCoreReg(PC_REG, &success);
5100  if (!success)
5101  return false;
5102 
5103  if (!MemAWrite(context, address + offset, pc, addr_byte_size))
5104  return false;
5105  }
5106 
5107  // if wback then R[n] = R[n] + 4*BitCount(registers);
5108  if (wback) {
5109  offset = addr_byte_size * BitCount(registers);
5110  context.type = EmulateInstruction::eContextAdjustBaseRegister;
5111  context.SetImmediateSigned(offset);
5112  addr_t data = Rn + offset;
5113  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5114  data))
5115  return false;
5116  }
5117  }
5118  return true;
5119 }
5120 
5121 // STR (store immediate) calculates an address from a base register value and an
5122 // immediate offset, and stores a word
5123 // from a register to memory. It can use offset, post-indexed, or pre-indexed
5124 // addressing.
5125 bool EmulateInstructionARM::EmulateSTRThumb(const uint32_t opcode,
5126  const ARMEncoding encoding) {
5127 #if 0
5128  if ConditionPassed() then
5129  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5130  offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5131  address = if index then offset_addr else R[n];
5132  if UnalignedSupport() || address<1:0> == '00' then
5133  MemU[address,4] = R[t];
5134  else // Can only occur before ARMv7
5135  MemU[address,4] = bits(32) UNKNOWN;
5136  if wback then R[n] = offset_addr;
5137 #endif
5138 
5139  bool success = false;
5140 
5141  if (ConditionPassed(opcode)) {
5142  const uint32_t addr_byte_size = GetAddressByteSize();
5143 
5144  uint32_t t;
5145  uint32_t n;
5146  uint32_t imm32;
5147  bool index;
5148  bool add;
5149  bool wback;
5150  // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
5151  switch (encoding) {
5152  case eEncodingT1:
5153  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
5154  t = Bits32(opcode, 2, 0);
5155  n = Bits32(opcode, 5, 3);
5156  imm32 = Bits32(opcode, 10, 6) << 2;
5157 
5158  // index = TRUE; add = TRUE; wback = FALSE;
5159  index = true;
5160  add = false;
5161  wback = false;
5162  break;
5163 
5164  case eEncodingT2:
5165  // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
5166  t = Bits32(opcode, 10, 8);
5167  n = 13;
5168  imm32 = Bits32(opcode, 7, 0) << 2;
5169 
5170  // index = TRUE; add = TRUE; wback = FALSE;
5171  index = true;
5172  add = true;
5173  wback = false;
5174  break;
5175 
5176  case eEncodingT3:
5177  // if Rn == '1111' then UNDEFINED;
5178  if (Bits32(opcode, 19, 16) == 15)
5179  return false;
5180 
5181  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5182  t = Bits32(opcode, 15, 12);
5183  n = Bits32(opcode, 19, 16);
5184  imm32 = Bits32(opcode, 11, 0);
5185 
5186  // index = TRUE; add = TRUE; wback = FALSE;
5187  index = true;
5188  add = true;
5189  wback = false;
5190 
5191  // if t == 15 then UNPREDICTABLE;
5192  if (t == 15)
5193  return false;
5194  break;
5195 
5196  case eEncodingT4:
5197  // if P == '1' && U == '1' && W == '0' then SEE STRT;
5198  // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 ==
5199  // '00000100' then SEE PUSH;
5200  // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
5201  if ((Bits32(opcode, 19, 16) == 15) ||
5202  (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)))
5203  return false;
5204 
5205  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5206  t = Bits32(opcode, 15, 12);
5207  n = Bits32(opcode, 19, 16);
5208  imm32 = Bits32(opcode, 7, 0);
5209 
5210  // index = (P == '1'); add = (U == '1'); wback = (W == '1');
5211  index = BitIsSet(opcode, 10);
5212  add = BitIsSet(opcode, 9);
5213  wback = BitIsSet(opcode, 8);
5214 
5215  // if t == 15 || (wback && n == t) then UNPREDICTABLE;
5216  if ((t == 15) || (wback && (n == t)))
5217  return false;
5218  break;
5219 
5220  default:
5221  return false;
5222  }
5223 
5224  addr_t offset_addr;
5225  addr_t address;
5226 
5227  // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5228  uint32_t base_address = ReadCoreReg(n, &success);
5229  if (!success)
5230  return false;
5231 
5232  if (add)
5233  offset_addr = base_address + imm32;
5234  else
5235  offset_addr = base_address - imm32;
5236 
5237  // address = if index then offset_addr else R[n];
5238  if (index)
5239  address = offset_addr;
5240  else
5241  address = base_address;
5242 
5244  if (n == 13)
5245  context.type = eContextPushRegisterOnStack;
5246  else
5247  context.type = eContextRegisterStore;
5248 
5249  RegisterInfo base_reg;
5250  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5251 
5252  // if UnalignedSupport() || address<1:0> == '00' then
5253  if (UnalignedSupport() ||
5254  (BitIsClear(address, 1) && BitIsClear(address, 0))) {
5255  // MemU[address,4] = R[t];
5256  uint32_t data =
5257  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5258  if (!success)
5259  return false;
5260 
5261  RegisterInfo data_reg;
5262  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5263  int32_t offset = address - base_address;
5264  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, offset);
5265  if (!MemUWrite(context, address, data, addr_byte_size))
5266  return false;
5267  } else {
5268  // MemU[address,4] = bits(32) UNKNOWN;
5269  WriteBits32UnknownToMemory(address);
5270  }
5271 
5272  // if wback then R[n] = offset_addr;
5273  if (wback) {
5274  if (n == 13)
5275  context.type = eContextAdjustStackPointer;
5276  else
5277  context.type = eContextAdjustBaseRegister;
5278  context.SetAddress(offset_addr);
5279 
5280  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5281  offset_addr))
5282  return false;
5283  }
5284  }
5285  return true;
5286 }
5287 
5288 // STR (Store Register) calculates an address from a base register value and an
5289 // offset register value, stores a
5290 // word from a register to memory. The offset register value can optionally
5291 // be shifted.
5292 bool EmulateInstructionARM::EmulateSTRRegister(const uint32_t opcode,
5293  const ARMEncoding encoding) {
5294 #if 0
5295  if ConditionPassed() then
5296  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5297  offset = Shift(R[m], shift_t, shift_n, APSR.C);
5298  offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5299  address = if index then offset_addr else R[n];
5300  if t == 15 then // Only possible for encoding A1
5301  data = PCStoreValue();
5302  else
5303  data = R[t];
5304  if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
5305  MemU[address,4] = data;
5306  else // Can only occur before ARMv7
5307  MemU[address,4] = bits(32) UNKNOWN;
5308  if wback then R[n] = offset_addr;
5309 #endif
5310 
5311  bool success = false;
5312 
5313  if (ConditionPassed(opcode)) {
5314  const uint32_t addr_byte_size = GetAddressByteSize();
5315 
5316  uint32_t t;
5317  uint32_t n;
5318  uint32_t m;
5319  ARM_ShifterType shift_t;
5320  uint32_t shift_n;
5321  bool index;
5322  bool add;
5323  bool wback;
5324 
5325  // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
5326  switch (encoding) {
5327  case eEncodingT1:
5328  // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation
5329  // in ThumbEE";
5330  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5331  t = Bits32(opcode, 2, 0);
5332  n = Bits32(opcode, 5, 3);
5333  m = Bits32(opcode, 8, 6);
5334 
5335  // index = TRUE; add = TRUE; wback = FALSE;
5336  index = true;
5337  add = true;
5338  wback = false;
5339 
5340  // (shift_t, shift_n) = (SRType_LSL, 0);
5341  shift_t = SRType_LSL;
5342  shift_n = 0;
5343  break;
5344 
5345  case eEncodingT2:
5346  // if Rn == '1111' then UNDEFINED;
5347  if (Bits32(opcode, 19, 16) == 15)
5348  return false;
5349 
5350  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5351  t = Bits32(opcode, 15, 12);
5352  n = Bits32(opcode, 19, 16);
5353  m = Bits32(opcode, 3, 0);
5354 
5355  // index = TRUE; add = TRUE; wback = FALSE;
5356  index = true;
5357  add = true;
5358  wback = false;
5359 
5360  // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
5361  shift_t = SRType_LSL;
5362  shift_n = Bits32(opcode, 5, 4);
5363 
5364  // if t == 15 || BadReg(m) then UNPREDICTABLE;
5365  if ((t == 15) || (BadReg(m)))
5366  return false;
5367  break;
5368 
5369  case eEncodingA1: {
5370  // if P == '0' && W == '1' then SEE STRT;
5371  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5372  t = Bits32(opcode, 15, 12);
5373  n = Bits32(opcode, 19, 16);
5374  m = Bits32(opcode, 3, 0);
5375 
5376  // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
5377  // (W == '1');
5378  index = BitIsSet(opcode, 24);
5379  add = BitIsSet(opcode, 23);
5380  wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
5381 
5382  // (shift_t, shift_n) = DecodeImmShift(type, imm5);
5383  uint32_t typ = Bits32(opcode, 6, 5);
5384  uint32_t imm5 = Bits32(opcode, 11, 7);
5385  shift_n = DecodeImmShift(typ, imm5, shift_t);
5386 
5387  // if m == 15 then UNPREDICTABLE;
5388  if (m == 15)
5389  return false;
5390 
5391  // if wback && (n == 15 || n == t) then UNPREDICTABLE;
5392  if (wback && ((n == 15) || (n == t)))
5393  return false;
5394 
5395  break;
5396  }
5397  default:
5398  return false;
5399  }
5400 
5401  addr_t offset_addr;
5402  addr_t address;
5403  int32_t offset = 0;
5404 
5405  addr_t base_address =
5406  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
5407  if (!success)
5408  return false;
5409 
5410  uint32_t Rm_data =
5411  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
5412  if (!success)
5413  return false;
5414 
5415  // offset = Shift(R[m], shift_t, shift_n, APSR.C);
5416  offset = Shift(Rm_data, shift_t, shift_n, APSR_C, &success);
5417  if (!success)
5418  return false;
5419 
5420  // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5421  if (add)
5422  offset_addr = base_address + offset;
5423  else
5424  offset_addr = base_address - offset;
5425 
5426  // address = if index then offset_addr else R[n];
5427  if (index)
5428  address = offset_addr;
5429  else
5430  address = base_address;
5431 
5432  uint32_t data;
5433  // if t == 15 then // Only possible for encoding A1
5434  if (t == 15)
5435  // data = PCStoreValue();
5436  data = ReadCoreReg(PC_REG, &success);
5437  else
5438  // data = R[t];
5439  data =
5440  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5441 
5442  if (!success)
5443  return false;
5444 
5446  context.type = eContextRegisterStore;
5447 
5448  // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() ==
5449  // InstrSet_ARM then
5450  if (UnalignedSupport() ||
5451  (BitIsClear(address, 1) && BitIsClear(address, 0)) ||
5452  CurrentInstrSet() == eModeARM) {
5453  // MemU[address,4] = data;
5454 
5455  RegisterInfo base_reg;
5456  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5457 
5458  RegisterInfo data_reg;
5459  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5460 
5461  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
5462  address - base_address);
5463  if (!MemUWrite(context, address, data, addr_byte_size))
5464  return false;
5465 
5466  } else
5467  // MemU[address,4] = bits(32) UNKNOWN;
5468  WriteBits32UnknownToMemory(address);
5469 
5470  // if wback then R[n] = offset_addr;
5471  if (wback) {
5472  context.type = eContextRegisterLoad;
5473  context.SetAddress(offset_addr);
5474  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5475  offset_addr))
5476  return false;
5477  }
5478  }
5479  return true;
5480 }
5481 
5482 bool EmulateInstructionARM::EmulateSTRBThumb(const uint32_t opcode,
5483  const ARMEncoding encoding) {
5484 #if 0
5485  if ConditionPassed() then
5486  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5487  offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5488  address = if index then offset_addr else R[n];
5489  MemU[address,1] = R[t]<7:0>;
5490  if wback then R[n] = offset_addr;
5491 #endif
5492 
5493  bool success = false;
5494 
5495  if (ConditionPassed(opcode)) {
5496  uint32_t t;
5497  uint32_t n;
5498  uint32_t imm32;
5499  bool index;
5500  bool add;
5501  bool wback;
5502  // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5503  switch (encoding) {
5504  case eEncodingT1:
5505  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
5506  t = Bits32(opcode, 2, 0);
5507  n = Bits32(opcode, 5, 3);
5508  imm32 = Bits32(opcode, 10, 6);
5509 
5510  // index = TRUE; add = TRUE; wback = FALSE;
5511  index = true;
5512  add = true;
5513  wback = false;
5514  break;
5515 
5516  case eEncodingT2:
5517  // if Rn == '1111' then UNDEFINED;
5518  if (Bits32(opcode, 19, 16) == 15)
5519  return false;
5520 
5521  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5522  t = Bits32(opcode, 15, 12);
5523  n = Bits32(opcode, 19, 16);
5524  imm32 = Bits32(opcode, 11, 0);
5525 
5526  // index = TRUE; add = TRUE; wback = FALSE;
5527  index = true;
5528  add = true;
5529  wback = false;
5530 
5531  // if BadReg(t) then UNPREDICTABLE;
5532  if (BadReg(t))
5533  return false;
5534  break;
5535 
5536  case eEncodingT3:
5537  // if P == '1' && U == '1' && W == '0' then SEE STRBT;
5538  // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
5539  if (Bits32(opcode, 19, 16) == 15)
5540  return false;
5541 
5542  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5543  t = Bits32(opcode, 15, 12);
5544  n = Bits32(opcode, 19, 16);
5545  imm32 = Bits32(opcode, 7, 0);
5546 
5547  // index = (P == '1'); add = (U == '1'); wback = (W == '1');
5548  index = BitIsSet(opcode, 10);
5549  add = BitIsSet(opcode, 9);
5550  wback = BitIsSet(opcode, 8);
5551 
5552  // if BadReg(t) || (wback && n == t) then UNPREDICTABLE
5553  if ((BadReg(t)) || (wback && (n == t)))
5554  return false;
5555  break;
5556 
5557  default:
5558  return false;
5559  }
5560 
5561  addr_t offset_addr;
5562  addr_t address;
5563  addr_t base_address =
5564  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
5565  if (!success)
5566  return false;
5567 
5568  // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5569  if (add)
5570  offset_addr = base_address + imm32;
5571  else
5572  offset_addr = base_address - imm32;
5573 
5574  // address = if index then offset_addr else R[n];
5575  if (index)
5576  address = offset_addr;
5577  else
5578  address = base_address;
5579 
5580  // MemU[address,1] = R[t]<7:0>
5581  RegisterInfo base_reg;
5582  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5583 
5584  RegisterInfo data_reg;
5585  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5586 
5588  context.type = eContextRegisterStore;
5589  context.SetRegisterToRegisterPlusOffset(data_reg, base_reg,
5590  address - base_address);
5591 
5592  uint32_t data =
5593  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5594  if (!success)
5595  return false;
5596 
5597  data = Bits32(data, 7, 0);
5598 
5599  if (!MemUWrite(context, address, data, 1))
5600  return false;
5601 
5602  // if wback then R[n] = offset_addr;
5603  if (wback) {
5604  context.type = eContextRegisterLoad;
5605  context.SetAddress(offset_addr);
5606  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5607  offset_addr))
5608  return false;
5609  }
5610  }
5611 
5612  return true;
5613 }
5614 
5615 // STRH (register) calculates an address from a base register value and an
5616 // offset register value, and stores a
5617 // halfword from a register to memory. The offset register value can be
5618 // shifted left by 0, 1, 2, or 3 bits.
5619 bool EmulateInstructionARM::EmulateSTRHRegister(const uint32_t opcode,
5620  const ARMEncoding encoding) {
5621 #if 0
5622  if ConditionPassed() then
5623  EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5624  offset = Shift(R[m], shift_t, shift_n, APSR.C);
5625  offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5626  address = if index then offset_addr else R[n];
5627  if UnalignedSupport() || address<0> == '0' then
5628  MemU[address,2] = R[t]<15:0>;
5629  else // Can only occur before ARMv7
5630  MemU[address,2] = bits(16) UNKNOWN;
5631  if wback then R[n] = offset_addr;
5632 #endif
5633 
5634  bool success = false;
5635 
5636  if (ConditionPassed(opcode)) {
5637  uint32_t t;
5638  uint32_t n;
5639  uint32_t m;
5640  bool index;
5641  bool add;
5642  bool wback;
5643  ARM_ShifterType shift_t;
5644  uint32_t shift_n;
5645 
5646  // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5647  switch (encoding) {
5648  case eEncodingT1:
5649  // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation
5650  // in ThumbEE";
5651  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5652  t = Bits32(opcode, 2, 0);
5653  n = Bits32(opcode, 5, 3);
5654  m = Bits32(opcode, 8, 6);
5655 
5656  // index = TRUE; add = TRUE; wback = FALSE;
5657  index = true;
5658  add = true;
5659  wback = false;
5660 
5661  // (shift_t, shift_n) = (SRType_LSL, 0);
5662  shift_t = SRType_LSL;
5663  shift_n = 0;
5664 
5665  break;
5666 
5667  case eEncodingT2:
5668  // if Rn == '1111' then UNDEFINED;
5669  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5670  t = Bits32(opcode, 15, 12);
5671  n = Bits32(opcode, 19, 16);
5672  m = Bits32(opcode, 3, 0);
5673  if (n == 15)
5674  return false;
5675 
5676  // index = TRUE; add = TRUE; wback = FALSE;
5677  index = true;
5678  add = true;
5679  wback = false;
5680 
5681  // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
5682  shift_t = SRType_LSL;
5683  shift_n = Bits32(opcode, 5, 4);
5684 
5685  // if BadReg(t) || BadReg(m) then UNPREDICTABLE;
5686  if (BadReg(t) || BadReg(m))
5687  return false;
5688 
5689  break;
5690 
5691  case eEncodingA1:
5692  // if P == '0' && W == '1' then SEE STRHT;
5693  // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5694  t = Bits32(opcode, 15, 12);
5695  n = Bits32(opcode, 19, 16);
5696  m = Bits32(opcode, 3, 0);
5697 
5698  // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
5699  // (W == '1');
5700  index = BitIsSet(opcode, 24);
5701  add = BitIsSet(opcode, 23);
5702  wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
5703 
5704  // (shift_t, shift_n) = (SRType_LSL, 0);
5705  shift_t = SRType_LSL;
5706  shift_n = 0;
5707 
5708  // if t == 15 || m == 15 then UNPREDICTABLE;
5709  if ((t == 15) || (m == 15))
5710  return false;
5711 
5712  // if wback && (n == 15 || n == t) then UNPREDICTABLE;
5713  if (wback && ((n == 15) || (n == t)))
5714  return false;
5715 
5716  break;
5717 
5718  default:
5719  return false;
5720  }
5721 
5722  uint32_t Rm = ReadCoreReg(m, &success);
5723  if (!success)
5724  return false;
5725 
5726  uint32_t Rn = ReadCoreReg(n, &success);
5727  if (!success)
5728  return false;
5729 
5730  // offset = Shift(R[m], shift_t, shift_n, APSR.C);
5731  uint32_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
5732  if (!success)
5733  return false;
5734 
5735  // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5736  addr_t offset_addr;
5737  if (add)
5738  offset_addr = Rn + offset;
5739  else
5740  offset_addr = Rn - offset;
5741 
5742  // address = if index then offset_addr else R[n];
5743  addr_t address;
5744  if (index)
5745  address = offset_addr;
5746  else
5747  address = Rn;
5748 
5750  context.type = eContextRegisterStore;
5751  RegisterInfo base_reg;
5752  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5753  RegisterInfo offset_reg;
5754  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
5755 
5756  // if UnalignedSupport() || address<0> == '0' then
5757  if (UnalignedSupport() || BitIsClear(address, 0)) {
5758  // MemU[address,2] = R[t]<15:0>;
5759  uint32_t Rt = ReadCoreReg(t, &success);
5760  if (!success)
5761  return false;
5762 
5764  context.type = eContextRegisterStore;
5765  RegisterInfo base_reg;
5766  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5767  RegisterInfo offset_reg;
5768  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
5769  RegisterInfo data_reg;
5770  GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5771  context.SetRegisterToRegisterPlusIndirectOffset(base_reg, offset_reg,
5772  data_reg);
5773 
5774  if (!MemUWrite(context, address, Bits32(Rt, 15, 0), 2))
5775  return false;
5776  } else // Can only occur before ARMv7
5777  {
5778  // MemU[address,2] = bits(16) UNKNOWN;
5779  }
5780 
5781  // if wback then R[n] = offset_addr;
5782  if (wback) {
5783  context.type = eContextAdjustBaseRegister;
5784  context.SetAddress(offset_addr);
5785  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
5786  offset_addr))
5787  return false;
5788  }
5789  }
5790 
5791  return true;
5792 }
5793 
5794 // Add with Carry (immediate) adds an immediate value and the carry flag value
5795 // to a register value, and writes the result to the destination register. It
5796 // can optionally update the condition flags based on the result.
5797 bool EmulateInstructionARM::EmulateADCImm(const uint32_t opcode,
5798  const ARMEncoding encoding) {
5799 #if 0
5800  // ARM pseudo code...
5801  if ConditionPassed() then
5802  EncodingSpecificOperations();
5803  (result, carry, overflow) = AddWithCarry(R[n], imm32, APSR.C);
5804  if d == 15 then // Can only occur for ARM encoding
5805  ALUWritePC(result); // setflags is always FALSE here
5806  else
5807  R[d] = result;
5808  if setflags then
5809  APSR.N = result<31>;
5810  APSR.Z = IsZeroBit(result);
5811  APSR.C = carry;
5812  APSR.V = overflow;
5813 #endif
5814 
5815  bool success = false;
5816 
5817  if (ConditionPassed(opcode)) {
5818  uint32_t Rd, Rn;
5819  uint32_t
5820  imm32; // the immediate value to be added to the value obtained from Rn
5821  bool setflags;
5822  switch (encoding) {
5823  case eEncodingT1:
5824  Rd = Bits32(opcode, 11, 8);
5825  Rn = Bits32(opcode, 19, 16);
5826  setflags = BitIsSet(opcode, 20);
5827  imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
5828  if (BadReg(Rd) || BadReg(Rn))
5829  return false;
5830  break;
5831  case eEncodingA1:
5832  Rd = Bits32(opcode, 15, 12);
5833  Rn = Bits32(opcode, 19, 16);
5834  setflags = BitIsSet(opcode, 20);
5835  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5836 
5837  if (Rd == 15 && setflags)
5838  return EmulateSUBSPcLrEtc(opcode, encoding);
5839  break;
5840  default:
5841  return false;
5842  }
5843 
5844  // Read the first operand.
5845  int32_t val1 = ReadCoreReg(Rn, &success);
5846  if (!success)
5847  return false;
5848 
5849  AddWithCarryResult res = AddWithCarry(val1, imm32, APSR_C);
5850 
5852  context.type = EmulateInstruction::eContextImmediate;
5853  context.SetNoArgs();
5854 
5855  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
5856  res.carry_out, res.overflow))
5857  return false;
5858  }
5859  return true;
5860 }
5861 
5862 // Add with Carry (register) adds a register value, the carry flag value, and
5863 // an optionally-shifted register value, and writes the result to the
5864 // destination register. It can optionally update the condition flags based on
5865 // the result.
5866 bool EmulateInstructionARM::EmulateADCReg(const uint32_t opcode,
5867  const ARMEncoding encoding) {
5868 #if 0
5869  // ARM pseudo code...
5870  if ConditionPassed() then
5871  EncodingSpecificOperations();
5872  shifted = Shift(R[m], shift_t, shift_n, APSR.C);
5873  (result, carry, overflow) = AddWithCarry(R[n], shifted, APSR.C);
5874  if d == 15 then // Can only occur for ARM encoding
5875  ALUWritePC(result); // setflags is always FALSE here
5876  else
5877  R[d] = result;
5878  if setflags then
5879  APSR.N = result<31>;
5880  APSR.Z = IsZeroBit(result);
5881  APSR.C = carry;
5882  APSR.V = overflow;
5883 #endif
5884 
5885  bool success = false;
5886 
5887  if (ConditionPassed(opcode)) {
5888  uint32_t Rd, Rn, Rm;
5889  ARM_ShifterType shift_t;
5890  uint32_t shift_n; // the shift applied to the value read from Rm
5891  bool setflags;
5892  switch (encoding) {
5893  case eEncodingT1:
5894  Rd = Rn = Bits32(opcode, 2, 0);
5895  Rm = Bits32(opcode, 5, 3);
5896  setflags = !InITBlock();
5897  shift_t = SRType_LSL;
5898  shift_n = 0;
5899  break;
5900  case eEncodingT2:
5901  Rd = Bits32(opcode, 11, 8);
5902  Rn = Bits32(opcode, 19, 16);
5903  Rm = Bits32(opcode, 3, 0);
5904  setflags = BitIsSet(opcode, 20);
5905  shift_n = DecodeImmShiftThumb(opcode, shift_t);
5906  if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5907  return false;
5908  break;
5909  case eEncodingA1:
5910  Rd = Bits32(opcode, 15, 12);
5911  Rn = Bits32(opcode, 19, 16);
5912  Rm = Bits32(opcode, 3, 0);
5913  setflags = BitIsSet(opcode, 20);
5914  shift_n = DecodeImmShiftARM(opcode, shift_t);
5915 
5916  if (Rd == 15 && setflags)
5917  return EmulateSUBSPcLrEtc(opcode, encoding);
5918  break;
5919  default:
5920  return false;
5921  }
5922 
5923  // Read the first operand.
5924  int32_t val1 = ReadCoreReg(Rn, &success);
5925  if (!success)
5926  return false;
5927 
5928  // Read the second operand.
5929  int32_t val2 = ReadCoreReg(Rm, &success);
5930  if (!success)
5931  return false;
5932 
5933  uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
5934  if (!success)
5935  return false;
5936  AddWithCarryResult res = AddWithCarry(val1, shifted, APSR_C);
5937 
5939  context.type = EmulateInstruction::eContextImmediate;
5940  context.SetNoArgs();
5941 
5942  if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
5943  res.carry_out, res.overflow))
5944  return false;
5945  }
5946  return true;
5947 }
5948 
5949 // This instruction adds an immediate value to the PC value to form a PC-
5950 // relative address, and writes the result to the destination register.
5951 bool EmulateInstructionARM::EmulateADR(const uint32_t opcode,
5952  const ARMEncoding encoding) {
5953 #if 0
5954  // ARM pseudo code...
5955  if ConditionPassed() then
5956  EncodingSpecificOperations();
5957  result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
5958  if d == 15 then // Can only occur for ARM encodings
5959  ALUWritePC(result);
5960  else
5961  R[d] = result;
5962 #endif
5963 
5964  bool success = false;
5965 
5966  if (ConditionPassed(opcode)) {
5967  uint32_t Rd;
5968  uint32_t imm32; // the immediate value to be added/subtracted to/from the PC
5969  bool add;
5970  switch (encoding) {
5971  case eEncodingT1:
5972  Rd = Bits32(opcode, 10, 8);
5973  imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32)
5974  add = true;
5975  break;
5976  case eEncodingT2:
5977  case eEncodingT3:
5978  Rd = Bits32(opcode, 11, 8);
5979  imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
5980  add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB
5981  if (BadReg(Rd))
5982  return false;
5983  break;
5984  case eEncodingA1:
5985  case eEncodingA2:
5986  Rd = Bits32(opcode, 15, 12);
5987  imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5988  add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB
5989  break;
5990  default:
5991  return false;
5992  }
5993 
5994  // Read the PC value.
5995  uint32_t pc = ReadCoreReg(PC_REG, &success);
5996  if (!success)
5997  return false;
5998 
5999  uint32_t result = (add ? Align(pc, 4) + imm32 : Align(pc, 4) - imm32);
6000 
6002  context.type = EmulateInstruction::eContextImmediate;
6003  context.SetNoArgs();
6004 
6005  if (!WriteCoreReg(context, result, Rd))
6006  return false;
6007  }
6008  return true;
6009 }
6010 
6011 // This instruction performs a bitwise AND of a register value and an immediate
6012 // value, and writes the result to the destination register. It can optionally
6013 // update the condition flags based on the result.
6014 bool EmulateInstructionARM::EmulateANDImm(const uint32_t opcode,
6015  const ARMEncoding encoding) {
6016 #if 0
6017  // ARM pseudo code...
6018  if ConditionPassed() then
6019  EncodingSpecificOperations();
6020  result = R[n] AND imm32;
6021  if d == 15 then // Can only occur for ARM encoding
6022  ALUWritePC(result); // setflags is always FALSE here
6023  else
6024  R[d] = result;
6025  if setflags then
6026  APSR.N = result<31>;
6027  APSR.Z = IsZeroBit(result);
6028  APSR.C = carry;
6029  // APSR.V unchanged
6030 #endif
6031 
6032  bool success = false;
6033 
6034  if (ConditionPassed(opcode)) {
6035  uint32_t Rd, Rn;
6036  uint32_t
6037  imm32; // the immediate value to be ANDed to the value obtained from Rn
6038  bool setflags;
6039  uint32_t carry; // the carry bit after ARM/Thumb Expand operation
6040  switch (encoding) {
6041  case eEncodingT1:
6042  Rd = Bits32(opcode, 11, 8);
6043  Rn = Bits32(opcode, 19, 16);
6044  setflags = BitIsSet(opcode, 20);
6045  imm32 = ThumbExpandImm_C(
6046  opcode, APSR_C,
6047  carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
6048  // if Rd == '1111' && S == '1' then SEE TST (immediate);
6049  if (Rd == 15 && setflags)
6050  return EmulateTSTImm(opcode, eEncodingT1);
6051  if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
6052  return false;
6053  break;
6054  case eEncodingA1:
6055  Rd = Bits32(opcode, 15, 12);
6056  Rn = Bits32(opcode, 19, 16);
6057  setflags = BitIsSet(opcode, 20);
6058  imm32 =
6059  ARMExpandImm_C(opcode, APSR_C,
6060  carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
6061 
6062  if (Rd == 15 && setflags)
6063  return EmulateSUBSPcLrEtc(opcode, encoding);
6064  break;
6065  default:
6066  return false;
6067  }
6068 
6069  // Read the first operand.
6070  uint32_t val1 = ReadCoreReg(Rn, &success);
6071  if (!success)
6072  return false;
6073 
6074  uint32_t result = val1 & imm32;
6075 
6077  context.type = EmulateInstruction::eContextImmediate;
6078  context.SetNoArgs();
6079 
6080  if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
6081  return false;
6082  }
6083  return true;
6084 }
6085 
6086 // This instruction performs a bitwise AND of a register value and an
6087 // optionally-shifted register value, and writes the result to the destination
6088 // register. It can optionally update the condition flags based on the result.
6089 bool EmulateInstructionARM::EmulateANDReg(const uint32_t opcode,
6090  const ARMEncoding encoding) {
6091 #if 0
6092  // ARM pseudo code...
6093  if ConditionPassed() then
6094  EncodingSpecificOperations();
6095  (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
6096  result = R[n] AND shifted;
6097  if d == 15 then // Can only occur for ARM encoding
6098  ALUWritePC(result); // setflags is always FALSE here
6099  else
6100  R[d] = result;
6101  if setflags then
6102  APSR.N = result<31>;
6103  APSR.Z = IsZeroBit(result);
6104  APSR.C = carry;
6105  // APSR.V unchanged
6106 #endif
6107