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EmulateInstructionRISCV.h
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1//===-- EmulateInstructionRISCV.h -----------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H
10#define LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H
11
12#include "RISCVInstructions.h"
13
16#include "lldb/Utility/Log.h"
18#include "lldb/Utility/Status.h"
19#include <optional>
20
21namespace lldb_private {
22
25public:
27 std::unique_ptr<EmulateInstruction> emulator)
28 : SingleStepBreakpointLocationsPredictor{std::move(emulator)} {}
29
31
32 llvm::Expected<unsigned> GetBreakpointSize(lldb::addr_t bp_addr) override;
33
34private:
35 static bool FoundLoadReserve(const RISCVInst &inst) {
36 return std::holds_alternative<LR_W>(inst) ||
37 std::holds_alternative<LR_D>(inst);
38 }
39
40 static bool FoundStoreConditional(const RISCVInst &inst) {
41 return std::holds_alternative<SC_W>(inst) ||
42 std::holds_alternative<SC_D>(inst);
43 }
44
46
47 static constexpr size_t s_max_atomic_sequence_length = 64;
48};
49
51public:
52 static llvm::StringRef GetPluginNameStatic() { return "riscv"; }
53
54 static llvm::StringRef GetPluginDescriptionStatic() {
55 return "Emulate instructions for the RISC-V architecture.";
56 }
57
59 switch (inst_type) {
62 return true;
64 return true;
66 return false;
67 }
68 llvm_unreachable("Fully covered switch above!");
69 }
70
71 static bool SupportsThisArch(const ArchSpec &arch);
72
75
76 static void Initialize();
77
78 static void Terminate();
79
80public:
82
83 llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
84
86 return SupportsThisInstructionType(inst_type);
87 }
88
89 bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override;
90 bool SetTargetTriple(const ArchSpec &arch) override;
91 bool ReadInstruction() override;
92 std::optional<uint32_t> GetLastInstrSize() override { return m_last_size; }
93 bool EvaluateInstruction(uint32_t options) override;
94 bool TestEmulation(Stream &out_stream, ArchSpec &arch,
95 OptionValueDictionary *test_data) override;
96 std::optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
97 uint32_t reg_num) override;
98
99 bool SetInstruction(const Opcode &opcode, const Address &inst_addr,
100 Target *target) override;
101 std::optional<DecodeResult> ReadInstructionAt(lldb::addr_t addr);
102 std::optional<DecodeResult> Decode(uint32_t inst);
103 bool Execute(DecodeResult inst, bool ignore_cond);
104
105 template <typename T>
106 std::enable_if_t<std::is_integral_v<T>, std::optional<T>>
107 ReadMem(uint64_t addr) {
110 ctx.SetNoArgs();
111 bool success = false;
112 T result = ReadMemoryUnsigned(ctx, addr, sizeof(T), T(), &success);
113 if (!success)
114 return {}; // aka return false
115 return result;
116 }
117
118 template <typename T> bool WriteMem(uint64_t addr, uint64_t value) {
121 ctx.SetNoArgs();
122 return WriteMemoryUnsigned(ctx, addr, value, sizeof(T));
123 }
124
125 llvm::RoundingMode GetRoundingMode();
126 bool SetAccruedExceptions(llvm::APFloatBase::opStatus);
127
128private:
131 return [](std::unique_ptr<EmulateInstruction> emulator_up) {
132 return std::make_unique<RISCVSingleStepBreakpointLocationsPredictor>(
133 std::move(emulator_up));
134 };
135 }
136 /// Last decoded instruction from m_opcode
138 /// Last decoded instruction size estimate.
139 std::optional<uint32_t> m_last_size;
140};
141
142} // namespace lldb_private
143
144#endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H
static llvm::raw_ostream & error(Stream &strm)
A section + offset based address class.
Definition Address.h:62
An architecture specification class.
Definition ArchSpec.h:31
std::optional< DecodeResult > ReadInstructionAt(lldb::addr_t addr)
std::optional< RegisterInfo > GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num) override
bool SetTargetTriple(const ArchSpec &arch) override
bool SetAccruedExceptions(llvm::APFloatBase::opStatus)
std::optional< uint32_t > m_last_size
Last decoded instruction size estimate.
bool WriteMem(uint64_t addr, uint64_t value)
bool TestEmulation(Stream &out_stream, ArchSpec &arch, OptionValueDictionary *test_data) override
static bool SupportsThisArch(const ArchSpec &arch)
std::optional< DecodeResult > Decode(uint32_t inst)
bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override
static llvm::StringRef GetPluginDescriptionStatic()
bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override
bool Execute(DecodeResult inst, bool ignore_cond)
std::enable_if_t< std::is_integral_v< T >, std::optional< T > > ReadMem(uint64_t addr)
std::optional< uint32_t > GetLastInstrSize() override
bool EvaluateInstruction(uint32_t options) override
BreakpointLocationsPredictorCreator GetSingleStepBreakpointLocationsPredictorCreator() override
bool SetInstruction(const Opcode &opcode, const Address &inst_addr, Target *target) override
static lldb_private::EmulateInstruction * CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type)
static bool SupportsThisInstructionType(InstructionType inst_type)
DecodeResult m_decoded
Last decoded instruction from m_opcode.
"lldb/Core/EmulateInstruction.h" A class that allows emulation of CPU opcodes.
bool WriteMemoryUnsigned(const Context &context, lldb::addr_t addr, uint64_t uval, size_t uval_byte_size)
std::function< std::unique_ptr< SingleStepBreakpointLocationsPredictor >( std::unique_ptr< EmulateInstruction >)> BreakpointLocationsPredictorCreator
uint64_t ReadMemoryUnsigned(const Context &context, lldb::addr_t addr, size_t byte_size, uint64_t fail_value, bool *success_ptr)
BreakpointLocations GetBreakpointLocations(Status &status) override
BreakpointLocations HandleAtomicSequence(lldb::addr_t pc, Status &error)
RISCVSingleStepBreakpointLocationsPredictor(std::unique_ptr< EmulateInstruction > emulator)
llvm::Expected< unsigned > GetBreakpointSize(lldb::addr_t bp_addr) override
SingleStepBreakpointLocationsPredictor(std::unique_ptr< EmulateInstruction > emulator_up)
An error handling class.
Definition Status.h:118
A stream class that can stream formatted output to a file.
Definition Stream.h:28
A class that represents a running process on the host machine.
std::variant< LUI, AUIPC, JAL, JALR, B, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND, LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW, SRLW, SRAW, MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU, MULW, DIVW, DIVUW, REMW, REMUW, LR_W, SC_W, AMOSWAP_W, AMOADD_W, AMOXOR_W, AMOAND_W, AMOOR_W, AMOMIN_W, AMOMAX_W, AMOMINU_W, AMOMAXU_W, LR_D, SC_D, AMOSWAP_D, AMOADD_D, AMOXOR_D, AMOAND_D, AMOOR_D, AMOMIN_D, AMOMAX_D, AMOMINU_D, AMOMAXU_D, FLW, FSW, FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FADD_S, FSUB_S, FMUL_S, FDIV_S, FSQRT_S, FSGNJ_S, FSGNJN_S, FSGNJX_S, FMIN_S, FMAX_S, FCVT_W_S, FCVT_WU_S, FMV_X_W, FEQ_S, FLT_S, FLE_S, FCLASS_S, FCVT_S_W, FCVT_S_WU, FMV_W_X, FCVT_L_S, FCVT_LU_S, FCVT_S_L, FCVT_S_LU, FLD, FSD, FMADD_D, FMSUB_D, FNMSUB_D, FNMADD_D, FADD_D, FSUB_D, FMUL_D, FDIV_D, FSQRT_D, FSGNJ_D, FSGNJN_D, FSGNJX_D, FMIN_D, FMAX_D, FCVT_S_D, FCVT_D_S, FEQ_D, FLT_D, FLE_D, FCLASS_D, FCVT_W_D, FCVT_WU_D, FCVT_D_W, FCVT_D_WU, FCVT_L_D, FCVT_LU_D, FMV_X_D, FCVT_D_L, FCVT_D_LU, FMV_D_X, INVALID, EBREAK, RESERVED, HINT, NOP > RISCVInst
InstructionType
Instruction types.
std::vector< lldb::addr_t > BreakpointLocations
uint64_t addr_t
Definition lldb-types.h:80
RegisterKind
Register numbering types.