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ArchSpec.h
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1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLDB_UTILITY_ARCHSPEC_H
10 #define LLDB_UTILITY_ARCHSPEC_H
11 
14 #include "lldb/lldb-enumerations.h"
15 #include "lldb/lldb-forward.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include <cstddef>
20 #include <cstdint>
21 #include <string>
22 
23 namespace lldb_private {
24 
25 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture
26 /// specification class.
27 ///
28 /// A class designed to be created from a cpu type and subtype, a
29 /// string representation, or an llvm::Triple. Keeping all of the conversions
30 /// of strings to architecture enumeration values confined to this class
31 /// allows new architecture support to be added easily.
32 class ArchSpec {
33 public:
34  enum MIPSSubType {
48  };
49 
50  // Masks for the ases word of an ABI flags structure.
51  enum MIPSASE {
52  eMIPSAse_dsp = 0x00000001, // DSP ASE
53  eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE
54  eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme
55  eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE
56  eMIPSAse_mdmx = 0x00000010, // MDMX ASE
57  eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE
58  eMIPSAse_mt = 0x00000040, // MT ASE
59  eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE
60  eMIPSAse_virt = 0x00000100, // VZ ASE
61  eMIPSAse_msa = 0x00000200, // MSA ASE
62  eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE
63  eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE
64  eMIPSAse_xpa = 0x00001000, // XPA ASE
65  eMIPSAse_mask = 0x00001fff,
66  eMIPSABI_O32 = 0x00002000,
67  eMIPSABI_N32 = 0x00004000,
68  eMIPSABI_N64 = 0x00008000,
69  eMIPSABI_O64 = 0x00020000,
70  eMIPSABI_EABI32 = 0x00040000,
71  eMIPSABI_EABI64 = 0x00080000,
72  eMIPSABI_mask = 0x000ff000
73  };
74 
75  // MIPS Floating point ABI Values
76  enum MIPS_ABI_FP {
77  eMIPS_ABI_FP_ANY = 0x00000000,
78  eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float
79  eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float
80  eMIPS_ABI_FP_SOFT = 0x00300000, // soft float
81  eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64
82  eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx
83  eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64
84  eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg
85  eMIPS_ABI_FP_mask = 0x00700000
86  };
87 
88  // ARM specific e_flags
89  enum ARMeflags {
90  eARM_abi_soft_float = 0x00000200,
91  eARM_abi_hard_float = 0x00000400
92  };
93 
94  enum RISCVeflags {
95  eRISCV_rvc = 0x00000001, /// RVC, +c
96  eRISCV_float_abi_soft = 0x00000000, /// soft float
97  eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f
98  eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d
99  eRISCV_float_abi_quad = 0x00000006, /// quad precision floating point, +q
100  eRISCV_float_abi_mask = 0x00000006,
101  eRISCV_rve = 0x00000008, /// RVE, +e
102  eRISCV_tso = 0x00000010, /// RVTSO (total store ordering)
103  };
104 
109  };
110 
115  };
116 
117  enum Core {
134 
153 
174 
188 
192 
194 
196 
198 
203 
205  eCore_x86_64_x86_64h, // Haswell enabled x86_64
209 
212 
215 
218 
219  eCore_arc, // little endian ARC
220 
222 
224 
226 
228  // The following constants are used for wildcard matching only
236 
239 
242 
245 
248 
251 
254 
257 
260 
263 
266 
269 
272 
273  };
274 
275  /// Default constructor.
276  ///
277  /// Default constructor that initializes the object with invalid cpu type
278  /// and subtype values.
279  ArchSpec();
280 
281  /// Constructor over triple.
282  ///
283  /// Constructs an ArchSpec with properties consistent with the given Triple.
284  explicit ArchSpec(const llvm::Triple &triple);
285  explicit ArchSpec(const char *triple_cstr);
286  explicit ArchSpec(llvm::StringRef triple_str);
287  /// Constructor over architecture name.
288  ///
289  /// Constructs an ArchSpec with properties consistent with the given object
290  /// type and architecture name.
291  explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type,
292  uint32_t cpu_subtype);
293 
294  /// Destructor.
295  ~ArchSpec();
296 
297  /// Returns true if the OS, vendor and environment fields of the triple are
298  /// unset. The triple is expected to be normalized
299  /// (llvm::Triple::normalize).
300  static bool ContainsOnlyArch(const llvm::Triple &normalized_triple);
301 
302  static void ListSupportedArchNames(StringList &list);
303  static void AutoComplete(CompletionRequest &request);
304 
305  /// Returns a static string representing the current architecture.
306  ///
307  /// \return A static string corresponding to the current
308  /// architecture.
309  const char *GetArchitectureName() const;
310 
311  /// if MIPS architecture return true.
312  ///
313  /// \return a boolean value.
314  bool IsMIPS() const;
315 
316  /// Returns a string representing current architecture as a target CPU for
317  /// tools like compiler, disassembler etc.
318  ///
319  /// \return A string representing target CPU for the current
320  /// architecture.
322 
323  /// Return a string representing target application ABI.
324  ///
325  /// \return A string representing target application ABI.
326  std::string GetTargetABI() const;
327 
328  /// Clears the object state.
329  ///
330  /// Clears the object state back to a default invalid state.
331  void Clear();
332 
333  /// Returns the size in bytes of an address of the current architecture.
334  ///
335  /// \return The byte size of an address of the current architecture.
337 
338  /// Returns a machine family for the current architecture.
339  ///
340  /// \return An LLVM arch type.
341  llvm::Triple::ArchType GetMachine() const;
342 
343  /// Returns the distribution id of the architecture.
344  ///
345  /// This will be something like "ubuntu", "fedora", etc. on Linux.
346  ///
347  /// \return A ConstString ref containing the distribution id,
348  /// potentially empty.
350 
351  /// Set the distribution id of the architecture.
352  ///
353  /// This will be something like "ubuntu", "fedora", etc. on Linux. This
354  /// should be the same value returned by HostInfo::GetDistributionId ().
355  void SetDistributionId(const char *distribution_id);
356 
357  /// Tests if this ArchSpec is valid.
358  ///
359  /// \return True if the current architecture is valid, false
360  /// otherwise.
361  bool IsValid() const {
362  return m_core >= eCore_arm_generic && m_core < kNumCores;
363  }
364  explicit operator bool() const { return IsValid(); }
365 
367  return !m_triple.getVendorName().empty();
368  }
369 
370  bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); }
371 
373  return m_triple.hasEnvironment();
374  }
375 
376  /// Merges fields from another ArchSpec into this ArchSpec.
377  ///
378  /// This will use the supplied ArchSpec to fill in any fields of the triple
379  /// in this ArchSpec which were unspecified. This can be used to refine a
380  /// generic ArchSpec with a more specific one. For example, if this
381  /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we
382  /// have a triple which is x64-pc-windows-msvc, then merging that triple
383  /// into this one will result in the triple i386-pc-windows-msvc.
384  ///
385  void MergeFrom(const ArchSpec &other);
386 
387  /// Change the architecture object type, CPU type and OS type.
388  ///
389  /// \param[in] arch_type The object type of this ArchSpec.
390  ///
391  /// \param[in] cpu The required CPU type.
392  ///
393  /// \param[in] os The optional OS type
394  /// The default value of 0 was chosen to from the ELF spec value
395  /// ELFOSABI_NONE. ELF is the only one using this parameter. If another
396  /// format uses this parameter and 0 does not work, use a value over
397  /// 255 because in the ELF header this is value is only a byte.
398  ///
399  /// \return True if the object, and CPU were successfully set.
400  ///
401  /// As a side effect, the vendor value is usually set to unknown. The
402  /// exceptions are
403  /// aarch64-apple-ios
404  /// arm-apple-ios
405  /// thumb-apple-ios
406  /// x86-apple-
407  /// x86_64-apple-
408  ///
409  /// As a side effect, the os value is usually set to unknown The exceptions
410  /// are
411  /// *-*-aix
412  /// aarch64-apple-ios
413  /// arm-apple-ios
414  /// thumb-apple-ios
415  /// powerpc-apple-darwin
416  /// *-*-freebsd
417  /// *-*-linux
418  /// *-*-netbsd
419  /// *-*-openbsd
420  /// *-*-solaris
421  bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub,
422  uint32_t os = 0);
423 
424  /// Returns the byte order for the architecture specification.
425  ///
426  /// \return The endian enumeration for the current endianness of
427  /// the architecture specification
429 
430  /// Sets this ArchSpec's byte order.
431  ///
432  /// In the common case there is no need to call this method as the byte
433  /// order can almost always be determined by the architecture. However, many
434  /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed
435  /// byte order may be incorrect.
436  void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; }
437 
439 
441 
442  Core GetCore() const { return m_core; }
443 
444  uint32_t GetMachOCPUType() const;
445 
447 
448  /// Architecture data byte width accessor
449  ///
450  /// \return the size in 8-bit (host) bytes of a minimum addressable unit
451  /// from the Architecture's data bus
452  uint32_t GetDataByteSize() const;
453 
454  /// Architecture code byte width accessor
455  ///
456  /// \return the size in 8-bit (host) bytes of a minimum addressable unit
457  /// from the Architecture's code bus
458  uint32_t GetCodeByteSize() const;
459 
460  /// Architecture triple accessor.
461  ///
462  /// \return A triple describing this ArchSpec.
463  llvm::Triple &GetTriple() { return m_triple; }
464 
465  /// Architecture triple accessor.
466  ///
467  /// \return A triple describing this ArchSpec.
468  const llvm::Triple &GetTriple() const { return m_triple; }
469 
470  void DumpTriple(llvm::raw_ostream &s) const;
471 
472  /// Architecture triple setter.
473  ///
474  /// Configures this ArchSpec according to the given triple. If the triple
475  /// has unknown components in all of the vendor, OS, and the optional
476  /// environment field (i.e. "i386-unknown-unknown") then default values are
477  /// taken from the host. Architecture and environment components are used
478  /// to further resolve the CPU type and subtype, endian characteristics,
479  /// etc.
480  ///
481  /// \return A triple describing this ArchSpec.
482  bool SetTriple(const llvm::Triple &triple);
483 
484  bool SetTriple(llvm::StringRef triple_str);
485 
486  /// Returns the default endianness of the architecture.
487  ///
488  /// \return The endian enumeration for the default endianness of
489  /// the architecture.
491 
492  /// Returns true if 'char' is a signed type by default in the architecture
493  /// false otherwise
494  ///
495  /// \return True if 'char' is a signed type by default on the
496  /// architecture and false otherwise.
497  bool CharIsSignedByDefault() const;
498 
500 
501  /// Compare this ArchSpec to another ArchSpec. \a match specifies the kind of
502  /// matching that is to be done. CompatibleMatch requires only a compatible
503  /// cpu type (e.g., armv7s is compatible with armv7). ExactMatch requires an
504  /// exact match (armv7s is not an exact match with armv7).
505  ///
506  /// \return true if the two ArchSpecs match.
507  bool IsMatch(const ArchSpec &rhs, MatchType match) const;
508 
509  /// Shorthand for IsMatch(rhs, ExactMatch).
510  bool IsExactMatch(const ArchSpec &rhs) const {
511  return IsMatch(rhs, ExactMatch);
512  }
513 
514  /// Shorthand for IsMatch(rhs, CompatibleMatch).
515  bool IsCompatibleMatch(const ArchSpec &rhs) const {
516  return IsMatch(rhs, CompatibleMatch);
517  }
518 
519  bool IsFullySpecifiedTriple() const;
520 
521  void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different,
522  bool &vendor_different, bool &os_different,
523  bool &os_version_different,
524  bool &env_different) const;
525 
526  /// Detect whether this architecture uses thumb code exclusively
527  ///
528  /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute
529  /// the Thumb instructions, never Arm. We should normally pick up
530  /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints
531  /// on each function - but when doing bare-boards low level debugging
532  /// (especially common with these embedded processors), we may not have
533  /// those things easily accessible.
534  ///
535  /// \return true if this is an arm ArchSpec which can only execute Thumb
536  /// instructions
537  bool IsAlwaysThumbInstructions() const;
538 
539  uint32_t GetFlags() const { return m_flags; }
540 
541  void SetFlags(uint32_t flags) { m_flags = flags; }
542 
543  void SetFlags(const std::string &elf_abi);
544 
545 protected:
546  void UpdateCore();
547 
548  llvm::Triple m_triple;
551 
552  // Additional arch flags which we cannot get from triple and core For MIPS
553  // these are application specific extensions like micromips, mips16 etc.
555 
557 
558  // Called when m_def or m_entry are changed. Fills in all remaining members
559  // with default values.
560  void CoreUpdated(bool update_triple);
561 };
562 
563 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than
564 /// operator.
565 ///
566 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs.
567 ///
568 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in]
569 /// rhs The Left Hand Side ArchSpec object to compare.
570 ///
571 /// \return true if \a lhs is less than \a rhs
572 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs);
573 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs);
574 
575 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch);
576 
577 } // namespace lldb_private
578 
579 #endif // LLDB_UTILITY_ARCHSPEC_H
lldb_private::ArchSpec::GetMinimumOpcodeByteSize
uint32_t GetMinimumOpcodeByteSize() const
Definition: ArchSpec.cpp:927
list
MATCHES FreeBSD list(APPEND FBSDKERNEL_LIBS kvm) endif() if(NOT FBSDKERNEL_LIBS) message(STATUS "Skipping FreeBSDKernel plugin due to missing libfbsdvmcore") return() endif() add_lldb_library(lldbPluginProcessFreeBSDKernel PLUGIN ProcessFreeBSDKernel.cpp RegisterContextFreeBSDKernel_arm64.cpp RegisterContextFreeBSDKernel_i386.cpp RegisterContextFreeBSDKernel_x86_64.cpp ThreadFreeBSDKernel.cpp LINK_LIBS lldbCore lldbTarget $
Definition: Plugins/Process/FreeBSDKernel/CMakeLists.txt:6
lldb_private::ArchSpec::kCore_mips32el_first
@ kCore_mips32el_first
Definition: ArchSpec.h:261
lldb_private::ArchSpec::eCore_arm_armv7k
@ eCore_arm_armv7k
Definition: ArchSpec.h:130
lldb_private::ArchSpec::GetByteOrder
lldb::ByteOrder GetByteOrder() const
Returns the byte order for the architecture specification.
Definition: ArchSpec.cpp:741
lldb_private::ArchSpec::eMIPS_ABI_FP_DOUBLE
@ eMIPS_ABI_FP_DOUBLE
Definition: ArchSpec.h:78
lldb_private::ArchSpec::eRISCVSubType_unknown
@ eRISCVSubType_unknown
Definition: ArchSpec.h:106
lldb_private::ArchSpec::eMIPSSubType_mips64el
@ eMIPSSubType_mips64el
Definition: ArchSpec.h:45
lldb_private::ArchSpec
Definition: ArchSpec.h:32
lldb_private::ArchSpec::IsMIPS
bool IsMIPS() const
if MIPS architecture return true.
Definition: ArchSpec.cpp:554
lldb_private::ArchSpec::kCore_x86_64_first
@ kCore_x86_64_first
Definition: ArchSpec.h:252
lldb_private::ArchSpec::eMIPSABI_EABI64
@ eMIPSABI_EABI64
Definition: ArchSpec.h:71
lldb_private::ArchSpec::m_distribution_id
ConstString m_distribution_id
Definition: ArchSpec.h:556
lldb_private::ArchSpec::eCore_x86_32_i486
@ eCore_x86_32_i486
Definition: ArchSpec.h:200
lldb_private::ArchSpec::TripleVendorWasSpecified
bool TripleVendorWasSpecified() const
Definition: ArchSpec.h:366
lldb_private::ArchSpec::eRISCV_float_abi_single
@ eRISCV_float_abi_single
soft float
Definition: ArchSpec.h:97
lldb_private::ArchSpec::GetMaximumOpcodeByteSize
uint32_t GetMaximumOpcodeByteSize() const
Definition: ArchSpec.cpp:934
lldb_private::ArchSpec::eCore_arm_armv5
@ eCore_arm_armv5
Definition: ArchSpec.h:121
lldb_private::ArchSpec::kCore_mips_first
@ kCore_mips_first
Definition: ArchSpec.h:270
lldb_private::ArchSpec::GetMachine
llvm::Triple::ArchType GetMachine() const
Returns a machine family for the current architecture.
Definition: ArchSpec.cpp:678
lldb_private::ArchSpec::eCore_ppc_generic
@ eCore_ppc_generic
Definition: ArchSpec.h:175
lldb_private::ArchSpec::eCore_ppc_ppc603ev
@ eCore_ppc_ppc603ev
Definition: ArchSpec.h:180
lldb_private::ArchSpec::ArchSpec
ArchSpec()
Default constructor.
lldb_private::ArchSpec::eMIPSAse_mdmx
@ eMIPSAse_mdmx
Definition: ArchSpec.h:56
lldb_private::ArchSpec::eMIPSSubType_mips32r6
@ eMIPSSubType_mips32r6
Definition: ArchSpec.h:38
lldb_private::ArchSpec::m_flags
uint32_t m_flags
Definition: ArchSpec.h:554
lldb_private::ArchSpec::eCore_thumbv7
@ eCore_thumbv7
Definition: ArchSpec.h:141
lldb_private::ArchSpec::CoreUpdated
void CoreUpdated(bool update_triple)
Definition: ArchSpec.cpp:1068
lldb_private::ArchSpec::eCore_thumbv7k
@ eCore_thumbv7k
Definition: ArchSpec.h:143
lldb_private::ArchSpec::GetCore
Core GetCore() const
Definition: ArchSpec.h:442
lldb_private::ArchSpec::eCore_arm_xscale
@ eCore_arm_xscale
Definition: ArchSpec.h:133
lldb_private::ArchSpec::eRISCV_tso
@ eRISCV_tso
RVE, +e.
Definition: ArchSpec.h:102
lldb_private::ArchSpec::GetDefaultEndian
lldb::ByteOrder GetDefaultEndian() const
Returns the default endianness of the architecture.
Definition: ArchSpec.cpp:708
lldb_private::ArchSpec::eCore_s390x_generic
@ eCore_s390x_generic
Definition: ArchSpec.h:193
lldb_private::ArchSpec::ListSupportedArchNames
static void ListSupportedArchNames(StringList &list)
Definition: ArchSpec.cpp:263
lldb_private::ArchSpec::eRISCVSubType_riscv64
@ eRISCVSubType_riscv64
Definition: ArchSpec.h:108
lldb_private::ArchSpec::eLoongArchSubType_unknown
@ eLoongArchSubType_unknown
Definition: ArchSpec.h:112
lldb_private::ArchSpec::eCore_thumbv7f
@ eCore_thumbv7f
Definition: ArchSpec.h:144
lldb_private::ArchSpec::eMIPSAse_dspr2
@ eMIPSAse_dspr2
Definition: ArchSpec.h:53
lldb_private::ArchSpec::eMIPSSubType_mips64r2
@ eMIPSSubType_mips64r2
Definition: ArchSpec.h:43
lldb_private::ArchSpec::eCore_arm_armv7f
@ eCore_arm_armv7f
Definition: ArchSpec.h:128
lldb_private::ArchSpec::MergeFrom
void MergeFrom(const ArchSpec &other)
Merges fields from another ArchSpec into this ArchSpec.
Definition: ArchSpec.cpp:812
lldb_private::ArchSpec::ContainsOnlyArch
static bool ContainsOnlyArch(const llvm::Triple &normalized_triple)
Returns true if the OS, vendor and environment fields of the triple are unset.
Definition: ArchSpec.cpp:805
lldb_private::ArchSpec::eMIPS_ABI_FP_XX
@ eMIPS_ABI_FP_XX
Definition: ArchSpec.h:82
lldb_private::ArchSpec::ExactMatch
@ ExactMatch
Definition: ArchSpec.h:499
lldb_private::ArchSpec::eCore_wasm32
@ eCore_wasm32
Definition: ArchSpec.h:223
lldb_private::ArchSpec::kCore_ppc64_any
@ kCore_ppc64_any
Definition: ArchSpec.h:232
lldb_private::ArchSpec::eCore_arm_arm64
@ eCore_arm_arm64
Definition: ArchSpec.h:147
lldb_private::ArchSpec::kNumCores
@ kNumCores
Definition: ArchSpec.h:225
lldb_private::ArchSpec::kCore_mips_last
@ kCore_mips_last
Definition: ArchSpec.h:271
lldb_private::ArchSpec::GetFlags
uint32_t GetFlags() const
Definition: ArchSpec.h:539
lldb_private::ArchSpec::SetFlags
void SetFlags(uint32_t flags)
Definition: ArchSpec.h:541
lldb_private::ArchSpec::eCore_arm_armv4
@ eCore_arm_armv4
Definition: ArchSpec.h:119
lldb_private::ArchSpec::eCore_arm_armv6m
@ eCore_arm_armv6m
Definition: ArchSpec.h:125
lldb_private::ArchSpec::eMIPSSubType_mips32r6el
@ eMIPSSubType_mips32r6el
Definition: ArchSpec.h:41
lldb_private::ArchSpec::eMIPSAse_mcu
@ eMIPSAse_mcu
Definition: ArchSpec.h:55
lldb_private::ArchSpec::eMIPSSubType_mips32el
@ eMIPSSubType_mips32el
Definition: ArchSpec.h:39
lldb_private::ArchSpec::eCore_ppc_ppc7450
@ eCore_ppc_ppc7450
Definition: ArchSpec.h:186
lldb_private::ArchSpec::eCore_sparc9_generic
@ eCore_sparc9_generic
Definition: ArchSpec.h:197
lldb_private::ArchSpec::eCore_thumbv7m
@ eCore_thumbv7m
Definition: ArchSpec.h:145
lldb_private::ArchSpec::eCore_arc
@ eCore_arc
Definition: ArchSpec.h:219
lldb_private::ArchSpec::eRISCV_rvc
@ eRISCV_rvc
Definition: ArchSpec.h:95
lldb_private::ArchSpec::GetCodeByteSize
uint32_t GetCodeByteSize() const
Architecture code byte width accessor.
Definition: ArchSpec.cpp:674
lldb_private::ArchSpec::MIPSSubType
MIPSSubType
Definition: ArchSpec.h:34
lldb_private::ArchSpec::GetTriple
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:463
lldb_private::ArchSpec::kCore_mips64_first
@ kCore_mips64_first
Definition: ArchSpec.h:264
lldb_private::ArchSpec::eCore_arm_armv5e
@ eCore_arm_armv5e
Definition: ArchSpec.h:122
lldb_private::ArchSpec::kCore_mips32el_last
@ kCore_mips32el_last
Definition: ArchSpec.h:262
lldb_private::ArchSpec::IsCompatibleMatch
bool IsCompatibleMatch(const ArchSpec &rhs) const
Shorthand for IsMatch(rhs, CompatibleMatch).
Definition: ArchSpec.h:515
lldb_private::ArchSpec::eCore_mips64
@ eCore_mips64
Definition: ArchSpec.h:164
lldb_private::ArchSpec::GetClangTargetCPU
std::string GetClangTargetCPU() const
Returns a string representing current architecture as a target CPU for tools like compiler,...
Definition: ArchSpec.cpp:592
lldb_private::ArchSpec::~ArchSpec
~ArchSpec()
Destructor.
lldb_private::ArchSpec::eRISCV_float_abi_mask
@ eRISCV_float_abi_mask
quad precision floating point, +q
Definition: ArchSpec.h:100
lldb-private-enumerations.h
CompletionRequest.h
lldb_private::ArchSpec::eCore_mips32r3
@ eCore_mips32r3
Definition: ArchSpec.h:156
lldb_private::ArchSpec::m_byte_order
lldb::ByteOrder m_byte_order
Definition: ArchSpec.h:550
lldb_private::ArchSpec::kCore_mips64_last
@ kCore_mips64_last
Definition: ArchSpec.h:265
lldb_private::ArchSpec::eCore_mips32el
@ eCore_mips32el
Definition: ArchSpec.h:159
lldb_private::ArchSpec::eRISCV_float_abi_soft
@ eRISCV_float_abi_soft
RVC, +c.
Definition: ArchSpec.h:96
lldb_private::ArchSpec::eCore_arm_armv8l
@ eCore_arm_armv8l
Definition: ArchSpec.h:149
lldb_private::ArchSpec::eCore_mips32r2
@ eCore_mips32r2
Definition: ArchSpec.h:155
lldb_private::ArchSpec::ARMeflags
ARMeflags
Definition: ArchSpec.h:89
lldb_private::ArchSpec::eCore_thumbv5
@ eCore_thumbv5
Definition: ArchSpec.h:137
lldb_private::ArchSpec::IsExactMatch
bool IsExactMatch(const ArchSpec &rhs) const
Shorthand for IsMatch(rhs, ExactMatch).
Definition: ArchSpec.h:510
lldb_private::ArchSpec::eCore_ppc_ppc602
@ eCore_ppc_ppc602
Definition: ArchSpec.h:177
lldb_private::ArchSpec::Core
Core
Definition: ArchSpec.h:117
lldb_private::ArchSpec::eMIPSAse_mt
@ eMIPSAse_mt
Definition: ArchSpec.h:58
lldb_private::ArchSpec::eMIPSAse_mask
@ eMIPSAse_mask
Definition: ArchSpec.h:65
lldb_private::ArchSpec::eCore_riscv64
@ eCore_riscv64
Definition: ArchSpec.h:211
lldb_private::ArchSpec::eCore_ppc64_generic
@ eCore_ppc64_generic
Definition: ArchSpec.h:190
lldb_private::ArchSpec::DumpTriple
void DumpTriple(llvm::raw_ostream &s) const
Definition: ArchSpec.cpp:1470
lldb_private::ArchSpec::kCore_mips64el_last
@ kCore_mips64el_last
Definition: ArchSpec.h:268
lldb_private::ArchSpec::eMIPS_ABI_FP_mask
@ eMIPS_ABI_FP_mask
Definition: ArchSpec.h:85
lldb_private::ArchSpec::eCore_uknownMach64
@ eCore_uknownMach64
Definition: ArchSpec.h:217
lldb_private::operator==
bool operator==(const Address &lhs, const Address &rhs)
Definition: Address.cpp:1016
lldb_private::ArchSpec::eCore_hexagon_hexagonv4
@ eCore_hexagon_hexagonv4
Definition: ArchSpec.h:207
lldb_private::ArchSpec::LoongArchSubType
LoongArchSubType
Definition: ArchSpec.h:111
lldb_private::ArchSpec::GetMachOCPUType
uint32_t GetMachOCPUType() const
Definition: ArchSpec.cpp:646
lldb_private::ArchSpec::RISCVeflags
RISCVeflags
Definition: ArchSpec.h:94
lldb_private::ArchSpec::eMIPSABI_mask
@ eMIPSABI_mask
Definition: ArchSpec.h:72
lldb_private::ArchSpec::kCore_hexagon_last
@ kCore_hexagon_last
Definition: ArchSpec.h:256
lldb_private::ArchSpec::eCore_arm_armv6
@ eCore_arm_armv6
Definition: ArchSpec.h:124
lldb_private::ArchSpec::kCore_invalid
@ kCore_invalid
Definition: ArchSpec.h:227
lldb_private::ArchSpec::m_triple
llvm::Triple m_triple
Definition: ArchSpec.h:548
lldb_private::ArchSpec::eMIPSSubType_mips64r6
@ eMIPSSubType_mips64r6
Definition: ArchSpec.h:44
lldb_private::ArchSpec::eCore_mips64r6el
@ eCore_mips64r6el
Definition: ArchSpec.h:173
lldb_private::ArchSpec::SetDistributionId
void SetDistributionId(const char *distribution_id)
Set the distribution id of the architecture.
Definition: ArchSpec.cpp:690
lldb_private::ArchSpec::eCore_ppc_ppc603
@ eCore_ppc_ppc603
Definition: ArchSpec.h:178
lldb_private::ArchSpec::eCore_mips64r2
@ eCore_mips64r2
Definition: ArchSpec.h:165
lldb_private::ArchSpec::SetTriple
bool SetTriple(const llvm::Triple &triple)
Architecture triple setter.
Definition: ArchSpec.cpp:750
lldb_private::ArchSpec::eCore_mips64r3
@ eCore_mips64r3
Definition: ArchSpec.h:166
lldb_private::ArchSpec::eCore_x86_64_x86_64h
@ eCore_x86_64_x86_64h
Definition: ArchSpec.h:205
lldb_private::ArchSpec::eMIPS_ABI_FP_SOFT
@ eMIPS_ABI_FP_SOFT
Definition: ArchSpec.h:80
lldb_private::ArchSpec::kCore_ppc_first
@ kCore_ppc_first
Definition: ArchSpec.h:243
lldb_private::ArchSpec::kCore_x86_64_last
@ kCore_x86_64_last
Definition: ArchSpec.h:253
lldb_private::ArchSpec::eCore_ppc_ppc7400
@ eCore_ppc_ppc7400
Definition: ArchSpec.h:185
lldb_private::ArchSpec::eCore_arm_armv7
@ eCore_arm_armv7
Definition: ArchSpec.h:126
lldb_private::ArchSpec::eCore_uknownMach32
@ eCore_uknownMach32
Definition: ArchSpec.h:216
lldb_private::ArchSpec::eMIPSAse_dsp
@ eMIPSAse_dsp
Definition: ArchSpec.h:52
lldb_private::StringList
Definition: StringList.h:26
lldb_private::ConstString
Definition: ConstString.h:39
lldb-enumerations.h
lldb_private::ArchSpec::eARM_abi_soft_float
@ eARM_abi_soft_float
Definition: ArchSpec.h:90
lldb_private::ArchSpec::eCore_arm_armv7m
@ eCore_arm_armv7m
Definition: ArchSpec.h:131
lldb_private::ArchSpec::eCore_arm_armv8
@ eCore_arm_armv8
Definition: ArchSpec.h:148
lldb_private::ArchSpec::kCore_any
@ kCore_any
Definition: ArchSpec.h:229
lldb_private::ArchSpec::eCore_thumbv5e
@ eCore_thumbv5e
Definition: ArchSpec.h:138
lldb_private::ArchSpec::GetMachOCPUSubType
uint32_t GetMachOCPUSubType() const
Definition: ArchSpec.cpp:658
lldb_private::ArchSpec::eCore_mips32r2el
@ eCore_mips32r2el
Definition: ArchSpec.h:160
lldb_private::ArchSpec::eCore_x86_32_i386
@ eCore_x86_32_i386
Definition: ArchSpec.h:199
lldb_private::ArchSpec::kCore_mips32_first
@ kCore_mips32_first
Definition: ArchSpec.h:258
lldb_private::ArchSpec::eMIPSSubType_mips64r2el
@ eMIPSSubType_mips64r2el
Definition: ArchSpec.h:46
lldb_private::ArchSpec::MIPS_ABI_FP
MIPS_ABI_FP
Definition: ArchSpec.h:76
lldb_private::ArchSpec::eMIPSSubType_mips32r2
@ eMIPSSubType_mips32r2
Definition: ArchSpec.h:37
lldb_private::ArchSpec::eCore_thumbv7em
@ eCore_thumbv7em
Definition: ArchSpec.h:146
lldb_private::ArchSpec::AutoComplete
static void AutoComplete(CompletionRequest &request)
Definition: ArchSpec.cpp:268
lldb_private::ArchSpec::TripleOSWasSpecified
bool TripleOSWasSpecified() const
Definition: ArchSpec.h:370
lldb_private::ArchSpec::eCore_ppc64_ppc970_64
@ eCore_ppc64_ppc970_64
Definition: ArchSpec.h:191
lldb_private::ArchSpec::eCore_hexagon_generic
@ eCore_hexagon_generic
Definition: ArchSpec.h:206
lldb_private::ArchSpec::eCore_mips64r5el
@ eCore_mips64r5el
Definition: ArchSpec.h:172
lldb_private::ArchSpec::eCore_arm_armv7em
@ eCore_arm_armv7em
Definition: ArchSpec.h:132
lldb_private::ArchSpec::IsMatch
bool IsMatch(const ArchSpec &rhs, MatchType match) const
Compare this ArchSpec to another ArchSpec.
Definition: ArchSpec.cpp:972
lldb_private::ArchSpec::kCore_thumb_last
@ kCore_thumb_last
Definition: ArchSpec.h:241
lldb_private::ArchSpec::kCore_ppc_any
@ kCore_ppc_any
Definition: ArchSpec.h:231
lldb_private::ArchSpec::eMIPSAse_smartmips
@ eMIPSAse_smartmips
Definition: ArchSpec.h:59
lldb_private::ArchSpec::eCore_mips64el
@ eCore_mips64el
Definition: ArchSpec.h:169
string
string(SUBSTRING ${p} 10 -1 pStripped) if($
Definition: Plugins/CMakeLists.txt:40
lldb_private::ArchSpec::eMIPSAse_virt
@ eMIPSAse_virt
Definition: ArchSpec.h:60
lldb_private::ArchSpec::eCore_mips64r2el
@ eCore_mips64r2el
Definition: ArchSpec.h:170
lldb_private::ArchSpec::eCore_mips64r6
@ eCore_mips64r6
Definition: ArchSpec.h:168
lldb_private::ArchSpec::IsValid
bool IsValid() const
Tests if this ArchSpec is valid.
Definition: ArchSpec.h:361
lldb_private::ArchSpec::eCore_mips64r3el
@ eCore_mips64r3el
Definition: ArchSpec.h:171
lldb_private::ArchSpec::eCore_arm_generic
@ eCore_arm_generic
Definition: ArchSpec.h:118
lldb_private::ArchSpec::eMIPSSubType_mips64r6el
@ eMIPSSubType_mips64r6el
Definition: ArchSpec.h:47
lldb_private::ArchSpec::eMIPSSubType_mips32r2el
@ eMIPSSubType_mips32r2el
Definition: ArchSpec.h:40
lldb_private::ArchSpec::eMIPSABI_N64
@ eMIPSABI_N64
Definition: ArchSpec.h:68
lldb_private::ArchSpec::eMIPSABI_EABI32
@ eMIPSABI_EABI32
Definition: ArchSpec.h:70
lldb_private::ArchSpec::kCore_ppc_last
@ kCore_ppc_last
Definition: ArchSpec.h:244
lldb_private::ArchSpec::GetAddressByteSize
uint32_t GetAddressByteSize() const
Returns the size in bytes of an address of the current architecture.
Definition: ArchSpec.cpp:694
lldb_private::ArchSpec::TripleEnvironmentWasSpecified
bool TripleEnvironmentWasSpecified() const
Definition: ArchSpec.h:372
lldb_private::ArchSpec::eRISCV_float_abi_quad
@ eRISCV_float_abi_quad
double precision floating point, +d
Definition: ArchSpec.h:99
lldb_private::ArchSpec::kCore_thumb_first
@ kCore_thumb_first
Definition: ArchSpec.h:240
lldb_private::ArchSpec::eMIPSABI_O64
@ eMIPSABI_O64
Definition: ArchSpec.h:69
lldb_private::ArchSpec::kCore_mips64el_first
@ kCore_mips64el_first
Definition: ArchSpec.h:267
lldb_private::ArchSpec::eMIPS_ABI_FP_OLD_64
@ eMIPS_ABI_FP_OLD_64
Definition: ArchSpec.h:81
lldb_private::ArchitectureType
ArchitectureType
Definition: lldb-private-enumerations.h:61
lldb_private::ArchSpec::SetArchitecture
bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os=0)
Change the architecture object type, CPU type and OS type.
Definition: ArchSpec.cpp:854
lldb_private::ArchSpec::eCore_x86_32_i486sx
@ eCore_x86_32_i486sx
Definition: ArchSpec.h:201
lldb_private::ArchSpec::eCore_mips32r5el
@ eCore_mips32r5el
Definition: ArchSpec.h:162
lldb_private::ArchSpec::eCore_thumbv4t
@ eCore_thumbv4t
Definition: ArchSpec.h:136
lldb_private::ArchSpec::eCore_ppc_ppc970
@ eCore_ppc_ppc970
Definition: ArchSpec.h:187
lldb_private::ArchSpec::SetByteOrder
void SetByteOrder(lldb::ByteOrder byte_order)
Sets this ArchSpec's byte order.
Definition: ArchSpec.h:436
lldb_private::ArchSpec::eCore_thumbv6m
@ eCore_thumbv6m
Definition: ArchSpec.h:140
lldb_private::ArchSpec::eMIPSAse_eva
@ eMIPSAse_eva
Definition: ArchSpec.h:54
lldb_private::ArchSpec::eCore_mips64r5
@ eCore_mips64r5
Definition: ArchSpec.h:167
lldb_private::ArchSpec::kCore_mips32_last
@ kCore_mips32_last
Definition: ArchSpec.h:259
lldb_private::ArchSpec::GetArchitectureName
const char * GetArchitectureName() const
Returns a static string representing the current architecture.
Definition: ArchSpec.cpp:547
lldb::eByteOrderInvalid
@ eByteOrderInvalid
Definition: lldb-enumerations.h:140
lldb_private::ArchSpec::eCore_thumbv6
@ eCore_thumbv6
Definition: ArchSpec.h:139
lldb_private::ArchSpec::eCore_ppc64le_generic
@ eCore_ppc64le_generic
Definition: ArchSpec.h:189
lldb_private::ArchSpec::PiecewiseTripleCompare
void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, bool &vendor_different, bool &os_different, bool &os_version_different, bool &env_different) const
Definition: ArchSpec.cpp:1426
lldb_private::ArchSpec::eMIPSAse_mips3d
@ eMIPSAse_mips3d
Definition: ArchSpec.h:57
uint32_t
lldb_private::ArchSpec::kCore_ppc64_last
@ kCore_ppc64_last
Definition: ArchSpec.h:247
lldb_private::ArchSpec::eMIPS_ABI_FP_64A
@ eMIPS_ABI_FP_64A
Definition: ArchSpec.h:84
lldb_private::ArchSpec::IsAlwaysThumbInstructions
bool IsAlwaysThumbInstructions() const
Detect whether this architecture uses thumb code exclusively.
Definition: ArchSpec.cpp:1443
lldb_private::ArchSpec::eCore_arm_armv7s
@ eCore_arm_armv7s
Definition: ArchSpec.h:129
lldb_private::ArchSpec::eMIPSABI_N32
@ eMIPSABI_N32
Definition: ArchSpec.h:67
lldb_private::ArchSpec::kCore_hexagon_any
@ kCore_hexagon_any
Definition: ArchSpec.h:235
lldb_private::ArchSpec::MatchType
MatchType
Definition: ArchSpec.h:499
lldb_private::ArchSpec::eMIPS_ABI_FP_SINGLE
@ eMIPS_ABI_FP_SINGLE
Definition: ArchSpec.h:79
lldb_private::ArchSpec::eMIPSSubType_unknown
@ eMIPSSubType_unknown
Definition: ArchSpec.h:35
lldb_private::ArchSpec::eCore_arm_armv5t
@ eCore_arm_armv5t
Definition: ArchSpec.h:123
lldb_private::ArchSpec::eCore_ppc_ppc601
@ eCore_ppc_ppc601
Definition: ArchSpec.h:176
lldb_private::ArchSpec::eCore_arm_arm64_32
@ eCore_arm_arm64_32
Definition: ArchSpec.h:151
lldb_private::ArchSpec::UpdateCore
void UpdateCore()
Definition: ArchSpec.cpp:1051
lldb_private::ArchSpec::eRISCV_rve
@ eRISCV_rve
Definition: ArchSpec.h:101
lldb_private::ArchSpec::eCore_mips32r6el
@ eCore_mips32r6el
Definition: ArchSpec.h:163
lldb_private::operator<
bool operator<(const Address &lhs, const Address &rhs)
Definition: Address.cpp:985
lldb_private::ArchSpec::CharIsSignedByDefault
bool CharIsSignedByDefault() const
Returns true if 'char' is a signed type by default in the architecture false otherwise.
Definition: ArchSpec.cpp:715
lldb_private::ArchSpec::kCore_x86_32_first
@ kCore_x86_32_first
Definition: ArchSpec.h:249
lldb_private::ArchSpec::eLoongArchSubType_loongarch64
@ eLoongArchSubType_loongarch64
Definition: ArchSpec.h:114
lldb_private::ArchSpec::eMIPSAse_mips16
@ eMIPSAse_mips16
Definition: ArchSpec.h:62
lldb_private::ArchSpec::eMIPSAse_xpa
@ eMIPSAse_xpa
Definition: ArchSpec.h:64
lldb_private::ArchSpec::eCore_arm_aarch64
@ eCore_arm_aarch64
Definition: ArchSpec.h:152
lldb_private::ArchSpec::GetDataByteSize
uint32_t GetDataByteSize() const
Architecture data byte width accessor.
Definition: ArchSpec.cpp:670
lldb-forward.h
lldb_private::ArchSpec::eCore_ppc_ppc604
@ eCore_ppc_ppc604
Definition: ArchSpec.h:181
lldb_private::ArchSpec::eMIPS_ABI_FP_64
@ eMIPS_ABI_FP_64
Definition: ArchSpec.h:83
lldb_private::ArchSpec::GetTriple
const llvm::Triple & GetTriple() const
Architecture triple accessor.
Definition: ArchSpec.h:468
lldb_private::ArchSpec::kCore_x86_32_any
@ kCore_x86_32_any
Definition: ArchSpec.h:233
lldb_private::ArchSpec::eCore_mips32r6
@ eCore_mips32r6
Definition: ArchSpec.h:158
lldb_private::ArchSpec::eMIPSAse_msa
@ eMIPSAse_msa
Definition: ArchSpec.h:61
lldb_private::ArchSpec::RISCVSubType
RISCVSubType
Definition: ArchSpec.h:105
lldb_private::ArchSpec::kCore_x86_32_last
@ kCore_x86_32_last
Definition: ArchSpec.h:250
lldb_private
A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
lldb_private::ArchSpec::kCore_ppc64_first
@ kCore_ppc64_first
Definition: ArchSpec.h:246
lldb_private::ArchSpec::eCore_avr
@ eCore_avr
Definition: ArchSpec.h:221
lldb_private::ArchSpec::eMIPS_ABI_FP_ANY
@ eMIPS_ABI_FP_ANY
Definition: ArchSpec.h:77
lldb_private::ArchSpec::eCore_loongarch64
@ eCore_loongarch64
Definition: ArchSpec.h:214
lldb_private::ArchSpec::kCore_arm_any
@ kCore_arm_any
Definition: ArchSpec.h:230
lldb_private::ArchSpec::eCore_mips32
@ eCore_mips32
Definition: ArchSpec.h:154
lldb_private::ArchSpec::eARM_abi_hard_float
@ eARM_abi_hard_float
Definition: ArchSpec.h:91
lldb_private::ArchSpec::eCore_ppc_ppc620
@ eCore_ppc_ppc620
Definition: ArchSpec.h:183
lldb_private::ArchSpec::eCore_sparc_generic
@ eCore_sparc_generic
Definition: ArchSpec.h:195
lldb_private::ArchSpec::eCore_x86_64_x86_64
@ eCore_x86_64_x86_64
Definition: ArchSpec.h:204
lldb_private::ArchSpec::eCore_x86_32_i686
@ eCore_x86_32_i686
Definition: ArchSpec.h:202
lldb_private::ArchSpec::eMIPSAse_micromips
@ eMIPSAse_micromips
Definition: ArchSpec.h:63
lldb_private::ArchSpec::GetTargetABI
std::string GetTargetABI() const
Return a string representing target application ABI.
Definition: ArchSpec.cpp:556
lldb_private::ArchSpec::eMIPSSubType_mips32
@ eMIPSSubType_mips32
Definition: ArchSpec.h:36
lldb_private::ArchSpec::eCore_loongarch32
@ eCore_loongarch32
Definition: ArchSpec.h:213
ConstString.h
lldb_private::ArchSpec::CompatibleMatch
@ CompatibleMatch
Definition: ArchSpec.h:499
lldb_private::ArchSpec::eCore_arm_arm64e
@ eCore_arm_arm64e
Definition: ArchSpec.h:150
lldb_private::ArchSpec::eCore_thumb
@ eCore_thumb
Definition: ArchSpec.h:135
lldb_private::ParseMachCPUDashSubtypeTriple
bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch)
Definition: ArchSpec.cpp:756
lldb_private::ArchSpec::eCore_mips32r3el
@ eCore_mips32r3el
Definition: ArchSpec.h:161
lldb_private::ArchSpec::eCore_ppc_ppc603e
@ eCore_ppc_ppc603e
Definition: ArchSpec.h:179
lldb_private::ArchSpec::GetDistributionId
ConstString GetDistributionId() const
Returns the distribution id of the architecture.
Definition: ArchSpec.cpp:686
lldb_private::ArchSpec::eCore_arm_armv7l
@ eCore_arm_armv7l
Definition: ArchSpec.h:127
lldb_private::ArchSpec::eCore_arm_armv4t
@ eCore_arm_armv4t
Definition: ArchSpec.h:120
lldb_private::ArchSpec::Clear
void Clear()
Clears the object state.
Definition: ArchSpec.cpp:536
lldb_private::ArchSpec::eCore_hexagon_hexagonv5
@ eCore_hexagon_hexagonv5
Definition: ArchSpec.h:208
lldb_private::ArchSpec::IsFullySpecifiedTriple
bool IsFullySpecifiedTriple() const
Definition: ArchSpec.cpp:1411
lldb_private::ArchSpec::eMIPSSubType_mips64
@ eMIPSSubType_mips64
Definition: ArchSpec.h:42
lldb_private::ArchSpec::eRISCV_float_abi_double
@ eRISCV_float_abi_double
single precision floating point, +f
Definition: ArchSpec.h:98
lldb_private::ArchSpec::kCore_arm_last
@ kCore_arm_last
Definition: ArchSpec.h:238
lldb_private::ArchSpec::eCore_ppc_ppc604e
@ eCore_ppc_ppc604e
Definition: ArchSpec.h:182
lldb_private::ArchSpec::eCore_mips32r5
@ eCore_mips32r5
Definition: ArchSpec.h:157
lldb_private::ArchSpec::eMIPSABI_O32
@ eMIPSABI_O32
Definition: ArchSpec.h:66
lldb_private::ArchSpec::eCore_riscv32
@ eCore_riscv32
Definition: ArchSpec.h:210
lldb_private::ArchSpec::MIPSASE
MIPSASE
Definition: ArchSpec.h:51
lldb_private::ArchSpec::m_core
Core m_core
Definition: ArchSpec.h:549
lldb_private::ArchSpec::kCore_hexagon_first
@ kCore_hexagon_first
Definition: ArchSpec.h:255
lldb_private::ArchSpec::kCore_x86_64_any
@ kCore_x86_64_any
Definition: ArchSpec.h:234
lldb_private::ArchSpec::kCore_arm_first
@ kCore_arm_first
Definition: ArchSpec.h:237
lldb_private::CompletionRequest
Definition: CompletionRequest.h:100
lldb_private::ArchSpec::eLoongArchSubType_loongarch32
@ eLoongArchSubType_loongarch32
Definition: ArchSpec.h:113
lldb_private::ArchSpec::eCore_thumbv7s
@ eCore_thumbv7s
Definition: ArchSpec.h:142
lldb::ByteOrder
ByteOrder
Byte ordering definitions.
Definition: lldb-enumerations.h:139
lldb_private::ArchSpec::eCore_ppc_ppc750
@ eCore_ppc_ppc750
Definition: ArchSpec.h:184
lldb_private::ArchSpec::eRISCVSubType_riscv32
@ eRISCVSubType_riscv32
Definition: ArchSpec.h:107