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ArchSpec.h
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1//===-- ArchSpec.h ----------------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLDB_UTILITY_ARCHSPEC_H
10#define LLDB_UTILITY_ARCHSPEC_H
11
14#include "lldb/lldb-forward.h"
16#include "llvm/ADT/StringRef.h"
17#include "llvm/TargetParser/Triple.h"
18#include <cstddef>
19#include <cstdint>
20#include <string>
21
22namespace lldb_private {
23
24/// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture
25/// specification class.
26///
27/// A class designed to be created from a cpu type and subtype, a
28/// string representation, or an llvm::Triple. Keeping all of the conversions
29/// of strings to architecture enumeration values confined to this class
30/// allows new architecture support to be added easily.
31class ArchSpec {
32public:
47 };
48
49 // Masks for the ases word of an ABI flags structure.
50 enum MIPSASE {
51 eMIPSAse_dsp = 0x00000001, // DSP ASE
52 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE
53 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme
54 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE
55 eMIPSAse_mdmx = 0x00000010, // MDMX ASE
56 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE
57 eMIPSAse_mt = 0x00000040, // MT ASE
58 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE
59 eMIPSAse_virt = 0x00000100, // VZ ASE
60 eMIPSAse_msa = 0x00000200, // MSA ASE
61 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE
62 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE
63 eMIPSAse_xpa = 0x00001000, // XPA ASE
64 eMIPSAse_mask = 0x00001fff,
65 eMIPSABI_O32 = 0x00002000,
66 eMIPSABI_N32 = 0x00004000,
67 eMIPSABI_N64 = 0x00008000,
68 eMIPSABI_O64 = 0x00020000,
69 eMIPSABI_EABI32 = 0x00040000,
70 eMIPSABI_EABI64 = 0x00080000,
71 eMIPSABI_mask = 0x000ff000
72 };
73
74 // MIPS Floating point ABI Values
76 eMIPS_ABI_FP_ANY = 0x00000000,
77 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float
78 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float
79 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float
80 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64
81 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx
82 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64
83 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg
84 eMIPS_ABI_FP_mask = 0x00700000
85 };
86
87 // ARM specific e_flags
88 enum ARMeflags {
89 eARM_abi_soft_float = 0x00000200,
90 eARM_abi_hard_float = 0x00000400
91 };
92
94 eRISCV_rvc = 0x00000001, /// RVC, +c
95 eRISCV_float_abi_soft = 0x00000000, /// soft float
96 eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f
97 eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d
98 eRISCV_float_abi_quad = 0x00000006, /// quad precision floating point, +q
100 eRISCV_rve = 0x00000008, /// RVE, +e
101 eRISCV_tso = 0x00000010, /// RVTSO (total store ordering)
102 };
103
108 };
109
114 };
115
116 enum Core {
133
152
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175
189
193
195
197
199
204
206 eCore_x86_64_x86_64h, // Haswell enabled x86_64
210
213
216
219
220 eCore_arc, // little endian ARC
221
223
225
227
229 // The following constants are used for wildcard matching only
237
240
243
246
249
252
255
258
261
264
267
270
273
274 };
275
276 /// Default constructor.
277 ///
278 /// Default constructor that initializes the object with invalid cpu type
279 /// and subtype values.
281
282 /// Constructor over triple.
283 ///
284 /// Constructs an ArchSpec with properties consistent with the given Triple.
285 explicit ArchSpec(const llvm::Triple &triple);
286 explicit ArchSpec(const char *triple_cstr);
287 explicit ArchSpec(llvm::StringRef triple_str);
288 /// Constructor over architecture name.
289 ///
290 /// Constructs an ArchSpec with properties consistent with the given object
291 /// type and architecture name.
292 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type,
293 uint32_t cpu_subtype);
294
295 /// Destructor.
297
298 /// Returns true if the OS, vendor and environment fields of the triple are
299 /// unset. The triple is expected to be normalized
300 /// (llvm::Triple::normalize).
301 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple);
302
303 static void ListSupportedArchNames(StringList &list);
304 static void AutoComplete(CompletionRequest &request);
305
306 /// Returns a static string representing the current architecture.
307 ///
308 /// \return A static string corresponding to the current
309 /// architecture.
310 const char *GetArchitectureName() const;
311
312 /// if MIPS architecture return true.
313 ///
314 /// \return a boolean value.
315 bool IsMIPS() const;
316
317 /// Returns a string representing current architecture as a target CPU for
318 /// tools like compiler, disassembler etc.
319 ///
320 /// \return A string representing target CPU for the current
321 /// architecture.
322 std::string GetClangTargetCPU() const;
323
324 /// Return a string representing target application ABI.
325 ///
326 /// \return A string representing target application ABI.
327 std::string GetTargetABI() const;
328
329 /// Clears the object state.
330 ///
331 /// Clears the object state back to a default invalid state.
332 void Clear();
333
334 /// Returns the size in bytes of an address of the current architecture.
335 ///
336 /// \return The byte size of an address of the current architecture.
337 uint32_t GetAddressByteSize() const;
338
339 /// Returns a machine family for the current architecture.
340 ///
341 /// \return An LLVM arch type.
342 llvm::Triple::ArchType GetMachine() const;
343
344 /// Tests if this ArchSpec is valid.
345 ///
346 /// \return True if the current architecture is valid, false
347 /// otherwise.
348 bool IsValid() const {
350 }
351 explicit operator bool() const { return IsValid(); }
352
354 return !m_triple.getVendorName().empty();
355 }
356
357 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); }
358
360 return m_triple.hasEnvironment();
361 }
362
363 /// Merges fields from another ArchSpec into this ArchSpec.
364 ///
365 /// This will use the supplied ArchSpec to fill in any fields of the triple
366 /// in this ArchSpec which were unspecified. This can be used to refine a
367 /// generic ArchSpec with a more specific one. For example, if this
368 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we
369 /// have a triple which is x64-pc-windows-msvc, then merging that triple
370 /// into this one will result in the triple i386-pc-windows-msvc.
371 ///
372 void MergeFrom(const ArchSpec &other);
373
374 /// Change the architecture object type, CPU type and OS type.
375 ///
376 /// \param[in] arch_type The object type of this ArchSpec.
377 ///
378 /// \param[in] cpu The required CPU type.
379 ///
380 /// \param[in] os The optional OS type
381 /// The default value of 0 was chosen to from the ELF spec value
382 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another
383 /// format uses this parameter and 0 does not work, use a value over
384 /// 255 because in the ELF header this is value is only a byte.
385 ///
386 /// \return True if the object, and CPU were successfully set.
387 ///
388 /// As a side effect, the vendor value is usually set to unknown. The
389 /// exceptions are
390 /// aarch64-apple-ios
391 /// arm-apple-ios
392 /// thumb-apple-ios
393 /// x86-apple-
394 /// x86_64-apple-
395 ///
396 /// As a side effect, the os value is usually set to unknown The exceptions
397 /// are
398 /// *-*-aix
399 /// aarch64-apple-ios
400 /// arm-apple-ios
401 /// thumb-apple-ios
402 /// powerpc-apple-darwin
403 /// *-*-freebsd
404 /// *-*-linux
405 /// *-*-netbsd
406 /// *-*-openbsd
407 /// *-*-solaris
408 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub,
409 uint32_t os = 0);
410
411 /// Returns the byte order for the architecture specification.
412 ///
413 /// \return The endian enumeration for the current endianness of
414 /// the architecture specification
416
417 /// Sets this ArchSpec's byte order.
418 ///
419 /// In the common case there is no need to call this method as the byte
420 /// order can almost always be determined by the architecture. However, many
421 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed
422 /// byte order may be incorrect.
423 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; }
424
425 uint32_t GetMinimumOpcodeByteSize() const;
426
427 uint32_t GetMaximumOpcodeByteSize() const;
428
429 Core GetCore() const { return m_core; }
430
431 uint32_t GetMachOCPUType() const;
432
433 uint32_t GetMachOCPUSubType() const;
434
435 /// Architecture data byte width accessor
436 ///
437 /// \return the size in 8-bit (host) bytes of a minimum addressable unit
438 /// from the Architecture's data bus
439 uint32_t GetDataByteSize() const;
440
441 /// Architecture code byte width accessor
442 ///
443 /// \return the size in 8-bit (host) bytes of a minimum addressable unit
444 /// from the Architecture's code bus
445 uint32_t GetCodeByteSize() const;
446
447 /// Architecture triple accessor.
448 ///
449 /// \return A triple describing this ArchSpec.
450 llvm::Triple &GetTriple() { return m_triple; }
451
452 /// Architecture triple accessor.
453 ///
454 /// \return A triple describing this ArchSpec.
455 const llvm::Triple &GetTriple() const { return m_triple; }
456
457 void DumpTriple(llvm::raw_ostream &s) const;
458
459 /// Architecture triple setter.
460 ///
461 /// Configures this ArchSpec according to the given triple. If the triple
462 /// has unknown components in all of the vendor, OS, and the optional
463 /// environment field (i.e. "i386-unknown-unknown") then default values are
464 /// taken from the host. Architecture and environment components are used
465 /// to further resolve the CPU type and subtype, endian characteristics,
466 /// etc.
467 ///
468 /// \return A triple describing this ArchSpec.
469 bool SetTriple(const llvm::Triple &triple);
470
471 bool SetTriple(llvm::StringRef triple_str);
472
473 /// Returns the default endianness of the architecture.
474 ///
475 /// \return The endian enumeration for the default endianness of
476 /// the architecture.
478
479 /// Returns true if 'char' is a signed type by default in the architecture
480 /// false otherwise
481 ///
482 /// \return True if 'char' is a signed type by default on the
483 /// architecture and false otherwise.
484 bool CharIsSignedByDefault() const;
485
487
488 /// Compare this ArchSpec to another ArchSpec. \a match specifies the kind of
489 /// matching that is to be done. CompatibleMatch requires only a compatible
490 /// cpu type (e.g., armv7s is compatible with armv7). ExactMatch requires an
491 /// exact match (armv7s is not an exact match with armv7).
492 ///
493 /// \return true if the two ArchSpecs match.
494 bool IsMatch(const ArchSpec &rhs, MatchType match) const;
495
496 /// Shorthand for IsMatch(rhs, ExactMatch).
497 bool IsExactMatch(const ArchSpec &rhs) const {
498 return IsMatch(rhs, ExactMatch);
499 }
500
501 /// Shorthand for IsMatch(rhs, CompatibleMatch).
502 bool IsCompatibleMatch(const ArchSpec &rhs) const {
503 return IsMatch(rhs, CompatibleMatch);
504 }
505
506 bool IsFullySpecifiedTriple() const;
507
508 /// Detect whether this architecture uses thumb code exclusively
509 ///
510 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute
511 /// the Thumb instructions, never Arm. We should normally pick up
512 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints
513 /// on each function - but when doing bare-boards low level debugging
514 /// (especially common with these embedded processors), we may not have
515 /// those things easily accessible.
516 ///
517 /// \return true if this is an arm ArchSpec which can only execute Thumb
518 /// instructions
519 bool IsAlwaysThumbInstructions() const;
520
521 uint32_t GetFlags() const { return m_flags; }
522
523 void SetFlags(uint32_t flags) { m_flags = flags; }
524
525 void SetFlags(const std::string &elf_abi);
526
527protected:
528 void UpdateCore();
529
530 llvm::Triple m_triple;
533
534 // Additional arch flags which we cannot get from triple and core For MIPS
535 // these are application specific extensions like micromips, mips16 etc.
536 uint32_t m_flags = 0;
537
538 // Called when m_def or m_entry are changed. Fills in all remaining members
539 // with default values.
540 void CoreUpdated(bool update_triple);
541};
542
543/// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than
544/// operator.
545///
546/// Tests two ArchSpec objects to see if \a lhs is less than \a rhs.
547///
548/// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in]
549/// rhs The Left Hand Side ArchSpec object to compare.
550///
551/// \return true if \a lhs is less than \a rhs
552bool operator<(const ArchSpec &lhs, const ArchSpec &rhs);
553bool operator==(const ArchSpec &lhs, const ArchSpec &rhs);
554
555bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch);
556
557} // namespace lldb_private
558
559#endif // LLDB_UTILITY_ARCHSPEC_H
An architecture specification class.
Definition: ArchSpec.h:31
static void ListSupportedArchNames(StringList &list)
Definition: ArchSpec.cpp:267
bool IsFullySpecifiedTriple() const
Definition: ArchSpec.cpp:1409
void SetByteOrder(lldb::ByteOrder byte_order)
Sets this ArchSpec's byte order.
Definition: ArchSpec.h:423
static void AutoComplete(CompletionRequest &request)
Definition: ArchSpec.cpp:272
uint32_t GetAddressByteSize() const
Returns the size in bytes of an address of the current architecture.
Definition: ArchSpec.cpp:691
uint32_t GetCodeByteSize() const
Architecture code byte width accessor.
Definition: ArchSpec.cpp:679
bool IsValid() const
Tests if this ArchSpec is valid.
Definition: ArchSpec.h:348
void Clear()
Clears the object state.
Definition: ArchSpec.cpp:542
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:450
void SetFlags(uint32_t flags)
Definition: ArchSpec.h:523
bool IsAlwaysThumbInstructions() const
Detect whether this architecture uses thumb code exclusively.
Definition: ArchSpec.cpp:1424
bool TripleEnvironmentWasSpecified() const
Definition: ArchSpec.h:359
bool IsMatch(const ArchSpec &rhs, MatchType match) const
Compare this ArchSpec to another ArchSpec.
Definition: ArchSpec.cpp:972
bool SetTriple(const llvm::Triple &triple)
Architecture triple setter.
Definition: ArchSpec.cpp:747
llvm::Triple m_triple
Definition: ArchSpec.h:530
lldb::ByteOrder GetDefaultEndian() const
Returns the default endianness of the architecture.
Definition: ArchSpec.cpp:705
lldb::ByteOrder m_byte_order
Definition: ArchSpec.h:532
~ArchSpec()
Destructor.
bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os=0)
Change the architecture object type, CPU type and OS type.
Definition: ArchSpec.cpp:851
void MergeFrom(const ArchSpec &other)
Merges fields from another ArchSpec into this ArchSpec.
Definition: ArchSpec.cpp:809
void DumpTriple(llvm::raw_ostream &s) const
Definition: ArchSpec.cpp:1451
uint32_t GetMachOCPUSubType() const
Definition: ArchSpec.cpp:663
void CoreUpdated(bool update_triple)
Definition: ArchSpec.cpp:1066
bool IsMIPS() const
if MIPS architecture return true.
Definition: ArchSpec.cpp:559
uint32_t GetDataByteSize() const
Architecture data byte width accessor.
Definition: ArchSpec.cpp:675
bool IsCompatibleMatch(const ArchSpec &rhs) const
Shorthand for IsMatch(rhs, CompatibleMatch).
Definition: ArchSpec.h:502
bool CharIsSignedByDefault() const
Returns true if 'char' is a signed type by default in the architecture false otherwise.
Definition: ArchSpec.cpp:712
bool IsExactMatch(const ArchSpec &rhs) const
Shorthand for IsMatch(rhs, ExactMatch).
Definition: ArchSpec.h:497
ArchSpec()
Default constructor.
uint32_t GetMachOCPUType() const
Definition: ArchSpec.cpp:651
std::string GetTargetABI() const
Return a string representing target application ABI.
Definition: ArchSpec.cpp:561
uint32_t GetMinimumOpcodeByteSize() const
Definition: ArchSpec.cpp:927
uint32_t GetFlags() const
Definition: ArchSpec.h:521
lldb::ByteOrder GetByteOrder() const
Returns the byte order for the architecture specification.
Definition: ArchSpec.cpp:738
llvm::Triple::ArchType GetMachine() const
Returns a machine family for the current architecture.
Definition: ArchSpec.cpp:683
@ eRISCV_tso
RVE, +e.
Definition: ArchSpec.h:101
@ eRISCV_float_abi_double
single precision floating point, +f
Definition: ArchSpec.h:97
@ eRISCV_float_abi_soft
RVC, +c.
Definition: ArchSpec.h:95
@ eRISCV_float_abi_quad
double precision floating point, +d
Definition: ArchSpec.h:98
@ eRISCV_float_abi_mask
quad precision floating point, +q
Definition: ArchSpec.h:99
@ eRISCV_float_abi_single
soft float
Definition: ArchSpec.h:96
std::string GetClangTargetCPU() const
Returns a string representing current architecture as a target CPU for tools like compiler,...
Definition: ArchSpec.cpp:597
uint32_t GetMaximumOpcodeByteSize() const
Definition: ArchSpec.cpp:934
bool TripleVendorWasSpecified() const
Definition: ArchSpec.h:353
Core GetCore() const
Definition: ArchSpec.h:429
bool TripleOSWasSpecified() const
Definition: ArchSpec.h:357
static bool ContainsOnlyArch(const llvm::Triple &normalized_triple)
Returns true if the OS, vendor and environment fields of the triple are unset.
Definition: ArchSpec.cpp:802
const llvm::Triple & GetTriple() const
Architecture triple accessor.
Definition: ArchSpec.h:455
const char * GetArchitectureName() const
Returns a static string representing the current architecture.
Definition: ArchSpec.cpp:552
"lldb/Utility/ArgCompletionRequest.h"
A class that represents a running process on the host machine.
Definition: SBAttachInfo.h:14
bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch)
Definition: ArchSpec.cpp:753
bool operator==(const Address &lhs, const Address &rhs)
Definition: Address.cpp:1022
bool operator<(const Address &lhs, const Address &rhs)
Definition: Address.cpp:991
ByteOrder
Byte ordering definitions.
@ eByteOrderInvalid