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RegisterInfos_mips64.h
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1 //===-- RegisterInfos_mips64.h ----------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include <stddef.h>
10 
11 #include "lldb/Core/dwarf.h"
12 #include "llvm/Support/Compiler.h"
13 
14 
15 #ifdef DECLARE_REGISTER_INFOS_MIPS64_STRUCT
16 
17 // Computes the offset of the given GPR in the user data area.
18 #ifdef LINUX_MIPS64
19 #define GPR_OFFSET(regname) \
20  (LLVM_EXTENSION offsetof(UserArea, gpr) + \
21  LLVM_EXTENSION offsetof(GPR_linux_mips, regname))
22 #else
23 #define GPR_OFFSET(regname) (LLVM_EXTENSION offsetof(GPR_freebsd_mips, regname))
24 #endif
25 
26 // Computes the offset of the given FPR in the extended data area.
27 #define FPR_OFFSET(regname) \
28  (LLVM_EXTENSION offsetof(UserArea, fpr) + \
29  LLVM_EXTENSION offsetof(FPR_linux_mips, regname))
30 
31 // Computes the offset of the given MSA in the extended data area.
32 #define MSA_OFFSET(regname) \
33  (LLVM_EXTENSION offsetof(UserArea, msa) + \
34  LLVM_EXTENSION offsetof(MSA_linux_mips, regname))
35 
36 // RegisterKind: EHFrame, DWARF, Generic, Process Plugin, LLDB
37 
38 // Note that the size and offset will be updated by platform-specific classes.
39 #ifdef LINUX_MIPS64
40 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3) \
41  { \
42  #reg, alt, sizeof(((GPR_linux_mips *) 0)->reg), \
43  GPR_OFFSET(reg), eEncodingUint, eFormatHex, \
44  {kind1, kind2, kind3, ptrace_##reg##_mips, \
45  gpr_##reg##_mips64 }, \
46  NULL, NULL, NULL, 0 \
47  }
48 #else
49 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
50  { \
51  #reg, alt, sizeof(((GPR_freebsd_mips *) 0)->reg), \
52  GPR_OFFSET(reg), eEncodingUint, eFormatHex, \
53  {kind1, kind2, kind3, kind4, \
54  gpr_##reg##_mips64 }, \
55  NULL, NULL, NULL, 0 \
56  }
57 #endif
58 
59 #define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3) \
60  { \
61  #reg, alt, sizeof(((GPR_linux_mips *) 0)->reg) / 2, \
62  GPR_OFFSET(reg), eEncodingUint, eFormatHex, \
63  {kind1, kind2, kind3, ptrace_##reg##_mips, \
64  gpr_##reg##_mips64 }, \
65  NULL, NULL, NULL, 0 \
66  }
67 
68 const uint8_t dwarf_opcode_mips64[] = {
69  llvm::dwarf::DW_OP_regx, dwarf_sr_mips64, llvm::dwarf::DW_OP_lit1,
70  llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shl, llvm::dwarf::DW_OP_and,
71  llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shr};
72 
73 #define DEFINE_FPR(reg, alt, kind1, kind2, kind3) \
74  { \
75  #reg, alt, sizeof(((FPR_linux_mips *) 0)->reg), \
76  FPR_OFFSET(reg), eEncodingIEEE754, eFormatFloat, \
77  {kind1, kind2, kind3, ptrace_##reg##_mips, \
78  fpr_##reg##_mips64 }, \
79  NULL, NULL, dwarf_opcode_mips64, \
80  sizeof(dwarf_opcode_mips64) \
81  }
82 
83 #define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3) \
84  { \
85  #reg, alt, sizeof(((FPR_linux_mips *) 0)->reg), \
86  FPR_OFFSET(reg), eEncodingUint, eFormatHex, \
87  {kind1, kind2, kind3, ptrace_##reg##_mips, \
88  fpr_##reg##_mips64 }, \
89  NULL, NULL, NULL, 0 \
90  }
91 
92 #define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4) \
93  { \
94  #reg, alt, sizeof(((MSA_linux_mips *) 0)->reg), \
95  MSA_OFFSET(reg), eEncodingVector, eFormatVectorOfUInt8, \
96  {kind1, kind2, kind3, kind4, \
97  msa_##reg##_mips64 }, \
98  NULL, NULL, NULL, 0 \
99  }
100 
101 #define DEFINE_MSA_INFO(reg, alt, kind1, kind2, kind3, kind4) \
102  { \
103  #reg, alt, sizeof(((MSA_linux_mips *) 0)->reg), \
104  MSA_OFFSET(reg), eEncodingUint, eFormatHex, \
105  {kind1, kind2, kind3, kind4, \
106  msa_##reg##_mips64 }, \
107  NULL, NULL, NULL, 0 \
108  }
109 
110 static RegisterInfo g_register_infos_mips64[] = {
111 // General purpose registers. EH_Frame, DWARF,
112 // Generic, Process Plugin
113 #ifndef LINUX_MIPS64
180  DEFINE_GPR(mullo, nullptr, dwarf_lo_mips64, dwarf_lo_mips64,
182  DEFINE_GPR(mulhi, nullptr, dwarf_hi_mips64, dwarf_hi_mips64,
184  DEFINE_GPR(badvaddr, nullptr, dwarf_bad_mips64, dwarf_bad_mips64,
194 #else
259  DEFINE_GPR_INFO(sr, nullptr, dwarf_sr_mips64, dwarf_sr_mips64,
261  DEFINE_GPR(mullo, nullptr, dwarf_lo_mips64, dwarf_lo_mips64,
263  DEFINE_GPR(mulhi, nullptr, dwarf_hi_mips64, dwarf_hi_mips64,
265  DEFINE_GPR(badvaddr, nullptr, dwarf_bad_mips64, dwarf_bad_mips64,
267  DEFINE_GPR_INFO(cause, nullptr, dwarf_cause_mips64, dwarf_cause_mips64,
271  DEFINE_GPR_INFO(config5, nullptr, dwarf_config5_mips64,
273  DEFINE_FPR(f0, nullptr, dwarf_f0_mips64, dwarf_f0_mips64,
275  DEFINE_FPR(f1, nullptr, dwarf_f1_mips64, dwarf_f1_mips64,
277  DEFINE_FPR(f2, nullptr, dwarf_f2_mips64, dwarf_f2_mips64,
279  DEFINE_FPR(f3, nullptr, dwarf_f3_mips64, dwarf_f3_mips64,
281  DEFINE_FPR(f4, nullptr, dwarf_f4_mips64, dwarf_f4_mips64,
283  DEFINE_FPR(f5, nullptr, dwarf_f5_mips64, dwarf_f5_mips64,
285  DEFINE_FPR(f6, nullptr, dwarf_f6_mips64, dwarf_f6_mips64,
287  DEFINE_FPR(f7, nullptr, dwarf_f7_mips64, dwarf_f7_mips64,
289  DEFINE_FPR(f8, nullptr, dwarf_f8_mips64, dwarf_f8_mips64,
291  DEFINE_FPR(f9, nullptr, dwarf_f9_mips64, dwarf_f9_mips64,
293  DEFINE_FPR(f10, nullptr, dwarf_f10_mips64, dwarf_f10_mips64,
295  DEFINE_FPR(f11, nullptr, dwarf_f11_mips64, dwarf_f11_mips64,
297  DEFINE_FPR(f12, nullptr, dwarf_f12_mips64, dwarf_f12_mips64,
299  DEFINE_FPR(f13, nullptr, dwarf_f13_mips64, dwarf_f13_mips64,
301  DEFINE_FPR(f14, nullptr, dwarf_f14_mips64, dwarf_f14_mips64,
303  DEFINE_FPR(f15, nullptr, dwarf_f15_mips64, dwarf_f15_mips64,
305  DEFINE_FPR(f16, nullptr, dwarf_f16_mips64, dwarf_f16_mips64,
307  DEFINE_FPR(f17, nullptr, dwarf_f17_mips64, dwarf_f17_mips64,
309  DEFINE_FPR(f18, nullptr, dwarf_f18_mips64, dwarf_f18_mips64,
311  DEFINE_FPR(f19, nullptr, dwarf_f19_mips64, dwarf_f19_mips64,
313  DEFINE_FPR(f20, nullptr, dwarf_f20_mips64, dwarf_f20_mips64,
315  DEFINE_FPR(f21, nullptr, dwarf_f21_mips64, dwarf_f21_mips64,
317  DEFINE_FPR(f22, nullptr, dwarf_f22_mips64, dwarf_f22_mips64,
319  DEFINE_FPR(f23, nullptr, dwarf_f23_mips64, dwarf_f23_mips64,
321  DEFINE_FPR(f24, nullptr, dwarf_f24_mips64, dwarf_f24_mips64,
323  DEFINE_FPR(f25, nullptr, dwarf_f25_mips64, dwarf_f25_mips64,
325  DEFINE_FPR(f26, nullptr, dwarf_f26_mips64, dwarf_f26_mips64,
327  DEFINE_FPR(f27, nullptr, dwarf_f27_mips64, dwarf_f27_mips64,
329  DEFINE_FPR(f28, nullptr, dwarf_f28_mips64, dwarf_f28_mips64,
331  DEFINE_FPR(f29, nullptr, dwarf_f29_mips64, dwarf_f29_mips64,
333  DEFINE_FPR(f30, nullptr, dwarf_f30_mips64, dwarf_f30_mips64,
335  DEFINE_FPR(f31, nullptr, dwarf_f31_mips64, dwarf_f31_mips64,
337  DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips64, dwarf_fcsr_mips64,
339  DEFINE_FPR_INFO(fir, nullptr, dwarf_fir_mips64, dwarf_fir_mips64,
341  DEFINE_FPR_INFO(config5, nullptr, dwarf_config5_mips64,
343  DEFINE_MSA(w0, nullptr, dwarf_w0_mips64, dwarf_w0_mips64,
345  DEFINE_MSA(w1, nullptr, dwarf_w1_mips64, dwarf_w1_mips64,
347  DEFINE_MSA(w2, nullptr, dwarf_w2_mips64, dwarf_w2_mips64,
349  DEFINE_MSA(w3, nullptr, dwarf_w3_mips64, dwarf_w3_mips64,
351  DEFINE_MSA(w4, nullptr, dwarf_w4_mips64, dwarf_w4_mips64,
353  DEFINE_MSA(w5, nullptr, dwarf_w5_mips64, dwarf_w5_mips64,
355  DEFINE_MSA(w6, nullptr, dwarf_w6_mips64, dwarf_w6_mips64,
357  DEFINE_MSA(w7, nullptr, dwarf_w7_mips64, dwarf_w7_mips64,
359  DEFINE_MSA(w8, nullptr, dwarf_w8_mips64, dwarf_w8_mips64,
361  DEFINE_MSA(w9, nullptr, dwarf_w9_mips64, dwarf_w9_mips64,
363  DEFINE_MSA(w10, nullptr, dwarf_w10_mips64, dwarf_w10_mips64,
365  DEFINE_MSA(w11, nullptr, dwarf_w11_mips64, dwarf_w11_mips64,
367  DEFINE_MSA(w12, nullptr, dwarf_w12_mips64, dwarf_w12_mips64,
369  DEFINE_MSA(w13, nullptr, dwarf_w13_mips64, dwarf_w13_mips64,
371  DEFINE_MSA(w14, nullptr, dwarf_w14_mips64, dwarf_w14_mips64,
373  DEFINE_MSA(w15, nullptr, dwarf_w15_mips64, dwarf_w15_mips64,
375  DEFINE_MSA(w16, nullptr, dwarf_w16_mips64, dwarf_w16_mips64,
377  DEFINE_MSA(w17, nullptr, dwarf_w17_mips64, dwarf_w17_mips64,
379  DEFINE_MSA(w18, nullptr, dwarf_w18_mips64, dwarf_w18_mips64,
381  DEFINE_MSA(w19, nullptr, dwarf_w19_mips64, dwarf_w19_mips64,
383  DEFINE_MSA(w20, nullptr, dwarf_w10_mips64, dwarf_w20_mips64,
385  DEFINE_MSA(w21, nullptr, dwarf_w21_mips64, dwarf_w21_mips64,
387  DEFINE_MSA(w22, nullptr, dwarf_w22_mips64, dwarf_w22_mips64,
389  DEFINE_MSA(w23, nullptr, dwarf_w23_mips64, dwarf_w23_mips64,
391  DEFINE_MSA(w24, nullptr, dwarf_w24_mips64, dwarf_w24_mips64,
393  DEFINE_MSA(w25, nullptr, dwarf_w25_mips64, dwarf_w25_mips64,
395  DEFINE_MSA(w26, nullptr, dwarf_w26_mips64, dwarf_w26_mips64,
397  DEFINE_MSA(w27, nullptr, dwarf_w27_mips64, dwarf_w27_mips64,
399  DEFINE_MSA(w28, nullptr, dwarf_w28_mips64, dwarf_w28_mips64,
401  DEFINE_MSA(w29, nullptr, dwarf_w29_mips64, dwarf_w29_mips64,
403  DEFINE_MSA(w30, nullptr, dwarf_w30_mips64, dwarf_w30_mips64,
405  DEFINE_MSA(w31, nullptr, dwarf_w31_mips64, dwarf_w31_mips64,
407  DEFINE_MSA_INFO(mcsr, nullptr, dwarf_mcsr_mips64, dwarf_mcsr_mips64,
409  DEFINE_MSA_INFO(mir, nullptr, dwarf_mir_mips64, dwarf_mir_mips64,
411  DEFINE_MSA_INFO(fcsr, nullptr, dwarf_fcsr_mips64, dwarf_fcsr_mips64,
413  DEFINE_MSA_INFO(fir, nullptr, dwarf_fir_mips64, dwarf_fir_mips64,
415  DEFINE_MSA_INFO(config5, nullptr, dwarf_config5_mips64,
418 #endif
419 };
420 
421 static_assert((sizeof(g_register_infos_mips64) /
423  "g_register_infos_mips64 has wrong number of register infos");
424 
425 #undef DEFINE_GPR
426 #undef DEFINE_GPR_INFO
427 #undef DEFINE_FPR
428 #undef DEFINE_FPR_INFO
429 #undef DEFINE_MSA
430 #undef DEFINE_MSA_INFO
431 #undef GPR_OFFSET
432 #undef FPR_OFFSET
433 #undef MSA_OFFSET
434 
435 #endif // DECLARE_REGISTER_INFOS_MIPS64_STRUCT
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:63
#define LLDB_REGNUM_GENERIC_ARG6
Definition: lldb-defines.h:78
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:66
#define LLDB_REGNUM_GENERIC_ARG4
Definition: lldb-defines.h:74
#define LLDB_REGNUM_GENERIC_ARG2
Definition: lldb-defines.h:70
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:64
#define LLDB_REGNUM_GENERIC_ARG7
Definition: lldb-defines.h:80
#define LLDB_REGNUM_GENERIC_ARG5
Definition: lldb-defines.h:76
#define LLDB_REGNUM_GENERIC_ARG1
Definition: lldb-defines.h:68
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:65
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:67
#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)
#define LLDB_REGNUM_GENERIC_ARG8
Definition: lldb-defines.h:82
#define LLDB_REGNUM_GENERIC_ARG3
Definition: lldb-defines.h:72
static const RegisterInfo g_register_infos_mips64[]
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:90