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RegisterInfos_riscv32.h
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1//===-- RegisterInfos_riscv32.h ---------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifdef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
10
11#include "Utility/RISCV_DWARF_Registers.h"
12#include "lldb-riscv-register-enums.h"
13#include "lldb/lldb-defines.h"
14#include "lldb/lldb-enumerations.h"
15#include "lldb/lldb-private.h"
16
17#include <stddef.h>
18
19#ifndef GPR_OFFSET
20#error GPR_OFFSET must be defined before including this header file
21#endif
22
23#ifndef FPR_OFFSET
24#error FPR_OFFSET must be defined before including this header file
25#endif
26
27using namespace riscv_dwarf;
28
29// Assuming register numbers seen in eh_frame and DWARF to be the same.
30#define KIND_HELPER(reg, generic_kind) \
31 {riscv_dwarf::dwarf_##reg, riscv_dwarf::dwarf_##reg, generic_kind, \
32 LLDB_INVALID_REGNUM, reg##_riscv}
33
34// Generates RegisterInfo::kinds for GPRs.
35#define GPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
36
37// Generates RegisterInfo::kinds for FPRs.
38#define FPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
39
40// Generates RegisterInfo::kinds for VPRs.
41#define VPR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
42
43// Generates RegisterInfo::kinds for CSRs.
44#define CSR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
45
46// Defines a 32-bit GPR.
47#define DEFINE_GPR32(reg, generic_kind) DEFINE_GPR32_ALT(reg, reg, generic_kind)
48
49// Defines a 32-bit GPR.
50#define DEFINE_GPR32_ALT(reg, alt, generic_kind) \
51 {#reg, \
52 #alt, \
53 4, \
54 GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv), \
55 lldb::eEncodingUint, \
56 lldb::eFormatHex, \
57 GPR32_KIND(gpr_##reg, generic_kind), \
58 nullptr, \
59 nullptr, \
60 nullptr}
61
62// Defines a 32-bit FPR.
63#define DEFINE_FPR32_ALT(reg, alt, generic_kind) \
64 DEFINE_FPR_ALT(reg, alt, 8, generic_kind)
65
66// Defines a 32-bit FPR.
67#define DEFINE_FPR_ALT(reg, alt, size, generic_kind) \
68 {#reg, \
69 #alt, \
70 size, \
71 FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \
72 lldb::eEncodingIEEE754, \
73 lldb::eFormatHex, \
74 FPR32_KIND(fpr_##reg, generic_kind), \
75 nullptr, \
76 nullptr, \
77 nullptr}
78
79// Defines a 32-bit VPR.
80#define DEFINE_VPR(reg, generic_kind) DEFINE_VPR_ALT(reg, reg, generic_kind)
81
82// Defines a scalable vector register with default size of 128 bits.
83// The byte offset of 0 is a placeholder and should be corrected at runtime.
84// Defines a 32-bit VPR.
85#define DEFINE_VPR_ALT(reg, alt, generic_kind) \
86 {#reg, \
87 #alt, \
88 16, \
89 0, \
90 lldb::eEncodingVector, \
91 lldb::eFormatVectorOfUInt8, \
92 VPR_KIND(vpr_##reg, generic_kind), \
93 nullptr, \
94 nullptr, \
95 nullptr}
96
97// Defines a 32-bit CSR.
98#define DEFINE_CSR32(reg, generic_kind) DEFINE_CSR32_ALT(reg, reg, generic_kind)
99
100// Defines a 32-bit CSR.
101// The byte offset of 0 is a placeholder and should be corrected at runtime.
102#define DEFINE_CSR32_ALT(reg, alt, generic_kind) \
103 {#reg, \
104 #alt, \
105 4, \
106 0, \
107 lldb::eEncodingUint, \
108 lldb::eFormatHex, \
109 CSR_KIND(csr_##reg, generic_kind), \
110 nullptr, \
111 nullptr, \
112 nullptr}
113
114static lldb_private::RegisterInfo g_register_infos_riscv32_le[] = {
115 // DEFINE_GPR32(name, GENERIC KIND)
116 DEFINE_GPR32(pc, LLDB_REGNUM_GENERIC_PC),
117 DEFINE_GPR32_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
118 DEFINE_GPR32_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
119 DEFINE_GPR32_ALT(gp, x3, LLDB_INVALID_REGNUM),
120 DEFINE_GPR32_ALT(tp, x4, LLDB_INVALID_REGNUM),
121 DEFINE_GPR32_ALT(t0, x5, LLDB_INVALID_REGNUM),
122 DEFINE_GPR32_ALT(t1, x6, LLDB_INVALID_REGNUM),
123 DEFINE_GPR32_ALT(t2, x7, LLDB_INVALID_REGNUM),
124 DEFINE_GPR32_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
125 DEFINE_GPR32_ALT(s1, x9, LLDB_INVALID_REGNUM),
126 DEFINE_GPR32_ALT(a0, x10, LLDB_REGNUM_GENERIC_ARG1),
127 DEFINE_GPR32_ALT(a1, x11, LLDB_REGNUM_GENERIC_ARG2),
128 DEFINE_GPR32_ALT(a2, x12, LLDB_REGNUM_GENERIC_ARG3),
129 DEFINE_GPR32_ALT(a3, x13, LLDB_REGNUM_GENERIC_ARG4),
130 DEFINE_GPR32_ALT(a4, x14, LLDB_REGNUM_GENERIC_ARG5),
131 DEFINE_GPR32_ALT(a5, x15, LLDB_REGNUM_GENERIC_ARG6),
132 DEFINE_GPR32_ALT(a6, x16, LLDB_REGNUM_GENERIC_ARG7),
133 DEFINE_GPR32_ALT(a7, x17, LLDB_REGNUM_GENERIC_ARG8),
134 DEFINE_GPR32_ALT(s2, x18, LLDB_INVALID_REGNUM),
135 DEFINE_GPR32_ALT(s3, x19, LLDB_INVALID_REGNUM),
136 DEFINE_GPR32_ALT(s4, x20, LLDB_INVALID_REGNUM),
137 DEFINE_GPR32_ALT(s5, x21, LLDB_INVALID_REGNUM),
138 DEFINE_GPR32_ALT(s6, x22, LLDB_INVALID_REGNUM),
139 DEFINE_GPR32_ALT(s7, x23, LLDB_INVALID_REGNUM),
140 DEFINE_GPR32_ALT(s8, x24, LLDB_INVALID_REGNUM),
141 DEFINE_GPR32_ALT(s9, x25, LLDB_INVALID_REGNUM),
142 DEFINE_GPR32_ALT(s10, x26, LLDB_INVALID_REGNUM),
143 DEFINE_GPR32_ALT(s11, x27, LLDB_INVALID_REGNUM),
144 DEFINE_GPR32_ALT(t3, x28, LLDB_INVALID_REGNUM),
145 DEFINE_GPR32_ALT(t4, x29, LLDB_INVALID_REGNUM),
146 DEFINE_GPR32_ALT(t5, x30, LLDB_INVALID_REGNUM),
147 DEFINE_GPR32_ALT(t6, x31, LLDB_INVALID_REGNUM),
148 DEFINE_GPR32_ALT(zero, x0, LLDB_INVALID_REGNUM),
149
150 DEFINE_FPR32_ALT(ft0, f0, LLDB_INVALID_REGNUM),
151 DEFINE_FPR32_ALT(ft1, f1, LLDB_INVALID_REGNUM),
152 DEFINE_FPR32_ALT(ft2, f2, LLDB_INVALID_REGNUM),
153 DEFINE_FPR32_ALT(ft3, f3, LLDB_INVALID_REGNUM),
154 DEFINE_FPR32_ALT(ft4, f4, LLDB_INVALID_REGNUM),
155 DEFINE_FPR32_ALT(ft5, f5, LLDB_INVALID_REGNUM),
156 DEFINE_FPR32_ALT(ft6, f6, LLDB_INVALID_REGNUM),
157 DEFINE_FPR32_ALT(ft7, f7, LLDB_INVALID_REGNUM),
158 DEFINE_FPR32_ALT(fs0, f8, LLDB_INVALID_REGNUM),
159 DEFINE_FPR32_ALT(fs1, f9, LLDB_INVALID_REGNUM),
160 DEFINE_FPR32_ALT(fa0, f10, LLDB_INVALID_REGNUM),
161 DEFINE_FPR32_ALT(fa1, f11, LLDB_INVALID_REGNUM),
162 DEFINE_FPR32_ALT(fa2, f12, LLDB_INVALID_REGNUM),
163 DEFINE_FPR32_ALT(fa3, f13, LLDB_INVALID_REGNUM),
164 DEFINE_FPR32_ALT(fa4, f14, LLDB_INVALID_REGNUM),
165 DEFINE_FPR32_ALT(fa5, f15, LLDB_INVALID_REGNUM),
166 DEFINE_FPR32_ALT(fa6, f16, LLDB_INVALID_REGNUM),
167 DEFINE_FPR32_ALT(fa7, f17, LLDB_INVALID_REGNUM),
168 DEFINE_FPR32_ALT(fs2, f18, LLDB_INVALID_REGNUM),
169 DEFINE_FPR32_ALT(fs3, f19, LLDB_INVALID_REGNUM),
170 DEFINE_FPR32_ALT(fs4, f20, LLDB_INVALID_REGNUM),
171 DEFINE_FPR32_ALT(fs5, f21, LLDB_INVALID_REGNUM),
172 DEFINE_FPR32_ALT(fs6, f22, LLDB_INVALID_REGNUM),
173 DEFINE_FPR32_ALT(fs7, f23, LLDB_INVALID_REGNUM),
174 DEFINE_FPR32_ALT(fs8, f24, LLDB_INVALID_REGNUM),
175 DEFINE_FPR32_ALT(fs9, f25, LLDB_INVALID_REGNUM),
176 DEFINE_FPR32_ALT(fs10, f26, LLDB_INVALID_REGNUM),
177 DEFINE_FPR32_ALT(fs11, f27, LLDB_INVALID_REGNUM),
178 DEFINE_FPR32_ALT(ft8, f28, LLDB_INVALID_REGNUM),
179 DEFINE_FPR32_ALT(ft9, f29, LLDB_INVALID_REGNUM),
180 DEFINE_FPR32_ALT(ft10, f30, LLDB_INVALID_REGNUM),
181 DEFINE_FPR32_ALT(ft11, f31, LLDB_INVALID_REGNUM),
182 DEFINE_FPR_ALT(fcsr, nullptr, 4, LLDB_INVALID_REGNUM),
183
184 DEFINE_VPR(v0, LLDB_INVALID_REGNUM),
185 DEFINE_VPR(v1, LLDB_INVALID_REGNUM),
186 DEFINE_VPR(v2, LLDB_INVALID_REGNUM),
187 DEFINE_VPR(v3, LLDB_INVALID_REGNUM),
188 DEFINE_VPR(v4, LLDB_INVALID_REGNUM),
189 DEFINE_VPR(v5, LLDB_INVALID_REGNUM),
190 DEFINE_VPR(v6, LLDB_INVALID_REGNUM),
191 DEFINE_VPR(v7, LLDB_INVALID_REGNUM),
192 DEFINE_VPR(v8, LLDB_INVALID_REGNUM),
193 DEFINE_VPR(v9, LLDB_INVALID_REGNUM),
194 DEFINE_VPR(v10, LLDB_INVALID_REGNUM),
195 DEFINE_VPR(v11, LLDB_INVALID_REGNUM),
196 DEFINE_VPR(v12, LLDB_INVALID_REGNUM),
197 DEFINE_VPR(v13, LLDB_INVALID_REGNUM),
198 DEFINE_VPR(v14, LLDB_INVALID_REGNUM),
199 DEFINE_VPR(v15, LLDB_INVALID_REGNUM),
200 DEFINE_VPR(v16, LLDB_INVALID_REGNUM),
201 DEFINE_VPR(v17, LLDB_INVALID_REGNUM),
202 DEFINE_VPR(v18, LLDB_INVALID_REGNUM),
203 DEFINE_VPR(v19, LLDB_INVALID_REGNUM),
204 DEFINE_VPR(v20, LLDB_INVALID_REGNUM),
205 DEFINE_VPR(v21, LLDB_INVALID_REGNUM),
206 DEFINE_VPR(v22, LLDB_INVALID_REGNUM),
207 DEFINE_VPR(v23, LLDB_INVALID_REGNUM),
208 DEFINE_VPR(v24, LLDB_INVALID_REGNUM),
209 DEFINE_VPR(v25, LLDB_INVALID_REGNUM),
210 DEFINE_VPR(v26, LLDB_INVALID_REGNUM),
211 DEFINE_VPR(v27, LLDB_INVALID_REGNUM),
212 DEFINE_VPR(v28, LLDB_INVALID_REGNUM),
213 DEFINE_VPR(v29, LLDB_INVALID_REGNUM),
214 DEFINE_VPR(v30, LLDB_INVALID_REGNUM),
215 DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
216};
217
218static lldb_private::RegisterInfo g_register_infos_riscv32_gpr[] = {
219 DEFINE_GPR32(pc, LLDB_REGNUM_GENERIC_PC),
220 DEFINE_GPR32_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
221 DEFINE_GPR32_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
222 DEFINE_GPR32_ALT(gp, x3, LLDB_INVALID_REGNUM),
223 DEFINE_GPR32_ALT(tp, x4, LLDB_INVALID_REGNUM),
224 DEFINE_GPR32_ALT(t0, x5, LLDB_INVALID_REGNUM),
225 DEFINE_GPR32_ALT(t1, x6, LLDB_INVALID_REGNUM),
226 DEFINE_GPR32_ALT(t2, x7, LLDB_INVALID_REGNUM),
227 DEFINE_GPR32_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
228 DEFINE_GPR32_ALT(s1, x9, LLDB_INVALID_REGNUM),
229 DEFINE_GPR32_ALT(a0, x10, LLDB_REGNUM_GENERIC_ARG1),
230 DEFINE_GPR32_ALT(a1, x11, LLDB_REGNUM_GENERIC_ARG2),
231 DEFINE_GPR32_ALT(a2, x12, LLDB_REGNUM_GENERIC_ARG3),
232 DEFINE_GPR32_ALT(a3, x13, LLDB_REGNUM_GENERIC_ARG4),
233 DEFINE_GPR32_ALT(a4, x14, LLDB_REGNUM_GENERIC_ARG5),
234 DEFINE_GPR32_ALT(a5, x15, LLDB_REGNUM_GENERIC_ARG6),
235 DEFINE_GPR32_ALT(a6, x16, LLDB_REGNUM_GENERIC_ARG7),
236 DEFINE_GPR32_ALT(a7, x17, LLDB_REGNUM_GENERIC_ARG8),
237 DEFINE_GPR32_ALT(s2, x18, LLDB_INVALID_REGNUM),
238 DEFINE_GPR32_ALT(s3, x19, LLDB_INVALID_REGNUM),
239 DEFINE_GPR32_ALT(s4, x20, LLDB_INVALID_REGNUM),
240 DEFINE_GPR32_ALT(s5, x21, LLDB_INVALID_REGNUM),
241 DEFINE_GPR32_ALT(s6, x22, LLDB_INVALID_REGNUM),
242 DEFINE_GPR32_ALT(s7, x23, LLDB_INVALID_REGNUM),
243 DEFINE_GPR32_ALT(s8, x24, LLDB_INVALID_REGNUM),
244 DEFINE_GPR32_ALT(s9, x25, LLDB_INVALID_REGNUM),
245 DEFINE_GPR32_ALT(s10, x26, LLDB_INVALID_REGNUM),
246 DEFINE_GPR32_ALT(s11, x27, LLDB_INVALID_REGNUM),
247 DEFINE_GPR32_ALT(t3, x28, LLDB_INVALID_REGNUM),
248 DEFINE_GPR32_ALT(t4, x29, LLDB_INVALID_REGNUM),
249 DEFINE_GPR32_ALT(t5, x30, LLDB_INVALID_REGNUM),
250 DEFINE_GPR32_ALT(t6, x31, LLDB_INVALID_REGNUM),
251 DEFINE_GPR32_ALT(zero, x0, LLDB_INVALID_REGNUM),
252};
253
254static lldb_private::RegisterInfo g_register_infos_riscv32_fpr[] = {
255 DEFINE_FPR32_ALT(ft0, f0, LLDB_INVALID_REGNUM),
256 DEFINE_FPR32_ALT(ft1, f1, LLDB_INVALID_REGNUM),
257 DEFINE_FPR32_ALT(ft2, f2, LLDB_INVALID_REGNUM),
258 DEFINE_FPR32_ALT(ft3, f3, LLDB_INVALID_REGNUM),
259 DEFINE_FPR32_ALT(ft4, f4, LLDB_INVALID_REGNUM),
260 DEFINE_FPR32_ALT(ft5, f5, LLDB_INVALID_REGNUM),
261 DEFINE_FPR32_ALT(ft6, f6, LLDB_INVALID_REGNUM),
262 DEFINE_FPR32_ALT(ft7, f7, LLDB_INVALID_REGNUM),
263 DEFINE_FPR32_ALT(fs0, f8, LLDB_INVALID_REGNUM),
264 DEFINE_FPR32_ALT(fs1, f9, LLDB_INVALID_REGNUM),
265 DEFINE_FPR32_ALT(fa0, f10, LLDB_INVALID_REGNUM),
266 DEFINE_FPR32_ALT(fa1, f11, LLDB_INVALID_REGNUM),
267 DEFINE_FPR32_ALT(fa2, f12, LLDB_INVALID_REGNUM),
268 DEFINE_FPR32_ALT(fa3, f13, LLDB_INVALID_REGNUM),
269 DEFINE_FPR32_ALT(fa4, f14, LLDB_INVALID_REGNUM),
270 DEFINE_FPR32_ALT(fa5, f15, LLDB_INVALID_REGNUM),
271 DEFINE_FPR32_ALT(fa6, f16, LLDB_INVALID_REGNUM),
272 DEFINE_FPR32_ALT(fa7, f17, LLDB_INVALID_REGNUM),
273 DEFINE_FPR32_ALT(fs2, f18, LLDB_INVALID_REGNUM),
274 DEFINE_FPR32_ALT(fs3, f19, LLDB_INVALID_REGNUM),
275 DEFINE_FPR32_ALT(fs4, f20, LLDB_INVALID_REGNUM),
276 DEFINE_FPR32_ALT(fs5, f21, LLDB_INVALID_REGNUM),
277 DEFINE_FPR32_ALT(fs6, f22, LLDB_INVALID_REGNUM),
278 DEFINE_FPR32_ALT(fs7, f23, LLDB_INVALID_REGNUM),
279 DEFINE_FPR32_ALT(fs8, f24, LLDB_INVALID_REGNUM),
280 DEFINE_FPR32_ALT(fs9, f25, LLDB_INVALID_REGNUM),
281 DEFINE_FPR32_ALT(fs10, f26, LLDB_INVALID_REGNUM),
282 DEFINE_FPR32_ALT(fs11, f27, LLDB_INVALID_REGNUM),
283 DEFINE_FPR32_ALT(ft8, f28, LLDB_INVALID_REGNUM),
284 DEFINE_FPR32_ALT(ft9, f29, LLDB_INVALID_REGNUM),
285 DEFINE_FPR32_ALT(ft10, f30, LLDB_INVALID_REGNUM),
286 DEFINE_FPR32_ALT(ft11, f31, LLDB_INVALID_REGNUM),
287};
288
289static lldb_private::RegisterInfo g_register_infos_riscv32_vpr[] = {
290 DEFINE_VPR(v0, LLDB_INVALID_REGNUM), DEFINE_VPR(v1, LLDB_INVALID_REGNUM),
291 DEFINE_VPR(v2, LLDB_INVALID_REGNUM), DEFINE_VPR(v3, LLDB_INVALID_REGNUM),
292 DEFINE_VPR(v4, LLDB_INVALID_REGNUM), DEFINE_VPR(v5, LLDB_INVALID_REGNUM),
293 DEFINE_VPR(v6, LLDB_INVALID_REGNUM), DEFINE_VPR(v7, LLDB_INVALID_REGNUM),
294 DEFINE_VPR(v8, LLDB_INVALID_REGNUM), DEFINE_VPR(v9, LLDB_INVALID_REGNUM),
295 DEFINE_VPR(v10, LLDB_INVALID_REGNUM), DEFINE_VPR(v11, LLDB_INVALID_REGNUM),
296 DEFINE_VPR(v12, LLDB_INVALID_REGNUM), DEFINE_VPR(v13, LLDB_INVALID_REGNUM),
297 DEFINE_VPR(v14, LLDB_INVALID_REGNUM), DEFINE_VPR(v15, LLDB_INVALID_REGNUM),
298 DEFINE_VPR(v16, LLDB_INVALID_REGNUM), DEFINE_VPR(v17, LLDB_INVALID_REGNUM),
299 DEFINE_VPR(v18, LLDB_INVALID_REGNUM), DEFINE_VPR(v19, LLDB_INVALID_REGNUM),
300 DEFINE_VPR(v20, LLDB_INVALID_REGNUM), DEFINE_VPR(v21, LLDB_INVALID_REGNUM),
301 DEFINE_VPR(v22, LLDB_INVALID_REGNUM), DEFINE_VPR(v23, LLDB_INVALID_REGNUM),
302 DEFINE_VPR(v24, LLDB_INVALID_REGNUM), DEFINE_VPR(v25, LLDB_INVALID_REGNUM),
303 DEFINE_VPR(v26, LLDB_INVALID_REGNUM), DEFINE_VPR(v27, LLDB_INVALID_REGNUM),
304 DEFINE_VPR(v28, LLDB_INVALID_REGNUM), DEFINE_VPR(v29, LLDB_INVALID_REGNUM),
305 DEFINE_VPR(v30, LLDB_INVALID_REGNUM), DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
306};
307
308static lldb_private::RegisterInfo g_register_infos_riscv32_csr_patch[] = {
309 DEFINE_CSR32_ALT(fflags, csr_0x001, LLDB_INVALID_REGNUM),
310 DEFINE_CSR32_ALT(frm, csr_0x002, LLDB_INVALID_REGNUM),
311 DEFINE_CSR32_ALT(fcsr, csr_0x003, LLDB_INVALID_REGNUM),
312 DEFINE_CSR32_ALT(vstart, csr_0x008, LLDB_INVALID_REGNUM),
313 DEFINE_CSR32_ALT(vxsat, csr_0x009, LLDB_INVALID_REGNUM),
314 DEFINE_CSR32_ALT(vxrm, csr_0x00a, LLDB_INVALID_REGNUM),
315 DEFINE_CSR32_ALT(vcsr, csr_0x00f, LLDB_INVALID_REGNUM),
316 DEFINE_CSR32_ALT(sstatus, csr_0x100, LLDB_INVALID_REGNUM),
317 DEFINE_CSR32_ALT(sie, csr_0x104, LLDB_INVALID_REGNUM),
318 DEFINE_CSR32_ALT(stvec, csr_0x105, LLDB_INVALID_REGNUM),
319 DEFINE_CSR32_ALT(scounteren, csr_0x106, LLDB_INVALID_REGNUM),
320 DEFINE_CSR32_ALT(senvcfg, csr_0x10a, LLDB_INVALID_REGNUM),
321 DEFINE_CSR32_ALT(sstateen0, csr_0x10c, LLDB_INVALID_REGNUM),
322 DEFINE_CSR32_ALT(sstateen1, csr_0x10d, LLDB_INVALID_REGNUM),
323 DEFINE_CSR32_ALT(sstateen2, csr_0x10e, LLDB_INVALID_REGNUM),
324 DEFINE_CSR32_ALT(sstateen3, csr_0x10f, LLDB_INVALID_REGNUM),
325 DEFINE_CSR32_ALT(scountinhibit, csr_0x120, LLDB_INVALID_REGNUM),
326 DEFINE_CSR32_ALT(sscratch, csr_0x140, LLDB_INVALID_REGNUM),
327 DEFINE_CSR32_ALT(sepc, csr_0x141, LLDB_INVALID_REGNUM),
328 DEFINE_CSR32_ALT(scause, csr_0x142, LLDB_INVALID_REGNUM),
329 DEFINE_CSR32_ALT(stval, csr_0x143, LLDB_INVALID_REGNUM),
330 DEFINE_CSR32_ALT(satp, csr_0x180, LLDB_INVALID_REGNUM),
331 DEFINE_CSR32_ALT(vsstatus, csr_0x200, LLDB_INVALID_REGNUM),
332 DEFINE_CSR32_ALT(vsie, csr_0x204, LLDB_INVALID_REGNUM),
333 DEFINE_CSR32_ALT(vstvec, csr_0x205, LLDB_INVALID_REGNUM),
334 DEFINE_CSR32_ALT(vsscratch, csr_0x240, LLDB_INVALID_REGNUM),
335 DEFINE_CSR32_ALT(vsepc, csr_0x241, LLDB_INVALID_REGNUM),
336 DEFINE_CSR32_ALT(vscause, csr_0x242, LLDB_INVALID_REGNUM),
337 DEFINE_CSR32_ALT(vstval, csr_0x243, LLDB_INVALID_REGNUM),
338 DEFINE_CSR32_ALT(vsip, csr_0x244, LLDB_INVALID_REGNUM),
339 DEFINE_CSR32_ALT(vsatp, csr_0x280, LLDB_INVALID_REGNUM),
340 DEFINE_CSR32_ALT(mstatus, csr_0x300, LLDB_INVALID_REGNUM),
341 DEFINE_CSR32_ALT(misa, csr_0x301, LLDB_INVALID_REGNUM),
342 DEFINE_CSR32_ALT(medeleg, csr_0x302, LLDB_INVALID_REGNUM),
343 DEFINE_CSR32_ALT(mideleg, csr_0x303, LLDB_INVALID_REGNUM),
344 DEFINE_CSR32_ALT(mie, csr_0x304, LLDB_INVALID_REGNUM),
345 DEFINE_CSR32_ALT(mtvec, csr_0x305, LLDB_INVALID_REGNUM),
346 DEFINE_CSR32_ALT(mcounteren, csr_0x306, LLDB_INVALID_REGNUM),
347 DEFINE_CSR32_ALT(menvcfg, csr_0x30a, LLDB_INVALID_REGNUM),
348 DEFINE_CSR32_ALT(mstateen0, csr_0x30c, LLDB_INVALID_REGNUM),
349 DEFINE_CSR32_ALT(mstateen1, csr_0x30d, LLDB_INVALID_REGNUM),
350 DEFINE_CSR32_ALT(mstateen2, csr_0x30e, LLDB_INVALID_REGNUM),
351 DEFINE_CSR32_ALT(mstateen3, csr_0x30f, LLDB_INVALID_REGNUM),
352 DEFINE_CSR32_ALT(mstatush, csr_0x310, LLDB_INVALID_REGNUM),
353 DEFINE_CSR32_ALT(medelegh, csr_0x312, LLDB_INVALID_REGNUM),
354 DEFINE_CSR32_ALT(menvcfgh, csr_0x31a, LLDB_INVALID_REGNUM),
355 DEFINE_CSR32_ALT(mstateen0h, csr_0x31c, LLDB_INVALID_REGNUM),
356 DEFINE_CSR32_ALT(mstateen1h, csr_0x31d, LLDB_INVALID_REGNUM),
357 DEFINE_CSR32_ALT(mstateen2h, csr_0x31e, LLDB_INVALID_REGNUM),
358 DEFINE_CSR32_ALT(mstateen3h, csr_0x31f, LLDB_INVALID_REGNUM),
359 DEFINE_CSR32_ALT(mcountinhibit, csr_0x320, LLDB_INVALID_REGNUM),
360 DEFINE_CSR32_ALT(mhpmevent3, csr_0x323, LLDB_INVALID_REGNUM),
361 DEFINE_CSR32_ALT(mhpmevent4, csr_0x324, LLDB_INVALID_REGNUM),
362 DEFINE_CSR32_ALT(mhpmevent5, csr_0x325, LLDB_INVALID_REGNUM),
363 DEFINE_CSR32_ALT(mhpmevent6, csr_0x326, LLDB_INVALID_REGNUM),
364 DEFINE_CSR32_ALT(mhpmevent7, csr_0x327, LLDB_INVALID_REGNUM),
365 DEFINE_CSR32_ALT(mhpmevent8, csr_0x328, LLDB_INVALID_REGNUM),
366 DEFINE_CSR32_ALT(mhpmevent9, csr_0x329, LLDB_INVALID_REGNUM),
367 DEFINE_CSR32_ALT(mhpmevent10, csr_0x32a, LLDB_INVALID_REGNUM),
368 DEFINE_CSR32_ALT(mhpmevent11, csr_0x32b, LLDB_INVALID_REGNUM),
369 DEFINE_CSR32_ALT(mhpmevent12, csr_0x32c, LLDB_INVALID_REGNUM),
370 DEFINE_CSR32_ALT(mhpmevent13, csr_0x32d, LLDB_INVALID_REGNUM),
371 DEFINE_CSR32_ALT(mhpmevent14, csr_0x32e, LLDB_INVALID_REGNUM),
372 DEFINE_CSR32_ALT(mhpmevent15, csr_0x32f, LLDB_INVALID_REGNUM),
373 DEFINE_CSR32_ALT(mhpmevent16, csr_0x330, LLDB_INVALID_REGNUM),
374 DEFINE_CSR32_ALT(mhpmevent17, csr_0x331, LLDB_INVALID_REGNUM),
375 DEFINE_CSR32_ALT(mhpmevent18, csr_0x332, LLDB_INVALID_REGNUM),
376 DEFINE_CSR32_ALT(mhpmevent19, csr_0x333, LLDB_INVALID_REGNUM),
377 DEFINE_CSR32_ALT(mhpmevent20, csr_0x334, LLDB_INVALID_REGNUM),
378 DEFINE_CSR32_ALT(mhpmevent21, csr_0x335, LLDB_INVALID_REGNUM),
379 DEFINE_CSR32_ALT(mhpmevent22, csr_0x336, LLDB_INVALID_REGNUM),
380 DEFINE_CSR32_ALT(mhpmevent23, csr_0x337, LLDB_INVALID_REGNUM),
381 DEFINE_CSR32_ALT(mhpmevent24, csr_0x338, LLDB_INVALID_REGNUM),
382 DEFINE_CSR32_ALT(mhpmevent25, csr_0x339, LLDB_INVALID_REGNUM),
383 DEFINE_CSR32_ALT(mhpmevent26, csr_0x33a, LLDB_INVALID_REGNUM),
384 DEFINE_CSR32_ALT(mhpmevent27, csr_0x33b, LLDB_INVALID_REGNUM),
385 DEFINE_CSR32_ALT(mhpmevent28, csr_0x33c, LLDB_INVALID_REGNUM),
386 DEFINE_CSR32_ALT(mhpmevent29, csr_0x33d, LLDB_INVALID_REGNUM),
387 DEFINE_CSR32_ALT(mhpmevent30, csr_0x33e, LLDB_INVALID_REGNUM),
388 DEFINE_CSR32_ALT(mhpmevent31, csr_0x33f, LLDB_INVALID_REGNUM),
389 DEFINE_CSR32_ALT(mscratch, csr_0x340, LLDB_INVALID_REGNUM),
390 DEFINE_CSR32_ALT(mepc, csr_0x341, LLDB_INVALID_REGNUM),
391 DEFINE_CSR32_ALT(mcause, csr_0x342, LLDB_INVALID_REGNUM),
392 DEFINE_CSR32_ALT(mtval, csr_0x343, LLDB_INVALID_REGNUM),
393 DEFINE_CSR32_ALT(mip, csr_0x344, LLDB_INVALID_REGNUM),
394 DEFINE_CSR32_ALT(mtinst, csr_0x34a, LLDB_INVALID_REGNUM),
395 DEFINE_CSR32_ALT(mtval2, csr_0x34b, LLDB_INVALID_REGNUM),
396 DEFINE_CSR32_ALT(pmpcfg0, csr_0x3a0, LLDB_INVALID_REGNUM),
397 DEFINE_CSR32_ALT(pmpcfg1, csr_0x3a1, LLDB_INVALID_REGNUM),
398 DEFINE_CSR32_ALT(pmpcfg2, csr_0x3a2, LLDB_INVALID_REGNUM),
399 DEFINE_CSR32_ALT(pmpcfg3, csr_0x3a3, LLDB_INVALID_REGNUM),
400 DEFINE_CSR32_ALT(pmpcfg4, csr_0x3a4, LLDB_INVALID_REGNUM),
401 DEFINE_CSR32_ALT(pmpcfg5, csr_0x3a5, LLDB_INVALID_REGNUM),
402 DEFINE_CSR32_ALT(pmpcfg6, csr_0x3a6, LLDB_INVALID_REGNUM),
403 DEFINE_CSR32_ALT(pmpcfg7, csr_0x3a7, LLDB_INVALID_REGNUM),
404 DEFINE_CSR32_ALT(pmpcfg8, csr_0x3a8, LLDB_INVALID_REGNUM),
405 DEFINE_CSR32_ALT(pmpcfg9, csr_0x3a9, LLDB_INVALID_REGNUM),
406 DEFINE_CSR32_ALT(pmpcfg10, csr_0x3aa, LLDB_INVALID_REGNUM),
407 DEFINE_CSR32_ALT(pmpcfg11, csr_0x3ab, LLDB_INVALID_REGNUM),
408 DEFINE_CSR32_ALT(pmpcfg12, csr_0x3ac, LLDB_INVALID_REGNUM),
409 DEFINE_CSR32_ALT(pmpcfg13, csr_0x3ad, LLDB_INVALID_REGNUM),
410 DEFINE_CSR32_ALT(pmpcfg14, csr_0x3ae, LLDB_INVALID_REGNUM),
411 DEFINE_CSR32_ALT(pmpcfg15, csr_0x3af, LLDB_INVALID_REGNUM),
412 DEFINE_CSR32_ALT(pmpaddr0, csr_0x3b0, LLDB_INVALID_REGNUM),
413 DEFINE_CSR32_ALT(pmpaddr1, csr_0x3b1, LLDB_INVALID_REGNUM),
414 DEFINE_CSR32_ALT(pmpaddr2, csr_0x3b2, LLDB_INVALID_REGNUM),
415 DEFINE_CSR32_ALT(pmpaddr3, csr_0x3b3, LLDB_INVALID_REGNUM),
416 DEFINE_CSR32_ALT(pmpaddr4, csr_0x3b4, LLDB_INVALID_REGNUM),
417 DEFINE_CSR32_ALT(pmpaddr5, csr_0x3b5, LLDB_INVALID_REGNUM),
418 DEFINE_CSR32_ALT(pmpaddr6, csr_0x3b6, LLDB_INVALID_REGNUM),
419 DEFINE_CSR32_ALT(pmpaddr7, csr_0x3b7, LLDB_INVALID_REGNUM),
420 DEFINE_CSR32_ALT(pmpaddr8, csr_0x3b8, LLDB_INVALID_REGNUM),
421 DEFINE_CSR32_ALT(pmpaddr9, csr_0x3b9, LLDB_INVALID_REGNUM),
422 DEFINE_CSR32_ALT(pmpaddr10, csr_0x3ba, LLDB_INVALID_REGNUM),
423 DEFINE_CSR32_ALT(pmpaddr11, csr_0x3bb, LLDB_INVALID_REGNUM),
424 DEFINE_CSR32_ALT(pmpaddr12, csr_0x3bc, LLDB_INVALID_REGNUM),
425 DEFINE_CSR32_ALT(pmpaddr13, csr_0x3bd, LLDB_INVALID_REGNUM),
426 DEFINE_CSR32_ALT(pmpaddr14, csr_0x3be, LLDB_INVALID_REGNUM),
427 DEFINE_CSR32_ALT(pmpaddr15, csr_0x3bf, LLDB_INVALID_REGNUM),
428 DEFINE_CSR32_ALT(pmpaddr16, csr_0x3c0, LLDB_INVALID_REGNUM),
429 DEFINE_CSR32_ALT(pmpaddr17, csr_0x3c1, LLDB_INVALID_REGNUM),
430 DEFINE_CSR32_ALT(pmpaddr18, csr_0x3c2, LLDB_INVALID_REGNUM),
431 DEFINE_CSR32_ALT(pmpaddr19, csr_0x3c3, LLDB_INVALID_REGNUM),
432 DEFINE_CSR32_ALT(pmpaddr20, csr_0x3c4, LLDB_INVALID_REGNUM),
433 DEFINE_CSR32_ALT(pmpaddr21, csr_0x3c5, LLDB_INVALID_REGNUM),
434 DEFINE_CSR32_ALT(pmpaddr22, csr_0x3c6, LLDB_INVALID_REGNUM),
435 DEFINE_CSR32_ALT(pmpaddr23, csr_0x3c7, LLDB_INVALID_REGNUM),
436 DEFINE_CSR32_ALT(pmpaddr24, csr_0x3c8, LLDB_INVALID_REGNUM),
437 DEFINE_CSR32_ALT(pmpaddr25, csr_0x3c9, LLDB_INVALID_REGNUM),
438 DEFINE_CSR32_ALT(pmpaddr26, csr_0x3ca, LLDB_INVALID_REGNUM),
439 DEFINE_CSR32_ALT(pmpaddr27, csr_0x3cb, LLDB_INVALID_REGNUM),
440 DEFINE_CSR32_ALT(pmpaddr28, csr_0x3cc, LLDB_INVALID_REGNUM),
441 DEFINE_CSR32_ALT(pmpaddr29, csr_0x3cd, LLDB_INVALID_REGNUM),
442 DEFINE_CSR32_ALT(pmpaddr30, csr_0x3ce, LLDB_INVALID_REGNUM),
443 DEFINE_CSR32_ALT(pmpaddr31, csr_0x3cf, LLDB_INVALID_REGNUM),
444 DEFINE_CSR32_ALT(pmpaddr32, csr_0x3d0, LLDB_INVALID_REGNUM),
445 DEFINE_CSR32_ALT(pmpaddr33, csr_0x3d1, LLDB_INVALID_REGNUM),
446 DEFINE_CSR32_ALT(pmpaddr34, csr_0x3d2, LLDB_INVALID_REGNUM),
447 DEFINE_CSR32_ALT(pmpaddr35, csr_0x3d3, LLDB_INVALID_REGNUM),
448 DEFINE_CSR32_ALT(pmpaddr36, csr_0x3d4, LLDB_INVALID_REGNUM),
449 DEFINE_CSR32_ALT(pmpaddr37, csr_0x3d5, LLDB_INVALID_REGNUM),
450 DEFINE_CSR32_ALT(pmpaddr38, csr_0x3d6, LLDB_INVALID_REGNUM),
451 DEFINE_CSR32_ALT(pmpaddr39, csr_0x3d7, LLDB_INVALID_REGNUM),
452 DEFINE_CSR32_ALT(pmpaddr40, csr_0x3d8, LLDB_INVALID_REGNUM),
453 DEFINE_CSR32_ALT(pmpaddr41, csr_0x3d9, LLDB_INVALID_REGNUM),
454 DEFINE_CSR32_ALT(pmpaddr42, csr_0x3da, LLDB_INVALID_REGNUM),
455 DEFINE_CSR32_ALT(pmpaddr43, csr_0x3db, LLDB_INVALID_REGNUM),
456 DEFINE_CSR32_ALT(pmpaddr44, csr_0x3dc, LLDB_INVALID_REGNUM),
457 DEFINE_CSR32_ALT(pmpaddr45, csr_0x3dd, LLDB_INVALID_REGNUM),
458 DEFINE_CSR32_ALT(pmpaddr46, csr_0x3de, LLDB_INVALID_REGNUM),
459 DEFINE_CSR32_ALT(pmpaddr47, csr_0x3df, LLDB_INVALID_REGNUM),
460 DEFINE_CSR32_ALT(pmpaddr48, csr_0x3e0, LLDB_INVALID_REGNUM),
461 DEFINE_CSR32_ALT(pmpaddr49, csr_0x3e1, LLDB_INVALID_REGNUM),
462 DEFINE_CSR32_ALT(pmpaddr50, csr_0x3e2, LLDB_INVALID_REGNUM),
463 DEFINE_CSR32_ALT(pmpaddr51, csr_0x3e3, LLDB_INVALID_REGNUM),
464 DEFINE_CSR32_ALT(pmpaddr52, csr_0x3e4, LLDB_INVALID_REGNUM),
465 DEFINE_CSR32_ALT(pmpaddr53, csr_0x3e5, LLDB_INVALID_REGNUM),
466 DEFINE_CSR32_ALT(pmpaddr54, csr_0x3e6, LLDB_INVALID_REGNUM),
467 DEFINE_CSR32_ALT(pmpaddr55, csr_0x3e7, LLDB_INVALID_REGNUM),
468 DEFINE_CSR32_ALT(pmpaddr56, csr_0x3e8, LLDB_INVALID_REGNUM),
469 DEFINE_CSR32_ALT(pmpaddr57, csr_0x3e9, LLDB_INVALID_REGNUM),
470 DEFINE_CSR32_ALT(pmpaddr58, csr_0x3ea, LLDB_INVALID_REGNUM),
471 DEFINE_CSR32_ALT(pmpaddr59, csr_0x3eb, LLDB_INVALID_REGNUM),
472 DEFINE_CSR32_ALT(pmpaddr60, csr_0x3ec, LLDB_INVALID_REGNUM),
473 DEFINE_CSR32_ALT(pmpaddr61, csr_0x3ed, LLDB_INVALID_REGNUM),
474 DEFINE_CSR32_ALT(pmpaddr62, csr_0x3ee, LLDB_INVALID_REGNUM),
475 DEFINE_CSR32_ALT(pmpaddr63, csr_0x3ef, LLDB_INVALID_REGNUM),
476 DEFINE_CSR32_ALT(scontext, csr_0x5a8, LLDB_INVALID_REGNUM),
477 DEFINE_CSR32_ALT(hstatus, csr_0x600, LLDB_INVALID_REGNUM),
478 DEFINE_CSR32_ALT(hedeleg, csr_0x602, LLDB_INVALID_REGNUM),
479 DEFINE_CSR32_ALT(hideleg, csr_0x603, LLDB_INVALID_REGNUM),
480 DEFINE_CSR32_ALT(hie, csr_0x604, LLDB_INVALID_REGNUM),
481 DEFINE_CSR32_ALT(htimedelta, csr_0x605, LLDB_INVALID_REGNUM),
482 DEFINE_CSR32_ALT(hcounteren, csr_0x606, LLDB_INVALID_REGNUM),
483 DEFINE_CSR32_ALT(hgeie, csr_0x607, LLDB_INVALID_REGNUM),
484 DEFINE_CSR32_ALT(henvcfg, csr_0x60a, LLDB_INVALID_REGNUM),
485 DEFINE_CSR32_ALT(hstateen0, csr_0x60c, LLDB_INVALID_REGNUM),
486 DEFINE_CSR32_ALT(hstateen1, csr_0x60d, LLDB_INVALID_REGNUM),
487 DEFINE_CSR32_ALT(hstateen2, csr_0x60e, LLDB_INVALID_REGNUM),
488 DEFINE_CSR32_ALT(hstateen3, csr_0x60f, LLDB_INVALID_REGNUM),
489 DEFINE_CSR32_ALT(hedelegh, csr_0x612, LLDB_INVALID_REGNUM),
490 DEFINE_CSR32_ALT(htimedeltah, csr_0x615, LLDB_INVALID_REGNUM),
491 DEFINE_CSR32_ALT(henvcfgh, csr_0x61a, LLDB_INVALID_REGNUM),
492 DEFINE_CSR32_ALT(hstateen0h, csr_0x61c, LLDB_INVALID_REGNUM),
493 DEFINE_CSR32_ALT(hstateen1h, csr_0x61d, LLDB_INVALID_REGNUM),
494 DEFINE_CSR32_ALT(hstateen2h, csr_0x61e, LLDB_INVALID_REGNUM),
495 DEFINE_CSR32_ALT(hstateen3h, csr_0x61f, LLDB_INVALID_REGNUM),
496 DEFINE_CSR32_ALT(htval, csr_0x643, LLDB_INVALID_REGNUM),
497 DEFINE_CSR32_ALT(hip, csr_0x644, LLDB_INVALID_REGNUM),
498 DEFINE_CSR32_ALT(hvip, csr_0x645, LLDB_INVALID_REGNUM),
499 DEFINE_CSR32_ALT(htinst, csr_0x64a, LLDB_INVALID_REGNUM),
500 DEFINE_CSR32_ALT(hgatp, csr_0x680, LLDB_INVALID_REGNUM),
501 DEFINE_CSR32_ALT(hcontext, csr_0x6a8, LLDB_INVALID_REGNUM),
502 DEFINE_CSR32_ALT(mhpmevent3h, csr_0x723, LLDB_INVALID_REGNUM),
503 DEFINE_CSR32_ALT(mhpmevent4h, csr_0x724, LLDB_INVALID_REGNUM),
504 DEFINE_CSR32_ALT(mhpmevent5h, csr_0x725, LLDB_INVALID_REGNUM),
505 DEFINE_CSR32_ALT(mhpmevent6h, csr_0x726, LLDB_INVALID_REGNUM),
506 DEFINE_CSR32_ALT(mhpmevent7h, csr_0x727, LLDB_INVALID_REGNUM),
507 DEFINE_CSR32_ALT(mhpmevent8h, csr_0x728, LLDB_INVALID_REGNUM),
508 DEFINE_CSR32_ALT(mhpmevent9h, csr_0x729, LLDB_INVALID_REGNUM),
509 DEFINE_CSR32_ALT(mhpmevent10h, csr_0x72a, LLDB_INVALID_REGNUM),
510 DEFINE_CSR32_ALT(mhpmevent11h, csr_0x72b, LLDB_INVALID_REGNUM),
511 DEFINE_CSR32_ALT(mhpmevent12h, csr_0x72c, LLDB_INVALID_REGNUM),
512 DEFINE_CSR32_ALT(mhpmevent13h, csr_0x72d, LLDB_INVALID_REGNUM),
513 DEFINE_CSR32_ALT(mhpmevent14h, csr_0x72e, LLDB_INVALID_REGNUM),
514 DEFINE_CSR32_ALT(mhpmevent15h, csr_0x72f, LLDB_INVALID_REGNUM),
515 DEFINE_CSR32_ALT(mhpmevent16h, csr_0x730, LLDB_INVALID_REGNUM),
516 DEFINE_CSR32_ALT(mhpmevent17h, csr_0x731, LLDB_INVALID_REGNUM),
517 DEFINE_CSR32_ALT(mhpmevent18h, csr_0x732, LLDB_INVALID_REGNUM),
518 DEFINE_CSR32_ALT(mhpmevent19h, csr_0x733, LLDB_INVALID_REGNUM),
519 DEFINE_CSR32_ALT(mhpmevent20h, csr_0x734, LLDB_INVALID_REGNUM),
520 DEFINE_CSR32_ALT(mhpmevent21h, csr_0x735, LLDB_INVALID_REGNUM),
521 DEFINE_CSR32_ALT(mhpmevent22h, csr_0x736, LLDB_INVALID_REGNUM),
522 DEFINE_CSR32_ALT(mhpmevent23h, csr_0x737, LLDB_INVALID_REGNUM),
523 DEFINE_CSR32_ALT(mhpmevent24h, csr_0x738, LLDB_INVALID_REGNUM),
524 DEFINE_CSR32_ALT(mhpmevent25h, csr_0x739, LLDB_INVALID_REGNUM),
525 DEFINE_CSR32_ALT(mhpmevent26h, csr_0x73a, LLDB_INVALID_REGNUM),
526 DEFINE_CSR32_ALT(mhpmevent27h, csr_0x73b, LLDB_INVALID_REGNUM),
527 DEFINE_CSR32_ALT(mhpmevent28h, csr_0x73c, LLDB_INVALID_REGNUM),
528 DEFINE_CSR32_ALT(mhpmevent29h, csr_0x73d, LLDB_INVALID_REGNUM),
529 DEFINE_CSR32_ALT(mhpmevent30h, csr_0x73e, LLDB_INVALID_REGNUM),
530 DEFINE_CSR32_ALT(mhpmevent31h, csr_0x73f, LLDB_INVALID_REGNUM),
531 DEFINE_CSR32_ALT(mnscratch, csr_0x740, LLDB_INVALID_REGNUM),
532 DEFINE_CSR32_ALT(mnepc, csr_0x741, LLDB_INVALID_REGNUM),
533 DEFINE_CSR32_ALT(mncause, csr_0x742, LLDB_INVALID_REGNUM),
534 DEFINE_CSR32_ALT(mnstatus, csr_0x744, LLDB_INVALID_REGNUM),
535 DEFINE_CSR32_ALT(mseccfg, csr_0x747, LLDB_INVALID_REGNUM),
536 DEFINE_CSR32_ALT(mseccfgh, csr_0x757, LLDB_INVALID_REGNUM),
537 DEFINE_CSR32_ALT(tselect, csr_0x7a0, LLDB_INVALID_REGNUM),
538 DEFINE_CSR32_ALT(tdata1, csr_0x7a1, LLDB_INVALID_REGNUM),
539 DEFINE_CSR32_ALT(tdata2, csr_0x7a2, LLDB_INVALID_REGNUM),
540 DEFINE_CSR32_ALT(tdata3, csr_0x7a3, LLDB_INVALID_REGNUM),
541 DEFINE_CSR32_ALT(mcontext, csr_0x7a8, LLDB_INVALID_REGNUM),
542 DEFINE_CSR32_ALT(dcsr, csr_0x7b0, LLDB_INVALID_REGNUM),
543 DEFINE_CSR32_ALT(dpc, csr_0x7b1, LLDB_INVALID_REGNUM),
544 DEFINE_CSR32_ALT(dscratch0, csr_0x7b2, LLDB_INVALID_REGNUM),
545 DEFINE_CSR32_ALT(dscratch1, csr_0x7b3, LLDB_INVALID_REGNUM),
546 DEFINE_CSR32_ALT(mcycle, csr_0xb00, LLDB_INVALID_REGNUM),
547 DEFINE_CSR32_ALT(minstret, csr_0xb02, LLDB_INVALID_REGNUM),
548 DEFINE_CSR32_ALT(mhpmcounter3, csr_0xb03, LLDB_INVALID_REGNUM),
549 DEFINE_CSR32_ALT(mhpmcounter4, csr_0xb04, LLDB_INVALID_REGNUM),
550 DEFINE_CSR32_ALT(mhpmcounter5, csr_0xb05, LLDB_INVALID_REGNUM),
551 DEFINE_CSR32_ALT(mhpmcounter6, csr_0xb06, LLDB_INVALID_REGNUM),
552 DEFINE_CSR32_ALT(mhpmcounter7, csr_0xb07, LLDB_INVALID_REGNUM),
553 DEFINE_CSR32_ALT(mhpmcounter8, csr_0xb08, LLDB_INVALID_REGNUM),
554 DEFINE_CSR32_ALT(mhpmcounter9, csr_0xb09, LLDB_INVALID_REGNUM),
555 DEFINE_CSR32_ALT(mhpmcounter10, csr_0xb0a, LLDB_INVALID_REGNUM),
556 DEFINE_CSR32_ALT(mhpmcounter11, csr_0xb0b, LLDB_INVALID_REGNUM),
557 DEFINE_CSR32_ALT(mhpmcounter12, csr_0xb0c, LLDB_INVALID_REGNUM),
558 DEFINE_CSR32_ALT(mhpmcounter13, csr_0xb0d, LLDB_INVALID_REGNUM),
559 DEFINE_CSR32_ALT(mhpmcounter14, csr_0xb0e, LLDB_INVALID_REGNUM),
560 DEFINE_CSR32_ALT(mhpmcounter15, csr_0xb0f, LLDB_INVALID_REGNUM),
561 DEFINE_CSR32_ALT(mhpmcounter16, csr_0xb10, LLDB_INVALID_REGNUM),
562 DEFINE_CSR32_ALT(mhpmcounter17, csr_0xb11, LLDB_INVALID_REGNUM),
563 DEFINE_CSR32_ALT(mhpmcounter18, csr_0xb12, LLDB_INVALID_REGNUM),
564 DEFINE_CSR32_ALT(mhpmcounter19, csr_0xb13, LLDB_INVALID_REGNUM),
565 DEFINE_CSR32_ALT(mhpmcounter20, csr_0xb14, LLDB_INVALID_REGNUM),
566 DEFINE_CSR32_ALT(mhpmcounter21, csr_0xb15, LLDB_INVALID_REGNUM),
567 DEFINE_CSR32_ALT(mhpmcounter22, csr_0xb16, LLDB_INVALID_REGNUM),
568 DEFINE_CSR32_ALT(mhpmcounter23, csr_0xb17, LLDB_INVALID_REGNUM),
569 DEFINE_CSR32_ALT(mhpmcounter24, csr_0xb18, LLDB_INVALID_REGNUM),
570 DEFINE_CSR32_ALT(mhpmcounter25, csr_0xb19, LLDB_INVALID_REGNUM),
571 DEFINE_CSR32_ALT(mhpmcounter26, csr_0xb1a, LLDB_INVALID_REGNUM),
572 DEFINE_CSR32_ALT(mhpmcounter27, csr_0xb1b, LLDB_INVALID_REGNUM),
573 DEFINE_CSR32_ALT(mhpmcounter28, csr_0xb1c, LLDB_INVALID_REGNUM),
574 DEFINE_CSR32_ALT(mhpmcounter29, csr_0xb1d, LLDB_INVALID_REGNUM),
575 DEFINE_CSR32_ALT(mhpmcounter30, csr_0xb1e, LLDB_INVALID_REGNUM),
576 DEFINE_CSR32_ALT(mhpmcounter31, csr_0xb1f, LLDB_INVALID_REGNUM),
577 DEFINE_CSR32_ALT(mcycleh, csr_0xb80, LLDB_INVALID_REGNUM),
578 DEFINE_CSR32_ALT(minstreth, csr_0xb82, LLDB_INVALID_REGNUM),
579 DEFINE_CSR32_ALT(mhpmcounter3h, csr_0xb83, LLDB_INVALID_REGNUM),
580 DEFINE_CSR32_ALT(mhpmcounter4h, csr_0xb84, LLDB_INVALID_REGNUM),
581 DEFINE_CSR32_ALT(mhpmcounter5h, csr_0xb85, LLDB_INVALID_REGNUM),
582 DEFINE_CSR32_ALT(mhpmcounter6h, csr_0xb86, LLDB_INVALID_REGNUM),
583 DEFINE_CSR32_ALT(mhpmcounter7h, csr_0xb87, LLDB_INVALID_REGNUM),
584 DEFINE_CSR32_ALT(mhpmcounter8h, csr_0xb88, LLDB_INVALID_REGNUM),
585 DEFINE_CSR32_ALT(mhpmcounter9h, csr_0xb89, LLDB_INVALID_REGNUM),
586 DEFINE_CSR32_ALT(mhpmcounter10h, csr_0xb8a, LLDB_INVALID_REGNUM),
587 DEFINE_CSR32_ALT(mhpmcounter11h, csr_0xb8b, LLDB_INVALID_REGNUM),
588 DEFINE_CSR32_ALT(mhpmcounter12h, csr_0xb8c, LLDB_INVALID_REGNUM),
589 DEFINE_CSR32_ALT(mhpmcounter13h, csr_0xb8d, LLDB_INVALID_REGNUM),
590 DEFINE_CSR32_ALT(mhpmcounter14h, csr_0xb8e, LLDB_INVALID_REGNUM),
591 DEFINE_CSR32_ALT(mhpmcounter15h, csr_0xb8f, LLDB_INVALID_REGNUM),
592 DEFINE_CSR32_ALT(mhpmcounter16h, csr_0xb90, LLDB_INVALID_REGNUM),
593 DEFINE_CSR32_ALT(mhpmcounter17h, csr_0xb91, LLDB_INVALID_REGNUM),
594 DEFINE_CSR32_ALT(mhpmcounter18h, csr_0xb92, LLDB_INVALID_REGNUM),
595 DEFINE_CSR32_ALT(mhpmcounter19h, csr_0xb93, LLDB_INVALID_REGNUM),
596 DEFINE_CSR32_ALT(mhpmcounter20h, csr_0xb94, LLDB_INVALID_REGNUM),
597 DEFINE_CSR32_ALT(mhpmcounter21h, csr_0xb95, LLDB_INVALID_REGNUM),
598 DEFINE_CSR32_ALT(mhpmcounter22h, csr_0xb96, LLDB_INVALID_REGNUM),
599 DEFINE_CSR32_ALT(mhpmcounter23h, csr_0xb97, LLDB_INVALID_REGNUM),
600 DEFINE_CSR32_ALT(mhpmcounter24h, csr_0xb98, LLDB_INVALID_REGNUM),
601 DEFINE_CSR32_ALT(mhpmcounter25h, csr_0xb99, LLDB_INVALID_REGNUM),
602 DEFINE_CSR32_ALT(mhpmcounter26h, csr_0xb9a, LLDB_INVALID_REGNUM),
603 DEFINE_CSR32_ALT(mhpmcounter27h, csr_0xb9b, LLDB_INVALID_REGNUM),
604 DEFINE_CSR32_ALT(mhpmcounter28h, csr_0xb9c, LLDB_INVALID_REGNUM),
605 DEFINE_CSR32_ALT(mhpmcounter29h, csr_0xb9d, LLDB_INVALID_REGNUM),
606 DEFINE_CSR32_ALT(mhpmcounter30h, csr_0xb9e, LLDB_INVALID_REGNUM),
607 DEFINE_CSR32_ALT(mhpmcounter31h, csr_0xb9f, LLDB_INVALID_REGNUM),
608 DEFINE_CSR32_ALT(cycle, csr_0xc00, LLDB_INVALID_REGNUM),
609 DEFINE_CSR32_ALT(time, csr_0xc01, LLDB_INVALID_REGNUM),
610 DEFINE_CSR32_ALT(instret, csr_0xc02, LLDB_INVALID_REGNUM),
611 DEFINE_CSR32_ALT(hpmcounter3, csr_0xc03, LLDB_INVALID_REGNUM),
612 DEFINE_CSR32_ALT(hpmcounter4, csr_0xc04, LLDB_INVALID_REGNUM),
613 DEFINE_CSR32_ALT(hpmcounter5, csr_0xc05, LLDB_INVALID_REGNUM),
614 DEFINE_CSR32_ALT(hpmcounter6, csr_0xc06, LLDB_INVALID_REGNUM),
615 DEFINE_CSR32_ALT(hpmcounter7, csr_0xc07, LLDB_INVALID_REGNUM),
616 DEFINE_CSR32_ALT(hpmcounter8, csr_0xc08, LLDB_INVALID_REGNUM),
617 DEFINE_CSR32_ALT(hpmcounter9, csr_0xc09, LLDB_INVALID_REGNUM),
618 DEFINE_CSR32_ALT(hpmcounter10, csr_0xc0a, LLDB_INVALID_REGNUM),
619 DEFINE_CSR32_ALT(hpmcounter11, csr_0xc0b, LLDB_INVALID_REGNUM),
620 DEFINE_CSR32_ALT(hpmcounter12, csr_0xc0c, LLDB_INVALID_REGNUM),
621 DEFINE_CSR32_ALT(hpmcounter13, csr_0xc0d, LLDB_INVALID_REGNUM),
622 DEFINE_CSR32_ALT(hpmcounter14, csr_0xc0e, LLDB_INVALID_REGNUM),
623 DEFINE_CSR32_ALT(hpmcounter15, csr_0xc0f, LLDB_INVALID_REGNUM),
624 DEFINE_CSR32_ALT(hpmcounter16, csr_0xc10, LLDB_INVALID_REGNUM),
625 DEFINE_CSR32_ALT(hpmcounter17, csr_0xc11, LLDB_INVALID_REGNUM),
626 DEFINE_CSR32_ALT(hpmcounter18, csr_0xc12, LLDB_INVALID_REGNUM),
627 DEFINE_CSR32_ALT(hpmcounter19, csr_0xc13, LLDB_INVALID_REGNUM),
628 DEFINE_CSR32_ALT(hpmcounter20, csr_0xc14, LLDB_INVALID_REGNUM),
629 DEFINE_CSR32_ALT(hpmcounter21, csr_0xc15, LLDB_INVALID_REGNUM),
630 DEFINE_CSR32_ALT(hpmcounter22, csr_0xc16, LLDB_INVALID_REGNUM),
631 DEFINE_CSR32_ALT(hpmcounter23, csr_0xc17, LLDB_INVALID_REGNUM),
632 DEFINE_CSR32_ALT(hpmcounter24, csr_0xc18, LLDB_INVALID_REGNUM),
633 DEFINE_CSR32_ALT(hpmcounter25, csr_0xc19, LLDB_INVALID_REGNUM),
634 DEFINE_CSR32_ALT(hpmcounter26, csr_0xc1a, LLDB_INVALID_REGNUM),
635 DEFINE_CSR32_ALT(hpmcounter27, csr_0xc1b, LLDB_INVALID_REGNUM),
636 DEFINE_CSR32_ALT(hpmcounter28, csr_0xc1c, LLDB_INVALID_REGNUM),
637 DEFINE_CSR32_ALT(hpmcounter29, csr_0xc1d, LLDB_INVALID_REGNUM),
638 DEFINE_CSR32_ALT(hpmcounter30, csr_0xc1e, LLDB_INVALID_REGNUM),
639 DEFINE_CSR32_ALT(hpmcounter31, csr_0xc1f, LLDB_INVALID_REGNUM),
640 DEFINE_CSR32_ALT(vl, csr_0xc20, LLDB_INVALID_REGNUM),
641 DEFINE_CSR32_ALT(vtype, csr_0xc21, LLDB_INVALID_REGNUM),
642 DEFINE_CSR32_ALT(vlenb, csr_0xc22, LLDB_INVALID_REGNUM),
643 DEFINE_CSR32_ALT(cycleh, csr_0xc80, LLDB_INVALID_REGNUM),
644 DEFINE_CSR32_ALT(timeh, csr_0xc81, LLDB_INVALID_REGNUM),
645 DEFINE_CSR32_ALT(instreth, csr_0xc82, LLDB_INVALID_REGNUM),
646 DEFINE_CSR32_ALT(hpmcounter3h, csr_0xc83, LLDB_INVALID_REGNUM),
647 DEFINE_CSR32_ALT(hpmcounter4h, csr_0xc84, LLDB_INVALID_REGNUM),
648 DEFINE_CSR32_ALT(hpmcounter5h, csr_0xc85, LLDB_INVALID_REGNUM),
649 DEFINE_CSR32_ALT(hpmcounter6h, csr_0xc86, LLDB_INVALID_REGNUM),
650 DEFINE_CSR32_ALT(hpmcounter7h, csr_0xc87, LLDB_INVALID_REGNUM),
651 DEFINE_CSR32_ALT(hpmcounter8h, csr_0xc88, LLDB_INVALID_REGNUM),
652 DEFINE_CSR32_ALT(hpmcounter9h, csr_0xc89, LLDB_INVALID_REGNUM),
653 DEFINE_CSR32_ALT(hpmcounter10h, csr_0xc8a, LLDB_INVALID_REGNUM),
654 DEFINE_CSR32_ALT(hpmcounter11h, csr_0xc8b, LLDB_INVALID_REGNUM),
655 DEFINE_CSR32_ALT(hpmcounter12h, csr_0xc8c, LLDB_INVALID_REGNUM),
656 DEFINE_CSR32_ALT(hpmcounter13h, csr_0xc8d, LLDB_INVALID_REGNUM),
657 DEFINE_CSR32_ALT(hpmcounter14h, csr_0xc8e, LLDB_INVALID_REGNUM),
658 DEFINE_CSR32_ALT(hpmcounter15h, csr_0xc8f, LLDB_INVALID_REGNUM),
659 DEFINE_CSR32_ALT(hpmcounter16h, csr_0xc90, LLDB_INVALID_REGNUM),
660 DEFINE_CSR32_ALT(hpmcounter17h, csr_0xc91, LLDB_INVALID_REGNUM),
661 DEFINE_CSR32_ALT(hpmcounter18h, csr_0xc92, LLDB_INVALID_REGNUM),
662 DEFINE_CSR32_ALT(hpmcounter19h, csr_0xc93, LLDB_INVALID_REGNUM),
663 DEFINE_CSR32_ALT(hpmcounter20h, csr_0xc94, LLDB_INVALID_REGNUM),
664 DEFINE_CSR32_ALT(hpmcounter21h, csr_0xc95, LLDB_INVALID_REGNUM),
665 DEFINE_CSR32_ALT(hpmcounter22h, csr_0xc96, LLDB_INVALID_REGNUM),
666 DEFINE_CSR32_ALT(hpmcounter23h, csr_0xc97, LLDB_INVALID_REGNUM),
667 DEFINE_CSR32_ALT(hpmcounter24h, csr_0xc98, LLDB_INVALID_REGNUM),
668 DEFINE_CSR32_ALT(hpmcounter25h, csr_0xc99, LLDB_INVALID_REGNUM),
669 DEFINE_CSR32_ALT(hpmcounter26h, csr_0xc9a, LLDB_INVALID_REGNUM),
670 DEFINE_CSR32_ALT(hpmcounter27h, csr_0xc9b, LLDB_INVALID_REGNUM),
671 DEFINE_CSR32_ALT(hpmcounter28h, csr_0xc9c, LLDB_INVALID_REGNUM),
672 DEFINE_CSR32_ALT(hpmcounter29h, csr_0xc9d, LLDB_INVALID_REGNUM),
673 DEFINE_CSR32_ALT(hpmcounter30h, csr_0xc9e, LLDB_INVALID_REGNUM),
674 DEFINE_CSR32_ALT(hpmcounter31h, csr_0xc9f, LLDB_INVALID_REGNUM),
675 DEFINE_CSR32_ALT(scountovf, csr_0xda0, LLDB_INVALID_REGNUM),
676 DEFINE_CSR32_ALT(hgeip, csr_0xe12, LLDB_INVALID_REGNUM),
677 DEFINE_CSR32_ALT(mvendorid, csr_0xf11, LLDB_INVALID_REGNUM),
678 DEFINE_CSR32_ALT(marchid, csr_0xf12, LLDB_INVALID_REGNUM),
679 DEFINE_CSR32_ALT(mimpid, csr_0xf13, LLDB_INVALID_REGNUM),
680 DEFINE_CSR32_ALT(mhartid, csr_0xf14, LLDB_INVALID_REGNUM),
681 DEFINE_CSR32_ALT(mconfigptr, csr_0xf15, LLDB_INVALID_REGNUM),
682};
683
684#endif // DECLARE_REGISTER_INFOS_RISCV32_STRUCT
RISCV_DWARF_Registers.h
LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_RA
Definition lldb-defines.h:59
LLDB_REGNUM_GENERIC_ARG8
#define LLDB_REGNUM_GENERIC_ARG8
Definition lldb-defines.h:75
LLDB_REGNUM_GENERIC_ARG6
#define LLDB_REGNUM_GENERIC_ARG6
Definition lldb-defines.h:71
LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_SP
Definition lldb-defines.h:57
LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG4
Definition lldb-defines.h:67
LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG3
Definition lldb-defines.h:65
LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG1
Definition lldb-defines.h:61
LLDB_REGNUM_GENERIC_ARG7
#define LLDB_REGNUM_GENERIC_ARG7
Definition lldb-defines.h:73
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition lldb-defines.h:90
LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_ARG2
Definition lldb-defines.h:63
LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_PC
Definition lldb-defines.h:56
LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_FP
Definition lldb-defines.h:58
LLDB_REGNUM_GENERIC_ARG5
#define LLDB_REGNUM_GENERIC_ARG5
Definition lldb-defines.h:69
riscv_dwarf
Definition RISCV_DWARF_Registers.h:14
lldb_private::RegisterInfo
Every register is described in detail including its name, alternate name (optional),...
Definition RegisterInfo.h:23
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