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ArchSpec.cpp
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1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 
11 #include "lldb/Utility/Log.h"
13 #include "lldb/Utility/Stream.h"
15 #include "lldb/lldb-defines.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/BinaryFormat/COFF.h"
19 #include "llvm/BinaryFormat/ELF.h"
20 #include "llvm/BinaryFormat/MachO.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Support/Host.h"
23 
24 using namespace lldb;
25 using namespace lldb_private;
26 
27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
28  bool try_inverse, bool enforce_exact_match);
29 
30 namespace lldb_private {
31 
37  llvm::Triple::ArchType machine;
39  const char *const name;
40 };
41 
42 } // namespace lldb_private
43 
44 // This core information can be looked using the ArchSpec::Core as the index
46  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
47  "arm"},
48  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
49  "armv4"},
50  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
51  "armv4t"},
52  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
53  "armv5"},
54  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
55  "armv5e"},
56  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
57  "armv5t"},
58  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
59  "armv6"},
60  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
61  "armv6m"},
62  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
63  "armv7"},
64  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
65  "armv7f"},
66  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
67  "armv7s"},
68  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
69  "armv7k"},
70  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
71  "armv7m"},
72  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
73  "armv7em"},
74  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
75  "xscale"},
76  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
77  "thumb"},
78  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
79  "thumbv4t"},
80  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
81  "thumbv5"},
82  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
83  "thumbv5e"},
84  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
85  "thumbv6"},
86  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
87  "thumbv6m"},
88  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
89  "thumbv7"},
90  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
91  "thumbv7f"},
92  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
93  "thumbv7s"},
94  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
95  "thumbv7k"},
96  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
97  "thumbv7m"},
98  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
99  "thumbv7em"},
100  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
101  ArchSpec::eCore_arm_arm64, "arm64"},
102  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
103  ArchSpec::eCore_arm_armv8, "armv8"},
104  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
105  ArchSpec::eCore_arm_aarch64, "aarch64"},
106 
107  // mips32, mips32r2, mips32r3, mips32r5, mips32r6
108  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
109  "mips"},
110  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
111  "mipsr2"},
112  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
113  "mipsr3"},
114  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
115  "mipsr5"},
116  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
117  "mipsr6"},
118  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
119  "mipsel"},
120  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
121  ArchSpec::eCore_mips32r2el, "mipsr2el"},
122  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
123  ArchSpec::eCore_mips32r3el, "mipsr3el"},
124  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
125  ArchSpec::eCore_mips32r5el, "mipsr5el"},
126  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
127  ArchSpec::eCore_mips32r6el, "mipsr6el"},
128 
129  // mips64, mips64r2, mips64r3, mips64r5, mips64r6
130  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
131  "mips64"},
132  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
133  "mips64r2"},
134  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
135  "mips64r3"},
136  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
137  "mips64r5"},
138  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
139  "mips64r6"},
140  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
141  ArchSpec::eCore_mips64el, "mips64el"},
142  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
143  ArchSpec::eCore_mips64r2el, "mips64r2el"},
144  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
145  ArchSpec::eCore_mips64r3el, "mips64r3el"},
146  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
147  ArchSpec::eCore_mips64r5el, "mips64r5el"},
148  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
149  ArchSpec::eCore_mips64r6el, "mips64r6el"},
150 
151  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
152  "powerpc"},
153  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
154  "ppc601"},
155  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
156  "ppc602"},
157  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
158  "ppc603"},
159  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
160  "ppc603e"},
161  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
162  "ppc603ev"},
163  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
164  "ppc604"},
165  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
166  "ppc604e"},
167  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
168  "ppc620"},
169  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
170  "ppc750"},
171  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
172  "ppc7400"},
173  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
174  "ppc7450"},
175  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
176  "ppc970"},
177 
178  {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
179  ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
180  {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
181  "powerpc64"},
182  {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
183  ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
184 
185  {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
186  ArchSpec::eCore_s390x_generic, "s390x"},
187 
188  {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
189  ArchSpec::eCore_sparc_generic, "sparc"},
190  {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
191  ArchSpec::eCore_sparc9_generic, "sparcv9"},
192 
193  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
194  "i386"},
195  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
196  "i486"},
197  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
198  ArchSpec::eCore_x86_32_i486sx, "i486sx"},
199  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
200  "i686"},
201 
202  {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
203  ArchSpec::eCore_x86_64_x86_64, "x86_64"},
204  {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
205  ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
206  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
207  ArchSpec::eCore_hexagon_generic, "hexagon"},
208  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
209  ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
210  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
211  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
212 
213  {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
214  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
215  {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
216  ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
217 };
218 
219 // Ensure that we have an entry in the g_core_definitions for each core. If you
220 // comment out an entry above, you will need to comment out the corresponding
221 // ArchSpec::Core enumeration.
222 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
223  ArchSpec::kNumCores,
224  "make sure we have one core definition for each core");
225 
232 };
233 
236  size_t num_entries;
238  const char *name;
239 };
240 
241 void ArchSpec::ListSupportedArchNames(StringList &list) {
242  for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
243  list.AppendString(g_core_definitions[i].name);
244 }
245 
246 size_t ArchSpec::AutoComplete(CompletionRequest &request) {
247  if (!request.GetCursorArgumentPrefix().empty()) {
248  for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) {
249  if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith,
250  request.GetCursorArgumentPrefix()))
251  request.AddCompletion(g_core_definitions[i].name);
252  }
253  } else {
254  StringList matches;
255  ListSupportedArchNames(matches);
256  request.AddCompletions(matches);
257  }
258  return request.GetNumberOfMatches();
259 }
260 
261 #define CPU_ANY (UINT32_MAX)
262 
263 //===----------------------------------------------------------------------===//
264 // A table that gets searched linearly for matches. This table is used to
265 // convert cpu type and subtypes to architecture names, and to convert
266 // architecture names to cpu types and subtypes. The ordering is important and
267 // allows the precedence to be set when the table is built.
268 #define SUBTYPE_MASK 0x00FFFFFFu
269 
271  {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY,
272  UINT32_MAX, UINT32_MAX},
273  {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX,
274  SUBTYPE_MASK},
275  {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX,
276  SUBTYPE_MASK},
277  {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX,
278  SUBTYPE_MASK},
279  {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX,
280  SUBTYPE_MASK},
281  {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX,
282  SUBTYPE_MASK},
283  {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
284  SUBTYPE_MASK},
285  {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
286  SUBTYPE_MASK},
287  {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
288  SUBTYPE_MASK},
289  {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX,
290  SUBTYPE_MASK},
291  {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX,
292  SUBTYPE_MASK},
293  {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX,
294  SUBTYPE_MASK},
295  {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX,
296  SUBTYPE_MASK},
297  {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX,
298  SUBTYPE_MASK},
299  {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX,
300  SUBTYPE_MASK},
301  {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX,
302  SUBTYPE_MASK},
303  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX,
304  SUBTYPE_MASK},
305  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX,
306  SUBTYPE_MASK},
307  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX,
308  SUBTYPE_MASK},
309  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY,
310  UINT32_MAX, SUBTYPE_MASK},
311  {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX,
312  SUBTYPE_MASK},
313  {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX,
314  SUBTYPE_MASK},
315  {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
316  SUBTYPE_MASK},
317  {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
318  SUBTYPE_MASK},
319  {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX,
320  SUBTYPE_MASK},
321  {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX,
322  SUBTYPE_MASK},
323  {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX,
324  SUBTYPE_MASK},
325  {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX,
326  SUBTYPE_MASK},
327  {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX,
328  SUBTYPE_MASK},
329  {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX,
330  SUBTYPE_MASK},
331  {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX,
332  SUBTYPE_MASK},
333  {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX,
334  SUBTYPE_MASK},
335  {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY,
336  UINT32_MAX, UINT32_MAX},
337  {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX,
338  SUBTYPE_MASK},
339  {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX,
340  SUBTYPE_MASK},
341  {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX,
342  SUBTYPE_MASK},
343  {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX,
344  SUBTYPE_MASK},
345  {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX,
346  SUBTYPE_MASK},
347  {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX,
348  SUBTYPE_MASK},
349  {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX,
350  SUBTYPE_MASK},
351  {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX,
352  SUBTYPE_MASK},
353  {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX,
354  SUBTYPE_MASK},
355  {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX,
356  SUBTYPE_MASK},
357  {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX,
358  SUBTYPE_MASK},
359  {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX,
360  SUBTYPE_MASK},
361  {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX,
362  SUBTYPE_MASK},
363  {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0,
364  UINT32_MAX, SUBTYPE_MASK},
365  {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY,
366  UINT32_MAX, SUBTYPE_MASK},
367  {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100,
368  UINT32_MAX, SUBTYPE_MASK},
369  {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX,
370  SUBTYPE_MASK},
371  {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX,
372  SUBTYPE_MASK},
373  {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84,
374  UINT32_MAX, SUBTYPE_MASK},
375  {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY,
376  UINT32_MAX, UINT32_MAX},
377  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX,
378  SUBTYPE_MASK},
379  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX,
380  SUBTYPE_MASK},
381  {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8,
382  UINT32_MAX, SUBTYPE_MASK},
383  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY,
384  UINT32_MAX, UINT32_MAX},
385  // Catch any unknown mach architectures so we can always use the object and
386  // symbol mach-o files
387  {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
388  {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u,
389  0x00000000u}};
390 
392  eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries),
393  g_macho_arch_entries, "mach-o"};
394 
395 //===----------------------------------------------------------------------===//
396 // A table that gets searched linearly for matches. This table is used to
397 // convert cpu type and subtypes to architecture names, and to convert
398 // architecture names to cpu types and subtypes. The ordering is important and
399 // allows the precedence to be set when the table is built.
401  {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
402  0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
403  {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
404  0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
405  {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
406  0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
407  {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
408  0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
409  {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
410  0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
411  {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
412  0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
413  {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
414  0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
415  {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
416  0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
417  {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
418  0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
419  {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
420  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
421  {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
422  0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
423  {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
424  0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
425  {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
426  ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
427  {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
428  ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
429  {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
430  ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
431  {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
432  ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
433  {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
434  ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
435  {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
436  0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
437  {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
438  ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
439  {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
440  ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
441  {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
442  ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
443  {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
444  ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
445  {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
446  ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
447  {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
448  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
449 };
450 
452  eArchTypeELF,
453  llvm::array_lengthof(g_elf_arch_entries),
455  "elf",
456 };
457 
459  {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
460  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
461  {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
462  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
463  {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
464  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
465  {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
466  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
467  {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
468  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
469  {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
470  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
471  {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
472  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64
473 };
474 
477  llvm::array_lengthof(g_coff_arch_entries),
479  "pe-coff",
480 };
481 
482 //===----------------------------------------------------------------------===//
483 // Table of all ArchDefinitions
485  &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def};
486 
487 static const size_t k_num_arch_definitions =
488  llvm::array_lengthof(g_arch_definitions);
489 
490 //===----------------------------------------------------------------------===//
491 // Static helper functions.
492 
493 // Get the architecture definition for a given object type.
495  for (unsigned int i = 0; i < k_num_arch_definitions; ++i) {
496  const ArchDefinition *def = g_arch_definitions[i];
497  if (def->type == arch_type)
498  return def;
499  }
500  return nullptr;
501 }
502 
503 // Get an architecture definition by name.
504 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
505  for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) {
506  if (name.equals_lower(g_core_definitions[i].name))
507  return &g_core_definitions[i];
508  }
509  return nullptr;
510 }
511 
513  if (core < llvm::array_lengthof(g_core_definitions))
514  return &g_core_definitions[core];
515  return nullptr;
516 }
517 
518 // Get a definition entry by cpu type and subtype.
519 static const ArchDefinitionEntry *
521  if (def == nullptr)
522  return nullptr;
523 
524  const ArchDefinitionEntry *entries = def->entries;
525  for (size_t i = 0; i < def->num_entries; ++i) {
526  if (entries[i].cpu == (cpu & entries[i].cpu_mask))
527  if (entries[i].sub == (sub & entries[i].sub_mask))
528  return &entries[i];
529  }
530  return nullptr;
531 }
532 
533 static const ArchDefinitionEntry *
535  if (def == nullptr)
536  return nullptr;
537 
538  const ArchDefinitionEntry *entries = def->entries;
539  for (size_t i = 0; i < def->num_entries; ++i) {
540  if (entries[i].core == core)
541  return &entries[i];
542  }
543  return nullptr;
544 }
545 
546 //===----------------------------------------------------------------------===//
547 // Constructors and destructors.
548 
549 ArchSpec::ArchSpec() {}
550 
551 ArchSpec::ArchSpec(const char *triple_cstr) {
552  if (triple_cstr)
553  SetTriple(triple_cstr);
554 }
555 
556 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
557 
558 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
559 
560 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
561  SetArchitecture(arch_type, cpu, subtype);
562 }
563 
564 ArchSpec::~ArchSpec() = default;
565 
566 //===----------------------------------------------------------------------===//
567 // Assignment and initialization.
568 
569 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) {
570  if (this != &rhs) {
571  m_triple = rhs.m_triple;
572  m_core = rhs.m_core;
573  m_byte_order = rhs.m_byte_order;
574  m_distribution_id = rhs.m_distribution_id;
575  m_flags = rhs.m_flags;
576  }
577  return *this;
578 }
579 
580 void ArchSpec::Clear() {
581  m_triple = llvm::Triple();
582  m_core = kCore_invalid;
583  m_byte_order = eByteOrderInvalid;
584  m_distribution_id.Clear();
585  m_flags = 0;
586 }
587 
588 //===----------------------------------------------------------------------===//
589 // Predicates.
590 
591 const char *ArchSpec::GetArchitectureName() const {
592  const CoreDefinition *core_def = FindCoreDefinition(m_core);
593  if (core_def)
594  return core_def->name;
595  return "unknown";
596 }
597 
598 bool ArchSpec::IsMIPS() const {
599  const llvm::Triple::ArchType machine = GetMachine();
600  return machine == llvm::Triple::mips || machine == llvm::Triple::mipsel ||
601  machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el;
602 }
603 
604 std::string ArchSpec::GetTargetABI() const {
605 
606  std::string abi;
607 
608  if (IsMIPS()) {
609  switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
610  case ArchSpec::eMIPSABI_N64:
611  abi = "n64";
612  return abi;
613  case ArchSpec::eMIPSABI_N32:
614  abi = "n32";
615  return abi;
616  case ArchSpec::eMIPSABI_O32:
617  abi = "o32";
618  return abi;
619  default:
620  return abi;
621  }
622  }
623  return abi;
624 }
625 
626 void ArchSpec::SetFlags(std::string elf_abi) {
627 
628  uint32_t flag = GetFlags();
629  if (IsMIPS()) {
630  if (elf_abi == "n64")
631  flag |= ArchSpec::eMIPSABI_N64;
632  else if (elf_abi == "n32")
633  flag |= ArchSpec::eMIPSABI_N32;
634  else if (elf_abi == "o32")
635  flag |= ArchSpec::eMIPSABI_O32;
636  }
637  SetFlags(flag);
638 }
639 
640 std::string ArchSpec::GetClangTargetCPU() const {
641  std::string cpu;
642  const llvm::Triple::ArchType machine = GetMachine();
643 
644  if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel ||
645  machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) {
646  switch (m_core) {
647  case ArchSpec::eCore_mips32:
648  case ArchSpec::eCore_mips32el:
649  cpu = "mips32";
650  break;
651  case ArchSpec::eCore_mips32r2:
652  case ArchSpec::eCore_mips32r2el:
653  cpu = "mips32r2";
654  break;
655  case ArchSpec::eCore_mips32r3:
656  case ArchSpec::eCore_mips32r3el:
657  cpu = "mips32r3";
658  break;
659  case ArchSpec::eCore_mips32r5:
660  case ArchSpec::eCore_mips32r5el:
661  cpu = "mips32r5";
662  break;
663  case ArchSpec::eCore_mips32r6:
664  case ArchSpec::eCore_mips32r6el:
665  cpu = "mips32r6";
666  break;
667  case ArchSpec::eCore_mips64:
668  case ArchSpec::eCore_mips64el:
669  cpu = "mips64";
670  break;
671  case ArchSpec::eCore_mips64r2:
672  case ArchSpec::eCore_mips64r2el:
673  cpu = "mips64r2";
674  break;
675  case ArchSpec::eCore_mips64r3:
676  case ArchSpec::eCore_mips64r3el:
677  cpu = "mips64r3";
678  break;
679  case ArchSpec::eCore_mips64r5:
680  case ArchSpec::eCore_mips64r5el:
681  cpu = "mips64r5";
682  break;
683  case ArchSpec::eCore_mips64r6:
684  case ArchSpec::eCore_mips64r6el:
685  cpu = "mips64r6";
686  break;
687  default:
688  break;
689  }
690  }
691  return cpu;
692 }
693 
694 uint32_t ArchSpec::GetMachOCPUType() const {
695  const CoreDefinition *core_def = FindCoreDefinition(m_core);
696  if (core_def) {
697  const ArchDefinitionEntry *arch_def =
698  FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
699  if (arch_def) {
700  return arch_def->cpu;
701  }
702  }
703  return LLDB_INVALID_CPUTYPE;
704 }
705 
706 uint32_t ArchSpec::GetMachOCPUSubType() const {
707  const CoreDefinition *core_def = FindCoreDefinition(m_core);
708  if (core_def) {
709  const ArchDefinitionEntry *arch_def =
710  FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
711  if (arch_def) {
712  return arch_def->sub;
713  }
714  }
715  return LLDB_INVALID_CPUTYPE;
716 }
717 
718 uint32_t ArchSpec::GetDataByteSize() const {
719  return 1;
720 }
721 
722 uint32_t ArchSpec::GetCodeByteSize() const {
723  return 1;
724 }
725 
726 llvm::Triple::ArchType ArchSpec::GetMachine() const {
727  const CoreDefinition *core_def = FindCoreDefinition(m_core);
728  if (core_def)
729  return core_def->machine;
730 
731  return llvm::Triple::UnknownArch;
732 }
733 
734 ConstString ArchSpec::GetDistributionId() const {
735  return m_distribution_id;
736 }
737 
738 void ArchSpec::SetDistributionId(const char *distribution_id) {
739  m_distribution_id.SetCString(distribution_id);
740 }
741 
742 uint32_t ArchSpec::GetAddressByteSize() const {
743  const CoreDefinition *core_def = FindCoreDefinition(m_core);
744  if (core_def) {
745  if (core_def->machine == llvm::Triple::mips64 ||
746  core_def->machine == llvm::Triple::mips64el) {
747  // For N32/O32 applications Address size is 4 bytes.
748  if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
749  return 4;
750  }
751  return core_def->addr_byte_size;
752  }
753  return 0;
754 }
755 
756 ByteOrder ArchSpec::GetDefaultEndian() const {
757  const CoreDefinition *core_def = FindCoreDefinition(m_core);
758  if (core_def)
759  return core_def->default_byte_order;
760  return eByteOrderInvalid;
761 }
762 
763 bool ArchSpec::CharIsSignedByDefault() const {
764  switch (m_triple.getArch()) {
765  default:
766  return true;
767 
768  case llvm::Triple::aarch64:
769  case llvm::Triple::aarch64_be:
770  case llvm::Triple::arm:
771  case llvm::Triple::armeb:
772  case llvm::Triple::thumb:
773  case llvm::Triple::thumbeb:
774  return m_triple.isOSDarwin() || m_triple.isOSWindows();
775 
776  case llvm::Triple::ppc:
777  case llvm::Triple::ppc64:
778  return m_triple.isOSDarwin();
779 
780  case llvm::Triple::ppc64le:
781  case llvm::Triple::systemz:
782  case llvm::Triple::xcore:
783  case llvm::Triple::arc:
784  return false;
785  }
786 }
787 
788 lldb::ByteOrder ArchSpec::GetByteOrder() const {
789  if (m_byte_order == eByteOrderInvalid)
790  return GetDefaultEndian();
791  return m_byte_order;
792 }
793 
794 //===----------------------------------------------------------------------===//
795 // Mutators.
796 
797 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
798  m_triple = triple;
799  UpdateCore();
800  return IsValid();
801 }
802 
803 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
804  ArchSpec &arch) {
805  // Accept "12-10" or "12.10" as cpu type/subtype
806  if (triple_str.empty())
807  return false;
808 
809  size_t pos = triple_str.find_first_of("-.");
810  if (pos == llvm::StringRef::npos)
811  return false;
812 
813  llvm::StringRef cpu_str = triple_str.substr(0, pos);
814  llvm::StringRef remainder = triple_str.substr(pos + 1);
815  if (cpu_str.empty() || remainder.empty())
816  return false;
817 
818  llvm::StringRef sub_str;
819  llvm::StringRef vendor;
820  llvm::StringRef os;
821  std::tie(sub_str, remainder) = remainder.split('-');
822  std::tie(vendor, os) = remainder.split('-');
823 
824  uint32_t cpu = 0;
825  uint32_t sub = 0;
826  if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
827  return false;
828 
829  if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
830  return false;
831  if (!vendor.empty() && !os.empty()) {
832  arch.GetTriple().setVendorName(vendor);
833  arch.GetTriple().setOSName(os);
834  }
835 
836  return true;
837 }
838 
839 bool ArchSpec::SetTriple(llvm::StringRef triple) {
840  if (triple.empty()) {
841  Clear();
842  return false;
843  }
844 
845  if (ParseMachCPUDashSubtypeTriple(triple, *this))
846  return true;
847 
848  SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
849  return IsValid();
850 }
851 
852 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
853  return !normalized_triple.getArchName().empty() &&
854  normalized_triple.getOSName().empty() &&
855  normalized_triple.getVendorName().empty() &&
856  normalized_triple.getEnvironmentName().empty();
857 }
858 
859 void ArchSpec::MergeFrom(const ArchSpec &other) {
860  if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
861  GetTriple().setVendor(other.GetTriple().getVendor());
862  if (!TripleOSWasSpecified() && other.TripleVendorWasSpecified())
863  GetTriple().setOS(other.GetTriple().getOS());
864  if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
865  GetTriple().setArch(other.GetTriple().getArch());
866 
867  // MachO unknown64 isn't really invalid as the debugger can still obtain
868  // information from the binary, e.g. line tables. As such, we don't update
869  // the core here.
870  if (other.GetCore() != eCore_uknownMach64)
871  UpdateCore();
872  }
873  if (!TripleEnvironmentWasSpecified() &&
875  GetTriple().setEnvironment(other.GetTriple().getEnvironment());
876  }
877  // If this and other are both arm ArchSpecs and this ArchSpec is a generic
878  // "some kind of arm" spec but the other ArchSpec is a specific arm core,
879  // adopt the specific arm core.
880  if (GetTriple().getArch() == llvm::Triple::arm &&
881  other.GetTriple().getArch() == llvm::Triple::arm &&
882  IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
883  other.GetCore() != ArchSpec::eCore_arm_generic) {
884  m_core = other.GetCore();
885  CoreUpdated(true);
886  }
887  if (GetFlags() == 0) {
888  SetFlags(other.GetFlags());
889  }
890 }
891 
892 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
893  uint32_t sub, uint32_t os) {
894  m_core = kCore_invalid;
895  bool update_triple = true;
896  const ArchDefinition *arch_def = FindArchDefinition(arch_type);
897  if (arch_def) {
898  const ArchDefinitionEntry *arch_def_entry =
899  FindArchDefinitionEntry(arch_def, cpu, sub);
900  if (arch_def_entry) {
901  const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
902  if (core_def) {
903  m_core = core_def->core;
904  update_triple = false;
905  // Always use the architecture name because it might be more
906  // descriptive than the architecture enum ("armv7" ->
907  // llvm::Triple::arm).
908  m_triple.setArchName(llvm::StringRef(core_def->name));
909  if (arch_type == eArchTypeMachO) {
910  m_triple.setVendor(llvm::Triple::Apple);
911 
912  // Don't set the OS. It could be simulator, macosx, ios, watchos,
913  // tvos, bridgeos. We could get close with the cpu type - but we
914  // can't get it right all of the time. Better to leave this unset
915  // so other sections of code will set it when they have more
916  // information. NB: don't call m_triple.setOS
917  // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
918  // the ArchSpec::TripleVendorWasSpecified() method says that any
919  // OSName setting means it was specified.
920  } else if (arch_type == eArchTypeELF) {
921  switch (os) {
922  case llvm::ELF::ELFOSABI_AIX:
923  m_triple.setOS(llvm::Triple::OSType::AIX);
924  break;
925  case llvm::ELF::ELFOSABI_FREEBSD:
926  m_triple.setOS(llvm::Triple::OSType::FreeBSD);
927  break;
928  case llvm::ELF::ELFOSABI_GNU:
929  m_triple.setOS(llvm::Triple::OSType::Linux);
930  break;
931  case llvm::ELF::ELFOSABI_NETBSD:
932  m_triple.setOS(llvm::Triple::OSType::NetBSD);
933  break;
934  case llvm::ELF::ELFOSABI_OPENBSD:
935  m_triple.setOS(llvm::Triple::OSType::OpenBSD);
936  break;
937  case llvm::ELF::ELFOSABI_SOLARIS:
938  m_triple.setOS(llvm::Triple::OSType::Solaris);
939  break;
940  }
941  } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
942  m_triple.setVendor(llvm::Triple::PC);
943  m_triple.setOS(llvm::Triple::Win32);
944  } else {
945  m_triple.setVendor(llvm::Triple::UnknownVendor);
946  m_triple.setOS(llvm::Triple::UnknownOS);
947  }
948  // Fall back onto setting the machine type if the arch by name
949  // failed...
950  if (m_triple.getArch() == llvm::Triple::UnknownArch)
951  m_triple.setArch(core_def->machine);
952  }
953  } else {
955  if (log)
956  log->Printf("Unable to find a core definition for cpu 0x%" PRIx32 " sub %" PRId32, cpu, sub);
957  }
958  }
959  CoreUpdated(update_triple);
960  return IsValid();
961 }
962 
963 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
964  const CoreDefinition *core_def = FindCoreDefinition(m_core);
965  if (core_def)
966  return core_def->min_opcode_byte_size;
967  return 0;
968 }
969 
970 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
971  const CoreDefinition *core_def = FindCoreDefinition(m_core);
972  if (core_def)
973  return core_def->max_opcode_byte_size;
974  return 0;
975 }
976 
977 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const {
978  return IsEqualTo(rhs, true);
979 }
980 
981 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const {
982  return IsEqualTo(rhs, false);
983 }
984 
985 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
986  llvm::Triple::EnvironmentType rhs) {
987  if (lhs == rhs)
988  return true;
989 
990  // If any of the environment is unknown then they are compatible
991  if (lhs == llvm::Triple::UnknownEnvironment ||
992  rhs == llvm::Triple::UnknownEnvironment)
993  return true;
994 
995  // If one of the environment is Android and the other one is EABI then they
996  // are considered to be compatible. This is required as a workaround for
997  // shared libraries compiled for Android without the NOTE section indicating
998  // that they are using the Android ABI.
999  if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
1000  (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
1001  (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
1002  (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
1003  (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
1004  (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
1005  return true;
1006 
1007  return false;
1008 }
1009 
1010 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const {
1011  // explicitly ignoring m_distribution_id in this method.
1012 
1013  if (GetByteOrder() != rhs.GetByteOrder())
1014  return false;
1015 
1016  const ArchSpec::Core lhs_core = GetCore();
1017  const ArchSpec::Core rhs_core = rhs.GetCore();
1018 
1019  const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match);
1020 
1021  if (core_match) {
1022  const llvm::Triple &lhs_triple = GetTriple();
1023  const llvm::Triple &rhs_triple = rhs.GetTriple();
1024 
1025  const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
1026  const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
1027  if (lhs_triple_vendor != rhs_triple_vendor) {
1028  const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
1029  const bool lhs_vendor_specified = TripleVendorWasSpecified();
1030  // Both architectures had the vendor specified, so if they aren't equal
1031  // then we return false
1032  if (rhs_vendor_specified && lhs_vendor_specified)
1033  return false;
1034 
1035  // Only fail if both vendor types are not unknown
1036  if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
1037  rhs_triple_vendor != llvm::Triple::UnknownVendor)
1038  return false;
1039  }
1040 
1041  const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
1042  const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
1043  if (lhs_triple_os != rhs_triple_os) {
1044  const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1045  const bool lhs_os_specified = TripleOSWasSpecified();
1046  // Both architectures had the OS specified, so if they aren't equal then
1047  // we return false
1048  if (rhs_os_specified && lhs_os_specified)
1049  return false;
1050 
1051  // Only fail if both os types are not unknown
1052  if (lhs_triple_os != llvm::Triple::UnknownOS &&
1053  rhs_triple_os != llvm::Triple::UnknownOS)
1054  return false;
1055  }
1056 
1057  const llvm::Triple::EnvironmentType lhs_triple_env =
1058  lhs_triple.getEnvironment();
1059  const llvm::Triple::EnvironmentType rhs_triple_env =
1060  rhs_triple.getEnvironment();
1061 
1062  return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1063  }
1064  return false;
1065 }
1066 
1067 void ArchSpec::UpdateCore() {
1068  llvm::StringRef arch_name(m_triple.getArchName());
1069  const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1070  if (core_def) {
1071  m_core = core_def->core;
1072  // Set the byte order to the default byte order for an architecture. This
1073  // can be modified if needed for cases when cores handle both big and
1074  // little endian
1075  m_byte_order = core_def->default_byte_order;
1076  } else {
1077  Clear();
1078  }
1079 }
1080 
1081 //===----------------------------------------------------------------------===//
1082 // Helper methods.
1083 
1084 void ArchSpec::CoreUpdated(bool update_triple) {
1085  const CoreDefinition *core_def = FindCoreDefinition(m_core);
1086  if (core_def) {
1087  if (update_triple)
1088  m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1089  m_byte_order = core_def->default_byte_order;
1090  } else {
1091  if (update_triple)
1092  m_triple = llvm::Triple();
1093  m_byte_order = eByteOrderInvalid;
1094  }
1095 }
1096 
1097 //===----------------------------------------------------------------------===//
1098 // Operators.
1099 
1100 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1101  bool try_inverse, bool enforce_exact_match) {
1102  if (core1 == core2)
1103  return true;
1104 
1105  switch (core1) {
1106  case ArchSpec::kCore_any:
1107  return true;
1108 
1109  case ArchSpec::eCore_arm_generic:
1110  if (enforce_exact_match)
1111  break;
1112  LLVM_FALLTHROUGH;
1113  case ArchSpec::kCore_arm_any:
1114  if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1115  return true;
1116  if (core2 >= ArchSpec::kCore_thumb_first &&
1117  core2 <= ArchSpec::kCore_thumb_last)
1118  return true;
1119  if (core2 == ArchSpec::kCore_arm_any)
1120  return true;
1121  break;
1122 
1123  case ArchSpec::kCore_x86_32_any:
1124  if ((core2 >= ArchSpec::kCore_x86_32_first &&
1125  core2 <= ArchSpec::kCore_x86_32_last) ||
1126  (core2 == ArchSpec::kCore_x86_32_any))
1127  return true;
1128  break;
1129 
1130  case ArchSpec::kCore_x86_64_any:
1131  if ((core2 >= ArchSpec::kCore_x86_64_first &&
1132  core2 <= ArchSpec::kCore_x86_64_last) ||
1133  (core2 == ArchSpec::kCore_x86_64_any))
1134  return true;
1135  break;
1136 
1137  case ArchSpec::kCore_ppc_any:
1138  if ((core2 >= ArchSpec::kCore_ppc_first &&
1139  core2 <= ArchSpec::kCore_ppc_last) ||
1140  (core2 == ArchSpec::kCore_ppc_any))
1141  return true;
1142  break;
1143 
1144  case ArchSpec::kCore_ppc64_any:
1145  if ((core2 >= ArchSpec::kCore_ppc64_first &&
1146  core2 <= ArchSpec::kCore_ppc64_last) ||
1147  (core2 == ArchSpec::kCore_ppc64_any))
1148  return true;
1149  break;
1150 
1151  case ArchSpec::eCore_arm_armv6m:
1152  if (!enforce_exact_match) {
1153  if (core2 == ArchSpec::eCore_arm_generic)
1154  return true;
1155  try_inverse = false;
1156  if (core2 == ArchSpec::eCore_arm_armv7)
1157  return true;
1158  if (core2 == ArchSpec::eCore_arm_armv6m)
1159  return true;
1160  }
1161  break;
1162 
1163  case ArchSpec::kCore_hexagon_any:
1164  if ((core2 >= ArchSpec::kCore_hexagon_first &&
1165  core2 <= ArchSpec::kCore_hexagon_last) ||
1166  (core2 == ArchSpec::kCore_hexagon_any))
1167  return true;
1168  break;
1169 
1170  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1171  // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 -
1172  // ARMv7E-M - armv7em
1173  case ArchSpec::eCore_arm_armv7em:
1174  if (!enforce_exact_match) {
1175  if (core2 == ArchSpec::eCore_arm_generic)
1176  return true;
1177  if (core2 == ArchSpec::eCore_arm_armv7m)
1178  return true;
1179  if (core2 == ArchSpec::eCore_arm_armv6m)
1180  return true;
1181  if (core2 == ArchSpec::eCore_arm_armv7)
1182  return true;
1183  try_inverse = true;
1184  }
1185  break;
1186 
1187  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1188  // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 -
1189  // ARMv7E-M - armv7em
1190  case ArchSpec::eCore_arm_armv7m:
1191  if (!enforce_exact_match) {
1192  if (core2 == ArchSpec::eCore_arm_generic)
1193  return true;
1194  if (core2 == ArchSpec::eCore_arm_armv6m)
1195  return true;
1196  if (core2 == ArchSpec::eCore_arm_armv7)
1197  return true;
1198  if (core2 == ArchSpec::eCore_arm_armv7em)
1199  return true;
1200  try_inverse = true;
1201  }
1202  break;
1203 
1204  case ArchSpec::eCore_arm_armv7f:
1205  case ArchSpec::eCore_arm_armv7k:
1206  case ArchSpec::eCore_arm_armv7s:
1207  if (!enforce_exact_match) {
1208  if (core2 == ArchSpec::eCore_arm_generic)
1209  return true;
1210  if (core2 == ArchSpec::eCore_arm_armv7)
1211  return true;
1212  try_inverse = false;
1213  }
1214  break;
1215 
1216  case ArchSpec::eCore_x86_64_x86_64h:
1217  if (!enforce_exact_match) {
1218  try_inverse = false;
1219  if (core2 == ArchSpec::eCore_x86_64_x86_64)
1220  return true;
1221  }
1222  break;
1223 
1224  case ArchSpec::eCore_arm_armv8:
1225  if (!enforce_exact_match) {
1226  if (core2 == ArchSpec::eCore_arm_arm64)
1227  return true;
1228  if (core2 == ArchSpec::eCore_arm_aarch64)
1229  return true;
1230  try_inverse = false;
1231  }
1232  break;
1233 
1234  case ArchSpec::eCore_arm_aarch64:
1235  if (!enforce_exact_match) {
1236  if (core2 == ArchSpec::eCore_arm_arm64)
1237  return true;
1238  if (core2 == ArchSpec::eCore_arm_armv8)
1239  return true;
1240  try_inverse = false;
1241  }
1242  break;
1243 
1244  case ArchSpec::eCore_arm_arm64:
1245  if (!enforce_exact_match) {
1246  if (core2 == ArchSpec::eCore_arm_aarch64)
1247  return true;
1248  if (core2 == ArchSpec::eCore_arm_armv8)
1249  return true;
1250  try_inverse = false;
1251  }
1252  break;
1253 
1254  case ArchSpec::eCore_mips32:
1255  if (!enforce_exact_match) {
1256  if (core2 >= ArchSpec::kCore_mips32_first &&
1257  core2 <= ArchSpec::kCore_mips32_last)
1258  return true;
1259  try_inverse = false;
1260  }
1261  break;
1262 
1263  case ArchSpec::eCore_mips32el:
1264  if (!enforce_exact_match) {
1265  if (core2 >= ArchSpec::kCore_mips32el_first &&
1266  core2 <= ArchSpec::kCore_mips32el_last)
1267  return true;
1268  try_inverse = true;
1269  }
1270  break;
1271 
1272  case ArchSpec::eCore_mips64:
1273  if (!enforce_exact_match) {
1274  if (core2 >= ArchSpec::kCore_mips32_first &&
1275  core2 <= ArchSpec::kCore_mips32_last)
1276  return true;
1277  if (core2 >= ArchSpec::kCore_mips64_first &&
1278  core2 <= ArchSpec::kCore_mips64_last)
1279  return true;
1280  try_inverse = false;
1281  }
1282  break;
1283 
1284  case ArchSpec::eCore_mips64el:
1285  if (!enforce_exact_match) {
1286  if (core2 >= ArchSpec::kCore_mips32el_first &&
1287  core2 <= ArchSpec::kCore_mips32el_last)
1288  return true;
1289  if (core2 >= ArchSpec::kCore_mips64el_first &&
1290  core2 <= ArchSpec::kCore_mips64el_last)
1291  return true;
1292  try_inverse = false;
1293  }
1294  break;
1295 
1296  case ArchSpec::eCore_mips64r2:
1297  case ArchSpec::eCore_mips64r3:
1298  case ArchSpec::eCore_mips64r5:
1299  if (!enforce_exact_match) {
1300  if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1301  return true;
1302  if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1303  return true;
1304  try_inverse = false;
1305  }
1306  break;
1307 
1308  case ArchSpec::eCore_mips64r2el:
1309  case ArchSpec::eCore_mips64r3el:
1310  case ArchSpec::eCore_mips64r5el:
1311  if (!enforce_exact_match) {
1312  if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1313  return true;
1314  if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1315  return true;
1316  try_inverse = false;
1317  }
1318  break;
1319 
1320  case ArchSpec::eCore_mips32r2:
1321  case ArchSpec::eCore_mips32r3:
1322  case ArchSpec::eCore_mips32r5:
1323  if (!enforce_exact_match) {
1324  if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1325  return true;
1326  }
1327  break;
1328 
1329  case ArchSpec::eCore_mips32r2el:
1330  case ArchSpec::eCore_mips32r3el:
1331  case ArchSpec::eCore_mips32r5el:
1332  if (!enforce_exact_match) {
1333  if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1334  return true;
1335  }
1336  break;
1337 
1338  case ArchSpec::eCore_mips32r6:
1339  if (!enforce_exact_match) {
1340  if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1341  return true;
1342  }
1343  break;
1344 
1345  case ArchSpec::eCore_mips32r6el:
1346  if (!enforce_exact_match) {
1347  if (core2 == ArchSpec::eCore_mips32el ||
1348  core2 == ArchSpec::eCore_mips32r6el)
1349  return true;
1350  }
1351  break;
1352 
1353  case ArchSpec::eCore_mips64r6:
1354  if (!enforce_exact_match) {
1355  if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1356  return true;
1357  if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1358  return true;
1359  }
1360  break;
1361 
1362  case ArchSpec::eCore_mips64r6el:
1363  if (!enforce_exact_match) {
1364  if (core2 == ArchSpec::eCore_mips32el ||
1365  core2 == ArchSpec::eCore_mips32r6el)
1366  return true;
1367  if (core2 == ArchSpec::eCore_mips64el ||
1368  core2 == ArchSpec::eCore_mips64r6el)
1369  return true;
1370  }
1371  break;
1372 
1373  default:
1374  break;
1375  }
1376  if (try_inverse)
1377  return cores_match(core2, core1, false, enforce_exact_match);
1378  return false;
1379 }
1380 
1381 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1382  const ArchSpec::Core lhs_core = lhs.GetCore();
1383  const ArchSpec::Core rhs_core = rhs.GetCore();
1384  return lhs_core < rhs_core;
1385 }
1386 
1387 
1388 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1389  return lhs.GetCore() == rhs.GetCore();
1390 }
1391 
1392 bool ArchSpec::IsFullySpecifiedTriple() const {
1393  const auto &user_specified_triple = GetTriple();
1394 
1395  bool user_triple_fully_specified = false;
1396 
1397  if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) ||
1398  TripleOSWasSpecified()) {
1399  if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) ||
1400  TripleVendorWasSpecified()) {
1401  const unsigned unspecified = 0;
1402  if (user_specified_triple.getOSMajorVersion() != unspecified) {
1403  user_triple_fully_specified = true;
1404  }
1405  }
1406  }
1407 
1408  return user_triple_fully_specified;
1409 }
1410 
1411 void ArchSpec::PiecewiseTripleCompare(
1412  const ArchSpec &other, bool &arch_different, bool &vendor_different,
1413  bool &os_different, bool &os_version_different, bool &env_different) const {
1414  const llvm::Triple &me(GetTriple());
1415  const llvm::Triple &them(other.GetTriple());
1416 
1417  arch_different = (me.getArch() != them.getArch());
1418 
1419  vendor_different = (me.getVendor() != them.getVendor());
1420 
1421  os_different = (me.getOS() != them.getOS());
1422 
1423  os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
1424 
1425  env_different = (me.getEnvironment() != them.getEnvironment());
1426 }
1427 
1428 bool ArchSpec::IsAlwaysThumbInstructions() const {
1429  std::string Status;
1430  if (GetTriple().getArch() == llvm::Triple::arm ||
1431  GetTriple().getArch() == llvm::Triple::thumb) {
1432  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1433  //
1434  // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1435  // execute thumb instructions. We map the cores to arch names like this:
1436  //
1437  // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
1438  // Cortex-M7: armv7em
1439 
1440  if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1441  GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1442  GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1443  GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1444  GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1445  GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1446  return true;
1447  }
1448  }
1449  return false;
1450 }
1451 
1452 void ArchSpec::DumpTriple(Stream &s) const {
1453  const llvm::Triple &triple = GetTriple();
1454  llvm::StringRef arch_str = triple.getArchName();
1455  llvm::StringRef vendor_str = triple.getVendorName();
1456  llvm::StringRef os_str = triple.getOSName();
1457  llvm::StringRef environ_str = triple.getEnvironmentName();
1458 
1459  s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(),
1460  vendor_str.empty() ? "*" : vendor_str.str().c_str(),
1461  os_str.empty() ? "*" : os_str.str().c_str());
1462 
1463  if (!environ_str.empty())
1464  s.Printf("-%s", environ_str.str().c_str());
1465 }
uint32_t GetFlags() const
Definition: ArchSpec.h:501
bool NameMatches(llvm::StringRef name, NameMatch match_type, llvm::StringRef match)
Definition: NameMatches.cpp:15
Core GetCore() const
Definition: ArchSpec.h:410
#define LIBLLDB_LOG_PROCESS
Definition: Logging.h:15
Enumerations for broadcasting.
Definition: SBLaunchInfo.h:14
A stream class that can stream formatted output to a file.
Definition: Stream.h:28
#define CPU_ANY
Definition: ArchSpec.cpp:261
static const CoreDefinition g_core_definitions[]
Definition: ArchSpec.cpp:45
static const ArchDefinition * FindArchDefinition(ArchitectureType arch_type)
Definition: ArchSpec.cpp:494
bool TripleEnvironmentWasSpecified() const
Definition: ArchSpec.h:340
An architecture specification class.
Definition: ArchSpec.h:32
const char *const name
Definition: ArchSpec.cpp:39
void AddCompletions(const StringList &completions)
Adds multiple possible completion strings.
std::size_t GetNumberOfMatches() const
#define LIBLLDB_LOG_PLATFORM
Definition: Logging.h:39
static const ArchDefinitionEntry g_macho_arch_entries[]
Definition: ArchSpec.cpp:270
static const ArchDefinition g_coff_arch_def
Definition: ArchSpec.cpp:475
static const ArchDefinition * g_arch_definitions[]
Definition: ArchSpec.cpp:484
void AddCompletion(llvm::StringRef completion, llvm::StringRef description="")
Adds a possible completion string.
#define LLDB_INVALID_CPUTYPE
Definition: lldb-defines.h:104
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:431
static const ArchDefinitionEntry g_coff_arch_entries[]
Definition: ArchSpec.cpp:458
bool TripleVendorWasSpecified() const
Definition: ArchSpec.h:334
"lldb/Utility/ArgCompletionRequest.h"
bool operator==(const Address &lhs, const Address &rhs)
Definition: Address.cpp:973
#define UINT32_MAX
Definition: lldb-defines.h:31
static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, llvm::Triple::EnvironmentType rhs)
Definition: ArchSpec.cpp:985
llvm::StringRef GetCursorArgumentPrefix() const
static const ArchDefinition g_elf_arch_def
Definition: ArchSpec.cpp:451
lldb::ByteOrder m_byte_order
Definition: ArchSpec.h:513
size_t num_entries
Definition: ArchSpec.cpp:236
static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
Definition: ArchSpec.cpp:1100
static const ArchDefinitionEntry * FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub)
Definition: ArchSpec.cpp:520
ConstString m_distribution_id
Definition: ArchSpec.h:519
lldb::ByteOrder GetByteOrder() const
Returns the byte order for the architecture specification.
Definition: ArchSpec.cpp:788
#define LIBLLDB_LOG_TARGET
Definition: Logging.h:36
size_t Printf(const char *format,...) __attribute__((format(printf
Output printf formatted output to the stream.
Definition: Stream.cpp:106
const char * name
Definition: ArchSpec.cpp:238
static const size_t k_num_arch_definitions
Definition: ArchSpec.cpp:487
static const ArchDefinition g_macho_arch_def
Definition: ArchSpec.cpp:391
ArchitectureType type
Definition: ArchSpec.cpp:235
llvm::Triple::ArchType machine
Definition: ArchSpec.cpp:37
static const CoreDefinition * FindCoreDefinition(llvm::StringRef name)
Definition: ArchSpec.cpp:504
A uniqued constant string class.
Definition: ConstString.h:38
static const ArchDefinitionEntry g_elf_arch_entries[]
Definition: ArchSpec.cpp:400
const ArchDefinitionEntry * entries
Definition: ArchSpec.cpp:237
Log * GetLogIfAnyCategoriesSet(uint32_t mask)
Definition: Logging.cpp:61
Definition: SBAddress.h:15
bool TripleOSWasSpecified() const
Definition: ArchSpec.h:338
#define CPU_TYPE_ARM64
#define SUBTYPE_MASK
Definition: ArchSpec.cpp:268
bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os=0)
Change the architecture object type, CPU type and OS type.
Definition: ArchSpec.cpp:892
bool operator<(const Address &lhs, const Address &rhs)
Definition: Address.cpp:942
void AppendString(const std::string &s)
Definition: StringList.cpp:43
void Printf(const char *format,...) __attribute__((format(printf
Definition: Log.cpp:113
llvm::Triple m_triple
Definition: ArchSpec.h:511
ArchSpec::Core core
Definition: ArchSpec.cpp:227
An error handling class.
Definition: Status.h:44
void SetCString(const char *cstr)
Set the C string value.
bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch)
Definition: ArchSpec.cpp:803