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ArchSpec.cpp
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1//===-- ArchSpec.cpp ------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11
12#include "lldb/Utility/Log.h"
14#include "lldb/lldb-defines.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/BinaryFormat/COFF.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/BinaryFormat/MachO.h"
19#include "llvm/BinaryFormat/XCOFF.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/TargetParser/ARMTargetParser.h"
22
23using namespace lldb;
24using namespace lldb_private;
25
26static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
27 bool try_inverse, bool enforce_exact_match);
28
29namespace lldb_private {
30
36 llvm::Triple::ArchType machine;
38 const char *const name;
39};
40
41} // namespace lldb_private
42
43// This core information can be looked using the ArchSpec::Core as the index
44static constexpr const CoreDefinition g_core_definitions[] = {
45 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
46 "arm"},
47 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
48 "armv4"},
49 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
50 "armv4t"},
51 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
52 "armv5"},
53 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
54 "armv5e"},
55 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
56 "armv5t"},
57 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
58 "armv6"},
59 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
60 "armv6m"},
61 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
62 "armv7"},
63 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7a,
64 "armv7a"},
65 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
66 "armv7l"},
67 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
68 "armv7f"},
69 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
70 "armv7s"},
71 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
72 "armv7k"},
73 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
74 "armv7m"},
75 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
76 "armv7em"},
77 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
78 "xscale"},
79 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
80 "thumb"},
81 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
82 "thumbv4t"},
83 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
84 "thumbv5"},
85 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
86 "thumbv5e"},
87 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
88 "thumbv6"},
89 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
90 "thumbv6m"},
91 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
92 "thumbv7"},
93 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
94 "thumbv7s"},
95 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
96 "thumbv7k"},
97 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
98 "thumbv7f"},
99 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
100 "thumbv7m"},
101 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
102 "thumbv7em"},
103 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
105 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
107 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
109 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
110 "armv8l"},
111 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
113 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
114 ArchSpec::eCore_arm_arm64_32, "arm64_32"},
115 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
116 ArchSpec::eCore_arm_aarch64, "aarch64"},
117
118 // mips32, mips32r2, mips32r3, mips32r5, mips32r6
119 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
120 "mips"},
121 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
122 "mipsr2"},
123 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
124 "mipsr3"},
125 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
126 "mipsr5"},
127 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
128 "mipsr6"},
129 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
130 "mipsel"},
131 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
132 ArchSpec::eCore_mips32r2el, "mipsr2el"},
133 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
134 ArchSpec::eCore_mips32r3el, "mipsr3el"},
135 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
136 ArchSpec::eCore_mips32r5el, "mipsr5el"},
137 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
138 ArchSpec::eCore_mips32r6el, "mipsr6el"},
139
140 // mips64, mips64r2, mips64r3, mips64r5, mips64r6
141 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
142 "mips64"},
143 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
144 "mips64r2"},
145 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
146 "mips64r3"},
147 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
148 "mips64r5"},
149 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
150 "mips64r6"},
151 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
152 ArchSpec::eCore_mips64el, "mips64el"},
153 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
154 ArchSpec::eCore_mips64r2el, "mips64r2el"},
155 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
156 ArchSpec::eCore_mips64r3el, "mips64r3el"},
157 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
158 ArchSpec::eCore_mips64r5el, "mips64r5el"},
159 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
160 ArchSpec::eCore_mips64r6el, "mips64r6el"},
161
162 // MSP430
163 {eByteOrderLittle, 2, 2, 4, llvm::Triple::msp430, ArchSpec::eCore_msp430,
164 "msp430"},
165
166 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
167 "powerpc"},
168 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
169 "ppc601"},
170 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
171 "ppc602"},
172 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
173 "ppc603"},
174 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
175 "ppc603e"},
176 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
177 "ppc603ev"},
178 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
179 "ppc604"},
180 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
181 "ppc604e"},
182 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
183 "ppc620"},
184 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
185 "ppc750"},
186 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
187 "ppc7400"},
188 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
189 "ppc7450"},
190 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
191 "ppc970"},
192
193 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
194 ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
195 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
196 "powerpc64"},
197 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
199
200 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
202
203 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
205 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
207
208 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
209 "i386"},
210 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
211 "i486"},
212 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
214 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
215 "i686"},
216
217 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
219 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
221 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
223
224 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
226 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
228 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
230
231 {eByteOrderLittle, 4, 2, 8, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
232 "riscv32"},
233 {eByteOrderLittle, 8, 2, 8, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
234 "riscv64"},
235
236 {eByteOrderLittle, 4, 4, 4, llvm::Triple::loongarch32,
237 ArchSpec::eCore_loongarch32, "loongarch32"},
238 {eByteOrderLittle, 8, 4, 4, llvm::Triple::loongarch64,
239 ArchSpec::eCore_loongarch64, "loongarch64"},
240
241 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
242 ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
243 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
244 ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
245 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
246
247 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
248
249 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
250 "wasm32"},
251};
252
253// Ensure that we have an entry in the g_core_definitions for each core. If you
254// comment out an entry above, you will need to comment out the corresponding
255// ArchSpec::Core enumeration.
256static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
258 "make sure we have one core definition for each core");
259
260template <int I> struct ArchSpecValidator : ArchSpecValidator<I + 1> {
261 static_assert(g_core_definitions[I].core == I,
262 "g_core_definitions order doesn't match Core enumeration");
263};
264
265template <> struct ArchSpecValidator<ArchSpec::kNumCores> {};
266
268
276
283
285 for (const auto &def : g_core_definitions)
286 list.AppendString(def.name);
287}
288
290 for (const auto &def : g_core_definitions)
291 request.TryCompleteCurrentArg(def.name);
292}
293
294#define CPU_ANY (UINT32_MAX)
295
296//===----------------------------------------------------------------------===//
297// A table that gets searched linearly for matches. This table is used to
298// convert cpu type and subtypes to architecture names, and to convert
299// architecture names to cpu types and subtypes. The ordering is important and
300// allows the precedence to be set when the table is built.
301#define SUBTYPE_MASK 0x00FFFFFFu
302
303// clang-format off
305 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
306 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
307 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
308 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
309 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
310 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
311 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
312 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
313 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
314 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
315 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
316 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
317 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
318 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
319 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
320 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
321 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
322 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
323 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
324 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK},
325 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK},
326 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK},
327 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
328 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
329 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
330 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
331 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
332 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
333 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
334 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
335 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
336 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
337 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
338 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
339 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
340 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
341 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
342 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
343 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
344 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
345 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
346 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
347 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
348 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
349 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
350 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
351 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
352 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
353 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
354 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
355 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
356 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK},
357 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
358 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
359 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
360 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
361 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
362 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
363 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
364 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
365 {ArchSpec::eCore_riscv32, llvm::MachO::CPU_TYPE_RISCV, llvm::MachO::CPU_SUBTYPE_RISCV_ALL, UINT32_MAX, SUBTYPE_MASK},
366 {ArchSpec::eCore_riscv32, llvm::MachO::CPU_TYPE_RISCV, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
367 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
368 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
369 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}
370};
371// clang-format on
372
376
377//===----------------------------------------------------------------------===//
378// A table that gets searched linearly for matches. This table is used to
379// convert cpu type and subtypes to architecture names, and to convert
380// architecture names to cpu types and subtypes. The ordering is important and
381// allows the precedence to be set when the table is built.
382// clang-format off
384 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC }, // Sparc
385 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386 }, // Intel 80386
386 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU }, // Intel MCU // FIXME: is this correct?
387 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC }, // PowerPC
388 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, ArchSpec::eCore_ppc64le_generic}, // PowerPC64le
389 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, ArchSpec::eCore_ppc64_generic}, // PowerPC64
390 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM }, // ARM
391 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64 }, // ARM64
392 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390 }, // SystemZ
393 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9 }, // SPARC V9
394 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64 }, // AMD64
395 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32}, // mips32
396 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32r2}, // mips32r2
397 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32r6}, // mips32r6
398 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32el}, // mips32el
399 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32r2el}, // mips32r2el
400 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32r6el}, // mips32r6el
402 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64r2}, // mips64r2
403 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64r6}, // mips64r6
404 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64el}, // mips64el
405 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64r2el}, // mips64r2el
406 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64r6el}, // mips64r6el
407 {ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430 }, // MSP430
408 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON }, // HEXAGON
409 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2}, // ARC
410 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR }, // AVR
411 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, ArchSpec::eRISCVSubType_riscv32}, // riscv32
412 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, ArchSpec::eRISCVSubType_riscv64}, // riscv64
413 {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH, ArchSpec::eLoongArchSubType_loongarch32}, // loongarch32
414 {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH, ArchSpec::eLoongArchSubType_loongarch64}, // loongarch64
415};
416// clang-format on
417
420 std::size(g_elf_arch_entries),
422 "elf",
423};
424// clang-format off
426 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386}, // Intel 80x86
427 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC}, // PowerPC
428 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP}, // PowerPC (with FPU)
429 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM}, // ARM
430 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT}, // ARMv7
431 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB}, // ARMv7
432 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64}, // AMD64
433 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64} // ARM64
434};
435// clang-format on
436
439 std::size(g_coff_arch_entries),
441 "pe-coff",
442};
443
444// clang-format off
446 {ArchSpec::eCore_ppc_generic, llvm::XCOFF::TCPU_COM},
447 {ArchSpec::eCore_ppc64_generic, llvm::XCOFF::TCPU_PPC64}
448};
449// clang-format on
450
453 std::size(g_xcoff_arch_entries),
455 "xcoff",
456};
457
458//===----------------------------------------------------------------------===//
459// Table of all ArchDefinitions
462
463//===----------------------------------------------------------------------===//
464// Static helper functions.
465
466// Get the architecture definition for a given object type.
468 for (const ArchDefinition *def : g_arch_definitions) {
469 if (def->type == arch_type)
470 return def;
471 }
472 return nullptr;
473}
474
475// Get an architecture definition by name.
476static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
477 for (const auto &def : g_core_definitions) {
478 if (name.equals_insensitive(def.name))
479 return &def;
480 }
481 return nullptr;
482}
483
485 if (core < std::size(g_core_definitions))
486 return &g_core_definitions[core];
487 return nullptr;
488}
489
490// Get a definition entry by cpu type and subtype.
491static const ArchDefinitionEntry *
492FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) {
493 if (def == nullptr)
494 return nullptr;
495
496 const ArchDefinitionEntry *entries = def->entries;
497 for (size_t i = 0; i < def->num_entries; ++i) {
498 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
499 if (entries[i].sub == (sub & entries[i].sub_mask))
500 return &entries[i];
501 }
502 return nullptr;
503}
504
505static const ArchDefinitionEntry *
507 if (def == nullptr)
508 return nullptr;
509
510 const ArchDefinitionEntry *entries = def->entries;
511 for (size_t i = 0; i < def->num_entries; ++i) {
512 if (entries[i].core == core)
513 return &entries[i];
514 }
515 return nullptr;
516}
517
518//===----------------------------------------------------------------------===//
519// Constructors and destructors.
520
521ArchSpec::ArchSpec() = default;
522
523ArchSpec::ArchSpec(const char *triple_cstr) {
524 if (triple_cstr)
525 SetTriple(triple_cstr);
526}
527
528ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
529
530ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
531
532ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
533 SetArchitecture(arch_type, cpu, subtype);
534}
535
536ArchSpec::~ArchSpec() = default;
537
539 m_triple = llvm::Triple();
542 m_flags = 0;
543}
544
545//===----------------------------------------------------------------------===//
546// Predicates.
547
548const char *ArchSpec::GetArchitectureName() const {
549 const CoreDefinition *core_def = FindCoreDefinition(m_core);
550 if (core_def)
551 return core_def->name;
552 return "unknown";
553}
554
555bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
556
557bool ArchSpec::IsNVPTX() const { return GetTriple().isNVPTX(); }
558
559std::string ArchSpec::GetTargetABI() const {
560
561 std::string abi;
562
563 if (IsMIPS()) {
564 switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
566 abi = "n64";
567 return abi;
569 abi = "n32";
570 return abi;
572 abi = "o32";
573 return abi;
574 default:
575 return abi;
576 }
577 }
578 return abi;
579}
580
581void ArchSpec::SetFlags(const std::string &elf_abi) {
582
583 uint32_t flag = GetFlags();
584 if (IsMIPS()) {
585 if (elf_abi == "n64")
587 else if (elf_abi == "n32")
589 else if (elf_abi == "o32")
591 }
592 SetFlags(flag);
593}
594
595std::string ArchSpec::GetClangTargetCPU() const {
596 std::string cpu;
597 if (IsMIPS()) {
598 switch (m_core) {
601 cpu = "mips32";
602 break;
605 cpu = "mips32r2";
606 break;
609 cpu = "mips32r3";
610 break;
613 cpu = "mips32r5";
614 break;
617 cpu = "mips32r6";
618 break;
621 cpu = "mips64";
622 break;
625 cpu = "mips64r2";
626 break;
629 cpu = "mips64r3";
630 break;
633 cpu = "mips64r5";
634 break;
637 cpu = "mips64r6";
638 break;
639 default:
640 break;
641 }
642 }
643
644 if (GetTriple().isARM())
645 cpu = llvm::ARM::getARMCPUForArch(GetTriple(), "").str();
646 return cpu;
647}
648
650 const CoreDefinition *core_def = FindCoreDefinition(m_core);
651 if (core_def) {
652 const ArchDefinitionEntry *arch_def =
654 if (arch_def) {
655 return arch_def->cpu;
656 }
657 }
659}
660
662 const CoreDefinition *core_def = FindCoreDefinition(m_core);
663 if (core_def) {
664 const ArchDefinitionEntry *arch_def =
666 if (arch_def) {
667 return arch_def->sub;
668 }
669 }
671}
672
673uint32_t ArchSpec::GetDataByteSize() const { return 1; }
674
675uint32_t ArchSpec::GetCodeByteSize() const { return 1; }
676
677llvm::Triple::ArchType ArchSpec::GetMachine() const {
678 const CoreDefinition *core_def = FindCoreDefinition(m_core);
679 if (core_def)
680 return core_def->machine;
681
682 return llvm::Triple::UnknownArch;
683}
684
686 const CoreDefinition *core_def = FindCoreDefinition(m_core);
687 if (core_def) {
688 if (core_def->machine == llvm::Triple::mips64 ||
689 core_def->machine == llvm::Triple::mips64el) {
690 // For N32/O32 applications Address size is 4 bytes.
692 return 4;
693 }
694 return core_def->addr_byte_size;
695 }
696 return 0;
697}
698
700 const CoreDefinition *core_def = FindCoreDefinition(m_core);
701 if (core_def)
702 return core_def->default_byte_order;
703 return eByteOrderInvalid;
704}
705
707 switch (m_triple.getArch()) {
708 default:
709 return true;
710
711 case llvm::Triple::aarch64:
712 case llvm::Triple::aarch64_32:
713 case llvm::Triple::aarch64_be:
714 case llvm::Triple::arm:
715 case llvm::Triple::armeb:
716 case llvm::Triple::thumb:
717 case llvm::Triple::thumbeb:
718 return m_triple.isOSDarwin() || m_triple.isOSWindows();
719
720 case llvm::Triple::ppc:
721 case llvm::Triple::ppc64:
722 return m_triple.isOSDarwin();
723
724 case llvm::Triple::ppc64le:
725 case llvm::Triple::systemz:
726 case llvm::Triple::xcore:
727 case llvm::Triple::arc:
728 return false;
729 }
730}
731
737
738//===----------------------------------------------------------------------===//
739// Mutators.
740
741bool ArchSpec::SetTriple(const llvm::Triple &triple) {
742 m_triple = triple;
743 UpdateCore();
744 return IsValid();
745}
746
747bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
748 ArchSpec &arch) {
749 // Accept "12-10" or "12.10" as cpu type/subtype
750 if (triple_str.empty())
751 return false;
752
753 size_t pos = triple_str.find_first_of("-.");
754 if (pos == llvm::StringRef::npos)
755 return false;
756
757 llvm::StringRef cpu_str = triple_str.substr(0, pos);
758 llvm::StringRef remainder = triple_str.substr(pos + 1);
759 if (cpu_str.empty() || remainder.empty())
760 return false;
761
762 llvm::StringRef sub_str;
763 llvm::StringRef vendor;
764 llvm::StringRef os;
765 std::tie(sub_str, remainder) = remainder.split('-');
766 std::tie(vendor, os) = remainder.split('-');
767
768 uint32_t cpu = 0;
769 uint32_t sub = 0;
770 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
771 return false;
772
773 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
774 return false;
775 if (!vendor.empty() && !os.empty()) {
776 arch.GetTriple().setVendorName(vendor);
777 arch.GetTriple().setOSName(os);
778 }
779
780 return true;
781}
782
783bool ArchSpec::SetTriple(llvm::StringRef triple) {
784 if (triple.empty()) {
785 Clear();
786 return false;
787 }
788
789 if (ParseMachCPUDashSubtypeTriple(triple, *this))
790 return true;
791
792 SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
793 return IsValid();
794}
795
796bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
797 return !normalized_triple.getArchName().empty() &&
798 normalized_triple.getOSName().empty() &&
799 normalized_triple.getVendorName().empty() &&
800 normalized_triple.getEnvironmentName().empty();
801}
802
803void ArchSpec::MergeFrom(const ArchSpec &other) {
804 // ios-macabi always wins over macosx.
805 if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
806 GetTriple().getOS() == llvm::Triple::UnknownOS) &&
807 other.GetTriple().getOS() == llvm::Triple::IOS &&
808 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
809 (*this) = other;
810 return;
811 }
812
814 GetTriple().setVendor(other.GetTriple().getVendor());
816 GetTriple().setOS(other.GetTriple().getOS());
817 if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
818 GetTriple().setArch(other.GetTriple().getArch());
819
820 // MachO unknown64 isn't really invalid as the debugger can still obtain
821 // information from the binary, e.g. line tables. As such, we don't update
822 // the core here.
823 if (other.GetCore() != eCore_uknownMach64)
824 UpdateCore();
825 }
828 GetTriple().setEnvironment(other.GetTriple().getEnvironment());
829 }
830 // If this and other are both arm ArchSpecs and this ArchSpec is a generic
831 // "some kind of arm" spec but the other ArchSpec is a specific arm core,
832 // adopt the specific arm core.
833 if (GetTriple().getArch() == llvm::Triple::arm &&
834 other.GetTriple().getArch() == llvm::Triple::arm &&
837 m_core = other.GetCore();
838 CoreUpdated(false);
839 }
840 if (GetFlags() == 0) {
841 SetFlags(other.GetFlags());
842 }
843}
844
845bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
846 uint32_t sub, uint32_t os) {
848 bool update_triple = true;
849 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
850 if (arch_def) {
851 const ArchDefinitionEntry *arch_def_entry =
852 FindArchDefinitionEntry(arch_def, cpu, sub);
853 if (arch_def_entry) {
854 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
855 if (core_def) {
856 m_core = core_def->core;
857 update_triple = false;
858 // Always use the architecture name because it might be more
859 // descriptive than the architecture enum ("armv7" ->
860 // llvm::Triple::arm).
861 m_triple.setArchName(llvm::StringRef(core_def->name));
862 if (arch_type == eArchTypeMachO) {
863 m_triple.setVendor(llvm::Triple::Apple);
864
865 // Don't set the OS. It could be simulator, macosx, ios, watchos,
866 // tvos, bridgeos. We could get close with the cpu type - but we
867 // can't get it right all of the time. Better to leave this unset
868 // so other sections of code will set it when they have more
869 // information. NB: don't call m_triple.setOS
870 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
871 // the ArchSpec::TripleVendorWasSpecified() method says that any
872 // OSName setting means it was specified.
873 } else if (arch_type == eArchTypeELF) {
874 switch (os) {
875 case llvm::ELF::ELFOSABI_AIX:
876 m_triple.setOS(llvm::Triple::OSType::AIX);
877 break;
878 case llvm::ELF::ELFOSABI_FREEBSD:
879 m_triple.setOS(llvm::Triple::OSType::FreeBSD);
880 break;
881 case llvm::ELF::ELFOSABI_GNU:
882 m_triple.setOS(llvm::Triple::OSType::Linux);
883 break;
884 case llvm::ELF::ELFOSABI_NETBSD:
885 m_triple.setOS(llvm::Triple::OSType::NetBSD);
886 break;
887 case llvm::ELF::ELFOSABI_OPENBSD:
888 m_triple.setOS(llvm::Triple::OSType::OpenBSD);
889 break;
890 case llvm::ELF::ELFOSABI_SOLARIS:
891 m_triple.setOS(llvm::Triple::OSType::Solaris);
892 break;
893 case llvm::ELF::ELFOSABI_STANDALONE:
894 m_triple.setOS(llvm::Triple::OSType::UnknownOS);
895 break;
896 }
897 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
898 m_triple.setVendor(llvm::Triple::PC);
899 m_triple.setOS(llvm::Triple::Win32);
900 } else if (arch_type == eArchTypeXCOFF && os == llvm::Triple::AIX) {
901 m_triple.setVendor(llvm::Triple::IBM);
902 m_triple.setOS(llvm::Triple::AIX);
903 } else {
904 m_triple.setVendor(llvm::Triple::UnknownVendor);
905 m_triple.setOS(llvm::Triple::UnknownOS);
906 }
907 // Fall back onto setting the machine type if the arch by name
908 // failed...
909 if (m_triple.getArch() == llvm::Triple::UnknownArch)
910 m_triple.setArch(core_def->machine);
911 }
912 } else {
914 LLDB_LOGF(log,
915 "Unable to find a core definition for cpu 0x%" PRIx32
916 " sub %" PRId32,
917 cpu, sub);
918 }
919 }
920 CoreUpdated(update_triple);
921 return IsValid();
922}
923
925 const CoreDefinition *core_def = FindCoreDefinition(m_core);
926 if (core_def)
927 return core_def->min_opcode_byte_size;
928 return 0;
929}
930
932 const CoreDefinition *core_def = FindCoreDefinition(m_core);
933 if (core_def)
934 return core_def->max_opcode_byte_size;
935 return 0;
936}
937
938static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
939 llvm::Triple::EnvironmentType rhs) {
940 if (lhs == rhs)
941 return true;
942
943 // Apple simulators are a different platform than what they simulate.
944 // As the environments are different at this point, if one of them is a
945 // simulator, then they are different.
946 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
947 return false;
948
949 // If any of the environment is unknown then they are compatible
950 if (lhs == llvm::Triple::UnknownEnvironment ||
951 rhs == llvm::Triple::UnknownEnvironment)
952 return true;
953
954 // If one of the environment is Android and the other one is EABI then they
955 // are considered to be compatible. This is required as a workaround for
956 // shared libraries compiled for Android without the NOTE section indicating
957 // that they are using the Android ABI.
958 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
959 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
960 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
961 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
962 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
963 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
964 return true;
965
966 return false;
967}
968
969bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const {
970 if (GetByteOrder() != rhs.GetByteOrder() ||
971 !cores_match(GetCore(), rhs.GetCore(), true, match == ExactMatch))
972 return false;
973
974 const llvm::Triple &lhs_triple = GetTriple();
975 const llvm::Triple &rhs_triple = rhs.GetTriple();
976
977 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
978 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
979
980 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
981 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
982
983 bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows();
984
985 // On Windows, the vendor field doesn't have any practical effect, but
986 // it is often set to either "pc" or "w64".
987 if ((lhs_triple_vendor != rhs_triple_vendor) &&
988 (match == ExactMatch || !both_windows)) {
989 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
990 const bool lhs_vendor_specified = TripleVendorWasSpecified();
991 // Both architectures had the vendor specified, so if they aren't equal
992 // then we return false
993 if (rhs_vendor_specified && lhs_vendor_specified)
994 return false;
995
996 // Only fail if both vendor types are not unknown
997 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
998 rhs_triple_vendor != llvm::Triple::UnknownVendor)
999 return false;
1000 }
1001
1002 const llvm::Triple::EnvironmentType lhs_triple_env =
1003 lhs_triple.getEnvironment();
1004 const llvm::Triple::EnvironmentType rhs_triple_env =
1005 rhs_triple.getEnvironment();
1006
1007 if (match == CompatibleMatch) {
1008 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
1009 if ((lhs_triple_os == llvm::Triple::IOS &&
1010 lhs_triple_env == llvm::Triple::MacABI &&
1011 rhs_triple_os == llvm::Triple::MacOSX) ||
1012 (lhs_triple_os == llvm::Triple::MacOSX &&
1013 rhs_triple_os == llvm::Triple::IOS &&
1014 rhs_triple_env == llvm::Triple::MacABI))
1015 return true;
1016 // x86_64-apple-driverkit, x86_64-apple-macosx are compatible, no match.
1017 if ((lhs_triple_os == llvm::Triple::DriverKit &&
1018 rhs_triple_os == llvm::Triple::MacOSX) ||
1019 (lhs_triple_os == llvm::Triple::MacOSX &&
1020 rhs_triple_os == llvm::Triple::DriverKit))
1021 return true;
1022 }
1023
1024 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1025 if (lhs_triple_os == llvm::Triple::IOS &&
1026 rhs_triple_os == llvm::Triple::IOS &&
1027 (lhs_triple_env == llvm::Triple::MacABI ||
1028 rhs_triple_env == llvm::Triple::MacABI) &&
1029 lhs_triple_env != rhs_triple_env)
1030 return false;
1031
1032 if (lhs_triple_os != rhs_triple_os) {
1033 const bool lhs_os_specified = TripleOSWasSpecified();
1034 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1035 // If both OS types are specified and different, fail.
1036 if (lhs_os_specified && rhs_os_specified)
1037 return false;
1038
1039 // If the pair of os+env is both unspecified, match any other os+env combo.
1040 if (match == CompatibleMatch &&
1041 ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1042 (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1043 return true;
1044 }
1045
1046 if (match == CompatibleMatch && both_windows)
1047 return true; // The Windows environments (MSVC vs GNU) are compatible
1048
1049 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1050}
1051
1053 llvm::StringRef arch_name(m_triple.getArchName());
1054 const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1055 if (core_def) {
1056 m_core = core_def->core;
1057 // Set the byte order to the default byte order for an architecture. This
1058 // can be modified if needed for cases when cores handle both big and
1059 // little endian
1060 m_byte_order = core_def->default_byte_order;
1061 } else {
1062 Clear();
1063 }
1064}
1065
1066//===----------------------------------------------------------------------===//
1067// Helper methods.
1068
1069void ArchSpec::CoreUpdated(bool update_triple) {
1070 const CoreDefinition *core_def = FindCoreDefinition(m_core);
1071 if (core_def) {
1072 if (update_triple)
1073 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1074 m_byte_order = core_def->default_byte_order;
1075 } else {
1076 if (update_triple)
1077 m_triple = llvm::Triple();
1079 }
1080}
1081
1082//===----------------------------------------------------------------------===//
1083// Operators.
1084
1085static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1086 bool try_inverse, bool enforce_exact_match) {
1087 if (core1 == core2)
1088 return true;
1089
1090 switch (core1) {
1092 return true;
1093
1095 if (enforce_exact_match)
1096 break;
1097 [[fallthrough]];
1099 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1100 return true;
1101 if (core2 >= ArchSpec::kCore_thumb_first &&
1103 return true;
1104 if (core2 == ArchSpec::kCore_arm_any)
1105 return true;
1106 break;
1107
1109 if ((core2 >= ArchSpec::kCore_x86_32_first &&
1110 core2 <= ArchSpec::kCore_x86_32_last) ||
1111 (core2 == ArchSpec::kCore_x86_32_any))
1112 return true;
1113 break;
1114
1116 if ((core2 >= ArchSpec::kCore_x86_64_first &&
1117 core2 <= ArchSpec::kCore_x86_64_last) ||
1118 (core2 == ArchSpec::kCore_x86_64_any))
1119 return true;
1120 break;
1121
1123 if ((core2 >= ArchSpec::kCore_ppc_first &&
1124 core2 <= ArchSpec::kCore_ppc_last) ||
1125 (core2 == ArchSpec::kCore_ppc_any))
1126 return true;
1127 break;
1128
1130 if ((core2 >= ArchSpec::kCore_ppc64_first &&
1131 core2 <= ArchSpec::kCore_ppc64_last) ||
1132 (core2 == ArchSpec::kCore_ppc64_any))
1133 return true;
1134 break;
1135
1137 if ((core2 >= ArchSpec::kCore_hexagon_first &&
1138 core2 <= ArchSpec::kCore_hexagon_last) ||
1139 (core2 == ArchSpec::kCore_hexagon_any))
1140 return true;
1141 break;
1142
1143 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1144 // Cortex-M0 - ARMv6-M - armv6m
1145 // Cortex-M3 - ARMv7-M - armv7m
1146 // Cortex-M4 - ARMv7E-M - armv7em
1148 if (!enforce_exact_match) {
1149 if (core2 == ArchSpec::eCore_arm_generic)
1150 return true;
1151 if (core2 == ArchSpec::eCore_arm_armv7m)
1152 return true;
1153 if (core2 == ArchSpec::eCore_arm_armv6m)
1154 return true;
1155 if (core2 == ArchSpec::eCore_arm_armv7)
1156 return true;
1157 try_inverse = true;
1158 }
1159 break;
1160
1161 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1162 // Cortex-M0 - ARMv6-M - armv6m
1163 // Cortex-M3 - ARMv7-M - armv7m
1164 // Cortex-M4 - ARMv7E-M - armv7em
1166 if (!enforce_exact_match) {
1167 if (core2 == ArchSpec::eCore_arm_generic)
1168 return true;
1169 if (core2 == ArchSpec::eCore_arm_armv6m)
1170 return true;
1171 if (core2 == ArchSpec::eCore_arm_armv7)
1172 return true;
1173 if (core2 == ArchSpec::eCore_arm_armv7em)
1174 return true;
1175 try_inverse = true;
1176 }
1177 break;
1178
1179 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1180 // Cortex-M0 - ARMv6-M - armv6m
1181 // Cortex-M3 - ARMv7-M - armv7m
1182 // Cortex-M4 - ARMv7E-M - armv7em
1184 if (!enforce_exact_match) {
1185 if (core2 == ArchSpec::eCore_arm_generic)
1186 return true;
1187 if (core2 == ArchSpec::eCore_arm_armv7em)
1188 return true;
1189 if (core2 == ArchSpec::eCore_arm_armv7)
1190 return true;
1191 if (core2 == ArchSpec::eCore_arm_armv6m)
1192 return true;
1193 try_inverse = false;
1194 }
1195 break;
1196
1202 if (!enforce_exact_match) {
1203 if (core2 == ArchSpec::eCore_arm_generic)
1204 return true;
1205 if (core2 == ArchSpec::eCore_arm_armv7)
1206 return true;
1207 try_inverse = false;
1208 }
1209 break;
1210
1213 if (!enforce_exact_match) {
1214 try_inverse = false;
1215 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1216 return true;
1217 }
1218 break;
1219
1221 if (!enforce_exact_match) {
1222 if (core2 == ArchSpec::eCore_arm_arm64)
1223 return true;
1224 if (core2 == ArchSpec::eCore_arm_aarch64)
1225 return true;
1226 if (core2 == ArchSpec::eCore_arm_arm64e)
1227 return true;
1228 try_inverse = false;
1229 }
1230 break;
1231
1233 if (!enforce_exact_match) {
1234 if (core2 == ArchSpec::eCore_arm_arm64)
1235 return true;
1236 if (core2 == ArchSpec::eCore_arm_aarch64)
1237 return true;
1238 if (core2 == ArchSpec::eCore_arm_armv8)
1239 return true;
1240 try_inverse = false;
1241 }
1242 break;
1244 if (!enforce_exact_match) {
1245 if (core2 == ArchSpec::eCore_arm_arm64)
1246 return true;
1247 if (core2 == ArchSpec::eCore_arm_armv8)
1248 return true;
1249 if (core2 == ArchSpec::eCore_arm_arm64e)
1250 return true;
1251 try_inverse = false;
1252 }
1253 break;
1254
1256 if (!enforce_exact_match) {
1257 if (core2 == ArchSpec::eCore_arm_aarch64)
1258 return true;
1259 if (core2 == ArchSpec::eCore_arm_armv8)
1260 return true;
1261 if (core2 == ArchSpec::eCore_arm_arm64e)
1262 return true;
1263 try_inverse = false;
1264 }
1265 break;
1266
1268 if (!enforce_exact_match) {
1269 if (core2 == ArchSpec::eCore_arm_generic)
1270 return true;
1271 try_inverse = false;
1272 }
1273 break;
1274
1276 if (!enforce_exact_match) {
1277 if (core2 >= ArchSpec::kCore_mips32_first &&
1279 return true;
1280 try_inverse = false;
1281 }
1282 break;
1283
1285 if (!enforce_exact_match) {
1286 if (core2 >= ArchSpec::kCore_mips32el_first &&
1288 return true;
1289 try_inverse = true;
1290 }
1291 break;
1292
1294 if (!enforce_exact_match) {
1295 if (core2 >= ArchSpec::kCore_mips32_first &&
1297 return true;
1298 if (core2 >= ArchSpec::kCore_mips64_first &&
1300 return true;
1301 try_inverse = false;
1302 }
1303 break;
1304
1306 if (!enforce_exact_match) {
1307 if (core2 >= ArchSpec::kCore_mips32el_first &&
1309 return true;
1310 if (core2 >= ArchSpec::kCore_mips64el_first &&
1312 return true;
1313 try_inverse = false;
1314 }
1315 break;
1316
1320 if (!enforce_exact_match) {
1321 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1322 return true;
1323 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1324 return true;
1325 try_inverse = false;
1326 }
1327 break;
1328
1332 if (!enforce_exact_match) {
1333 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1334 return true;
1335 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1336 return true;
1337 try_inverse = false;
1338 }
1339 break;
1340
1344 if (!enforce_exact_match) {
1345 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1346 return true;
1347 }
1348 break;
1349
1353 if (!enforce_exact_match) {
1354 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1355 return true;
1356 }
1357 break;
1358
1360 if (!enforce_exact_match) {
1361 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1362 return true;
1363 }
1364 break;
1365
1367 if (!enforce_exact_match) {
1368 if (core2 == ArchSpec::eCore_mips32el ||
1370 return true;
1371 }
1372 break;
1373
1375 if (!enforce_exact_match) {
1376 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1377 return true;
1378 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1379 return true;
1380 }
1381 break;
1382
1384 if (!enforce_exact_match) {
1385 if (core2 == ArchSpec::eCore_mips32el ||
1387 return true;
1388 if (core2 == ArchSpec::eCore_mips64el ||
1390 return true;
1391 }
1392 break;
1393
1394 default:
1395 break;
1396 }
1397 if (try_inverse)
1398 return cores_match(core2, core1, false, enforce_exact_match);
1399 return false;
1400}
1401
1402bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1403 const ArchSpec::Core lhs_core = lhs.GetCore();
1404 const ArchSpec::Core rhs_core = rhs.GetCore();
1405 return lhs_core < rhs_core;
1406}
1407
1408bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1409 return lhs.GetCore() == rhs.GetCore();
1410}
1411
1412bool lldb_private::operator!=(const ArchSpec &lhs, const ArchSpec &rhs) {
1413 return !(lhs == rhs);
1414}
1415
1417 if (!TripleOSWasSpecified())
1418 return false;
1419
1421 return false;
1422
1423 const unsigned unspecified = 0;
1424 const llvm::Triple &triple = GetTriple();
1425 if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified)
1426 return false;
1427
1428 return true;
1429}
1430
1432 if (GetTriple().getArch() == llvm::Triple::arm ||
1433 GetTriple().getArch() == llvm::Triple::thumb) {
1434 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1435 //
1436 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1437 // execute thumb instructions. We map the cores to arch names like this:
1438 //
1439 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
1440 // Cortex-M7: armv7em
1441
1448 return true;
1449 }
1450 // Windows on ARM is always thumb.
1451 if (GetTriple().isOSWindows())
1452 return true;
1453 }
1454 return false;
1455}
1456
1457void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1458 const llvm::Triple &triple = GetTriple();
1459 llvm::StringRef arch_str = triple.getArchName();
1460 llvm::StringRef vendor_str = triple.getVendorName();
1461 llvm::StringRef os_str = triple.getOSName();
1462 llvm::StringRef environ_str = triple.getEnvironmentName();
1463
1464 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
1465 vendor_str.empty() ? "*" : vendor_str,
1466 os_str.empty() ? "*" : os_str);
1467
1468 if (!environ_str.empty())
1469 s << "-" << environ_str;
1470}
#define SUBTYPE_MASK
Definition ArchSpec.cpp:301
static const ArchDefinition g_elf_arch_def
Definition ArchSpec.cpp:418
static const CoreDefinition * FindCoreDefinition(llvm::StringRef name)
Definition ArchSpec.cpp:476
static const ArchDefinitionEntry * FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub)
Definition ArchSpec.cpp:492
static const ArchDefinitionEntry g_macho_arch_entries[]
Definition ArchSpec.cpp:304
static const ArchDefinitionEntry g_xcoff_arch_entries[]
Definition ArchSpec.cpp:445
static const ArchDefinitionEntry g_coff_arch_entries[]
Definition ArchSpec.cpp:425
static const ArchDefinitionEntry g_elf_arch_entries[]
Definition ArchSpec.cpp:383
static const ArchDefinition * FindArchDefinition(ArchitectureType arch_type)
Definition ArchSpec.cpp:467
static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
#define CPU_ANY
Definition ArchSpec.cpp:294
static const ArchDefinition g_xcoff_arch_def
Definition ArchSpec.cpp:451
static constexpr const CoreDefinition g_core_definitions[]
Definition ArchSpec.cpp:44
static const ArchDefinition * g_arch_definitions[]
Definition ArchSpec.cpp:460
static const ArchDefinition g_coff_arch_def
Definition ArchSpec.cpp:437
static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, llvm::Triple::EnvironmentType rhs)
Definition ArchSpec.cpp:938
static const ArchDefinition g_macho_arch_def
Definition ArchSpec.cpp:373
#define LLDB_LOGF(log,...)
Definition Log.h:376
An architecture specification class.
Definition ArchSpec.h:31
static void ListSupportedArchNames(StringList &list)
Definition ArchSpec.cpp:284
bool IsFullySpecifiedTriple() const
bool IsNVPTX() const
If NVPTX architecture return true.
Definition ArchSpec.cpp:557
static void AutoComplete(CompletionRequest &request)
Definition ArchSpec.cpp:289
uint32_t GetAddressByteSize() const
Returns the size in bytes of an address of the current architecture.
Definition ArchSpec.cpp:685
uint32_t GetCodeByteSize() const
Architecture code byte width accessor.
Definition ArchSpec.cpp:675
bool IsValid() const
Tests if this ArchSpec is valid.
Definition ArchSpec.h:366
void Clear()
Clears the object state.
Definition ArchSpec.cpp:538
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition ArchSpec.h:468
void SetFlags(uint32_t flags)
Definition ArchSpec.h:541
bool IsAlwaysThumbInstructions() const
Detect whether this architecture uses thumb code exclusively.
bool TripleEnvironmentWasSpecified() const
Definition ArchSpec.h:377
bool IsMatch(const ArchSpec &rhs, MatchType match) const
Compare this ArchSpec to another ArchSpec.
Definition ArchSpec.cpp:969
bool SetTriple(const llvm::Triple &triple)
Architecture triple setter.
Definition ArchSpec.cpp:741
llvm::Triple m_triple
Definition ArchSpec.h:548
lldb::ByteOrder GetDefaultEndian() const
Returns the default endianness of the architecture.
Definition ArchSpec.cpp:699
lldb::ByteOrder m_byte_order
Definition ArchSpec.h:550
~ArchSpec()
Destructor.
bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os=0)
Change the architecture object type, CPU type and OS type.
Definition ArchSpec.cpp:845
void MergeFrom(const ArchSpec &other)
Merges fields from another ArchSpec into this ArchSpec.
Definition ArchSpec.cpp:803
void DumpTriple(llvm::raw_ostream &s) const
uint32_t GetMachOCPUSubType() const
Definition ArchSpec.cpp:661
void CoreUpdated(bool update_triple)
bool IsMIPS() const
if MIPS architecture return true.
Definition ArchSpec.cpp:555
uint32_t GetDataByteSize() const
Architecture data byte width accessor.
Definition ArchSpec.cpp:673
bool IsCompatibleMatch(const ArchSpec &rhs) const
Shorthand for IsMatch(rhs, CompatibleMatch).
Definition ArchSpec.h:520
bool CharIsSignedByDefault() const
Returns true if 'char' is a signed type by default in the architecture false otherwise.
Definition ArchSpec.cpp:706
ArchSpec()
Default constructor.
uint32_t GetMachOCPUType() const
Definition ArchSpec.cpp:649
std::string GetTargetABI() const
Return a string representing target application ABI.
Definition ArchSpec.cpp:559
uint32_t GetMinimumOpcodeByteSize() const
Definition ArchSpec.cpp:924
uint32_t GetFlags() const
Definition ArchSpec.h:539
lldb::ByteOrder GetByteOrder() const
Returns the byte order for the architecture specification.
Definition ArchSpec.cpp:732
llvm::Triple::ArchType GetMachine() const
Returns a machine family for the current architecture.
Definition ArchSpec.cpp:677
std::string GetClangTargetCPU() const
Returns a string representing current architecture as a target CPU for tools like compiler,...
Definition ArchSpec.cpp:595
uint32_t GetMaximumOpcodeByteSize() const
Definition ArchSpec.cpp:931
bool TripleVendorWasSpecified() const
Definition ArchSpec.h:371
Core GetCore() const
Definition ArchSpec.h:447
bool TripleOSWasSpecified() const
Definition ArchSpec.h:375
static bool ContainsOnlyArch(const llvm::Triple &normalized_triple)
Returns true if the OS, vendor and environment fields of the triple are unset.
Definition ArchSpec.cpp:796
const char * GetArchitectureName() const
Returns a static string representing the current architecture.
Definition ArchSpec.cpp:548
"lldb/Utility/ArgCompletionRequest.h"
void TryCompleteCurrentArg(llvm::StringRef completion, llvm::StringRef description="")
Adds a possible completion string if the completion would complete the current argument.
void AppendString(const std::string &s)
#define LLDB_INVALID_CPUTYPE
#define UINT32_MAX
A class that represents a running process on the host machine.
Log * GetLog(Cat mask)
Retrieve the Log object for the channel associated with the given log enum.
Definition Log.h:332
bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch)
Definition ArchSpec.cpp:747
bool operator!=(const Address &lhs, const Address &rhs)
Definition Address.cpp:1017
TableValidator< 0 > validator
bool operator==(const Address &lhs, const Address &rhs)
Definition Address.cpp:1011
bool operator<(const Address &lhs, const Address &rhs)
Definition Address.cpp:980
ByteOrder
Byte ordering definitions.
ArchSpec::Core core
Definition ArchSpec.cpp:270
ArchitectureType type
Definition ArchSpec.cpp:278
const ArchDefinitionEntry * entries
Definition ArchSpec.cpp:280
size_t num_entries
Definition ArchSpec.cpp:279
const char * name
Definition ArchSpec.cpp:281
llvm::Triple::ArchType machine
Definition ArchSpec.cpp:36
const char *const name
Definition ArchSpec.cpp:38