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ArchSpec.cpp
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1 //===-- ArchSpec.cpp ------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "lldb/Utility/LLDBLog.h"
11 
12 #include "lldb/Utility/Log.h"
14 #include "lldb/lldb-defines.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/BinaryFormat/COFF.h"
17 #include "llvm/BinaryFormat/ELF.h"
18 #include "llvm/BinaryFormat/MachO.h"
19 #include "llvm/Support/Compiler.h"
20 
21 using namespace lldb;
22 using namespace lldb_private;
23 
24 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
25  bool try_inverse, bool enforce_exact_match);
26 
27 namespace lldb_private {
28 
34  llvm::Triple::ArchType machine;
36  const char *const name;
37 };
38 
39 } // namespace lldb_private
40 
41 // This core information can be looked using the ArchSpec::Core as the index
43  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
44  "arm"},
45  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
46  "armv4"},
47  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
48  "armv4t"},
49  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
50  "armv5"},
51  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
52  "armv5e"},
53  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
54  "armv5t"},
55  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
56  "armv6"},
57  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
58  "armv6m"},
59  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
60  "armv7"},
61  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
62  "armv7l"},
63  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
64  "armv7f"},
65  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
66  "armv7s"},
67  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
68  "armv7k"},
69  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
70  "armv7m"},
71  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
72  "armv7em"},
73  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
74  "xscale"},
75  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
76  "thumb"},
77  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
78  "thumbv4t"},
79  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
80  "thumbv5"},
81  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
82  "thumbv5e"},
83  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
84  "thumbv6"},
85  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
86  "thumbv6m"},
87  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
88  "thumbv7"},
89  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
90  "thumbv7f"},
91  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
92  "thumbv7s"},
93  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
94  "thumbv7k"},
95  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
96  "thumbv7m"},
97  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
98  "thumbv7em"},
99  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
100  ArchSpec::eCore_arm_arm64, "arm64"},
101  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
102  ArchSpec::eCore_arm_armv8, "armv8"},
103  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
104  "armv8l"},
105  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
106  ArchSpec::eCore_arm_arm64e, "arm64e"},
107  {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
108  ArchSpec::eCore_arm_arm64_32, "arm64_32"},
109  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
110  ArchSpec::eCore_arm_aarch64, "aarch64"},
111 
112  // mips32, mips32r2, mips32r3, mips32r5, mips32r6
113  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
114  "mips"},
115  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
116  "mipsr2"},
117  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
118  "mipsr3"},
119  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
120  "mipsr5"},
121  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
122  "mipsr6"},
123  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
124  "mipsel"},
125  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
126  ArchSpec::eCore_mips32r2el, "mipsr2el"},
127  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
128  ArchSpec::eCore_mips32r3el, "mipsr3el"},
129  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
130  ArchSpec::eCore_mips32r5el, "mipsr5el"},
131  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
132  ArchSpec::eCore_mips32r6el, "mipsr6el"},
133 
134  // mips64, mips64r2, mips64r3, mips64r5, mips64r6
135  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
136  "mips64"},
137  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
138  "mips64r2"},
139  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
140  "mips64r3"},
141  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
142  "mips64r5"},
143  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
144  "mips64r6"},
145  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
146  ArchSpec::eCore_mips64el, "mips64el"},
147  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
148  ArchSpec::eCore_mips64r2el, "mips64r2el"},
149  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
150  ArchSpec::eCore_mips64r3el, "mips64r3el"},
151  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
152  ArchSpec::eCore_mips64r5el, "mips64r5el"},
153  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
154  ArchSpec::eCore_mips64r6el, "mips64r6el"},
155 
156  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
157  "powerpc"},
158  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
159  "ppc601"},
160  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
161  "ppc602"},
162  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
163  "ppc603"},
164  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
165  "ppc603e"},
166  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
167  "ppc603ev"},
168  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
169  "ppc604"},
170  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
171  "ppc604e"},
172  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
173  "ppc620"},
174  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
175  "ppc750"},
176  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
177  "ppc7400"},
178  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
179  "ppc7450"},
180  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
181  "ppc970"},
182 
183  {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
184  ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
185  {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
186  "powerpc64"},
187  {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
188  ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
189 
190  {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
191  ArchSpec::eCore_s390x_generic, "s390x"},
192 
193  {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
194  ArchSpec::eCore_sparc_generic, "sparc"},
195  {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
196  ArchSpec::eCore_sparc9_generic, "sparcv9"},
197 
198  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
199  "i386"},
200  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
201  "i486"},
202  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
203  ArchSpec::eCore_x86_32_i486sx, "i486sx"},
204  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
205  "i686"},
206 
207  {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
208  ArchSpec::eCore_x86_64_x86_64, "x86_64"},
209  {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
210  ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
211  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
212  ArchSpec::eCore_hexagon_generic, "hexagon"},
213  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
214  ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
215  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
216  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
217 
218  {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
219  "riscv32"},
220  {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
221  "riscv64"},
222 
223  {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
224  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
225  {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
226  ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
227  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
228 
229  {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
230 
231  {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
232  "wasm32"},
233 };
234 
235 // Ensure that we have an entry in the g_core_definitions for each core. If you
236 // comment out an entry above, you will need to comment out the corresponding
237 // ArchSpec::Core enumeration.
238 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
239  ArchSpec::kNumCores,
240  "make sure we have one core definition for each core");
241 
248 };
249 
252  size_t num_entries;
254  const char *name;
255 };
256 
257 void ArchSpec::ListSupportedArchNames(StringList &list) {
258  for (const auto &def : g_core_definitions)
259  list.AppendString(def.name);
260 }
261 
262 void ArchSpec::AutoComplete(CompletionRequest &request) {
263  for (const auto &def : g_core_definitions)
264  request.TryCompleteCurrentArg(def.name);
265 }
266 
267 #define CPU_ANY (UINT32_MAX)
268 
269 //===----------------------------------------------------------------------===//
270 // A table that gets searched linearly for matches. This table is used to
271 // convert cpu type and subtypes to architecture names, and to convert
272 // architecture names to cpu types and subtypes. The ordering is important and
273 // allows the precedence to be set when the table is built.
274 #define SUBTYPE_MASK 0x00FFFFFFu
275 
276 // clang-format off
278  {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
279  {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
280  {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
281  {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
282  {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
283  {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
284  {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
285  {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
286  {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
287  {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
288  {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
289  {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
290  {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
291  {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
292  {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
293  {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
294  {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
295  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
296  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
297  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK},
298  {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK},
299  {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK},
300  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
301  {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
302  {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
303  {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
304  {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
305  {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
306  {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
307  {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
308  {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
309  {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
310  {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
311  {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
312  {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
313  {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
314  {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
315  {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
316  {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
317  {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
318  {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
319  {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
320  {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
321  {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
322  {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
323  {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
324  {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
325  {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
326  {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
327  {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
328  {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
329  {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK},
330  {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
331  {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
332  {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
333  {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
334  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
335  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
336  {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
337  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
338  // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
339  {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
340  {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
341 // clang-format on
342 
344  std::size(g_macho_arch_entries),
345  g_macho_arch_entries, "mach-o"};
346 
347 //===----------------------------------------------------------------------===//
348 // A table that gets searched linearly for matches. This table is used to
349 // convert cpu type and subtypes to architecture names, and to convert
350 // architecture names to cpu types and subtypes. The ordering is important and
351 // allows the precedence to be set when the table is built.
353  {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
354  0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
355  {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
356  0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
357  {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
358  0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
359  {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
360  0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
361  {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
362  ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
363  {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
364  ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
365  {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
366  0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
367  {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
368  0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
369  {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
370  0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
371  {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
372  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
373  {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
374  0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
375  {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
376  0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
377  {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
378  ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
379  {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
380  ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
381  {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
382  ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
383  {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
384  ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
385  {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
386  ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
387  {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
388  0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
389  {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
390  ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
391  {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
392  ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
393  {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
394  ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
395  {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
396  ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
397  {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
398  ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
399  {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
400  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
401  {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
402  0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
403  {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
404  0xFFFFFFFFu}, // AVR
405  {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
406  ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
407  {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
408  ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
409 };
410 
412  eArchTypeELF,
413  std::size(g_elf_arch_entries),
415  "elf",
416 };
417 
419  {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
420  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
421  {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
422  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
423  {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
424  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
425  {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
426  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
427  {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
428  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
429  {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
430  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
431  {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
432  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
433  {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
434  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
435 };
436 
439  std::size(g_coff_arch_entries),
441  "pe-coff",
442 };
443 
444 //===----------------------------------------------------------------------===//
445 // Table of all ArchDefinitions
448 
449 //===----------------------------------------------------------------------===//
450 // Static helper functions.
451 
452 // Get the architecture definition for a given object type.
454  for (const ArchDefinition *def : g_arch_definitions) {
455  if (def->type == arch_type)
456  return def;
457  }
458  return nullptr;
459 }
460 
461 // Get an architecture definition by name.
462 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
463  for (const auto &def : g_core_definitions) {
464  if (name.equals_insensitive(def.name))
465  return &def;
466  }
467  return nullptr;
468 }
469 
471  if (core < std::size(g_core_definitions))
472  return &g_core_definitions[core];
473  return nullptr;
474 }
475 
476 // Get a definition entry by cpu type and subtype.
477 static const ArchDefinitionEntry *
479  if (def == nullptr)
480  return nullptr;
481 
482  const ArchDefinitionEntry *entries = def->entries;
483  for (size_t i = 0; i < def->num_entries; ++i) {
484  if (entries[i].cpu == (cpu & entries[i].cpu_mask))
485  if (entries[i].sub == (sub & entries[i].sub_mask))
486  return &entries[i];
487  }
488  return nullptr;
489 }
490 
491 static const ArchDefinitionEntry *
493  if (def == nullptr)
494  return nullptr;
495 
496  const ArchDefinitionEntry *entries = def->entries;
497  for (size_t i = 0; i < def->num_entries; ++i) {
498  if (entries[i].core == core)
499  return &entries[i];
500  }
501  return nullptr;
502 }
503 
504 //===----------------------------------------------------------------------===//
505 // Constructors and destructors.
506 
507 ArchSpec::ArchSpec() = default;
508 
509 ArchSpec::ArchSpec(const char *triple_cstr) {
510  if (triple_cstr)
511  SetTriple(triple_cstr);
512 }
513 
514 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
515 
516 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
517 
518 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
519  SetArchitecture(arch_type, cpu, subtype);
520 }
521 
522 ArchSpec::~ArchSpec() = default;
523 
524 void ArchSpec::Clear() {
525  m_triple = llvm::Triple();
526  m_core = kCore_invalid;
527  m_byte_order = eByteOrderInvalid;
528  m_distribution_id.Clear();
529  m_flags = 0;
530 }
531 
532 //===----------------------------------------------------------------------===//
533 // Predicates.
534 
535 const char *ArchSpec::GetArchitectureName() const {
536  const CoreDefinition *core_def = FindCoreDefinition(m_core);
537  if (core_def)
538  return core_def->name;
539  return "unknown";
540 }
541 
542 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
543 
544 std::string ArchSpec::GetTargetABI() const {
545 
546  std::string abi;
547 
548  if (IsMIPS()) {
549  switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
550  case ArchSpec::eMIPSABI_N64:
551  abi = "n64";
552  return abi;
553  case ArchSpec::eMIPSABI_N32:
554  abi = "n32";
555  return abi;
556  case ArchSpec::eMIPSABI_O32:
557  abi = "o32";
558  return abi;
559  default:
560  return abi;
561  }
562  }
563  return abi;
564 }
565 
566 void ArchSpec::SetFlags(const std::string &elf_abi) {
567 
568  uint32_t flag = GetFlags();
569  if (IsMIPS()) {
570  if (elf_abi == "n64")
571  flag |= ArchSpec::eMIPSABI_N64;
572  else if (elf_abi == "n32")
573  flag |= ArchSpec::eMIPSABI_N32;
574  else if (elf_abi == "o32")
575  flag |= ArchSpec::eMIPSABI_O32;
576  }
577  SetFlags(flag);
578 }
579 
580 std::string ArchSpec::GetClangTargetCPU() const {
581  std::string cpu;
582  if (IsMIPS()) {
583  switch (m_core) {
584  case ArchSpec::eCore_mips32:
585  case ArchSpec::eCore_mips32el:
586  cpu = "mips32";
587  break;
588  case ArchSpec::eCore_mips32r2:
589  case ArchSpec::eCore_mips32r2el:
590  cpu = "mips32r2";
591  break;
592  case ArchSpec::eCore_mips32r3:
593  case ArchSpec::eCore_mips32r3el:
594  cpu = "mips32r3";
595  break;
596  case ArchSpec::eCore_mips32r5:
597  case ArchSpec::eCore_mips32r5el:
598  cpu = "mips32r5";
599  break;
600  case ArchSpec::eCore_mips32r6:
601  case ArchSpec::eCore_mips32r6el:
602  cpu = "mips32r6";
603  break;
604  case ArchSpec::eCore_mips64:
605  case ArchSpec::eCore_mips64el:
606  cpu = "mips64";
607  break;
608  case ArchSpec::eCore_mips64r2:
609  case ArchSpec::eCore_mips64r2el:
610  cpu = "mips64r2";
611  break;
612  case ArchSpec::eCore_mips64r3:
613  case ArchSpec::eCore_mips64r3el:
614  cpu = "mips64r3";
615  break;
616  case ArchSpec::eCore_mips64r5:
617  case ArchSpec::eCore_mips64r5el:
618  cpu = "mips64r5";
619  break;
620  case ArchSpec::eCore_mips64r6:
621  case ArchSpec::eCore_mips64r6el:
622  cpu = "mips64r6";
623  break;
624  default:
625  break;
626  }
627  }
628 
629  if (GetTriple().isARM())
630  cpu = GetTriple().getARMCPUForArch("").str();
631  return cpu;
632 }
633 
634 uint32_t ArchSpec::GetMachOCPUType() const {
635  const CoreDefinition *core_def = FindCoreDefinition(m_core);
636  if (core_def) {
637  const ArchDefinitionEntry *arch_def =
639  if (arch_def) {
640  return arch_def->cpu;
641  }
642  }
643  return LLDB_INVALID_CPUTYPE;
644 }
645 
646 uint32_t ArchSpec::GetMachOCPUSubType() const {
647  const CoreDefinition *core_def = FindCoreDefinition(m_core);
648  if (core_def) {
649  const ArchDefinitionEntry *arch_def =
651  if (arch_def) {
652  return arch_def->sub;
653  }
654  }
655  return LLDB_INVALID_CPUTYPE;
656 }
657 
658 uint32_t ArchSpec::GetDataByteSize() const {
659  return 1;
660 }
661 
662 uint32_t ArchSpec::GetCodeByteSize() const {
663  return 1;
664 }
665 
666 llvm::Triple::ArchType ArchSpec::GetMachine() const {
667  const CoreDefinition *core_def = FindCoreDefinition(m_core);
668  if (core_def)
669  return core_def->machine;
670 
671  return llvm::Triple::UnknownArch;
672 }
673 
674 ConstString ArchSpec::GetDistributionId() const {
675  return m_distribution_id;
676 }
677 
678 void ArchSpec::SetDistributionId(const char *distribution_id) {
679  m_distribution_id.SetCString(distribution_id);
680 }
681 
682 uint32_t ArchSpec::GetAddressByteSize() const {
683  const CoreDefinition *core_def = FindCoreDefinition(m_core);
684  if (core_def) {
685  if (core_def->machine == llvm::Triple::mips64 ||
686  core_def->machine == llvm::Triple::mips64el) {
687  // For N32/O32 applications Address size is 4 bytes.
688  if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
689  return 4;
690  }
691  return core_def->addr_byte_size;
692  }
693  return 0;
694 }
695 
696 ByteOrder ArchSpec::GetDefaultEndian() const {
697  const CoreDefinition *core_def = FindCoreDefinition(m_core);
698  if (core_def)
699  return core_def->default_byte_order;
700  return eByteOrderInvalid;
701 }
702 
703 bool ArchSpec::CharIsSignedByDefault() const {
704  switch (m_triple.getArch()) {
705  default:
706  return true;
707 
708  case llvm::Triple::aarch64:
709  case llvm::Triple::aarch64_32:
710  case llvm::Triple::aarch64_be:
711  case llvm::Triple::arm:
712  case llvm::Triple::armeb:
713  case llvm::Triple::thumb:
714  case llvm::Triple::thumbeb:
715  return m_triple.isOSDarwin() || m_triple.isOSWindows();
716 
717  case llvm::Triple::ppc:
718  case llvm::Triple::ppc64:
719  return m_triple.isOSDarwin();
720 
721  case llvm::Triple::ppc64le:
722  case llvm::Triple::systemz:
723  case llvm::Triple::xcore:
724  case llvm::Triple::arc:
725  return false;
726  }
727 }
728 
729 lldb::ByteOrder ArchSpec::GetByteOrder() const {
730  if (m_byte_order == eByteOrderInvalid)
731  return GetDefaultEndian();
732  return m_byte_order;
733 }
734 
735 //===----------------------------------------------------------------------===//
736 // Mutators.
737 
738 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
739  m_triple = triple;
740  UpdateCore();
741  return IsValid();
742 }
743 
744 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
745  ArchSpec &arch) {
746  // Accept "12-10" or "12.10" as cpu type/subtype
747  if (triple_str.empty())
748  return false;
749 
750  size_t pos = triple_str.find_first_of("-.");
751  if (pos == llvm::StringRef::npos)
752  return false;
753 
754  llvm::StringRef cpu_str = triple_str.substr(0, pos);
755  llvm::StringRef remainder = triple_str.substr(pos + 1);
756  if (cpu_str.empty() || remainder.empty())
757  return false;
758 
759  llvm::StringRef sub_str;
760  llvm::StringRef vendor;
761  llvm::StringRef os;
762  std::tie(sub_str, remainder) = remainder.split('-');
763  std::tie(vendor, os) = remainder.split('-');
764 
765  uint32_t cpu = 0;
766  uint32_t sub = 0;
767  if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
768  return false;
769 
770  if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
771  return false;
772  if (!vendor.empty() && !os.empty()) {
773  arch.GetTriple().setVendorName(vendor);
774  arch.GetTriple().setOSName(os);
775  }
776 
777  return true;
778 }
779 
780 bool ArchSpec::SetTriple(llvm::StringRef triple) {
781  if (triple.empty()) {
782  Clear();
783  return false;
784  }
785 
786  if (ParseMachCPUDashSubtypeTriple(triple, *this))
787  return true;
788 
789  SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
790  return IsValid();
791 }
792 
793 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
794  return !normalized_triple.getArchName().empty() &&
795  normalized_triple.getOSName().empty() &&
796  normalized_triple.getVendorName().empty() &&
797  normalized_triple.getEnvironmentName().empty();
798 }
799 
800 void ArchSpec::MergeFrom(const ArchSpec &other) {
801  // ios-macabi always wins over macosx.
802  if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
803  GetTriple().getOS() == llvm::Triple::UnknownOS) &&
804  other.GetTriple().getOS() == llvm::Triple::IOS &&
805  other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
806  (*this) = other;
807  return;
808  }
809 
810  if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
811  GetTriple().setVendor(other.GetTriple().getVendor());
812  if (!TripleOSWasSpecified() && other.TripleOSWasSpecified())
813  GetTriple().setOS(other.GetTriple().getOS());
814  if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
815  GetTriple().setArch(other.GetTriple().getArch());
816 
817  // MachO unknown64 isn't really invalid as the debugger can still obtain
818  // information from the binary, e.g. line tables. As such, we don't update
819  // the core here.
820  if (other.GetCore() != eCore_uknownMach64)
821  UpdateCore();
822  }
823  if (!TripleEnvironmentWasSpecified() &&
825  GetTriple().setEnvironment(other.GetTriple().getEnvironment());
826  }
827  // If this and other are both arm ArchSpecs and this ArchSpec is a generic
828  // "some kind of arm" spec but the other ArchSpec is a specific arm core,
829  // adopt the specific arm core.
830  if (GetTriple().getArch() == llvm::Triple::arm &&
831  other.GetTriple().getArch() == llvm::Triple::arm &&
832  IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
833  other.GetCore() != ArchSpec::eCore_arm_generic) {
834  m_core = other.GetCore();
835  CoreUpdated(false);
836  }
837  if (GetFlags() == 0) {
838  SetFlags(other.GetFlags());
839  }
840 }
841 
842 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
843  uint32_t sub, uint32_t os) {
844  m_core = kCore_invalid;
845  bool update_triple = true;
846  const ArchDefinition *arch_def = FindArchDefinition(arch_type);
847  if (arch_def) {
848  const ArchDefinitionEntry *arch_def_entry =
849  FindArchDefinitionEntry(arch_def, cpu, sub);
850  if (arch_def_entry) {
851  const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
852  if (core_def) {
853  m_core = core_def->core;
854  update_triple = false;
855  // Always use the architecture name because it might be more
856  // descriptive than the architecture enum ("armv7" ->
857  // llvm::Triple::arm).
858  m_triple.setArchName(llvm::StringRef(core_def->name));
859  if (arch_type == eArchTypeMachO) {
860  m_triple.setVendor(llvm::Triple::Apple);
861 
862  // Don't set the OS. It could be simulator, macosx, ios, watchos,
863  // tvos, bridgeos. We could get close with the cpu type - but we
864  // can't get it right all of the time. Better to leave this unset
865  // so other sections of code will set it when they have more
866  // information. NB: don't call m_triple.setOS
867  // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
868  // the ArchSpec::TripleVendorWasSpecified() method says that any
869  // OSName setting means it was specified.
870  } else if (arch_type == eArchTypeELF) {
871  switch (os) {
872  case llvm::ELF::ELFOSABI_AIX:
873  m_triple.setOS(llvm::Triple::OSType::AIX);
874  break;
875  case llvm::ELF::ELFOSABI_FREEBSD:
876  m_triple.setOS(llvm::Triple::OSType::FreeBSD);
877  break;
878  case llvm::ELF::ELFOSABI_GNU:
879  m_triple.setOS(llvm::Triple::OSType::Linux);
880  break;
881  case llvm::ELF::ELFOSABI_NETBSD:
882  m_triple.setOS(llvm::Triple::OSType::NetBSD);
883  break;
884  case llvm::ELF::ELFOSABI_OPENBSD:
885  m_triple.setOS(llvm::Triple::OSType::OpenBSD);
886  break;
887  case llvm::ELF::ELFOSABI_SOLARIS:
888  m_triple.setOS(llvm::Triple::OSType::Solaris);
889  break;
890  }
891  } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
892  m_triple.setVendor(llvm::Triple::PC);
893  m_triple.setOS(llvm::Triple::Win32);
894  } else {
895  m_triple.setVendor(llvm::Triple::UnknownVendor);
896  m_triple.setOS(llvm::Triple::UnknownOS);
897  }
898  // Fall back onto setting the machine type if the arch by name
899  // failed...
900  if (m_triple.getArch() == llvm::Triple::UnknownArch)
901  m_triple.setArch(core_def->machine);
902  }
903  } else {
904  Log *log(GetLog(LLDBLog::Target | LLDBLog::Process | LLDBLog::Platform));
905  LLDB_LOGF(log,
906  "Unable to find a core definition for cpu 0x%" PRIx32
907  " sub %" PRId32,
908  cpu, sub);
909  }
910  }
911  CoreUpdated(update_triple);
912  return IsValid();
913 }
914 
915 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
916  const CoreDefinition *core_def = FindCoreDefinition(m_core);
917  if (core_def)
918  return core_def->min_opcode_byte_size;
919  return 0;
920 }
921 
922 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
923  const CoreDefinition *core_def = FindCoreDefinition(m_core);
924  if (core_def)
925  return core_def->max_opcode_byte_size;
926  return 0;
927 }
928 
929 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
930  llvm::Triple::EnvironmentType rhs) {
931  if (lhs == rhs)
932  return true;
933 
934  // Apple simulators are a different platform than what they simulate.
935  // As the environments are different at this point, if one of them is a
936  // simulator, then they are different.
937  if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
938  return false;
939 
940  // If any of the environment is unknown then they are compatible
941  if (lhs == llvm::Triple::UnknownEnvironment ||
942  rhs == llvm::Triple::UnknownEnvironment)
943  return true;
944 
945  // If one of the environment is Android and the other one is EABI then they
946  // are considered to be compatible. This is required as a workaround for
947  // shared libraries compiled for Android without the NOTE section indicating
948  // that they are using the Android ABI.
949  if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
950  (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
951  (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
952  (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
953  (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
954  (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
955  return true;
956 
957  return false;
958 }
959 
960 bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const {
961  // explicitly ignoring m_distribution_id in this method.
962 
963  if (GetByteOrder() != rhs.GetByteOrder() ||
964  !cores_match(GetCore(), rhs.GetCore(), true, match == ExactMatch))
965  return false;
966 
967  const llvm::Triple &lhs_triple = GetTriple();
968  const llvm::Triple &rhs_triple = rhs.GetTriple();
969 
970  const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
971  const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
972 
973  const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
974  const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
975 
976  bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows();
977 
978  // On Windows, the vendor field doesn't have any practical effect, but
979  // it is often set to either "pc" or "w64".
980  if ((lhs_triple_vendor != rhs_triple_vendor) &&
981  (match == ExactMatch || !both_windows)) {
982  const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
983  const bool lhs_vendor_specified = TripleVendorWasSpecified();
984  // Both architectures had the vendor specified, so if they aren't equal
985  // then we return false
986  if (rhs_vendor_specified && lhs_vendor_specified)
987  return false;
988 
989  // Only fail if both vendor types are not unknown
990  if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
991  rhs_triple_vendor != llvm::Triple::UnknownVendor)
992  return false;
993  }
994 
995  const llvm::Triple::EnvironmentType lhs_triple_env =
996  lhs_triple.getEnvironment();
997  const llvm::Triple::EnvironmentType rhs_triple_env =
998  rhs_triple.getEnvironment();
999 
1000  if (match == CompatibleMatch) {
1001  // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
1002  if ((lhs_triple_os == llvm::Triple::IOS &&
1003  lhs_triple_env == llvm::Triple::MacABI &&
1004  rhs_triple_os == llvm::Triple::MacOSX) ||
1005  (lhs_triple_os == llvm::Triple::MacOSX &&
1006  rhs_triple_os == llvm::Triple::IOS &&
1007  rhs_triple_env == llvm::Triple::MacABI))
1008  return true;
1009  }
1010 
1011  // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1012  if (lhs_triple_os == llvm::Triple::IOS &&
1013  rhs_triple_os == llvm::Triple::IOS &&
1014  (lhs_triple_env == llvm::Triple::MacABI ||
1015  rhs_triple_env == llvm::Triple::MacABI) &&
1016  lhs_triple_env != rhs_triple_env)
1017  return false;
1018 
1019  if (lhs_triple_os != rhs_triple_os) {
1020  const bool lhs_os_specified = TripleOSWasSpecified();
1021  const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1022  // If both OS types are specified and different, fail.
1023  if (lhs_os_specified && rhs_os_specified)
1024  return false;
1025 
1026  // If the pair of os+env is both unspecified, match any other os+env combo.
1027  if (match == CompatibleMatch &&
1028  ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1029  (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1030  return true;
1031  }
1032 
1033  if (match == CompatibleMatch && both_windows)
1034  return true; // The Windows environments (MSVC vs GNU) are compatible
1035 
1036  return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1037 }
1038 
1039 void ArchSpec::UpdateCore() {
1040  llvm::StringRef arch_name(m_triple.getArchName());
1041  const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1042  if (core_def) {
1043  m_core = core_def->core;
1044  // Set the byte order to the default byte order for an architecture. This
1045  // can be modified if needed for cases when cores handle both big and
1046  // little endian
1047  m_byte_order = core_def->default_byte_order;
1048  } else {
1049  Clear();
1050  }
1051 }
1052 
1053 //===----------------------------------------------------------------------===//
1054 // Helper methods.
1055 
1056 void ArchSpec::CoreUpdated(bool update_triple) {
1057  const CoreDefinition *core_def = FindCoreDefinition(m_core);
1058  if (core_def) {
1059  if (update_triple)
1060  m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1061  m_byte_order = core_def->default_byte_order;
1062  } else {
1063  if (update_triple)
1064  m_triple = llvm::Triple();
1065  m_byte_order = eByteOrderInvalid;
1066  }
1067 }
1068 
1069 //===----------------------------------------------------------------------===//
1070 // Operators.
1071 
1072 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1073  bool try_inverse, bool enforce_exact_match) {
1074  if (core1 == core2)
1075  return true;
1076 
1077  switch (core1) {
1078  case ArchSpec::kCore_any:
1079  return true;
1080 
1081  case ArchSpec::eCore_arm_generic:
1082  if (enforce_exact_match)
1083  break;
1084  [[fallthrough]];
1085  case ArchSpec::kCore_arm_any:
1086  if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1087  return true;
1088  if (core2 >= ArchSpec::kCore_thumb_first &&
1089  core2 <= ArchSpec::kCore_thumb_last)
1090  return true;
1091  if (core2 == ArchSpec::kCore_arm_any)
1092  return true;
1093  break;
1094 
1095  case ArchSpec::kCore_x86_32_any:
1096  if ((core2 >= ArchSpec::kCore_x86_32_first &&
1097  core2 <= ArchSpec::kCore_x86_32_last) ||
1098  (core2 == ArchSpec::kCore_x86_32_any))
1099  return true;
1100  break;
1101 
1102  case ArchSpec::kCore_x86_64_any:
1103  if ((core2 >= ArchSpec::kCore_x86_64_first &&
1104  core2 <= ArchSpec::kCore_x86_64_last) ||
1105  (core2 == ArchSpec::kCore_x86_64_any))
1106  return true;
1107  break;
1108 
1109  case ArchSpec::kCore_ppc_any:
1110  if ((core2 >= ArchSpec::kCore_ppc_first &&
1111  core2 <= ArchSpec::kCore_ppc_last) ||
1112  (core2 == ArchSpec::kCore_ppc_any))
1113  return true;
1114  break;
1115 
1116  case ArchSpec::kCore_ppc64_any:
1117  if ((core2 >= ArchSpec::kCore_ppc64_first &&
1118  core2 <= ArchSpec::kCore_ppc64_last) ||
1119  (core2 == ArchSpec::kCore_ppc64_any))
1120  return true;
1121  break;
1122 
1123  case ArchSpec::kCore_hexagon_any:
1124  if ((core2 >= ArchSpec::kCore_hexagon_first &&
1125  core2 <= ArchSpec::kCore_hexagon_last) ||
1126  (core2 == ArchSpec::kCore_hexagon_any))
1127  return true;
1128  break;
1129 
1130  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1131  // Cortex-M0 - ARMv6-M - armv6m
1132  // Cortex-M3 - ARMv7-M - armv7m
1133  // Cortex-M4 - ARMv7E-M - armv7em
1134  case ArchSpec::eCore_arm_armv7em:
1135  if (!enforce_exact_match) {
1136  if (core2 == ArchSpec::eCore_arm_generic)
1137  return true;
1138  if (core2 == ArchSpec::eCore_arm_armv7m)
1139  return true;
1140  if (core2 == ArchSpec::eCore_arm_armv6m)
1141  return true;
1142  if (core2 == ArchSpec::eCore_arm_armv7)
1143  return true;
1144  try_inverse = true;
1145  }
1146  break;
1147 
1148  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1149  // Cortex-M0 - ARMv6-M - armv6m
1150  // Cortex-M3 - ARMv7-M - armv7m
1151  // Cortex-M4 - ARMv7E-M - armv7em
1152  case ArchSpec::eCore_arm_armv7m:
1153  if (!enforce_exact_match) {
1154  if (core2 == ArchSpec::eCore_arm_generic)
1155  return true;
1156  if (core2 == ArchSpec::eCore_arm_armv6m)
1157  return true;
1158  if (core2 == ArchSpec::eCore_arm_armv7)
1159  return true;
1160  if (core2 == ArchSpec::eCore_arm_armv7em)
1161  return true;
1162  try_inverse = true;
1163  }
1164  break;
1165 
1166  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1167  // Cortex-M0 - ARMv6-M - armv6m
1168  // Cortex-M3 - ARMv7-M - armv7m
1169  // Cortex-M4 - ARMv7E-M - armv7em
1170  case ArchSpec::eCore_arm_armv6m:
1171  if (!enforce_exact_match) {
1172  if (core2 == ArchSpec::eCore_arm_generic)
1173  return true;
1174  if (core2 == ArchSpec::eCore_arm_armv7em)
1175  return true;
1176  if (core2 == ArchSpec::eCore_arm_armv7)
1177  return true;
1178  if (core2 == ArchSpec::eCore_arm_armv6m)
1179  return true;
1180  try_inverse = false;
1181  }
1182  break;
1183 
1184  case ArchSpec::eCore_arm_armv7f:
1185  case ArchSpec::eCore_arm_armv7k:
1186  case ArchSpec::eCore_arm_armv7s:
1187  case ArchSpec::eCore_arm_armv7l:
1188  case ArchSpec::eCore_arm_armv8l:
1189  if (!enforce_exact_match) {
1190  if (core2 == ArchSpec::eCore_arm_generic)
1191  return true;
1192  if (core2 == ArchSpec::eCore_arm_armv7)
1193  return true;
1194  try_inverse = false;
1195  }
1196  break;
1197 
1198  case ArchSpec::eCore_x86_64_x86_64h:
1199  if (!enforce_exact_match) {
1200  try_inverse = false;
1201  if (core2 == ArchSpec::eCore_x86_64_x86_64)
1202  return true;
1203  }
1204  break;
1205 
1206  case ArchSpec::eCore_arm_armv8:
1207  if (!enforce_exact_match) {
1208  if (core2 == ArchSpec::eCore_arm_arm64)
1209  return true;
1210  if (core2 == ArchSpec::eCore_arm_aarch64)
1211  return true;
1212  if (core2 == ArchSpec::eCore_arm_arm64e)
1213  return true;
1214  try_inverse = false;
1215  }
1216  break;
1217 
1218  case ArchSpec::eCore_arm_arm64e:
1219  if (!enforce_exact_match) {
1220  if (core2 == ArchSpec::eCore_arm_arm64)
1221  return true;
1222  if (core2 == ArchSpec::eCore_arm_aarch64)
1223  return true;
1224  if (core2 == ArchSpec::eCore_arm_armv8)
1225  return true;
1226  try_inverse = false;
1227  }
1228  break;
1229  case ArchSpec::eCore_arm_aarch64:
1230  if (!enforce_exact_match) {
1231  if (core2 == ArchSpec::eCore_arm_arm64)
1232  return true;
1233  if (core2 == ArchSpec::eCore_arm_armv8)
1234  return true;
1235  if (core2 == ArchSpec::eCore_arm_arm64e)
1236  return true;
1237  try_inverse = false;
1238  }
1239  break;
1240 
1241  case ArchSpec::eCore_arm_arm64:
1242  if (!enforce_exact_match) {
1243  if (core2 == ArchSpec::eCore_arm_aarch64)
1244  return true;
1245  if (core2 == ArchSpec::eCore_arm_armv8)
1246  return true;
1247  if (core2 == ArchSpec::eCore_arm_arm64e)
1248  return true;
1249  try_inverse = false;
1250  }
1251  break;
1252 
1253  case ArchSpec::eCore_arm_arm64_32:
1254  if (!enforce_exact_match) {
1255  if (core2 == ArchSpec::eCore_arm_generic)
1256  return true;
1257  try_inverse = false;
1258  }
1259  break;
1260 
1261  case ArchSpec::eCore_mips32:
1262  if (!enforce_exact_match) {
1263  if (core2 >= ArchSpec::kCore_mips32_first &&
1264  core2 <= ArchSpec::kCore_mips32_last)
1265  return true;
1266  try_inverse = false;
1267  }
1268  break;
1269 
1270  case ArchSpec::eCore_mips32el:
1271  if (!enforce_exact_match) {
1272  if (core2 >= ArchSpec::kCore_mips32el_first &&
1273  core2 <= ArchSpec::kCore_mips32el_last)
1274  return true;
1275  try_inverse = true;
1276  }
1277  break;
1278 
1279  case ArchSpec::eCore_mips64:
1280  if (!enforce_exact_match) {
1281  if (core2 >= ArchSpec::kCore_mips32_first &&
1282  core2 <= ArchSpec::kCore_mips32_last)
1283  return true;
1284  if (core2 >= ArchSpec::kCore_mips64_first &&
1285  core2 <= ArchSpec::kCore_mips64_last)
1286  return true;
1287  try_inverse = false;
1288  }
1289  break;
1290 
1291  case ArchSpec::eCore_mips64el:
1292  if (!enforce_exact_match) {
1293  if (core2 >= ArchSpec::kCore_mips32el_first &&
1294  core2 <= ArchSpec::kCore_mips32el_last)
1295  return true;
1296  if (core2 >= ArchSpec::kCore_mips64el_first &&
1297  core2 <= ArchSpec::kCore_mips64el_last)
1298  return true;
1299  try_inverse = false;
1300  }
1301  break;
1302 
1303  case ArchSpec::eCore_mips64r2:
1304  case ArchSpec::eCore_mips64r3:
1305  case ArchSpec::eCore_mips64r5:
1306  if (!enforce_exact_match) {
1307  if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1308  return true;
1309  if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1310  return true;
1311  try_inverse = false;
1312  }
1313  break;
1314 
1315  case ArchSpec::eCore_mips64r2el:
1316  case ArchSpec::eCore_mips64r3el:
1317  case ArchSpec::eCore_mips64r5el:
1318  if (!enforce_exact_match) {
1319  if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1320  return true;
1321  if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1322  return true;
1323  try_inverse = false;
1324  }
1325  break;
1326 
1327  case ArchSpec::eCore_mips32r2:
1328  case ArchSpec::eCore_mips32r3:
1329  case ArchSpec::eCore_mips32r5:
1330  if (!enforce_exact_match) {
1331  if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1332  return true;
1333  }
1334  break;
1335 
1336  case ArchSpec::eCore_mips32r2el:
1337  case ArchSpec::eCore_mips32r3el:
1338  case ArchSpec::eCore_mips32r5el:
1339  if (!enforce_exact_match) {
1340  if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1341  return true;
1342  }
1343  break;
1344 
1345  case ArchSpec::eCore_mips32r6:
1346  if (!enforce_exact_match) {
1347  if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1348  return true;
1349  }
1350  break;
1351 
1352  case ArchSpec::eCore_mips32r6el:
1353  if (!enforce_exact_match) {
1354  if (core2 == ArchSpec::eCore_mips32el ||
1355  core2 == ArchSpec::eCore_mips32r6el)
1356  return true;
1357  }
1358  break;
1359 
1360  case ArchSpec::eCore_mips64r6:
1361  if (!enforce_exact_match) {
1362  if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1363  return true;
1364  if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1365  return true;
1366  }
1367  break;
1368 
1369  case ArchSpec::eCore_mips64r6el:
1370  if (!enforce_exact_match) {
1371  if (core2 == ArchSpec::eCore_mips32el ||
1372  core2 == ArchSpec::eCore_mips32r6el)
1373  return true;
1374  if (core2 == ArchSpec::eCore_mips64el ||
1375  core2 == ArchSpec::eCore_mips64r6el)
1376  return true;
1377  }
1378  break;
1379 
1380  default:
1381  break;
1382  }
1383  if (try_inverse)
1384  return cores_match(core2, core1, false, enforce_exact_match);
1385  return false;
1386 }
1387 
1388 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1389  const ArchSpec::Core lhs_core = lhs.GetCore();
1390  const ArchSpec::Core rhs_core = rhs.GetCore();
1391  return lhs_core < rhs_core;
1392 }
1393 
1394 
1395 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1396  return lhs.GetCore() == rhs.GetCore();
1397 }
1398 
1399 bool ArchSpec::IsFullySpecifiedTriple() const {
1400  if (!TripleOSWasSpecified())
1401  return false;
1402 
1403  if (!TripleVendorWasSpecified())
1404  return false;
1405 
1406  const unsigned unspecified = 0;
1407  const llvm::Triple &triple = GetTriple();
1408  if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified)
1409  return false;
1410 
1411  return true;
1412 }
1413 
1414 void ArchSpec::PiecewiseTripleCompare(
1415  const ArchSpec &other, bool &arch_different, bool &vendor_different,
1416  bool &os_different, bool &os_version_different, bool &env_different) const {
1417  const llvm::Triple &me(GetTriple());
1418  const llvm::Triple &them(other.GetTriple());
1419 
1420  arch_different = (me.getArch() != them.getArch());
1421 
1422  vendor_different = (me.getVendor() != them.getVendor());
1423 
1424  os_different = (me.getOS() != them.getOS());
1425 
1426  os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
1427 
1428  env_different = (me.getEnvironment() != them.getEnvironment());
1429 }
1430 
1431 bool ArchSpec::IsAlwaysThumbInstructions() const {
1433  if (GetTriple().getArch() == llvm::Triple::arm ||
1434  GetTriple().getArch() == llvm::Triple::thumb) {
1435  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1436  //
1437  // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1438  // execute thumb instructions. We map the cores to arch names like this:
1439  //
1440  // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
1441  // Cortex-M7: armv7em
1442 
1443  if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1444  GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1445  GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1446  GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1447  GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1448  GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1449  return true;
1450  }
1451  // Windows on ARM is always thumb.
1452  if (GetTriple().isOSWindows())
1453  return true;
1454  }
1455  return false;
1456 }
1457 
1458 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1459  const llvm::Triple &triple = GetTriple();
1460  llvm::StringRef arch_str = triple.getArchName();
1461  llvm::StringRef vendor_str = triple.getVendorName();
1462  llvm::StringRef os_str = triple.getOSName();
1463  llvm::StringRef environ_str = triple.getEnvironmentName();
1464 
1465  s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
1466  vendor_str.empty() ? "*" : vendor_str,
1467  os_str.empty() ? "*" : os_str);
1468 
1469  if (!environ_str.empty())
1470  s << "-" << environ_str;
1471 }
list
MATCHES FreeBSD list(APPEND FBSDKERNEL_LIBS kvm) endif() if(NOT FBSDKERNEL_LIBS) message(STATUS "Skipping FreeBSDKernel plugin due to missing libfbsdvmcore") return() endif() add_lldb_library(lldbPluginProcessFreeBSDKernel PLUGIN ProcessFreeBSDKernel.cpp RegisterContextFreeBSDKernel_arm64.cpp RegisterContextFreeBSDKernel_i386.cpp RegisterContextFreeBSDKernel_x86_64.cpp ThreadFreeBSDKernel.cpp LINK_LIBS lldbCore lldbTarget $
Definition: Plugins/Process/FreeBSDKernel/CMakeLists.txt:6
lldb_private::ArchSpec::GetByteOrder
lldb::ByteOrder GetByteOrder() const
Returns the byte order for the architecture specification.
Definition: ArchSpec.cpp:729
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static const ArchDefinition * g_arch_definitions[]
Definition: ArchSpec.cpp:446
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ArchSpec::Core core
Definition: ArchSpec.cpp:35
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Definition: ArchSpec.h:32
lldb_private::ArchSpec::TripleVendorWasSpecified
bool TripleVendorWasSpecified() const
Definition: ArchSpec.h:357
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@ eArchTypeCOFF
Definition: lldb-private-enumerations.h:65
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uint32_t addr_byte_size
Definition: ArchSpec.cpp:31
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static const CoreDefinition g_core_definitions[]
Definition: ArchSpec.cpp:42
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void TryCompleteCurrentArg(llvm::StringRef completion, llvm::StringRef description="")
Adds a possible completion string if the completion would complete the current argument.
Definition: CompletionRequest.h:180
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Definition: ArchSpec.cpp:246
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Core GetCore() const
Definition: ArchSpec.h:433
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static const ArchDefinition * FindArchDefinition(ArchitectureType arch_type)
Definition: ArchSpec.cpp:453
LLDB_LOGF
#define LLDB_LOGF(log,...)
Definition: Log.h:344
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static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, llvm::Triple::EnvironmentType rhs)
Definition: ArchSpec.cpp:929
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uint32_t GetFlags() const
Definition: ArchSpec.h:530
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void SetCString(const char *cstr)
Set the C string value.
Definition: ConstString.cpp:301
CPU_ANY
#define CPU_ANY
Definition: ArchSpec.cpp:267
lldb_private::ArchSpec::GetTriple
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:454
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ByteOrder default_byte_order
Definition: ArchSpec.cpp:30
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#define LLDB_INVALID_CPUTYPE
Definition: lldb-defines.h:95
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@ eArchTypeMachO
Definition: lldb-private-enumerations.h:63
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static const ArchDefinitionEntry * FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub)
Definition: ArchSpec.cpp:478
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Definition: ArchSpec.h:111
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const char *const name
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Definition: ArchSpec.cpp:437
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bool operator==(const Address &lhs, const Address &rhs)
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size_t num_entries
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Definition: ArchSpec.cpp:343
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Definition: ArchSpec.cpp:1072
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static const CoreDefinition * FindCoreDefinition(llvm::StringRef name)
Definition: ArchSpec.cpp:462
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ArchitectureType type
Definition: ArchSpec.cpp:251
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Definition: ArchSpec.cpp:243
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const char * name
Definition: ArchSpec.cpp:254
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Definition: StringList.h:26
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Definition: ConstString.h:39
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bool TripleOSWasSpecified() const
Definition: ArchSpec.h:361
string
string(SUBSTRING ${p} 10 -1 pStripped) if($
Definition: Plugins/CMakeLists.txt:40
StringList.h
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static const ArchDefinitionEntry g_coff_arch_entries[]
Definition: ArchSpec.cpp:418
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#define CPU_TYPE_ARM64_32
Definition: HostInfoMacOSX.mm:57
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bool TripleEnvironmentWasSpecified() const
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uint32_t cpu
Definition: ArchSpec.cpp:244
lldb_private::ArchitectureType
ArchitectureType
Definition: lldb-private-enumerations.h:61
lldb_private::ArchSpec::SetArchitecture
bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os=0)
Change the architecture object type, CPU type and OS type.
Definition: ArchSpec.cpp:842
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Definition: ArchSpec.cpp:29
SUBTYPE_MASK
#define SUBTYPE_MASK
Definition: ArchSpec.cpp:274
ArchDefinition::entries
const ArchDefinitionEntry * entries
Definition: ArchSpec.cpp:253
ArchDefinitionEntry
Definition: ArchSpec.cpp:242
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Definition: Status.h:44
lldb::eByteOrderInvalid
@ eByteOrderInvalid
Definition: lldb-enumerations.h:139
uint32_t
lldb_private::CoreDefinition::min_opcode_byte_size
uint32_t min_opcode_byte_size
Definition: ArchSpec.cpp:32
lldb_private::eArchTypeELF
@ eArchTypeELF
Definition: lldb-private-enumerations.h:64
lldb_private::ArchSpec::MatchType
MatchType
Definition: ArchSpec.h:490
ArchSpec.h
UINT32_MAX
#define UINT32_MAX
Definition: lldb-defines.h:19
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bool operator<(const Address &lhs, const Address &rhs)
Definition: Address.cpp:985
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uint32_t sub
Definition: ArchSpec.cpp:245
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Definition: ArchSpec.cpp:250
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#define CPU_SUBTYPE_X86_64_H
Definition: HostInfoMacOSX.mm:49
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A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
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static const ArchDefinitionEntry g_elf_arch_entries[]
Definition: ArchSpec.cpp:352
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uint32_t max_opcode_byte_size
Definition: ArchSpec.cpp:33
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@ eByteOrderBig
Definition: lldb-enumerations.h:140
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bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch)
Definition: ArchSpec.cpp:744
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Definition: Log.h:115
lldb_private::GetLog
Log * GetLog(Cat mask)
Retrieve the Log object for the channel associated with the given log enum.
Definition: Log.h:309
lldb::eByteOrderLittle
@ eByteOrderLittle
Definition: lldb-enumerations.h:142
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Definition: SBAddress.h:15
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#define CPU_TYPE_ARM64
Definition: HostInfoMacOSX.mm:52
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Definition: CompletionRequest.h:100
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Byte ordering definitions.
Definition: lldb-enumerations.h:138