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ArchSpec.cpp
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1 //===-- ArchSpec.cpp ------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 
11 #include "lldb/Utility/Log.h"
13 #include "lldb/lldb-defines.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/BinaryFormat/COFF.h"
16 #include "llvm/BinaryFormat/ELF.h"
17 #include "llvm/BinaryFormat/MachO.h"
18 #include "llvm/Support/Compiler.h"
19 
20 using namespace lldb;
21 using namespace lldb_private;
22 
23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
24  bool try_inverse, bool enforce_exact_match);
25 
26 namespace lldb_private {
27 
33  llvm::Triple::ArchType machine;
35  const char *const name;
36 };
37 
38 } // namespace lldb_private
39 
40 // This core information can be looked using the ArchSpec::Core as the index
42  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
43  "arm"},
44  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
45  "armv4"},
46  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
47  "armv4t"},
48  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
49  "armv5"},
50  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
51  "armv5e"},
52  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
53  "armv5t"},
54  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
55  "armv6"},
56  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
57  "armv6m"},
58  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
59  "armv7"},
60  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
61  "armv7l"},
62  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
63  "armv7f"},
64  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
65  "armv7s"},
66  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
67  "armv7k"},
68  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
69  "armv7m"},
70  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
71  "armv7em"},
72  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
73  "xscale"},
74  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
75  "thumb"},
76  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
77  "thumbv4t"},
78  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
79  "thumbv5"},
80  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
81  "thumbv5e"},
82  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
83  "thumbv6"},
84  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
85  "thumbv6m"},
86  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
87  "thumbv7"},
88  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
89  "thumbv7f"},
90  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
91  "thumbv7s"},
92  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
93  "thumbv7k"},
94  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
95  "thumbv7m"},
96  {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
97  "thumbv7em"},
98  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
99  ArchSpec::eCore_arm_arm64, "arm64"},
100  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
101  ArchSpec::eCore_arm_armv8, "armv8"},
102  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
103  "armv8l"},
104  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
105  ArchSpec::eCore_arm_arm64e, "arm64e"},
106  {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
107  ArchSpec::eCore_arm_arm64_32, "arm64_32"},
108  {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
109  ArchSpec::eCore_arm_aarch64, "aarch64"},
110 
111  // mips32, mips32r2, mips32r3, mips32r5, mips32r6
112  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
113  "mips"},
114  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
115  "mipsr2"},
116  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
117  "mipsr3"},
118  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
119  "mipsr5"},
120  {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
121  "mipsr6"},
122  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
123  "mipsel"},
124  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
125  ArchSpec::eCore_mips32r2el, "mipsr2el"},
126  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
127  ArchSpec::eCore_mips32r3el, "mipsr3el"},
128  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
129  ArchSpec::eCore_mips32r5el, "mipsr5el"},
130  {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
131  ArchSpec::eCore_mips32r6el, "mipsr6el"},
132 
133  // mips64, mips64r2, mips64r3, mips64r5, mips64r6
134  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
135  "mips64"},
136  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
137  "mips64r2"},
138  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
139  "mips64r3"},
140  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
141  "mips64r5"},
142  {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
143  "mips64r6"},
144  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
145  ArchSpec::eCore_mips64el, "mips64el"},
146  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
147  ArchSpec::eCore_mips64r2el, "mips64r2el"},
148  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
149  ArchSpec::eCore_mips64r3el, "mips64r3el"},
150  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
151  ArchSpec::eCore_mips64r5el, "mips64r5el"},
152  {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
153  ArchSpec::eCore_mips64r6el, "mips64r6el"},
154 
155  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
156  "powerpc"},
157  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
158  "ppc601"},
159  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
160  "ppc602"},
161  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
162  "ppc603"},
163  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
164  "ppc603e"},
165  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
166  "ppc603ev"},
167  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
168  "ppc604"},
169  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
170  "ppc604e"},
171  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
172  "ppc620"},
173  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
174  "ppc750"},
175  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
176  "ppc7400"},
177  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
178  "ppc7450"},
179  {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
180  "ppc970"},
181 
182  {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
183  ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
184  {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
185  "powerpc64"},
186  {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
187  ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
188 
189  {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
190  ArchSpec::eCore_s390x_generic, "s390x"},
191 
192  {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
193  ArchSpec::eCore_sparc_generic, "sparc"},
194  {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
195  ArchSpec::eCore_sparc9_generic, "sparcv9"},
196 
197  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
198  "i386"},
199  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
200  "i486"},
201  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
202  ArchSpec::eCore_x86_32_i486sx, "i486sx"},
203  {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
204  "i686"},
205 
206  {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
207  ArchSpec::eCore_x86_64_x86_64, "x86_64"},
208  {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
209  ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
210  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
211  ArchSpec::eCore_hexagon_generic, "hexagon"},
212  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
213  ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
214  {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
215  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
216 
217  {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
218  "riscv32"},
219  {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
220  "riscv64"},
221 
222  {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
223  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
224  {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
225  ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
226  {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
227 
228  {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
229 
230  {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
231  "wasm32"},
232 };
233 
234 // Ensure that we have an entry in the g_core_definitions for each core. If you
235 // comment out an entry above, you will need to comment out the corresponding
236 // ArchSpec::Core enumeration.
237 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
238  ArchSpec::kNumCores,
239  "make sure we have one core definition for each core");
240 
247 };
248 
251  size_t num_entries;
253  const char *name;
254 };
255 
256 void ArchSpec::ListSupportedArchNames(StringList &list) {
257  for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
259 }
260 
261 void ArchSpec::AutoComplete(CompletionRequest &request) {
262  for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
264 }
265 
266 #define CPU_ANY (UINT32_MAX)
267 
268 //===----------------------------------------------------------------------===//
269 // A table that gets searched linearly for matches. This table is used to
270 // convert cpu type and subtypes to architecture names, and to convert
271 // architecture names to cpu types and subtypes. The ordering is important and
272 // allows the precedence to be set when the table is built.
273 #define SUBTYPE_MASK 0x00FFFFFFu
274 
275 // clang-format off
277  {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
278  {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
279  {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
280  {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
281  {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
282  {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
283  {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
284  {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
285  {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
286  {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
287  {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
288  {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
289  {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
290  {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
291  {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
292  {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
293  {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
294  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
295  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
296  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK},
297  {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK},
298  {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK},
299  {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
300  {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
301  {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
302  {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
303  {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
304  {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
305  {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
306  {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
307  {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
308  {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
309  {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
310  {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
311  {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
312  {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
313  {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
314  {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
315  {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
316  {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
317  {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
318  {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
319  {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
320  {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
321  {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
322  {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
323  {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
324  {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
325  {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
326  {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
327  {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
328  {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK},
329  {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
330  {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
331  {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
332  {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
333  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
334  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
335  {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
336  {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
337  // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
338  {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
339  {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
340 // clang-format on
341 
343  eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries),
344  g_macho_arch_entries, "mach-o"};
345 
346 //===----------------------------------------------------------------------===//
347 // A table that gets searched linearly for matches. This table is used to
348 // convert cpu type and subtypes to architecture names, and to convert
349 // architecture names to cpu types and subtypes. The ordering is important and
350 // allows the precedence to be set when the table is built.
352  {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
353  0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
354  {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
355  0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
356  {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
357  0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
358  {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
359  0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
360  {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
361  0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
362  {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
363  0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
364  {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
365  0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
366  {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
367  0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
368  {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
369  0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
370  {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
371  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
372  {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
373  0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
374  {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
375  0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
376  {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
377  ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
378  {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
379  ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
380  {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
381  ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
382  {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
383  ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
384  {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
385  ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
386  {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
387  0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
388  {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
389  ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
390  {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
391  ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
392  {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
393  ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
394  {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
395  ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
396  {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
397  ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
398  {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
399  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
400  {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
401  0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
402  {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
403  0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR
404  {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
405  ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
406  {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
407  ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
408 };
409 
411  eArchTypeELF,
412  llvm::array_lengthof(g_elf_arch_entries),
414  "elf",
415 };
416 
418  {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
419  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
420  {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
421  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
422  {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
423  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
424  {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
425  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
426  {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
427  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
428  {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
429  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
430  {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
431  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
432  {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
433  LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
434 };
435 
438  llvm::array_lengthof(g_coff_arch_entries),
440  "pe-coff",
441 };
442 
443 //===----------------------------------------------------------------------===//
444 // Table of all ArchDefinitions
447 
448 static const size_t k_num_arch_definitions =
449  llvm::array_lengthof(g_arch_definitions);
450 
451 //===----------------------------------------------------------------------===//
452 // Static helper functions.
453 
454 // Get the architecture definition for a given object type.
456  for (unsigned int i = 0; i < k_num_arch_definitions; ++i) {
457  const ArchDefinition *def = g_arch_definitions[i];
458  if (def->type == arch_type)
459  return def;
460  }
461  return nullptr;
462 }
463 
464 // Get an architecture definition by name.
465 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
466  for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) {
467  if (name.equals_insensitive(g_core_definitions[i].name))
468  return &g_core_definitions[i];
469  }
470  return nullptr;
471 }
472 
474  if (core < llvm::array_lengthof(g_core_definitions))
475  return &g_core_definitions[core];
476  return nullptr;
477 }
478 
479 // Get a definition entry by cpu type and subtype.
480 static const ArchDefinitionEntry *
482  if (def == nullptr)
483  return nullptr;
484 
485  const ArchDefinitionEntry *entries = def->entries;
486  for (size_t i = 0; i < def->num_entries; ++i) {
487  if (entries[i].cpu == (cpu & entries[i].cpu_mask))
488  if (entries[i].sub == (sub & entries[i].sub_mask))
489  return &entries[i];
490  }
491  return nullptr;
492 }
493 
494 static const ArchDefinitionEntry *
496  if (def == nullptr)
497  return nullptr;
498 
499  const ArchDefinitionEntry *entries = def->entries;
500  for (size_t i = 0; i < def->num_entries; ++i) {
501  if (entries[i].core == core)
502  return &entries[i];
503  }
504  return nullptr;
505 }
506 
507 //===----------------------------------------------------------------------===//
508 // Constructors and destructors.
509 
510 ArchSpec::ArchSpec() = default;
511 
512 ArchSpec::ArchSpec(const char *triple_cstr) {
513  if (triple_cstr)
514  SetTriple(triple_cstr);
515 }
516 
517 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
518 
519 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
520 
521 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
522  SetArchitecture(arch_type, cpu, subtype);
523 }
524 
525 ArchSpec::~ArchSpec() = default;
526 
527 void ArchSpec::Clear() {
528  m_triple = llvm::Triple();
529  m_core = kCore_invalid;
530  m_byte_order = eByteOrderInvalid;
531  m_distribution_id.Clear();
532  m_flags = 0;
533 }
534 
535 //===----------------------------------------------------------------------===//
536 // Predicates.
537 
538 const char *ArchSpec::GetArchitectureName() const {
539  const CoreDefinition *core_def = FindCoreDefinition(m_core);
540  if (core_def)
541  return core_def->name;
542  return "unknown";
543 }
544 
545 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
546 
547 std::string ArchSpec::GetTargetABI() const {
548 
549  std::string abi;
550 
551  if (IsMIPS()) {
552  switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
553  case ArchSpec::eMIPSABI_N64:
554  abi = "n64";
555  return abi;
556  case ArchSpec::eMIPSABI_N32:
557  abi = "n32";
558  return abi;
559  case ArchSpec::eMIPSABI_O32:
560  abi = "o32";
561  return abi;
562  default:
563  return abi;
564  }
565  }
566  return abi;
567 }
568 
569 void ArchSpec::SetFlags(const std::string &elf_abi) {
570 
571  uint32_t flag = GetFlags();
572  if (IsMIPS()) {
573  if (elf_abi == "n64")
574  flag |= ArchSpec::eMIPSABI_N64;
575  else if (elf_abi == "n32")
576  flag |= ArchSpec::eMIPSABI_N32;
577  else if (elf_abi == "o32")
578  flag |= ArchSpec::eMIPSABI_O32;
579  }
580  SetFlags(flag);
581 }
582 
583 std::string ArchSpec::GetClangTargetCPU() const {
584  std::string cpu;
585 
586  if (IsMIPS()) {
587  switch (m_core) {
588  case ArchSpec::eCore_mips32:
589  case ArchSpec::eCore_mips32el:
590  cpu = "mips32";
591  break;
592  case ArchSpec::eCore_mips32r2:
593  case ArchSpec::eCore_mips32r2el:
594  cpu = "mips32r2";
595  break;
596  case ArchSpec::eCore_mips32r3:
597  case ArchSpec::eCore_mips32r3el:
598  cpu = "mips32r3";
599  break;
600  case ArchSpec::eCore_mips32r5:
601  case ArchSpec::eCore_mips32r5el:
602  cpu = "mips32r5";
603  break;
604  case ArchSpec::eCore_mips32r6:
605  case ArchSpec::eCore_mips32r6el:
606  cpu = "mips32r6";
607  break;
608  case ArchSpec::eCore_mips64:
609  case ArchSpec::eCore_mips64el:
610  cpu = "mips64";
611  break;
612  case ArchSpec::eCore_mips64r2:
613  case ArchSpec::eCore_mips64r2el:
614  cpu = "mips64r2";
615  break;
616  case ArchSpec::eCore_mips64r3:
617  case ArchSpec::eCore_mips64r3el:
618  cpu = "mips64r3";
619  break;
620  case ArchSpec::eCore_mips64r5:
621  case ArchSpec::eCore_mips64r5el:
622  cpu = "mips64r5";
623  break;
624  case ArchSpec::eCore_mips64r6:
625  case ArchSpec::eCore_mips64r6el:
626  cpu = "mips64r6";
627  break;
628  default:
629  break;
630  }
631  }
632  return cpu;
633 }
634 
635 uint32_t ArchSpec::GetMachOCPUType() const {
636  const CoreDefinition *core_def = FindCoreDefinition(m_core);
637  if (core_def) {
638  const ArchDefinitionEntry *arch_def =
640  if (arch_def) {
641  return arch_def->cpu;
642  }
643  }
644  return LLDB_INVALID_CPUTYPE;
645 }
646 
647 uint32_t ArchSpec::GetMachOCPUSubType() const {
648  const CoreDefinition *core_def = FindCoreDefinition(m_core);
649  if (core_def) {
650  const ArchDefinitionEntry *arch_def =
652  if (arch_def) {
653  return arch_def->sub;
654  }
655  }
656  return LLDB_INVALID_CPUTYPE;
657 }
658 
659 uint32_t ArchSpec::GetDataByteSize() const {
660  return 1;
661 }
662 
663 uint32_t ArchSpec::GetCodeByteSize() const {
664  return 1;
665 }
666 
667 llvm::Triple::ArchType ArchSpec::GetMachine() const {
668  const CoreDefinition *core_def = FindCoreDefinition(m_core);
669  if (core_def)
670  return core_def->machine;
671 
672  return llvm::Triple::UnknownArch;
673 }
674 
675 ConstString ArchSpec::GetDistributionId() const {
676  return m_distribution_id;
677 }
678 
679 void ArchSpec::SetDistributionId(const char *distribution_id) {
680  m_distribution_id.SetCString(distribution_id);
681 }
682 
683 uint32_t ArchSpec::GetAddressByteSize() const {
684  const CoreDefinition *core_def = FindCoreDefinition(m_core);
685  if (core_def) {
686  if (core_def->machine == llvm::Triple::mips64 ||
687  core_def->machine == llvm::Triple::mips64el) {
688  // For N32/O32 applications Address size is 4 bytes.
689  if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
690  return 4;
691  }
692  return core_def->addr_byte_size;
693  }
694  return 0;
695 }
696 
697 ByteOrder ArchSpec::GetDefaultEndian() const {
698  const CoreDefinition *core_def = FindCoreDefinition(m_core);
699  if (core_def)
700  return core_def->default_byte_order;
701  return eByteOrderInvalid;
702 }
703 
704 bool ArchSpec::CharIsSignedByDefault() const {
705  switch (m_triple.getArch()) {
706  default:
707  return true;
708 
709  case llvm::Triple::aarch64:
710  case llvm::Triple::aarch64_32:
711  case llvm::Triple::aarch64_be:
712  case llvm::Triple::arm:
713  case llvm::Triple::armeb:
714  case llvm::Triple::thumb:
715  case llvm::Triple::thumbeb:
716  return m_triple.isOSDarwin() || m_triple.isOSWindows();
717 
718  case llvm::Triple::ppc:
719  case llvm::Triple::ppc64:
720  return m_triple.isOSDarwin();
721 
722  case llvm::Triple::ppc64le:
723  case llvm::Triple::systemz:
724  case llvm::Triple::xcore:
725  case llvm::Triple::arc:
726  return false;
727  }
728 }
729 
730 lldb::ByteOrder ArchSpec::GetByteOrder() const {
731  if (m_byte_order == eByteOrderInvalid)
732  return GetDefaultEndian();
733  return m_byte_order;
734 }
735 
736 //===----------------------------------------------------------------------===//
737 // Mutators.
738 
739 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
740  m_triple = triple;
741  UpdateCore();
742  return IsValid();
743 }
744 
745 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
746  ArchSpec &arch) {
747  // Accept "12-10" or "12.10" as cpu type/subtype
748  if (triple_str.empty())
749  return false;
750 
751  size_t pos = triple_str.find_first_of("-.");
752  if (pos == llvm::StringRef::npos)
753  return false;
754 
755  llvm::StringRef cpu_str = triple_str.substr(0, pos);
756  llvm::StringRef remainder = triple_str.substr(pos + 1);
757  if (cpu_str.empty() || remainder.empty())
758  return false;
759 
760  llvm::StringRef sub_str;
761  llvm::StringRef vendor;
762  llvm::StringRef os;
763  std::tie(sub_str, remainder) = remainder.split('-');
764  std::tie(vendor, os) = remainder.split('-');
765 
766  uint32_t cpu = 0;
767  uint32_t sub = 0;
768  if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
769  return false;
770 
771  if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
772  return false;
773  if (!vendor.empty() && !os.empty()) {
774  arch.GetTriple().setVendorName(vendor);
775  arch.GetTriple().setOSName(os);
776  }
777 
778  return true;
779 }
780 
781 bool ArchSpec::SetTriple(llvm::StringRef triple) {
782  if (triple.empty()) {
783  Clear();
784  return false;
785  }
786 
787  if (ParseMachCPUDashSubtypeTriple(triple, *this))
788  return true;
789 
790  SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
791  return IsValid();
792 }
793 
794 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
795  return !normalized_triple.getArchName().empty() &&
796  normalized_triple.getOSName().empty() &&
797  normalized_triple.getVendorName().empty() &&
798  normalized_triple.getEnvironmentName().empty();
799 }
800 
801 void ArchSpec::MergeFrom(const ArchSpec &other) {
802  // ios-macabi always wins over macosx.
803  if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
804  GetTriple().getOS() == llvm::Triple::UnknownOS) &&
805  other.GetTriple().getOS() == llvm::Triple::IOS &&
806  other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
807  (*this) = other;
808  return;
809  }
810 
811  if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
812  GetTriple().setVendor(other.GetTriple().getVendor());
813  if (!TripleOSWasSpecified() && other.TripleOSWasSpecified())
814  GetTriple().setOS(other.GetTriple().getOS());
815  if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
816  GetTriple().setArch(other.GetTriple().getArch());
817 
818  // MachO unknown64 isn't really invalid as the debugger can still obtain
819  // information from the binary, e.g. line tables. As such, we don't update
820  // the core here.
821  if (other.GetCore() != eCore_uknownMach64)
822  UpdateCore();
823  }
824  if (!TripleEnvironmentWasSpecified() &&
826  GetTriple().setEnvironment(other.GetTriple().getEnvironment());
827  }
828  // If this and other are both arm ArchSpecs and this ArchSpec is a generic
829  // "some kind of arm" spec but the other ArchSpec is a specific arm core,
830  // adopt the specific arm core.
831  if (GetTriple().getArch() == llvm::Triple::arm &&
832  other.GetTriple().getArch() == llvm::Triple::arm &&
833  IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
834  other.GetCore() != ArchSpec::eCore_arm_generic) {
835  m_core = other.GetCore();
836  CoreUpdated(false);
837  }
838  if (GetFlags() == 0) {
839  SetFlags(other.GetFlags());
840  }
841 }
842 
843 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
844  uint32_t sub, uint32_t os) {
845  m_core = kCore_invalid;
846  bool update_triple = true;
847  const ArchDefinition *arch_def = FindArchDefinition(arch_type);
848  if (arch_def) {
849  const ArchDefinitionEntry *arch_def_entry =
850  FindArchDefinitionEntry(arch_def, cpu, sub);
851  if (arch_def_entry) {
852  const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
853  if (core_def) {
854  m_core = core_def->core;
855  update_triple = false;
856  // Always use the architecture name because it might be more
857  // descriptive than the architecture enum ("armv7" ->
858  // llvm::Triple::arm).
859  m_triple.setArchName(llvm::StringRef(core_def->name));
860  if (arch_type == eArchTypeMachO) {
861  m_triple.setVendor(llvm::Triple::Apple);
862 
863  // Don't set the OS. It could be simulator, macosx, ios, watchos,
864  // tvos, bridgeos. We could get close with the cpu type - but we
865  // can't get it right all of the time. Better to leave this unset
866  // so other sections of code will set it when they have more
867  // information. NB: don't call m_triple.setOS
868  // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
869  // the ArchSpec::TripleVendorWasSpecified() method says that any
870  // OSName setting means it was specified.
871  } else if (arch_type == eArchTypeELF) {
872  switch (os) {
873  case llvm::ELF::ELFOSABI_AIX:
874  m_triple.setOS(llvm::Triple::OSType::AIX);
875  break;
876  case llvm::ELF::ELFOSABI_FREEBSD:
877  m_triple.setOS(llvm::Triple::OSType::FreeBSD);
878  break;
879  case llvm::ELF::ELFOSABI_GNU:
880  m_triple.setOS(llvm::Triple::OSType::Linux);
881  break;
882  case llvm::ELF::ELFOSABI_NETBSD:
883  m_triple.setOS(llvm::Triple::OSType::NetBSD);
884  break;
885  case llvm::ELF::ELFOSABI_OPENBSD:
886  m_triple.setOS(llvm::Triple::OSType::OpenBSD);
887  break;
888  case llvm::ELF::ELFOSABI_SOLARIS:
889  m_triple.setOS(llvm::Triple::OSType::Solaris);
890  break;
891  }
892  } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
893  m_triple.setVendor(llvm::Triple::PC);
894  m_triple.setOS(llvm::Triple::Win32);
895  } else {
896  m_triple.setVendor(llvm::Triple::UnknownVendor);
897  m_triple.setOS(llvm::Triple::UnknownOS);
898  }
899  // Fall back onto setting the machine type if the arch by name
900  // failed...
901  if (m_triple.getArch() == llvm::Triple::UnknownArch)
902  m_triple.setArch(core_def->machine);
903  }
904  } else {
906  LLDB_LOGF(log,
907  "Unable to find a core definition for cpu 0x%" PRIx32
908  " sub %" PRId32,
909  cpu, sub);
910  }
911  }
912  CoreUpdated(update_triple);
913  return IsValid();
914 }
915 
916 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
917  const CoreDefinition *core_def = FindCoreDefinition(m_core);
918  if (core_def)
919  return core_def->min_opcode_byte_size;
920  return 0;
921 }
922 
923 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
924  const CoreDefinition *core_def = FindCoreDefinition(m_core);
925  if (core_def)
926  return core_def->max_opcode_byte_size;
927  return 0;
928 }
929 
930 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const {
931  return IsEqualTo(rhs, true);
932 }
933 
934 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const {
935  return IsEqualTo(rhs, false);
936 }
937 
938 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
939  llvm::Triple::EnvironmentType rhs) {
940  if (lhs == rhs)
941  return true;
942 
943  // Apple simulators are a different platform than what they simulate.
944  // As the environments are different at this point, if one of them is a
945  // simulator, then they are different.
946  if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
947  return false;
948 
949  // If any of the environment is unknown then they are compatible
950  if (lhs == llvm::Triple::UnknownEnvironment ||
951  rhs == llvm::Triple::UnknownEnvironment)
952  return true;
953 
954  // If one of the environment is Android and the other one is EABI then they
955  // are considered to be compatible. This is required as a workaround for
956  // shared libraries compiled for Android without the NOTE section indicating
957  // that they are using the Android ABI.
958  if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
959  (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
960  (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
961  (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
962  (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
963  (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
964  return true;
965 
966  return false;
967 }
968 
969 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const {
970  // explicitly ignoring m_distribution_id in this method.
971 
972  if (GetByteOrder() != rhs.GetByteOrder() ||
973  !cores_match(GetCore(), rhs.GetCore(), true, exact_match))
974  return false;
975 
976  const llvm::Triple &lhs_triple = GetTriple();
977  const llvm::Triple &rhs_triple = rhs.GetTriple();
978 
979  const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
980  const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
981  if (lhs_triple_vendor != rhs_triple_vendor) {
982  const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
983  const bool lhs_vendor_specified = TripleVendorWasSpecified();
984  // Both architectures had the vendor specified, so if they aren't equal
985  // then we return false
986  if (rhs_vendor_specified && lhs_vendor_specified)
987  return false;
988 
989  // Only fail if both vendor types are not unknown
990  if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
991  rhs_triple_vendor != llvm::Triple::UnknownVendor)
992  return false;
993  }
994 
995  const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
996  const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
997  const llvm::Triple::EnvironmentType lhs_triple_env =
998  lhs_triple.getEnvironment();
999  const llvm::Triple::EnvironmentType rhs_triple_env =
1000  rhs_triple.getEnvironment();
1001 
1002  if (!exact_match) {
1003  // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
1004  if ((lhs_triple_os == llvm::Triple::IOS &&
1005  lhs_triple_env == llvm::Triple::MacABI &&
1006  rhs_triple_os == llvm::Triple::MacOSX) ||
1007  (lhs_triple_os == llvm::Triple::MacOSX &&
1008  rhs_triple_os == llvm::Triple::IOS &&
1009  rhs_triple_env == llvm::Triple::MacABI))
1010  return true;
1011  }
1012 
1013  // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1014  if (lhs_triple_os == llvm::Triple::IOS &&
1015  rhs_triple_os == llvm::Triple::IOS &&
1016  (lhs_triple_env == llvm::Triple::MacABI ||
1017  rhs_triple_env == llvm::Triple::MacABI) &&
1018  lhs_triple_env != rhs_triple_env)
1019  return false;
1020 
1021  if (lhs_triple_os != rhs_triple_os) {
1022  const bool lhs_os_specified = TripleOSWasSpecified();
1023  const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1024  // If both OS types are specified and different, fail.
1025  if (lhs_os_specified && rhs_os_specified)
1026  return false;
1027 
1028  // If the pair of os+env is both unspecified, match any other os+env combo.
1029  if (!exact_match && ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1030  (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1031  return true;
1032  }
1033 
1034  return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1035 }
1036 
1037 void ArchSpec::UpdateCore() {
1038  llvm::StringRef arch_name(m_triple.getArchName());
1039  const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1040  if (core_def) {
1041  m_core = core_def->core;
1042  // Set the byte order to the default byte order for an architecture. This
1043  // can be modified if needed for cases when cores handle both big and
1044  // little endian
1045  m_byte_order = core_def->default_byte_order;
1046  } else {
1047  Clear();
1048  }
1049 }
1050 
1051 //===----------------------------------------------------------------------===//
1052 // Helper methods.
1053 
1054 void ArchSpec::CoreUpdated(bool update_triple) {
1055  const CoreDefinition *core_def = FindCoreDefinition(m_core);
1056  if (core_def) {
1057  if (update_triple)
1058  m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1059  m_byte_order = core_def->default_byte_order;
1060  } else {
1061  if (update_triple)
1062  m_triple = llvm::Triple();
1063  m_byte_order = eByteOrderInvalid;
1064  }
1065 }
1066 
1067 //===----------------------------------------------------------------------===//
1068 // Operators.
1069 
1070 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1071  bool try_inverse, bool enforce_exact_match) {
1072  if (core1 == core2)
1073  return true;
1074 
1075  switch (core1) {
1076  case ArchSpec::kCore_any:
1077  return true;
1078 
1079  case ArchSpec::eCore_arm_generic:
1080  if (enforce_exact_match)
1081  break;
1082  LLVM_FALLTHROUGH;
1083  case ArchSpec::kCore_arm_any:
1084  if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1085  return true;
1086  if (core2 >= ArchSpec::kCore_thumb_first &&
1087  core2 <= ArchSpec::kCore_thumb_last)
1088  return true;
1089  if (core2 == ArchSpec::kCore_arm_any)
1090  return true;
1091  break;
1092 
1093  case ArchSpec::kCore_x86_32_any:
1094  if ((core2 >= ArchSpec::kCore_x86_32_first &&
1095  core2 <= ArchSpec::kCore_x86_32_last) ||
1096  (core2 == ArchSpec::kCore_x86_32_any))
1097  return true;
1098  break;
1099 
1100  case ArchSpec::kCore_x86_64_any:
1101  if ((core2 >= ArchSpec::kCore_x86_64_first &&
1102  core2 <= ArchSpec::kCore_x86_64_last) ||
1103  (core2 == ArchSpec::kCore_x86_64_any))
1104  return true;
1105  break;
1106 
1107  case ArchSpec::kCore_ppc_any:
1108  if ((core2 >= ArchSpec::kCore_ppc_first &&
1109  core2 <= ArchSpec::kCore_ppc_last) ||
1110  (core2 == ArchSpec::kCore_ppc_any))
1111  return true;
1112  break;
1113 
1114  case ArchSpec::kCore_ppc64_any:
1115  if ((core2 >= ArchSpec::kCore_ppc64_first &&
1116  core2 <= ArchSpec::kCore_ppc64_last) ||
1117  (core2 == ArchSpec::kCore_ppc64_any))
1118  return true;
1119  break;
1120 
1121  case ArchSpec::kCore_hexagon_any:
1122  if ((core2 >= ArchSpec::kCore_hexagon_first &&
1123  core2 <= ArchSpec::kCore_hexagon_last) ||
1124  (core2 == ArchSpec::kCore_hexagon_any))
1125  return true;
1126  break;
1127 
1128  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1129  // Cortex-M0 - ARMv6-M - armv6m
1130  // Cortex-M3 - ARMv7-M - armv7m
1131  // Cortex-M4 - ARMv7E-M - armv7em
1132  case ArchSpec::eCore_arm_armv7em:
1133  if (!enforce_exact_match) {
1134  if (core2 == ArchSpec::eCore_arm_generic)
1135  return true;
1136  if (core2 == ArchSpec::eCore_arm_armv7m)
1137  return true;
1138  if (core2 == ArchSpec::eCore_arm_armv6m)
1139  return true;
1140  if (core2 == ArchSpec::eCore_arm_armv7)
1141  return true;
1142  try_inverse = true;
1143  }
1144  break;
1145 
1146  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1147  // Cortex-M0 - ARMv6-M - armv6m
1148  // Cortex-M3 - ARMv7-M - armv7m
1149  // Cortex-M4 - ARMv7E-M - armv7em
1150  case ArchSpec::eCore_arm_armv7m:
1151  if (!enforce_exact_match) {
1152  if (core2 == ArchSpec::eCore_arm_generic)
1153  return true;
1154  if (core2 == ArchSpec::eCore_arm_armv6m)
1155  return true;
1156  if (core2 == ArchSpec::eCore_arm_armv7)
1157  return true;
1158  if (core2 == ArchSpec::eCore_arm_armv7em)
1159  return true;
1160  try_inverse = true;
1161  }
1162  break;
1163 
1164  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1165  // Cortex-M0 - ARMv6-M - armv6m
1166  // Cortex-M3 - ARMv7-M - armv7m
1167  // Cortex-M4 - ARMv7E-M - armv7em
1168  case ArchSpec::eCore_arm_armv6m:
1169  if (!enforce_exact_match) {
1170  if (core2 == ArchSpec::eCore_arm_generic)
1171  return true;
1172  if (core2 == ArchSpec::eCore_arm_armv7em)
1173  return true;
1174  if (core2 == ArchSpec::eCore_arm_armv7)
1175  return true;
1176  if (core2 == ArchSpec::eCore_arm_armv6m)
1177  return true;
1178  try_inverse = false;
1179  }
1180  break;
1181 
1182  case ArchSpec::eCore_arm_armv7f:
1183  case ArchSpec::eCore_arm_armv7k:
1184  case ArchSpec::eCore_arm_armv7s:
1185  case ArchSpec::eCore_arm_armv7l:
1186  case ArchSpec::eCore_arm_armv8l:
1187  if (!enforce_exact_match) {
1188  if (core2 == ArchSpec::eCore_arm_generic)
1189  return true;
1190  if (core2 == ArchSpec::eCore_arm_armv7)
1191  return true;
1192  try_inverse = false;
1193  }
1194  break;
1195 
1196  case ArchSpec::eCore_x86_64_x86_64h:
1197  if (!enforce_exact_match) {
1198  try_inverse = false;
1199  if (core2 == ArchSpec::eCore_x86_64_x86_64)
1200  return true;
1201  }
1202  break;
1203 
1204  case ArchSpec::eCore_arm_armv8:
1205  if (!enforce_exact_match) {
1206  if (core2 == ArchSpec::eCore_arm_arm64)
1207  return true;
1208  if (core2 == ArchSpec::eCore_arm_aarch64)
1209  return true;
1210  if (core2 == ArchSpec::eCore_arm_arm64e)
1211  return true;
1212  try_inverse = false;
1213  }
1214  break;
1215 
1216  case ArchSpec::eCore_arm_arm64e:
1217  if (!enforce_exact_match) {
1218  if (core2 == ArchSpec::eCore_arm_arm64)
1219  return true;
1220  if (core2 == ArchSpec::eCore_arm_aarch64)
1221  return true;
1222  if (core2 == ArchSpec::eCore_arm_armv8)
1223  return true;
1224  try_inverse = false;
1225  }
1226  break;
1227  case ArchSpec::eCore_arm_aarch64:
1228  if (!enforce_exact_match) {
1229  if (core2 == ArchSpec::eCore_arm_arm64)
1230  return true;
1231  if (core2 == ArchSpec::eCore_arm_armv8)
1232  return true;
1233  if (core2 == ArchSpec::eCore_arm_arm64e)
1234  return true;
1235  try_inverse = false;
1236  }
1237  break;
1238 
1239  case ArchSpec::eCore_arm_arm64:
1240  if (!enforce_exact_match) {
1241  if (core2 == ArchSpec::eCore_arm_aarch64)
1242  return true;
1243  if (core2 == ArchSpec::eCore_arm_armv8)
1244  return true;
1245  if (core2 == ArchSpec::eCore_arm_arm64e)
1246  return true;
1247  try_inverse = false;
1248  }
1249  break;
1250 
1251  case ArchSpec::eCore_arm_arm64_32:
1252  if (!enforce_exact_match) {
1253  if (core2 == ArchSpec::eCore_arm_generic)
1254  return true;
1255  try_inverse = false;
1256  }
1257  break;
1258 
1259  case ArchSpec::eCore_mips32:
1260  if (!enforce_exact_match) {
1261  if (core2 >= ArchSpec::kCore_mips32_first &&
1262  core2 <= ArchSpec::kCore_mips32_last)
1263  return true;
1264  try_inverse = false;
1265  }
1266  break;
1267 
1268  case ArchSpec::eCore_mips32el:
1269  if (!enforce_exact_match) {
1270  if (core2 >= ArchSpec::kCore_mips32el_first &&
1271  core2 <= ArchSpec::kCore_mips32el_last)
1272  return true;
1273  try_inverse = true;
1274  }
1275  break;
1276 
1277  case ArchSpec::eCore_mips64:
1278  if (!enforce_exact_match) {
1279  if (core2 >= ArchSpec::kCore_mips32_first &&
1280  core2 <= ArchSpec::kCore_mips32_last)
1281  return true;
1282  if (core2 >= ArchSpec::kCore_mips64_first &&
1283  core2 <= ArchSpec::kCore_mips64_last)
1284  return true;
1285  try_inverse = false;
1286  }
1287  break;
1288 
1289  case ArchSpec::eCore_mips64el:
1290  if (!enforce_exact_match) {
1291  if (core2 >= ArchSpec::kCore_mips32el_first &&
1292  core2 <= ArchSpec::kCore_mips32el_last)
1293  return true;
1294  if (core2 >= ArchSpec::kCore_mips64el_first &&
1295  core2 <= ArchSpec::kCore_mips64el_last)
1296  return true;
1297  try_inverse = false;
1298  }
1299  break;
1300 
1301  case ArchSpec::eCore_mips64r2:
1302  case ArchSpec::eCore_mips64r3:
1303  case ArchSpec::eCore_mips64r5:
1304  if (!enforce_exact_match) {
1305  if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1306  return true;
1307  if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1308  return true;
1309  try_inverse = false;
1310  }
1311  break;
1312 
1313  case ArchSpec::eCore_mips64r2el:
1314  case ArchSpec::eCore_mips64r3el:
1315  case ArchSpec::eCore_mips64r5el:
1316  if (!enforce_exact_match) {
1317  if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1318  return true;
1319  if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1320  return true;
1321  try_inverse = false;
1322  }
1323  break;
1324 
1325  case ArchSpec::eCore_mips32r2:
1326  case ArchSpec::eCore_mips32r3:
1327  case ArchSpec::eCore_mips32r5:
1328  if (!enforce_exact_match) {
1329  if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1330  return true;
1331  }
1332  break;
1333 
1334  case ArchSpec::eCore_mips32r2el:
1335  case ArchSpec::eCore_mips32r3el:
1336  case ArchSpec::eCore_mips32r5el:
1337  if (!enforce_exact_match) {
1338  if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1339  return true;
1340  }
1341  break;
1342 
1343  case ArchSpec::eCore_mips32r6:
1344  if (!enforce_exact_match) {
1345  if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1346  return true;
1347  }
1348  break;
1349 
1350  case ArchSpec::eCore_mips32r6el:
1351  if (!enforce_exact_match) {
1352  if (core2 == ArchSpec::eCore_mips32el ||
1353  core2 == ArchSpec::eCore_mips32r6el)
1354  return true;
1355  }
1356  break;
1357 
1358  case ArchSpec::eCore_mips64r6:
1359  if (!enforce_exact_match) {
1360  if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1361  return true;
1362  if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1363  return true;
1364  }
1365  break;
1366 
1367  case ArchSpec::eCore_mips64r6el:
1368  if (!enforce_exact_match) {
1369  if (core2 == ArchSpec::eCore_mips32el ||
1370  core2 == ArchSpec::eCore_mips32r6el)
1371  return true;
1372  if (core2 == ArchSpec::eCore_mips64el ||
1373  core2 == ArchSpec::eCore_mips64r6el)
1374  return true;
1375  }
1376  break;
1377 
1378  default:
1379  break;
1380  }
1381  if (try_inverse)
1382  return cores_match(core2, core1, false, enforce_exact_match);
1383  return false;
1384 }
1385 
1386 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1387  const ArchSpec::Core lhs_core = lhs.GetCore();
1388  const ArchSpec::Core rhs_core = rhs.GetCore();
1389  return lhs_core < rhs_core;
1390 }
1391 
1392 
1393 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1394  return lhs.GetCore() == rhs.GetCore();
1395 }
1396 
1397 bool ArchSpec::IsFullySpecifiedTriple() const {
1398  const auto &user_specified_triple = GetTriple();
1399 
1400  bool user_triple_fully_specified = false;
1401 
1402  if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) ||
1403  TripleOSWasSpecified()) {
1404  if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) ||
1405  TripleVendorWasSpecified()) {
1406  const unsigned unspecified = 0;
1407  if (!user_specified_triple.isOSDarwin() ||
1408  user_specified_triple.getOSMajorVersion() != unspecified) {
1409  user_triple_fully_specified = true;
1410  }
1411  }
1412  }
1413 
1414  return user_triple_fully_specified;
1415 }
1416 
1417 void ArchSpec::PiecewiseTripleCompare(
1418  const ArchSpec &other, bool &arch_different, bool &vendor_different,
1419  bool &os_different, bool &os_version_different, bool &env_different) const {
1420  const llvm::Triple &me(GetTriple());
1421  const llvm::Triple &them(other.GetTriple());
1422 
1423  arch_different = (me.getArch() != them.getArch());
1424 
1425  vendor_different = (me.getVendor() != them.getVendor());
1426 
1427  os_different = (me.getOS() != them.getOS());
1428 
1429  os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
1430 
1431  env_different = (me.getEnvironment() != them.getEnvironment());
1432 }
1433 
1434 bool ArchSpec::IsAlwaysThumbInstructions() const {
1436  if (GetTriple().getArch() == llvm::Triple::arm ||
1437  GetTriple().getArch() == llvm::Triple::thumb) {
1438  // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1439  //
1440  // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1441  // execute thumb instructions. We map the cores to arch names like this:
1442  //
1443  // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
1444  // Cortex-M7: armv7em
1445 
1446  if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1447  GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1448  GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1449  GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1450  GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1451  GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1452  return true;
1453  }
1454  // Windows on ARM is always thumb.
1455  if (GetTriple().isOSWindows())
1456  return true;
1457  }
1458  return false;
1459 }
1460 
1461 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1462  const llvm::Triple &triple = GetTriple();
1463  llvm::StringRef arch_str = triple.getArchName();
1464  llvm::StringRef vendor_str = triple.getVendorName();
1465  llvm::StringRef os_str = triple.getOSName();
1466  llvm::StringRef environ_str = triple.getEnvironmentName();
1467 
1468  s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
1469  vendor_str.empty() ? "*" : vendor_str,
1470  os_str.empty() ? "*" : os_str);
1471 
1472  if (!environ_str.empty())
1473  s << "-" << environ_str;
1474 }
1475 
1476 void llvm::yaml::ScalarTraits<ArchSpec>::output(const ArchSpec &Val, void *,
1477  raw_ostream &Out) {
1478  Val.DumpTriple(Out);
1479 }
1480 
1481 llvm::StringRef
1482 llvm::yaml::ScalarTraits<ArchSpec>::input(llvm::StringRef Scalar, void *,
1483  ArchSpec &Val) {
1484  Val = ArchSpec(Scalar);
1485  return {};
1486 }
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lldb::ByteOrder GetByteOrder() const
Returns the byte order for the architecture specification.
Definition: ArchSpec.cpp:730
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Definition: ArchSpec.cpp:445
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Definition: ArchSpec.cpp:34
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Definition: Logging.h:36
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Definition: ArchSpec.h:347
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@ eArchTypeCOFF
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Definition: ArchSpec.cpp:30
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Definition: ArchSpec.cpp:41
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Adds a possible completion string if the completion would complete the current argument.
Definition: CompletionRequest.h:180
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Definition: ArchSpec.cpp:245
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Definition: ArchSpec.h:423
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Definition: ArchSpec.cpp:455
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Definition: Scalar.h:34
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Definition: Logging.h:39
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Definition: ConstString.cpp:302
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Definition: ArchSpec.cpp:266
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Definition: ArchSpec.h:444
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Definition: ArchSpec.cpp:29
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@ eArchTypeMachO
Definition: lldb-private-enumerations.h:63
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Definition: ArchSpec.cpp:481
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Definition: ArchSpec.cpp:1461
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Definition: ArchSpec.cpp:436
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Definition: ArchSpec.cpp:246
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Definition: ArchSpec.cpp:342
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Definition: ArchSpec.cpp:1070
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Definition: ArchSpec.cpp:465
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Definition: ArchSpec.cpp:242
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Definition: ConstString.h:40
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Definition: ArchSpec.h:351
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Definition: ArchSpec.cpp:417
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Definition: ArchSpec.h:353
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Definition: ArchSpec.cpp:243
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Definition: lldb-private-enumerations.h:61
lldb_private::ArchSpec::SetArchitecture
bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os=0)
Change the architecture object type, CPU type and OS type.
Definition: ArchSpec.cpp:843
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Definition: ArchSpec.cpp:28
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Definition: ArchSpec.cpp:273
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Definition: ArchSpec.cpp:252
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Definition: ArchSpec.cpp:241
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Definition: Status.h:44
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@ eByteOrderInvalid
Definition: lldb-enumerations.h:139
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Definition: ArchSpec.cpp:31
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@ eArchTypeELF
Definition: lldb-private-enumerations.h:64
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Definition: lldb-defines.h:31
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Definition: Address.cpp:968
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Definition: ArchSpec.cpp:244
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Definition: ArchSpec.cpp:249
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Definition: HostInfoMacOSX.mm:43
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Definition: SBCommandInterpreterRunOptions.h:16
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Definition: ArchSpec.cpp:351
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Definition: ArchSpec.cpp:448
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Definition: ArchSpec.cpp:32
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@ eByteOrderBig
Definition: lldb-enumerations.h:140
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Definition: ArchSpec.cpp:745
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Definition: Log.h:49
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Definition: Logging.cpp:62
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@ eByteOrderLittle
Definition: lldb-enumerations.h:142
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Definition: Logging.h:15
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Definition: HostInfoMacOSX.mm:46
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Definition: CompletionRequest.h:100
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Byte ordering definitions.
Definition: lldb-enumerations.h:138