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ArchSpec.cpp
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1//===-- ArchSpec.cpp ------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11
12#include "lldb/Utility/Log.h"
14#include "lldb/lldb-defines.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/BinaryFormat/COFF.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/BinaryFormat/MachO.h"
19#include "llvm/Support/ARMTargetParser.h"
20#include "llvm/Support/Compiler.h"
21
22using namespace lldb;
23using namespace lldb_private;
24
25static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
26 bool try_inverse, bool enforce_exact_match);
27
28namespace lldb_private {
29
35 llvm::Triple::ArchType machine;
37 const char *const name;
38};
39
40} // namespace lldb_private
41
42// This core information can be looked using the ArchSpec::Core as the index
44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
45 "arm"},
46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
47 "armv4"},
48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
49 "armv4t"},
50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
51 "armv5"},
52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
53 "armv5e"},
54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
55 "armv5t"},
56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
57 "armv6"},
58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
59 "armv6m"},
60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
61 "armv7"},
62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
63 "armv7l"},
64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
65 "armv7f"},
66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
67 "armv7s"},
68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
69 "armv7k"},
70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
71 "armv7m"},
72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
73 "armv7em"},
74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
75 "xscale"},
76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
77 "thumb"},
78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
79 "thumbv4t"},
80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
81 "thumbv5"},
82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
83 "thumbv5e"},
84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
85 "thumbv6"},
86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
87 "thumbv6m"},
88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
89 "thumbv7"},
90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
91 "thumbv7f"},
92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
93 "thumbv7s"},
94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
95 "thumbv7k"},
96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
97 "thumbv7m"},
98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
99 "thumbv7em"},
100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
104 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
105 "armv8l"},
106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
108 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
109 ArchSpec::eCore_arm_arm64_32, "arm64_32"},
110 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
111 ArchSpec::eCore_arm_aarch64, "aarch64"},
112
113 // mips32, mips32r2, mips32r3, mips32r5, mips32r6
114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
115 "mips"},
116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
117 "mipsr2"},
118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
119 "mipsr3"},
120 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
121 "mipsr5"},
122 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
123 "mipsr6"},
124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
125 "mipsel"},
126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
127 ArchSpec::eCore_mips32r2el, "mipsr2el"},
128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
129 ArchSpec::eCore_mips32r3el, "mipsr3el"},
130 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
131 ArchSpec::eCore_mips32r5el, "mipsr5el"},
132 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
133 ArchSpec::eCore_mips32r6el, "mipsr6el"},
134
135 // mips64, mips64r2, mips64r3, mips64r5, mips64r6
136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
137 "mips64"},
138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
139 "mips64r2"},
140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
141 "mips64r3"},
142 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
143 "mips64r5"},
144 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
145 "mips64r6"},
146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
147 ArchSpec::eCore_mips64el, "mips64el"},
148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
149 ArchSpec::eCore_mips64r2el, "mips64r2el"},
150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
151 ArchSpec::eCore_mips64r3el, "mips64r3el"},
152 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
153 ArchSpec::eCore_mips64r5el, "mips64r5el"},
154 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
155 ArchSpec::eCore_mips64r6el, "mips64r6el"},
156
157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
158 "powerpc"},
159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
160 "ppc601"},
161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
162 "ppc602"},
163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
164 "ppc603"},
165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
166 "ppc603e"},
167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
168 "ppc603ev"},
169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
170 "ppc604"},
171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
172 "ppc604e"},
173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
174 "ppc620"},
175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
176 "ppc750"},
177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
178 "ppc7400"},
179 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
180 "ppc7450"},
181 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
182 "ppc970"},
183
184 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
185 ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
186 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
187 "powerpc64"},
188 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
190
191 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
193
194 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
196 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
198
199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
200 "i386"},
201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
202 "i486"},
203 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
205 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
206 "i686"},
207
208 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
210 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
216 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
218
219 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
220 "riscv32"},
221 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
222 "riscv64"},
223
224 {eByteOrderLittle, 4, 4, 4, llvm::Triple::loongarch32,
225 ArchSpec::eCore_loongarch32, "loongarch32"},
226 {eByteOrderLittle, 8, 4, 4, llvm::Triple::loongarch64,
227 ArchSpec::eCore_loongarch64, "loongarch64"},
228
229 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
230 ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
231 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
232 ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
233 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
234
235 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
236
237 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
238 "wasm32"},
239};
240
241// Ensure that we have an entry in the g_core_definitions for each core. If you
242// comment out an entry above, you will need to comment out the corresponding
243// ArchSpec::Core enumeration.
244static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
246 "make sure we have one core definition for each core");
247
254};
255
260 const char *name;
261};
262
264 for (const auto &def : g_core_definitions)
265 list.AppendString(def.name);
266}
267
269 for (const auto &def : g_core_definitions)
270 request.TryCompleteCurrentArg(def.name);
271}
272
273#define CPU_ANY (UINT32_MAX)
274
275//===----------------------------------------------------------------------===//
276// A table that gets searched linearly for matches. This table is used to
277// convert cpu type and subtypes to architecture names, and to convert
278// architecture names to cpu types and subtypes. The ordering is important and
279// allows the precedence to be set when the table is built.
280#define SUBTYPE_MASK 0x00FFFFFFu
281
282// clang-format off
284 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
285 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
286 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
287 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
288 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
289 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
290 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
291 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
292 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
293 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
294 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
295 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
296 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
297 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
298 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
299 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
300 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
301 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
302 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
303 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK},
304 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK},
305 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK},
306 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
307 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
308 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
309 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
310 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
311 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
312 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
313 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
314 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
315 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
316 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
317 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
318 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
319 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
320 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
321 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
322 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
323 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
324 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
325 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
326 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
327 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
328 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
329 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
330 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
331 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
332 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
333 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
334 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
335 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK},
336 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
337 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
338 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
339 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
340 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
341 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
342 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
343 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
344 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
345 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
346 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
347// clang-format on
348
350 std::size(g_macho_arch_entries),
351 g_macho_arch_entries, "mach-o"};
352
353//===----------------------------------------------------------------------===//
354// A table that gets searched linearly for matches. This table is used to
355// convert cpu type and subtypes to architecture names, and to convert
356// architecture names to cpu types and subtypes. The ordering is important and
357// allows the precedence to be set when the table is built.
360 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
362 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
364 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
366 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
367 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
368 ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
369 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
370 ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
372 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
373 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
374 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
376 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
377 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
378 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
380 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
382 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
383 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
384 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
385 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
386 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
387 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
388 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
389 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
390 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
391 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
392 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
394 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
395 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
396 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
397 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
398 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
399 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
400 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
401 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
402 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
403 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
404 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
405 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
406 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
407 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
408 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
409 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
410 0xFFFFFFFFu}, // AVR
411 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
412 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
413 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
414 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
415 {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH,
417 0xFFFFFFFFu}, // loongarch32
418 {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH,
420 0xFFFFFFFFu}, // loongarch64
421};
422
425 std::size(g_elf_arch_entries),
427 "elf",
428};
429
431 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
432 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
433 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
434 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
435 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
436 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
437 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
438 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
439 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
440 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
441 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
442 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
443 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
444 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
445 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
446 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
447};
448
451 std::size(g_coff_arch_entries),
453 "pe-coff",
454};
455
456//===----------------------------------------------------------------------===//
457// Table of all ArchDefinitions
460
461//===----------------------------------------------------------------------===//
462// Static helper functions.
463
464// Get the architecture definition for a given object type.
466 for (const ArchDefinition *def : g_arch_definitions) {
467 if (def->type == arch_type)
468 return def;
469 }
470 return nullptr;
471}
472
473// Get an architecture definition by name.
474static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
475 for (const auto &def : g_core_definitions) {
476 if (name.equals_insensitive(def.name))
477 return &def;
478 }
479 return nullptr;
480}
481
483 if (core < std::size(g_core_definitions))
484 return &g_core_definitions[core];
485 return nullptr;
486}
487
488// Get a definition entry by cpu type and subtype.
489static const ArchDefinitionEntry *
491 if (def == nullptr)
492 return nullptr;
493
494 const ArchDefinitionEntry *entries = def->entries;
495 for (size_t i = 0; i < def->num_entries; ++i) {
496 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
497 if (entries[i].sub == (sub & entries[i].sub_mask))
498 return &entries[i];
499 }
500 return nullptr;
501}
502
503static const ArchDefinitionEntry *
505 if (def == nullptr)
506 return nullptr;
507
508 const ArchDefinitionEntry *entries = def->entries;
509 for (size_t i = 0; i < def->num_entries; ++i) {
510 if (entries[i].core == core)
511 return &entries[i];
512 }
513 return nullptr;
514}
515
516//===----------------------------------------------------------------------===//
517// Constructors and destructors.
518
519ArchSpec::ArchSpec() = default;
520
521ArchSpec::ArchSpec(const char *triple_cstr) {
522 if (triple_cstr)
523 SetTriple(triple_cstr);
524}
525
526ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
527
528ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
529
531 SetArchitecture(arch_type, cpu, subtype);
532}
533
534ArchSpec::~ArchSpec() = default;
535
537 m_triple = llvm::Triple();
541 m_flags = 0;
542}
543
544//===----------------------------------------------------------------------===//
545// Predicates.
546
547const char *ArchSpec::GetArchitectureName() const {
548 const CoreDefinition *core_def = FindCoreDefinition(m_core);
549 if (core_def)
550 return core_def->name;
551 return "unknown";
552}
553
554bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
555
556std::string ArchSpec::GetTargetABI() const {
557
558 std::string abi;
559
560 if (IsMIPS()) {
561 switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
563 abi = "n64";
564 return abi;
566 abi = "n32";
567 return abi;
569 abi = "o32";
570 return abi;
571 default:
572 return abi;
573 }
574 }
575 return abi;
576}
577
578void ArchSpec::SetFlags(const std::string &elf_abi) {
579
580 uint32_t flag = GetFlags();
581 if (IsMIPS()) {
582 if (elf_abi == "n64")
584 else if (elf_abi == "n32")
586 else if (elf_abi == "o32")
588 }
589 SetFlags(flag);
590}
591
592std::string ArchSpec::GetClangTargetCPU() const {
593 std::string cpu;
594 if (IsMIPS()) {
595 switch (m_core) {
598 cpu = "mips32";
599 break;
602 cpu = "mips32r2";
603 break;
606 cpu = "mips32r3";
607 break;
610 cpu = "mips32r5";
611 break;
614 cpu = "mips32r6";
615 break;
618 cpu = "mips64";
619 break;
622 cpu = "mips64r2";
623 break;
626 cpu = "mips64r3";
627 break;
630 cpu = "mips64r5";
631 break;
634 cpu = "mips64r6";
635 break;
636 default:
637 break;
638 }
639 }
640
641 if (GetTriple().isARM())
642 cpu = llvm::ARM::getARMCPUForArch(GetTriple(), "").str();
643 return cpu;
644}
645
647 const CoreDefinition *core_def = FindCoreDefinition(m_core);
648 if (core_def) {
649 const ArchDefinitionEntry *arch_def =
651 if (arch_def) {
652 return arch_def->cpu;
653 }
654 }
656}
657
659 const CoreDefinition *core_def = FindCoreDefinition(m_core);
660 if (core_def) {
661 const ArchDefinitionEntry *arch_def =
663 if (arch_def) {
664 return arch_def->sub;
665 }
666 }
668}
669
671 return 1;
672}
673
675 return 1;
676}
677
678llvm::Triple::ArchType ArchSpec::GetMachine() const {
679 const CoreDefinition *core_def = FindCoreDefinition(m_core);
680 if (core_def)
681 return core_def->machine;
682
683 return llvm::Triple::UnknownArch;
684}
685
687 return m_distribution_id;
688}
689
690void ArchSpec::SetDistributionId(const char *distribution_id) {
691 m_distribution_id.SetCString(distribution_id);
692}
693
695 const CoreDefinition *core_def = FindCoreDefinition(m_core);
696 if (core_def) {
697 if (core_def->machine == llvm::Triple::mips64 ||
698 core_def->machine == llvm::Triple::mips64el) {
699 // For N32/O32 applications Address size is 4 bytes.
701 return 4;
702 }
703 return core_def->addr_byte_size;
704 }
705 return 0;
706}
707
709 const CoreDefinition *core_def = FindCoreDefinition(m_core);
710 if (core_def)
711 return core_def->default_byte_order;
712 return eByteOrderInvalid;
713}
714
716 switch (m_triple.getArch()) {
717 default:
718 return true;
719
720 case llvm::Triple::aarch64:
721 case llvm::Triple::aarch64_32:
722 case llvm::Triple::aarch64_be:
723 case llvm::Triple::arm:
724 case llvm::Triple::armeb:
725 case llvm::Triple::thumb:
726 case llvm::Triple::thumbeb:
727 return m_triple.isOSDarwin() || m_triple.isOSWindows();
728
729 case llvm::Triple::ppc:
730 case llvm::Triple::ppc64:
731 return m_triple.isOSDarwin();
732
733 case llvm::Triple::ppc64le:
734 case llvm::Triple::systemz:
735 case llvm::Triple::xcore:
736 case llvm::Triple::arc:
737 return false;
738 }
739}
740
743 return GetDefaultEndian();
744 return m_byte_order;
745}
746
747//===----------------------------------------------------------------------===//
748// Mutators.
749
750bool ArchSpec::SetTriple(const llvm::Triple &triple) {
751 m_triple = triple;
752 UpdateCore();
753 return IsValid();
754}
755
756bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
757 ArchSpec &arch) {
758 // Accept "12-10" or "12.10" as cpu type/subtype
759 if (triple_str.empty())
760 return false;
761
762 size_t pos = triple_str.find_first_of("-.");
763 if (pos == llvm::StringRef::npos)
764 return false;
765
766 llvm::StringRef cpu_str = triple_str.substr(0, pos);
767 llvm::StringRef remainder = triple_str.substr(pos + 1);
768 if (cpu_str.empty() || remainder.empty())
769 return false;
770
771 llvm::StringRef sub_str;
772 llvm::StringRef vendor;
773 llvm::StringRef os;
774 std::tie(sub_str, remainder) = remainder.split('-');
775 std::tie(vendor, os) = remainder.split('-');
776
777 uint32_t cpu = 0;
778 uint32_t sub = 0;
779 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
780 return false;
781
782 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
783 return false;
784 if (!vendor.empty() && !os.empty()) {
785 arch.GetTriple().setVendorName(vendor);
786 arch.GetTriple().setOSName(os);
787 }
788
789 return true;
790}
791
792bool ArchSpec::SetTriple(llvm::StringRef triple) {
793 if (triple.empty()) {
794 Clear();
795 return false;
796 }
797
798 if (ParseMachCPUDashSubtypeTriple(triple, *this))
799 return true;
800
801 SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
802 return IsValid();
803}
804
805bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
806 return !normalized_triple.getArchName().empty() &&
807 normalized_triple.getOSName().empty() &&
808 normalized_triple.getVendorName().empty() &&
809 normalized_triple.getEnvironmentName().empty();
810}
811
812void ArchSpec::MergeFrom(const ArchSpec &other) {
813 // ios-macabi always wins over macosx.
814 if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
815 GetTriple().getOS() == llvm::Triple::UnknownOS) &&
816 other.GetTriple().getOS() == llvm::Triple::IOS &&
817 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
818 (*this) = other;
819 return;
820 }
821
823 GetTriple().setVendor(other.GetTriple().getVendor());
825 GetTriple().setOS(other.GetTriple().getOS());
826 if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
827 GetTriple().setArch(other.GetTriple().getArch());
828
829 // MachO unknown64 isn't really invalid as the debugger can still obtain
830 // information from the binary, e.g. line tables. As such, we don't update
831 // the core here.
832 if (other.GetCore() != eCore_uknownMach64)
833 UpdateCore();
834 }
837 GetTriple().setEnvironment(other.GetTriple().getEnvironment());
838 }
839 // If this and other are both arm ArchSpecs and this ArchSpec is a generic
840 // "some kind of arm" spec but the other ArchSpec is a specific arm core,
841 // adopt the specific arm core.
842 if (GetTriple().getArch() == llvm::Triple::arm &&
843 other.GetTriple().getArch() == llvm::Triple::arm &&
846 m_core = other.GetCore();
847 CoreUpdated(false);
848 }
849 if (GetFlags() == 0) {
850 SetFlags(other.GetFlags());
851 }
852}
853
855 uint32_t sub, uint32_t os) {
857 bool update_triple = true;
858 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
859 if (arch_def) {
860 const ArchDefinitionEntry *arch_def_entry =
861 FindArchDefinitionEntry(arch_def, cpu, sub);
862 if (arch_def_entry) {
863 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
864 if (core_def) {
865 m_core = core_def->core;
866 update_triple = false;
867 // Always use the architecture name because it might be more
868 // descriptive than the architecture enum ("armv7" ->
869 // llvm::Triple::arm).
870 m_triple.setArchName(llvm::StringRef(core_def->name));
871 if (arch_type == eArchTypeMachO) {
872 m_triple.setVendor(llvm::Triple::Apple);
873
874 // Don't set the OS. It could be simulator, macosx, ios, watchos,
875 // tvos, bridgeos. We could get close with the cpu type - but we
876 // can't get it right all of the time. Better to leave this unset
877 // so other sections of code will set it when they have more
878 // information. NB: don't call m_triple.setOS
879 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
880 // the ArchSpec::TripleVendorWasSpecified() method says that any
881 // OSName setting means it was specified.
882 } else if (arch_type == eArchTypeELF) {
883 switch (os) {
884 case llvm::ELF::ELFOSABI_AIX:
885 m_triple.setOS(llvm::Triple::OSType::AIX);
886 break;
887 case llvm::ELF::ELFOSABI_FREEBSD:
888 m_triple.setOS(llvm::Triple::OSType::FreeBSD);
889 break;
890 case llvm::ELF::ELFOSABI_GNU:
891 m_triple.setOS(llvm::Triple::OSType::Linux);
892 break;
893 case llvm::ELF::ELFOSABI_NETBSD:
894 m_triple.setOS(llvm::Triple::OSType::NetBSD);
895 break;
896 case llvm::ELF::ELFOSABI_OPENBSD:
897 m_triple.setOS(llvm::Triple::OSType::OpenBSD);
898 break;
899 case llvm::ELF::ELFOSABI_SOLARIS:
900 m_triple.setOS(llvm::Triple::OSType::Solaris);
901 break;
902 }
903 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
904 m_triple.setVendor(llvm::Triple::PC);
905 m_triple.setOS(llvm::Triple::Win32);
906 } else {
907 m_triple.setVendor(llvm::Triple::UnknownVendor);
908 m_triple.setOS(llvm::Triple::UnknownOS);
909 }
910 // Fall back onto setting the machine type if the arch by name
911 // failed...
912 if (m_triple.getArch() == llvm::Triple::UnknownArch)
913 m_triple.setArch(core_def->machine);
914 }
915 } else {
917 LLDB_LOGF(log,
918 "Unable to find a core definition for cpu 0x%" PRIx32
919 " sub %" PRId32,
920 cpu, sub);
921 }
922 }
923 CoreUpdated(update_triple);
924 return IsValid();
925}
926
928 const CoreDefinition *core_def = FindCoreDefinition(m_core);
929 if (core_def)
930 return core_def->min_opcode_byte_size;
931 return 0;
932}
933
935 const CoreDefinition *core_def = FindCoreDefinition(m_core);
936 if (core_def)
937 return core_def->max_opcode_byte_size;
938 return 0;
939}
940
941static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
942 llvm::Triple::EnvironmentType rhs) {
943 if (lhs == rhs)
944 return true;
945
946 // Apple simulators are a different platform than what they simulate.
947 // As the environments are different at this point, if one of them is a
948 // simulator, then they are different.
949 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
950 return false;
951
952 // If any of the environment is unknown then they are compatible
953 if (lhs == llvm::Triple::UnknownEnvironment ||
954 rhs == llvm::Triple::UnknownEnvironment)
955 return true;
956
957 // If one of the environment is Android and the other one is EABI then they
958 // are considered to be compatible. This is required as a workaround for
959 // shared libraries compiled for Android without the NOTE section indicating
960 // that they are using the Android ABI.
961 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
962 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
963 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
964 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
965 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
966 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
967 return true;
968
969 return false;
970}
971
972bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const {
973 // explicitly ignoring m_distribution_id in this method.
974
975 if (GetByteOrder() != rhs.GetByteOrder() ||
976 !cores_match(GetCore(), rhs.GetCore(), true, match == ExactMatch))
977 return false;
978
979 const llvm::Triple &lhs_triple = GetTriple();
980 const llvm::Triple &rhs_triple = rhs.GetTriple();
981
982 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
983 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
984
985 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
986 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
987
988 bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows();
989
990 // On Windows, the vendor field doesn't have any practical effect, but
991 // it is often set to either "pc" or "w64".
992 if ((lhs_triple_vendor != rhs_triple_vendor) &&
993 (match == ExactMatch || !both_windows)) {
994 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
995 const bool lhs_vendor_specified = TripleVendorWasSpecified();
996 // Both architectures had the vendor specified, so if they aren't equal
997 // then we return false
998 if (rhs_vendor_specified && lhs_vendor_specified)
999 return false;
1000
1001 // Only fail if both vendor types are not unknown
1002 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
1003 rhs_triple_vendor != llvm::Triple::UnknownVendor)
1004 return false;
1005 }
1006
1007 const llvm::Triple::EnvironmentType lhs_triple_env =
1008 lhs_triple.getEnvironment();
1009 const llvm::Triple::EnvironmentType rhs_triple_env =
1010 rhs_triple.getEnvironment();
1011
1012 if (match == CompatibleMatch) {
1013 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
1014 if ((lhs_triple_os == llvm::Triple::IOS &&
1015 lhs_triple_env == llvm::Triple::MacABI &&
1016 rhs_triple_os == llvm::Triple::MacOSX) ||
1017 (lhs_triple_os == llvm::Triple::MacOSX &&
1018 rhs_triple_os == llvm::Triple::IOS &&
1019 rhs_triple_env == llvm::Triple::MacABI))
1020 return true;
1021 }
1022
1023 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1024 if (lhs_triple_os == llvm::Triple::IOS &&
1025 rhs_triple_os == llvm::Triple::IOS &&
1026 (lhs_triple_env == llvm::Triple::MacABI ||
1027 rhs_triple_env == llvm::Triple::MacABI) &&
1028 lhs_triple_env != rhs_triple_env)
1029 return false;
1030
1031 if (lhs_triple_os != rhs_triple_os) {
1032 const bool lhs_os_specified = TripleOSWasSpecified();
1033 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1034 // If both OS types are specified and different, fail.
1035 if (lhs_os_specified && rhs_os_specified)
1036 return false;
1037
1038 // If the pair of os+env is both unspecified, match any other os+env combo.
1039 if (match == CompatibleMatch &&
1040 ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1041 (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1042 return true;
1043 }
1044
1045 if (match == CompatibleMatch && both_windows)
1046 return true; // The Windows environments (MSVC vs GNU) are compatible
1047
1048 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1049}
1050
1052 llvm::StringRef arch_name(m_triple.getArchName());
1053 const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1054 if (core_def) {
1055 m_core = core_def->core;
1056 // Set the byte order to the default byte order for an architecture. This
1057 // can be modified if needed for cases when cores handle both big and
1058 // little endian
1059 m_byte_order = core_def->default_byte_order;
1060 } else {
1061 Clear();
1062 }
1063}
1064
1065//===----------------------------------------------------------------------===//
1066// Helper methods.
1067
1068void ArchSpec::CoreUpdated(bool update_triple) {
1069 const CoreDefinition *core_def = FindCoreDefinition(m_core);
1070 if (core_def) {
1071 if (update_triple)
1072 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1073 m_byte_order = core_def->default_byte_order;
1074 } else {
1075 if (update_triple)
1076 m_triple = llvm::Triple();
1078 }
1079}
1080
1081//===----------------------------------------------------------------------===//
1082// Operators.
1083
1084static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1085 bool try_inverse, bool enforce_exact_match) {
1086 if (core1 == core2)
1087 return true;
1088
1089 switch (core1) {
1091 return true;
1092
1094 if (enforce_exact_match)
1095 break;
1096 [[fallthrough]];
1098 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1099 return true;
1100 if (core2 >= ArchSpec::kCore_thumb_first &&
1102 return true;
1103 if (core2 == ArchSpec::kCore_arm_any)
1104 return true;
1105 break;
1106
1108 if ((core2 >= ArchSpec::kCore_x86_32_first &&
1109 core2 <= ArchSpec::kCore_x86_32_last) ||
1110 (core2 == ArchSpec::kCore_x86_32_any))
1111 return true;
1112 break;
1113
1115 if ((core2 >= ArchSpec::kCore_x86_64_first &&
1116 core2 <= ArchSpec::kCore_x86_64_last) ||
1117 (core2 == ArchSpec::kCore_x86_64_any))
1118 return true;
1119 break;
1120
1122 if ((core2 >= ArchSpec::kCore_ppc_first &&
1123 core2 <= ArchSpec::kCore_ppc_last) ||
1124 (core2 == ArchSpec::kCore_ppc_any))
1125 return true;
1126 break;
1127
1129 if ((core2 >= ArchSpec::kCore_ppc64_first &&
1130 core2 <= ArchSpec::kCore_ppc64_last) ||
1131 (core2 == ArchSpec::kCore_ppc64_any))
1132 return true;
1133 break;
1134
1136 if ((core2 >= ArchSpec::kCore_hexagon_first &&
1137 core2 <= ArchSpec::kCore_hexagon_last) ||
1138 (core2 == ArchSpec::kCore_hexagon_any))
1139 return true;
1140 break;
1141
1142 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1143 // Cortex-M0 - ARMv6-M - armv6m
1144 // Cortex-M3 - ARMv7-M - armv7m
1145 // Cortex-M4 - ARMv7E-M - armv7em
1147 if (!enforce_exact_match) {
1148 if (core2 == ArchSpec::eCore_arm_generic)
1149 return true;
1150 if (core2 == ArchSpec::eCore_arm_armv7m)
1151 return true;
1152 if (core2 == ArchSpec::eCore_arm_armv6m)
1153 return true;
1154 if (core2 == ArchSpec::eCore_arm_armv7)
1155 return true;
1156 try_inverse = true;
1157 }
1158 break;
1159
1160 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1161 // Cortex-M0 - ARMv6-M - armv6m
1162 // Cortex-M3 - ARMv7-M - armv7m
1163 // Cortex-M4 - ARMv7E-M - armv7em
1165 if (!enforce_exact_match) {
1166 if (core2 == ArchSpec::eCore_arm_generic)
1167 return true;
1168 if (core2 == ArchSpec::eCore_arm_armv6m)
1169 return true;
1170 if (core2 == ArchSpec::eCore_arm_armv7)
1171 return true;
1172 if (core2 == ArchSpec::eCore_arm_armv7em)
1173 return true;
1174 try_inverse = true;
1175 }
1176 break;
1177
1178 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1179 // Cortex-M0 - ARMv6-M - armv6m
1180 // Cortex-M3 - ARMv7-M - armv7m
1181 // Cortex-M4 - ARMv7E-M - armv7em
1183 if (!enforce_exact_match) {
1184 if (core2 == ArchSpec::eCore_arm_generic)
1185 return true;
1186 if (core2 == ArchSpec::eCore_arm_armv7em)
1187 return true;
1188 if (core2 == ArchSpec::eCore_arm_armv7)
1189 return true;
1190 if (core2 == ArchSpec::eCore_arm_armv6m)
1191 return true;
1192 try_inverse = false;
1193 }
1194 break;
1195
1201 if (!enforce_exact_match) {
1202 if (core2 == ArchSpec::eCore_arm_generic)
1203 return true;
1204 if (core2 == ArchSpec::eCore_arm_armv7)
1205 return true;
1206 try_inverse = false;
1207 }
1208 break;
1209
1211 if (!enforce_exact_match) {
1212 try_inverse = false;
1213 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1214 return true;
1215 }
1216 break;
1217
1219 if (!enforce_exact_match) {
1220 if (core2 == ArchSpec::eCore_arm_arm64)
1221 return true;
1222 if (core2 == ArchSpec::eCore_arm_aarch64)
1223 return true;
1224 if (core2 == ArchSpec::eCore_arm_arm64e)
1225 return true;
1226 try_inverse = false;
1227 }
1228 break;
1229
1231 if (!enforce_exact_match) {
1232 if (core2 == ArchSpec::eCore_arm_arm64)
1233 return true;
1234 if (core2 == ArchSpec::eCore_arm_aarch64)
1235 return true;
1236 if (core2 == ArchSpec::eCore_arm_armv8)
1237 return true;
1238 try_inverse = false;
1239 }
1240 break;
1242 if (!enforce_exact_match) {
1243 if (core2 == ArchSpec::eCore_arm_arm64)
1244 return true;
1245 if (core2 == ArchSpec::eCore_arm_armv8)
1246 return true;
1247 if (core2 == ArchSpec::eCore_arm_arm64e)
1248 return true;
1249 try_inverse = false;
1250 }
1251 break;
1252
1254 if (!enforce_exact_match) {
1255 if (core2 == ArchSpec::eCore_arm_aarch64)
1256 return true;
1257 if (core2 == ArchSpec::eCore_arm_armv8)
1258 return true;
1259 if (core2 == ArchSpec::eCore_arm_arm64e)
1260 return true;
1261 try_inverse = false;
1262 }
1263 break;
1264
1266 if (!enforce_exact_match) {
1267 if (core2 == ArchSpec::eCore_arm_generic)
1268 return true;
1269 try_inverse = false;
1270 }
1271 break;
1272
1274 if (!enforce_exact_match) {
1275 if (core2 >= ArchSpec::kCore_mips32_first &&
1277 return true;
1278 try_inverse = false;
1279 }
1280 break;
1281
1283 if (!enforce_exact_match) {
1284 if (core2 >= ArchSpec::kCore_mips32el_first &&
1286 return true;
1287 try_inverse = true;
1288 }
1289 break;
1290
1292 if (!enforce_exact_match) {
1293 if (core2 >= ArchSpec::kCore_mips32_first &&
1295 return true;
1296 if (core2 >= ArchSpec::kCore_mips64_first &&
1298 return true;
1299 try_inverse = false;
1300 }
1301 break;
1302
1304 if (!enforce_exact_match) {
1305 if (core2 >= ArchSpec::kCore_mips32el_first &&
1307 return true;
1308 if (core2 >= ArchSpec::kCore_mips64el_first &&
1310 return true;
1311 try_inverse = false;
1312 }
1313 break;
1314
1318 if (!enforce_exact_match) {
1319 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1320 return true;
1321 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1322 return true;
1323 try_inverse = false;
1324 }
1325 break;
1326
1330 if (!enforce_exact_match) {
1331 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1332 return true;
1333 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1334 return true;
1335 try_inverse = false;
1336 }
1337 break;
1338
1342 if (!enforce_exact_match) {
1343 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1344 return true;
1345 }
1346 break;
1347
1351 if (!enforce_exact_match) {
1352 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1353 return true;
1354 }
1355 break;
1356
1358 if (!enforce_exact_match) {
1359 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1360 return true;
1361 }
1362 break;
1363
1365 if (!enforce_exact_match) {
1366 if (core2 == ArchSpec::eCore_mips32el ||
1368 return true;
1369 }
1370 break;
1371
1373 if (!enforce_exact_match) {
1374 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1375 return true;
1376 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1377 return true;
1378 }
1379 break;
1380
1382 if (!enforce_exact_match) {
1383 if (core2 == ArchSpec::eCore_mips32el ||
1385 return true;
1386 if (core2 == ArchSpec::eCore_mips64el ||
1388 return true;
1389 }
1390 break;
1391
1392 default:
1393 break;
1394 }
1395 if (try_inverse)
1396 return cores_match(core2, core1, false, enforce_exact_match);
1397 return false;
1398}
1399
1400bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1401 const ArchSpec::Core lhs_core = lhs.GetCore();
1402 const ArchSpec::Core rhs_core = rhs.GetCore();
1403 return lhs_core < rhs_core;
1404}
1405
1406
1407bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1408 return lhs.GetCore() == rhs.GetCore();
1409}
1410
1412 if (!TripleOSWasSpecified())
1413 return false;
1414
1416 return false;
1417
1418 const unsigned unspecified = 0;
1419 const llvm::Triple &triple = GetTriple();
1420 if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified)
1421 return false;
1422
1423 return true;
1424}
1425
1427 const ArchSpec &other, bool &arch_different, bool &vendor_different,
1428 bool &os_different, bool &os_version_different, bool &env_different) const {
1429 const llvm::Triple &me(GetTriple());
1430 const llvm::Triple &them(other.GetTriple());
1431
1432 arch_different = (me.getArch() != them.getArch());
1433
1434 vendor_different = (me.getVendor() != them.getVendor());
1435
1436 os_different = (me.getOS() != them.getOS());
1437
1438 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
1439
1440 env_different = (me.getEnvironment() != them.getEnvironment());
1441}
1442
1444 std::string Status;
1445 if (GetTriple().getArch() == llvm::Triple::arm ||
1446 GetTriple().getArch() == llvm::Triple::thumb) {
1447 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1448 //
1449 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1450 // execute thumb instructions. We map the cores to arch names like this:
1451 //
1452 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
1453 // Cortex-M7: armv7em
1454
1461 return true;
1462 }
1463 // Windows on ARM is always thumb.
1464 if (GetTriple().isOSWindows())
1465 return true;
1466 }
1467 return false;
1468}
1469
1470void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1471 const llvm::Triple &triple = GetTriple();
1472 llvm::StringRef arch_str = triple.getArchName();
1473 llvm::StringRef vendor_str = triple.getVendorName();
1474 llvm::StringRef os_str = triple.getOSName();
1475 llvm::StringRef environ_str = triple.getEnvironmentName();
1476
1477 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
1478 vendor_str.empty() ? "*" : vendor_str,
1479 os_str.empty() ? "*" : os_str);
1480
1481 if (!environ_str.empty())
1482 s << "-" << environ_str;
1483}
#define SUBTYPE_MASK
Definition: ArchSpec.cpp:280
static const ArchDefinition g_elf_arch_def
Definition: ArchSpec.cpp:423
static const CoreDefinition * FindCoreDefinition(llvm::StringRef name)
Definition: ArchSpec.cpp:474
static const ArchDefinitionEntry * FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub)
Definition: ArchSpec.cpp:490
static const ArchDefinitionEntry g_macho_arch_entries[]
Definition: ArchSpec.cpp:283
static const ArchDefinitionEntry g_coff_arch_entries[]
Definition: ArchSpec.cpp:430
static const ArchDefinitionEntry g_elf_arch_entries[]
Definition: ArchSpec.cpp:358
static const ArchDefinition * FindArchDefinition(ArchitectureType arch_type)
Definition: ArchSpec.cpp:465
static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
Definition: ArchSpec.cpp:1084
#define CPU_ANY
Definition: ArchSpec.cpp:273
static const CoreDefinition g_core_definitions[]
Definition: ArchSpec.cpp:43
static const ArchDefinition * g_arch_definitions[]
Definition: ArchSpec.cpp:458
static const ArchDefinition g_coff_arch_def
Definition: ArchSpec.cpp:449
static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, llvm::Triple::EnvironmentType rhs)
Definition: ArchSpec.cpp:941
static const ArchDefinition g_macho_arch_def
Definition: ArchSpec.cpp:349
#define LLDB_LOGF(log,...)
Definition: Log.h:344
An architecture specification class.
Definition: ArchSpec.h:32
static void ListSupportedArchNames(StringList &list)
Definition: ArchSpec.cpp:263
bool IsFullySpecifiedTriple() const
Definition: ArchSpec.cpp:1411
static void AutoComplete(CompletionRequest &request)
Definition: ArchSpec.cpp:268
uint32_t GetAddressByteSize() const
Returns the size in bytes of an address of the current architecture.
Definition: ArchSpec.cpp:694
uint32_t GetCodeByteSize() const
Architecture code byte width accessor.
Definition: ArchSpec.cpp:674
bool IsValid() const
Tests if this ArchSpec is valid.
Definition: ArchSpec.h:361
void Clear()
Clears the object state.
Definition: ArchSpec.cpp:536
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:463
void SetFlags(uint32_t flags)
Definition: ArchSpec.h:541
bool IsAlwaysThumbInstructions() const
Detect whether this architecture uses thumb code exclusively.
Definition: ArchSpec.cpp:1443
bool TripleEnvironmentWasSpecified() const
Definition: ArchSpec.h:372
void SetDistributionId(const char *distribution_id)
Set the distribution id of the architecture.
Definition: ArchSpec.cpp:690
bool IsMatch(const ArchSpec &rhs, MatchType match) const
Compare this ArchSpec to another ArchSpec.
Definition: ArchSpec.cpp:972
bool SetTriple(const llvm::Triple &triple)
Architecture triple setter.
Definition: ArchSpec.cpp:750
llvm::Triple m_triple
Definition: ArchSpec.h:548
lldb::ByteOrder GetDefaultEndian() const
Returns the default endianness of the architecture.
Definition: ArchSpec.cpp:708
lldb::ByteOrder m_byte_order
Definition: ArchSpec.h:550
ConstString m_distribution_id
Definition: ArchSpec.h:556
~ArchSpec()
Destructor.
bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os=0)
Change the architecture object type, CPU type and OS type.
Definition: ArchSpec.cpp:854
void MergeFrom(const ArchSpec &other)
Merges fields from another ArchSpec into this ArchSpec.
Definition: ArchSpec.cpp:812
void DumpTriple(llvm::raw_ostream &s) const
Definition: ArchSpec.cpp:1470
uint32_t GetMachOCPUSubType() const
Definition: ArchSpec.cpp:658
void CoreUpdated(bool update_triple)
Definition: ArchSpec.cpp:1068
bool IsMIPS() const
if MIPS architecture return true.
Definition: ArchSpec.cpp:554
uint32_t GetDataByteSize() const
Architecture data byte width accessor.
Definition: ArchSpec.cpp:670
bool IsCompatibleMatch(const ArchSpec &rhs) const
Shorthand for IsMatch(rhs, CompatibleMatch).
Definition: ArchSpec.h:515
bool CharIsSignedByDefault() const
Returns true if 'char' is a signed type by default in the architecture false otherwise.
Definition: ArchSpec.cpp:715
ArchSpec()
Default constructor.
uint32_t GetMachOCPUType() const
Definition: ArchSpec.cpp:646
std::string GetTargetABI() const
Return a string representing target application ABI.
Definition: ArchSpec.cpp:556
uint32_t GetMinimumOpcodeByteSize() const
Definition: ArchSpec.cpp:927
uint32_t GetFlags() const
Definition: ArchSpec.h:539
ConstString GetDistributionId() const
Returns the distribution id of the architecture.
Definition: ArchSpec.cpp:686
lldb::ByteOrder GetByteOrder() const
Returns the byte order for the architecture specification.
Definition: ArchSpec.cpp:741
llvm::Triple::ArchType GetMachine() const
Returns a machine family for the current architecture.
Definition: ArchSpec.cpp:678
std::string GetClangTargetCPU() const
Returns a string representing current architecture as a target CPU for tools like compiler,...
Definition: ArchSpec.cpp:592
uint32_t GetMaximumOpcodeByteSize() const
Definition: ArchSpec.cpp:934
bool TripleVendorWasSpecified() const
Definition: ArchSpec.h:366
void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, bool &vendor_different, bool &os_different, bool &os_version_different, bool &env_different) const
Definition: ArchSpec.cpp:1426
Core GetCore() const
Definition: ArchSpec.h:442
bool TripleOSWasSpecified() const
Definition: ArchSpec.h:370
static bool ContainsOnlyArch(const llvm::Triple &normalized_triple)
Returns true if the OS, vendor and environment fields of the triple are unset.
Definition: ArchSpec.cpp:805
const char * GetArchitectureName() const
Returns a static string representing the current architecture.
Definition: ArchSpec.cpp:547
"lldb/Utility/ArgCompletionRequest.h"
void TryCompleteCurrentArg(llvm::StringRef completion, llvm::StringRef description="")
Adds a possible completion string if the completion would complete the current argument.
A uniqued constant string class.
Definition: ConstString.h:39
void SetCString(const char *cstr)
Set the C string value.
void Clear()
Clear this object's state.
Definition: ConstString.h:231
An error handling class.
Definition: Status.h:44
void AppendString(const std::string &s)
Definition: StringList.cpp:43
#define LLDB_INVALID_CPUTYPE
Definition: lldb-defines.h:95
#define UINT32_MAX
Definition: lldb-defines.h:19
A class that represents a running process on the host machine.
Log * GetLog(Cat mask)
Retrieve the Log object for the channel associated with the given log enum.
Definition: Log.h:309
bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch)
Definition: ArchSpec.cpp:756
bool operator==(const Address &lhs, const Address &rhs)
Definition: Address.cpp:1016
bool operator<(const Address &lhs, const Address &rhs)
Definition: Address.cpp:985
Definition: SBAddress.h:15
ByteOrder
Byte ordering definitions.
@ eByteOrderInvalid
@ eByteOrderLittle
ArchSpec::Core core
Definition: ArchSpec.cpp:249
ArchitectureType type
Definition: ArchSpec.cpp:257
const ArchDefinitionEntry * entries
Definition: ArchSpec.cpp:259
size_t num_entries
Definition: ArchSpec.cpp:258
const char * name
Definition: ArchSpec.cpp:260
llvm::Triple::ArchType machine
Definition: ArchSpec.cpp:35
const char *const name
Definition: ArchSpec.cpp:37