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RegisterContextDarwin_arm64.cpp
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1 //===-- RegisterContextDarwin_arm64.cpp ---------------------------*- C++
2 //-*-===//
3 //
4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // See https://llvm.org/LICENSE.txt for license information.
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //
8 //===----------------------------------------------------------------------===//
9 
12 
13 #include "lldb/Target/Process.h"
14 #include "lldb/Target/Thread.h"
17 #include "lldb/Utility/Endian.h"
18 #include "lldb/Utility/Log.h"
20 #include "lldb/Utility/Scalar.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Compiler.h"
23 
25 
26 #include <memory>
27 
28 // Support building against older versions of LLVM, this macro was added
29 // recently.
30 #ifndef LLVM_EXTENSION
31 #define LLVM_EXTENSION
32 #endif
33 
35 
36 using namespace lldb;
37 using namespace lldb_private;
38 
39 #define GPR_OFFSET(idx) ((idx)*8)
40 #define GPR_OFFSET_NAME(reg) \
41  (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::GPR, reg))
42 
43 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterContextDarwin_arm64::GPR))
44 #define FPU_OFFSET_NAME(reg) \
45  (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::FPU, reg))
46 
47 #define EXC_OFFSET_NAME(reg) \
48  (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::EXC, reg) + \
49  sizeof(RegisterContextDarwin_arm64::GPR) + \
50  sizeof(RegisterContextDarwin_arm64::FPU))
51 #define DBG_OFFSET_NAME(reg) \
52  (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::DBG, reg) + \
53  sizeof(RegisterContextDarwin_arm64::GPR) + \
54  sizeof(RegisterContextDarwin_arm64::FPU) + \
55  sizeof(RegisterContextDarwin_arm64::EXC))
56 
57 #define DEFINE_DBG(reg, i) \
58  #reg, NULL, \
59  sizeof(((RegisterContextDarwin_arm64::DBG *) NULL)->reg[i]), \
60  DBG_OFFSET_NAME(reg[i]), eEncodingUint, eFormatHex, \
61  {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
62  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
63  LLDB_INVALID_REGNUM }, \
64  NULL, NULL, NULL, 0
65 #define REG_CONTEXT_SIZE \
66  (sizeof(RegisterContextDarwin_arm64::GPR) + \
67  sizeof(RegisterContextDarwin_arm64::FPU) + \
68  sizeof(RegisterContextDarwin_arm64::EXC))
69 
70 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
71 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
72 #include "RegisterInfos_arm64.h"
73 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
74 
75 // General purpose registers
76 static uint32_t g_gpr_regnums[] = {
77  gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6,
78  gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13,
79  gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20,
80  gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27,
81  gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr};
82 
83 // Floating point registers
84 static uint32_t g_fpu_regnums[] = {
85  fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6,
86  fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13,
87  fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20,
88  fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27,
89  fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr};
90 
91 // Exception registers
92 
94 
95 static size_t k_num_register_infos =
96  llvm::array_lengthof(g_register_infos_arm64_le);
97 
99  Thread &thread, uint32_t concrete_frame_idx)
100  : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
101  uint32_t i;
102  for (i = 0; i < kNumErrors; i++) {
103  gpr_errs[i] = -1;
104  fpu_errs[i] = -1;
105  exc_errs[i] = -1;
106  }
107 }
108 
110 
113 }
114 
117  return k_num_registers;
118 }
119 
120 const RegisterInfo *
123  if (reg < k_num_registers)
124  return &g_register_infos_arm64_le[reg];
125  return NULL;
126 }
127 
129  return k_num_register_infos;
130 }
131 
133  return g_register_infos_arm64_le;
134 }
135 
136 // Number of registers in each register set
137 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
138 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
139 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
140 
141 // Register set definitions. The first definitions at register set index of
142 // zero is for all registers, followed by other registers sets. The register
143 // information for the all register set need not be filled in.
144 static const RegisterSet g_reg_sets[] = {
145  {
146  "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
147  },
148  {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
149  {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
150 
151 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
152 
154  return k_num_regsets;
155 }
156 
157 const RegisterSet *RegisterContextDarwin_arm64::GetRegisterSet(size_t reg_set) {
158  if (reg_set < k_num_regsets)
159  return &g_reg_sets[reg_set];
160  return NULL;
161 }
162 
163 // Register information definitions for arm64
165  if (reg < fpu_v0)
166  return GPRRegSet;
167  else if (reg < exc_far)
168  return FPURegSet;
169  else if (reg < k_num_registers)
170  return EXCRegSet;
171  return -1;
172 }
173 
175  int set = GPRRegSet;
176  if (force || !RegisterSetIsCached(set)) {
177  SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
178  }
179  return GetError(GPRRegSet, Read);
180 }
181 
183  int set = FPURegSet;
184  if (force || !RegisterSetIsCached(set)) {
185  SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
186  }
187  return GetError(FPURegSet, Read);
188 }
189 
191  int set = EXCRegSet;
192  if (force || !RegisterSetIsCached(set)) {
193  SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
194  }
195  return GetError(EXCRegSet, Read);
196 }
197 
199  int set = DBGRegSet;
200  if (force || !RegisterSetIsCached(set)) {
201  SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg));
202  }
203  return GetError(DBGRegSet, Read);
204 }
205 
207  int set = GPRRegSet;
208  if (!RegisterSetIsCached(set)) {
209  SetError(set, Write, -1);
210  return KERN_INVALID_ARGUMENT;
211  }
212  SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
213  SetError(set, Read, -1);
214  return GetError(GPRRegSet, Write);
215 }
216 
218  int set = FPURegSet;
219  if (!RegisterSetIsCached(set)) {
220  SetError(set, Write, -1);
221  return KERN_INVALID_ARGUMENT;
222  }
223  SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
224  SetError(set, Read, -1);
225  return GetError(FPURegSet, Write);
226 }
227 
229  int set = EXCRegSet;
230  if (!RegisterSetIsCached(set)) {
231  SetError(set, Write, -1);
232  return KERN_INVALID_ARGUMENT;
233  }
234  SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
235  SetError(set, Read, -1);
236  return GetError(EXCRegSet, Write);
237 }
238 
240  int set = DBGRegSet;
241  if (!RegisterSetIsCached(set)) {
242  SetError(set, Write, -1);
243  return KERN_INVALID_ARGUMENT;
244  }
245  SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg));
246  SetError(set, Read, -1);
247  return GetError(DBGRegSet, Write);
248 }
249 
251  switch (set) {
252  case GPRRegSet:
253  return ReadGPR(force);
254  case FPURegSet:
255  return ReadFPU(force);
256  case EXCRegSet:
257  return ReadEXC(force);
258  case DBGRegSet:
259  return ReadDBG(force);
260  default:
261  break;
262  }
263  return KERN_INVALID_ARGUMENT;
264 }
265 
267  // Make sure we have a valid context to set.
268  if (RegisterSetIsCached(set)) {
269  switch (set) {
270  case GPRRegSet:
271  return WriteGPR();
272  case FPURegSet:
273  return WriteFPU();
274  case EXCRegSet:
275  return WriteEXC();
276  case DBGRegSet:
277  return WriteDBG();
278  default:
279  break;
280  }
281  }
282  return KERN_INVALID_ARGUMENT;
283 }
284 
286  if (log) {
287  for (uint32_t i = 0; i < 16; i++)
288  log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64
289  " } WVR%-2u/WCR%-2u "
290  "= { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 " }",
291  i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]);
292  }
293 }
294 
295 bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
296  RegisterValue &value) {
297  const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
299 
300  if (set == -1)
301  return false;
302 
303  if (ReadRegisterSet(set, false) != KERN_SUCCESS)
304  return false;
305 
306  switch (reg) {
307  case gpr_x0:
308  case gpr_x1:
309  case gpr_x2:
310  case gpr_x3:
311  case gpr_x4:
312  case gpr_x5:
313  case gpr_x6:
314  case gpr_x7:
315  case gpr_x8:
316  case gpr_x9:
317  case gpr_x10:
318  case gpr_x11:
319  case gpr_x12:
320  case gpr_x13:
321  case gpr_x14:
322  case gpr_x15:
323  case gpr_x16:
324  case gpr_x17:
325  case gpr_x18:
326  case gpr_x19:
327  case gpr_x20:
328  case gpr_x21:
329  case gpr_x22:
330  case gpr_x23:
331  case gpr_x24:
332  case gpr_x25:
333  case gpr_x26:
334  case gpr_x27:
335  case gpr_x28:
336  value.SetUInt64(gpr.x[reg - gpr_x0]);
337  break;
338  case gpr_fp:
339  value.SetUInt64(gpr.fp);
340  break;
341  case gpr_sp:
342  value.SetUInt64(gpr.sp);
343  break;
344  case gpr_lr:
345  value.SetUInt64(gpr.lr);
346  break;
347  case gpr_pc:
348  value.SetUInt64(gpr.pc);
349  break;
350  case gpr_cpsr:
351  value.SetUInt64(gpr.cpsr);
352  break;
353 
354  case gpr_w0:
355  case gpr_w1:
356  case gpr_w2:
357  case gpr_w3:
358  case gpr_w4:
359  case gpr_w5:
360  case gpr_w6:
361  case gpr_w7:
362  case gpr_w8:
363  case gpr_w9:
364  case gpr_w10:
365  case gpr_w11:
366  case gpr_w12:
367  case gpr_w13:
368  case gpr_w14:
369  case gpr_w15:
370  case gpr_w16:
371  case gpr_w17:
372  case gpr_w18:
373  case gpr_w19:
374  case gpr_w20:
375  case gpr_w21:
376  case gpr_w22:
377  case gpr_w23:
378  case gpr_w24:
379  case gpr_w25:
380  case gpr_w26:
381  case gpr_w27:
382  case gpr_w28: {
383  ProcessSP process_sp(m_thread.GetProcess());
384  if (process_sp.get()) {
385  DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(),
386  process_sp->GetAddressByteSize());
387  offset_t offset = 0;
388  uint64_t retval = regdata.GetMaxU64(&offset, 8);
389  uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff);
390  value.SetUInt32(retval_lower32);
391  }
392  } break;
393 
394  case fpu_v0:
395  case fpu_v1:
396  case fpu_v2:
397  case fpu_v3:
398  case fpu_v4:
399  case fpu_v5:
400  case fpu_v6:
401  case fpu_v7:
402  case fpu_v8:
403  case fpu_v9:
404  case fpu_v10:
405  case fpu_v11:
406  case fpu_v12:
407  case fpu_v13:
408  case fpu_v14:
409  case fpu_v15:
410  case fpu_v16:
411  case fpu_v17:
412  case fpu_v18:
413  case fpu_v19:
414  case fpu_v20:
415  case fpu_v21:
416  case fpu_v22:
417  case fpu_v23:
418  case fpu_v24:
419  case fpu_v25:
420  case fpu_v26:
421  case fpu_v27:
422  case fpu_v28:
423  case fpu_v29:
424  case fpu_v30:
425  case fpu_v31:
426  value.SetBytes(fpu.v[reg - fpu_v0].bytes.buffer, reg_info->byte_size,
428  break;
429 
430  case fpu_s0:
431  case fpu_s1:
432  case fpu_s2:
433  case fpu_s3:
434  case fpu_s4:
435  case fpu_s5:
436  case fpu_s6:
437  case fpu_s7:
438  case fpu_s8:
439  case fpu_s9:
440  case fpu_s10:
441  case fpu_s11:
442  case fpu_s12:
443  case fpu_s13:
444  case fpu_s14:
445  case fpu_s15:
446  case fpu_s16:
447  case fpu_s17:
448  case fpu_s18:
449  case fpu_s19:
450  case fpu_s20:
451  case fpu_s21:
452  case fpu_s22:
453  case fpu_s23:
454  case fpu_s24:
455  case fpu_s25:
456  case fpu_s26:
457  case fpu_s27:
458  case fpu_s28:
459  case fpu_s29:
460  case fpu_s30:
461  case fpu_s31: {
462  ProcessSP process_sp(m_thread.GetProcess());
463  if (process_sp.get()) {
464  DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(),
465  process_sp->GetAddressByteSize());
466  offset_t offset = 0;
467  value.SetFloat(regdata.GetFloat(&offset));
468  }
469  } break;
470 
471  case fpu_d0:
472  case fpu_d1:
473  case fpu_d2:
474  case fpu_d3:
475  case fpu_d4:
476  case fpu_d5:
477  case fpu_d6:
478  case fpu_d7:
479  case fpu_d8:
480  case fpu_d9:
481  case fpu_d10:
482  case fpu_d11:
483  case fpu_d12:
484  case fpu_d13:
485  case fpu_d14:
486  case fpu_d15:
487  case fpu_d16:
488  case fpu_d17:
489  case fpu_d18:
490  case fpu_d19:
491  case fpu_d20:
492  case fpu_d21:
493  case fpu_d22:
494  case fpu_d23:
495  case fpu_d24:
496  case fpu_d25:
497  case fpu_d26:
498  case fpu_d27:
499  case fpu_d28:
500  case fpu_d29:
501  case fpu_d30:
502  case fpu_d31: {
503  ProcessSP process_sp(m_thread.GetProcess());
504  if (process_sp.get()) {
505  DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(),
506  process_sp->GetAddressByteSize());
507  offset_t offset = 0;
508  value.SetDouble(regdata.GetDouble(&offset));
509  }
510  } break;
511 
512  case fpu_fpsr:
513  value.SetUInt32(fpu.fpsr);
514  break;
515 
516  case fpu_fpcr:
517  value.SetUInt32(fpu.fpcr);
518  break;
519 
520  case exc_exception:
521  value.SetUInt32(exc.exception);
522  break;
523  case exc_esr:
524  value.SetUInt32(exc.esr);
525  break;
526  case exc_far:
527  value.SetUInt64(exc.far);
528  break;
529 
530  default:
531  value.SetValueToInvalid();
532  return false;
533  }
534  return true;
535 }
536 
537 bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info,
538  const RegisterValue &value) {
539  const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
540  int set = GetSetForNativeRegNum(reg);
541 
542  if (set == -1)
543  return false;
544 
545  if (ReadRegisterSet(set, false) != KERN_SUCCESS)
546  return false;
547 
548  switch (reg) {
549  case gpr_x0:
550  case gpr_x1:
551  case gpr_x2:
552  case gpr_x3:
553  case gpr_x4:
554  case gpr_x5:
555  case gpr_x6:
556  case gpr_x7:
557  case gpr_x8:
558  case gpr_x9:
559  case gpr_x10:
560  case gpr_x11:
561  case gpr_x12:
562  case gpr_x13:
563  case gpr_x14:
564  case gpr_x15:
565  case gpr_x16:
566  case gpr_x17:
567  case gpr_x18:
568  case gpr_x19:
569  case gpr_x20:
570  case gpr_x21:
571  case gpr_x22:
572  case gpr_x23:
573  case gpr_x24:
574  case gpr_x25:
575  case gpr_x26:
576  case gpr_x27:
577  case gpr_x28:
578  case gpr_fp:
579  case gpr_sp:
580  case gpr_lr:
581  case gpr_pc:
582  case gpr_cpsr:
583  gpr.x[reg - gpr_x0] = value.GetAsUInt64();
584  break;
585 
586  case fpu_v0:
587  case fpu_v1:
588  case fpu_v2:
589  case fpu_v3:
590  case fpu_v4:
591  case fpu_v5:
592  case fpu_v6:
593  case fpu_v7:
594  case fpu_v8:
595  case fpu_v9:
596  case fpu_v10:
597  case fpu_v11:
598  case fpu_v12:
599  case fpu_v13:
600  case fpu_v14:
601  case fpu_v15:
602  case fpu_v16:
603  case fpu_v17:
604  case fpu_v18:
605  case fpu_v19:
606  case fpu_v20:
607  case fpu_v21:
608  case fpu_v22:
609  case fpu_v23:
610  case fpu_v24:
611  case fpu_v25:
612  case fpu_v26:
613  case fpu_v27:
614  case fpu_v28:
615  case fpu_v29:
616  case fpu_v30:
617  case fpu_v31:
618  ::memcpy(fpu.v[reg - fpu_v0].bytes.buffer, value.GetBytes(),
619  value.GetByteSize());
620  break;
621 
622  case fpu_fpsr:
623  fpu.fpsr = value.GetAsUInt32();
624  break;
625 
626  case fpu_fpcr:
627  fpu.fpcr = value.GetAsUInt32();
628  break;
629 
630  case exc_exception:
631  exc.exception = value.GetAsUInt32();
632  break;
633  case exc_esr:
634  exc.esr = value.GetAsUInt32();
635  break;
636  case exc_far:
637  exc.far = value.GetAsUInt64();
638  break;
639 
640  default:
641  return false;
642  }
643  return WriteRegisterSet(set) == KERN_SUCCESS;
644 }
645 
647  lldb::DataBufferSP &data_sp) {
648  data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
649  if (data_sp && ReadGPR(false) == KERN_SUCCESS &&
650  ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) {
651  uint8_t *dst = data_sp->GetBytes();
652  ::memcpy(dst, &gpr, sizeof(gpr));
653  dst += sizeof(gpr);
654 
655  ::memcpy(dst, &fpu, sizeof(fpu));
656  dst += sizeof(gpr);
657 
658  ::memcpy(dst, &exc, sizeof(exc));
659  return true;
660  }
661  return false;
662 }
663 
665  const lldb::DataBufferSP &data_sp) {
666  if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
667  const uint8_t *src = data_sp->GetBytes();
668  ::memcpy(&gpr, src, sizeof(gpr));
669  src += sizeof(gpr);
670 
671  ::memcpy(&fpu, src, sizeof(fpu));
672  src += sizeof(gpr);
673 
674  ::memcpy(&exc, src, sizeof(exc));
675  uint32_t success_count = 0;
676  if (WriteGPR() == KERN_SUCCESS)
677  ++success_count;
678  if (WriteFPU() == KERN_SUCCESS)
679  ++success_count;
680  if (WriteEXC() == KERN_SUCCESS)
681  ++success_count;
682  return success_count == 3;
683  }
684  return false;
685 }
686 
688  RegisterKind kind, uint32_t reg) {
689  if (kind == eRegisterKindGeneric) {
690  switch (reg) {
692  return gpr_pc;
694  return gpr_sp;
696  return gpr_fp;
698  return gpr_lr;
700  return gpr_cpsr;
701  default:
702  break;
703  }
704  } else if (kind == eRegisterKindDWARF) {
705  switch (reg) {
706  case arm64_dwarf::x0:
707  return gpr_x0;
708  case arm64_dwarf::x1:
709  return gpr_x1;
710  case arm64_dwarf::x2:
711  return gpr_x2;
712  case arm64_dwarf::x3:
713  return gpr_x3;
714  case arm64_dwarf::x4:
715  return gpr_x4;
716  case arm64_dwarf::x5:
717  return gpr_x5;
718  case arm64_dwarf::x6:
719  return gpr_x6;
720  case arm64_dwarf::x7:
721  return gpr_x7;
722  case arm64_dwarf::x8:
723  return gpr_x8;
724  case arm64_dwarf::x9:
725  return gpr_x9;
726  case arm64_dwarf::x10:
727  return gpr_x10;
728  case arm64_dwarf::x11:
729  return gpr_x11;
730  case arm64_dwarf::x12:
731  return gpr_x12;
732  case arm64_dwarf::x13:
733  return gpr_x13;
734  case arm64_dwarf::x14:
735  return gpr_x14;
736  case arm64_dwarf::x15:
737  return gpr_x15;
738  case arm64_dwarf::x16:
739  return gpr_x16;
740  case arm64_dwarf::x17:
741  return gpr_x17;
742  case arm64_dwarf::x18:
743  return gpr_x18;
744  case arm64_dwarf::x19:
745  return gpr_x19;
746  case arm64_dwarf::x20:
747  return gpr_x20;
748  case arm64_dwarf::x21:
749  return gpr_x21;
750  case arm64_dwarf::x22:
751  return gpr_x22;
752  case arm64_dwarf::x23:
753  return gpr_x23;
754  case arm64_dwarf::x24:
755  return gpr_x24;
756  case arm64_dwarf::x25:
757  return gpr_x25;
758  case arm64_dwarf::x26:
759  return gpr_x26;
760  case arm64_dwarf::x27:
761  return gpr_x27;
762  case arm64_dwarf::x28:
763  return gpr_x28;
764 
765  case arm64_dwarf::fp:
766  return gpr_fp;
767  case arm64_dwarf::sp:
768  return gpr_sp;
769  case arm64_dwarf::lr:
770  return gpr_lr;
771  case arm64_dwarf::pc:
772  return gpr_pc;
773  case arm64_dwarf::cpsr:
774  return gpr_cpsr;
775 
776  case arm64_dwarf::v0:
777  return fpu_v0;
778  case arm64_dwarf::v1:
779  return fpu_v1;
780  case arm64_dwarf::v2:
781  return fpu_v2;
782  case arm64_dwarf::v3:
783  return fpu_v3;
784  case arm64_dwarf::v4:
785  return fpu_v4;
786  case arm64_dwarf::v5:
787  return fpu_v5;
788  case arm64_dwarf::v6:
789  return fpu_v6;
790  case arm64_dwarf::v7:
791  return fpu_v7;
792  case arm64_dwarf::v8:
793  return fpu_v8;
794  case arm64_dwarf::v9:
795  return fpu_v9;
796  case arm64_dwarf::v10:
797  return fpu_v10;
798  case arm64_dwarf::v11:
799  return fpu_v11;
800  case arm64_dwarf::v12:
801  return fpu_v12;
802  case arm64_dwarf::v13:
803  return fpu_v13;
804  case arm64_dwarf::v14:
805  return fpu_v14;
806  case arm64_dwarf::v15:
807  return fpu_v15;
808  case arm64_dwarf::v16:
809  return fpu_v16;
810  case arm64_dwarf::v17:
811  return fpu_v17;
812  case arm64_dwarf::v18:
813  return fpu_v18;
814  case arm64_dwarf::v19:
815  return fpu_v19;
816  case arm64_dwarf::v20:
817  return fpu_v20;
818  case arm64_dwarf::v21:
819  return fpu_v21;
820  case arm64_dwarf::v22:
821  return fpu_v22;
822  case arm64_dwarf::v23:
823  return fpu_v23;
824  case arm64_dwarf::v24:
825  return fpu_v24;
826  case arm64_dwarf::v25:
827  return fpu_v25;
828  case arm64_dwarf::v26:
829  return fpu_v26;
830  case arm64_dwarf::v27:
831  return fpu_v27;
832  case arm64_dwarf::v28:
833  return fpu_v28;
834  case arm64_dwarf::v29:
835  return fpu_v29;
836  case arm64_dwarf::v30:
837  return fpu_v30;
838  case arm64_dwarf::v31:
839  return fpu_v31;
840 
841  default:
842  break;
843  }
844  } else if (kind == eRegisterKindEHFrame) {
845  switch (reg) {
846  case arm64_ehframe::x0:
847  return gpr_x0;
848  case arm64_ehframe::x1:
849  return gpr_x1;
850  case arm64_ehframe::x2:
851  return gpr_x2;
852  case arm64_ehframe::x3:
853  return gpr_x3;
854  case arm64_ehframe::x4:
855  return gpr_x4;
856  case arm64_ehframe::x5:
857  return gpr_x5;
858  case arm64_ehframe::x6:
859  return gpr_x6;
860  case arm64_ehframe::x7:
861  return gpr_x7;
862  case arm64_ehframe::x8:
863  return gpr_x8;
864  case arm64_ehframe::x9:
865  return gpr_x9;
866  case arm64_ehframe::x10:
867  return gpr_x10;
868  case arm64_ehframe::x11:
869  return gpr_x11;
870  case arm64_ehframe::x12:
871  return gpr_x12;
872  case arm64_ehframe::x13:
873  return gpr_x13;
874  case arm64_ehframe::x14:
875  return gpr_x14;
876  case arm64_ehframe::x15:
877  return gpr_x15;
878  case arm64_ehframe::x16:
879  return gpr_x16;
880  case arm64_ehframe::x17:
881  return gpr_x17;
882  case arm64_ehframe::x18:
883  return gpr_x18;
884  case arm64_ehframe::x19:
885  return gpr_x19;
886  case arm64_ehframe::x20:
887  return gpr_x20;
888  case arm64_ehframe::x21:
889  return gpr_x21;
890  case arm64_ehframe::x22:
891  return gpr_x22;
892  case arm64_ehframe::x23:
893  return gpr_x23;
894  case arm64_ehframe::x24:
895  return gpr_x24;
896  case arm64_ehframe::x25:
897  return gpr_x25;
898  case arm64_ehframe::x26:
899  return gpr_x26;
900  case arm64_ehframe::x27:
901  return gpr_x27;
902  case arm64_ehframe::x28:
903  return gpr_x28;
904  case arm64_ehframe::fp:
905  return gpr_fp;
906  case arm64_ehframe::sp:
907  return gpr_sp;
908  case arm64_ehframe::lr:
909  return gpr_lr;
910  case arm64_ehframe::pc:
911  return gpr_pc;
912  case arm64_ehframe::cpsr:
913  return gpr_cpsr;
914  }
915  } else if (kind == eRegisterKindLLDB) {
916  return reg;
917  }
918  return LLDB_INVALID_REGNUM;
919 }
920 
922 #if defined(__APPLE__) && (defined(__arm64__) || defined(__aarch64__))
923  // autodetect how many watchpoints are supported dynamically...
924  static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX;
925  if (g_num_supported_hw_watchpoints == UINT32_MAX) {
926  size_t len;
927  uint32_t n = 0;
928  len = sizeof(n);
929  if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) {
930  g_num_supported_hw_watchpoints = n;
931  }
932  }
933  return g_num_supported_hw_watchpoints;
934 #else
935  // TODO: figure out remote case here!
936  return 2;
937 #endif
938 }
939 
941  size_t size,
942  bool read,
943  bool write) {
944  // if (log) log->Printf
945  // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(addr = %8.8p,
946  // size = %u, read = %u, write = %u)", addr, size, read, write);
947 
948  const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
949 
950  // Can't watch zero bytes
951  if (size == 0)
952  return LLDB_INVALID_INDEX32;
953 
954  // We must watch for either read or write
955  if (!read && !write)
956  return LLDB_INVALID_INDEX32;
957 
958  // Can't watch more than 4 bytes per WVR/WCR pair
959  if (size > 4)
960  return LLDB_INVALID_INDEX32;
961 
962  // We can only watch up to four bytes that follow a 4 byte aligned address
963  // per watchpoint register pair. Since we have at most so we can only watch
964  // until the next 4 byte boundary and we need to make sure we can properly
965  // encode this.
966  uint32_t addr_word_offset = addr % 4;
967  // if (log) log->Printf
968  // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() -
969  // addr_word_offset = 0x%8.8x", addr_word_offset);
970 
971  uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset;
972  // if (log) log->Printf
973  // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - byte_mask =
974  // 0x%8.8x", byte_mask);
975  if (byte_mask > 0xfu)
976  return LLDB_INVALID_INDEX32;
977 
978  // Read the debug state
979  int kret = ReadDBG(false);
980 
981  if (kret == KERN_SUCCESS) {
982  // Check to make sure we have the needed hardware support
983  uint32_t i = 0;
984 
985  for (i = 0; i < num_hw_watchpoints; ++i) {
986  if ((dbg.wcr[i] & WCR_ENABLE) == 0)
987  break; // We found an available hw breakpoint slot (in i)
988  }
989 
990  // See if we found an available hw breakpoint slot above
991  if (i < num_hw_watchpoints) {
992  // Make the byte_mask into a valid Byte Address Select mask
993  uint32_t byte_address_select = byte_mask << 5;
994  // Make sure bits 1:0 are clear in our address
995  dbg.wvr[i] = addr & ~((lldb::addr_t)3);
996  dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA
997  // that we will watch
998  S_USER | // Stop only in user mode
999  (read ? WCR_LOAD : 0) | // Stop on read access?
1000  (write ? WCR_STORE : 0) | // Stop on write access?
1001  WCR_ENABLE; // Enable this watchpoint;
1002 
1003  kret = WriteDBG();
1004  // if (log) log->Printf
1005  // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint()
1006  // WriteDBG() => 0x%8.8x.", kret);
1007 
1008  if (kret == KERN_SUCCESS)
1009  return i;
1010  } else {
1011  // if (log) log->Printf
1012  // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint():
1013  // All hardware resources (%u) are in use.",
1014  // num_hw_watchpoints);
1015  }
1016  }
1017  return LLDB_INVALID_INDEX32;
1018 }
1019 
1021  int kret = ReadDBG(false);
1022 
1023  const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1024  if (kret == KERN_SUCCESS) {
1025  if (hw_index < num_hw_points) {
1026  dbg.wcr[hw_index] = 0;
1027  // if (log) log->Printf
1028  // ("RegisterContextDarwin_arm64::ClearHardwareWatchpoint( %u )
1029  // - WVR%u = 0x%8.8x WCR%u = 0x%8.8x",
1030  // hw_index,
1031  // hw_index,
1032  // dbg.wvr[hw_index],
1033  // hw_index,
1034  // dbg.wcr[hw_index]);
1035 
1036  kret = WriteDBG();
1037 
1038  if (kret == KERN_SUCCESS)
1039  return true;
1040  }
1041  }
1042  return false;
1043 }
RegisterContextDarwin_arm64(lldb_private::Thread &thread, uint32_t concrete_frame_idx)
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:63
An data extractor class.
Definition: DataExtractor.h:47
Enumerations for broadcasting.
Definition: SBLaunchInfo.h:14
const size_t k_num_regsets
virtual int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc)=0
virtual int DoWriteDBG(lldb::tid_t tid, int flavor, const DBG &dbg)=0
#define WCR_STORE
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:66
virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu)=0
virtual int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc)=0
#define REG_CONTEXT_SIZE
bool ClearHardwareWatchpoint(uint32_t hw_index) override
int ReadRegisterSet(uint32_t set, bool force)
#define WCR_LOAD
static const RegisterSet g_reg_sets[]
virtual int DoReadDBG(lldb::tid_t tid, int flavor, DBG &dbg)=0
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:64
bool WriteRegister(const lldb_private::RegisterInfo *reg_info, const lldb_private::RegisterValue &reg_value) override
static int GetSetForNativeRegNum(int reg_num)
virtual int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr)
bool SetError(int flavor, uint32_t err_idx, int err)
int GetError(int flavor, uint32_t err_idx) const
uint64_t GetAsUInt64(uint64_t fail_value=UINT64_MAX, bool *success_ptr=nullptr) const
void SetUInt64(uint64_t uint, Type t=eTypeUInt64)
const size_t k_num_gpr_registers
const lldb_private::RegisterSet * GetRegisterSet(size_t set) override
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:65
#define UINT32_MAX
Definition: lldb-defines.h:31
#define S_USER
bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override
#define LLDB_INVALID_INDEX32
Definition: lldb-defines.h:86
uint64_t offset_t
Definition: lldb-types.h:87
static void LogDBGRegisters(lldb_private::Log *log, const DBG &dbg)
#define KERN_INVALID_ARGUMENT
uint32_t SetHardwareWatchpoint(lldb::addr_t addr, size_t size, bool read, bool write) override
static uint32_t g_exc_regnums[]
#define WCR_ENABLE
static uint32_t g_gpr_regnums[]
virtual lldb::tid_t GetThreadID() const
const void * GetBytes() const
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:67
llvm::AlignedCharArray< 16, 16 > bytes
void SetUInt32(uint32_t uint, Type t=eTypeUInt32)
lldb::ProcessSP GetProcess() const
Definition: Thread.h:154
uint64_t GetMaxU64(lldb::offset_t *offset_ptr, size_t byte_size) const
Extract an unsigned integer of size byte_size from *offset_ptr.
uint32_t GetAsUInt32(uint32_t fail_value=UINT32_MAX, bool *success_ptr=nullptr) const
const size_t k_num_exc_registers
virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu)=0
bool ReadRegister(const lldb_private::RegisterInfo *reg_info, lldb_private::RegisterValue &reg_value) override
static uint32_t g_fpu_regnums[]
uint64_t addr_t
Definition: lldb-types.h:83
const lldb_private::RegisterInfo * GetRegisterInfoAtIndex(size_t reg) override
Definition: SBAddress.h:15
void SetBytes(const void *bytes, size_t length, lldb::ByteOrder byte_order)
const size_t k_num_fpu_registers
uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, uint32_t num) override
Convert from a given register numbering scheme to the lldb register numbering scheme.
virtual int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr)=0
lldb::ByteOrder InlHostByteOrder()
Definition: Endian.h:25
void Printf(const char *format,...) __attribute__((format(printf
Definition: Log.cpp:113
static size_t k_num_register_infos
#define KERN_SUCCESS
Constants returned by various RegisterContextDarwin_*** functions.
bool ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override
static const lldb_private::RegisterInfo * GetRegisterInfos()
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:90