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RegisterContextDarwin_i386.cpp
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1//===-- RegisterContextDarwin_i386.cpp ------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "lldb/Utility/Endian.h"
12#include "lldb/Utility/Log.h"
14#include "lldb/Utility/Scalar.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/Support/Compiler.h"
17
18#include <cstddef>
19
20#include <memory>
21
23
24using namespace lldb;
25using namespace lldb_private;
26
27enum {
44
71
75
77
78 // Aliases
86};
87
88enum {
99};
100
101enum {
129
130#define GPR_OFFSET(reg) \
131 (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::GPR, reg))
132#define FPU_OFFSET(reg) \
133 (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::FPU, reg) + \
134 sizeof(RegisterContextDarwin_i386::GPR))
135#define EXC_OFFSET(reg) \
136 (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::EXC, reg) + \
137 sizeof(RegisterContextDarwin_i386::GPR) + \
138 sizeof(RegisterContextDarwin_i386::FPU))
139
140// These macros will auto define the register name, alt name, register size,
141// register offset, encoding, format and native register. This ensures that the
142// register state structures are defined correctly and have the correct sizes
143// and offsets.
144#define DEFINE_GPR(reg, alt) \
145 #reg, alt, sizeof(((RegisterContextDarwin_i386::GPR *) NULL)->reg), \
146 GPR_OFFSET(reg), eEncodingUint, eFormatHex
147#define DEFINE_FPU_UINT(reg) \
148 #reg, NULL, sizeof(((RegisterContextDarwin_i386::FPU *) NULL)->reg), \
149 FPU_OFFSET(reg), eEncodingUint, eFormatHex
150#define DEFINE_FPU_VECT(reg, i) \
151 #reg #i, NULL, \
152 sizeof(((RegisterContextDarwin_i386::FPU *) NULL)->reg[i].bytes), \
153 FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8, \
154 {LLDB_INVALID_REGNUM, dwarf_##reg##i, \
155 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
156 fpu_##reg##i }, \
157 nullptr, nullptr, nullptr,
158
159#define DEFINE_EXC(reg) \
160 #reg, NULL, sizeof(((RegisterContextDarwin_i386::EXC *) NULL)->reg), \
161 EXC_OFFSET(reg), eEncodingUint, eFormatHex
162#define REG_CONTEXT_SIZE \
163 (sizeof(RegisterContextDarwin_i386::GPR) + \
164 sizeof(RegisterContextDarwin_i386::FPU) + \
165 sizeof(RegisterContextDarwin_i386::EXC))
166
168 // Macro auto defines most stuff eh_frame DWARF
169 // GENERIC PROCESS PLUGIN LLDB
170 // =============================== =======================
171 // =================== ========================= ==================
172 // =================
173 {DEFINE_GPR(eax, nullptr),
175 gpr_eax},
176 nullptr,
177 nullptr,
178 nullptr,
179 },
180 {DEFINE_GPR(ebx, nullptr),
182 gpr_ebx},
183 nullptr,
184 nullptr,
185 nullptr,
186 },
187 {DEFINE_GPR(ecx, nullptr),
189 gpr_ecx},
190 nullptr,
191 nullptr,
192 nullptr,
193 },
194 {DEFINE_GPR(edx, nullptr),
196 gpr_edx},
197 nullptr,
198 nullptr,
199 nullptr,
200 },
201 {DEFINE_GPR(edi, nullptr),
203 gpr_edi},
204 nullptr,
205 nullptr,
206 nullptr,
207 },
208 {DEFINE_GPR(esi, nullptr),
210 gpr_esi},
211 nullptr,
212 nullptr,
213 nullptr,
214 },
215 {DEFINE_GPR(ebp, "fp"),
217 gpr_ebp},
218 nullptr,
219 nullptr,
220 nullptr,
221 },
222 {DEFINE_GPR(esp, "sp"),
224 gpr_esp},
225 nullptr,
226 nullptr,
227 nullptr,
228 },
229 {DEFINE_GPR(ss, nullptr),
232 nullptr,
233 nullptr,
234 nullptr,
235 },
236 {DEFINE_GPR(eflags, "flags"),
239 nullptr,
240 nullptr,
241 nullptr,
242 },
243 {DEFINE_GPR(eip, "pc"),
245 gpr_eip},
246 nullptr,
247 nullptr,
248 nullptr,
249 },
250 {DEFINE_GPR(cs, nullptr),
253 nullptr,
254 nullptr,
255 nullptr,
256 },
257 {DEFINE_GPR(ds, nullptr),
260 nullptr,
261 nullptr,
262 nullptr,
263 },
264 {DEFINE_GPR(es, nullptr),
267 nullptr,
268 nullptr,
269 nullptr,
270 },
271 {DEFINE_GPR(fs, nullptr),
274 nullptr,
275 nullptr,
276 nullptr,
277 },
278 {DEFINE_GPR(gs, nullptr),
281 nullptr,
282 nullptr,
283 nullptr,
284 },
285
286 {DEFINE_FPU_UINT(fcw),
289 nullptr,
290 nullptr,
291 nullptr,
292 },
293 {DEFINE_FPU_UINT(fsw),
296 nullptr,
297 nullptr,
298 nullptr,
299 },
300 {DEFINE_FPU_UINT(ftw),
303 nullptr,
304 nullptr,
305 nullptr,
306 },
307 {DEFINE_FPU_UINT(fop),
310 nullptr,
311 nullptr,
312 nullptr,
313 },
314 {DEFINE_FPU_UINT(ip),
317 nullptr,
318 nullptr,
319 nullptr,
320 },
321 {DEFINE_FPU_UINT(cs),
324 nullptr,
325 nullptr,
326 nullptr,
327 },
328 {DEFINE_FPU_UINT(dp),
331 nullptr,
332 nullptr,
333 nullptr,
334 },
335 {DEFINE_FPU_UINT(ds),
338 nullptr,
339 nullptr,
340 nullptr,
341 },
342 {DEFINE_FPU_UINT(mxcsr),
345 nullptr,
346 nullptr,
347 nullptr,
348 },
349 {DEFINE_FPU_UINT(mxcsrmask),
352 nullptr,
353 nullptr,
354 nullptr,
355 },
356 {DEFINE_FPU_VECT(stmm, 0)},
357 {DEFINE_FPU_VECT(stmm, 1)},
358 {DEFINE_FPU_VECT(stmm, 2)},
359 {DEFINE_FPU_VECT(stmm, 3)},
360 {DEFINE_FPU_VECT(stmm, 4)},
361 {DEFINE_FPU_VECT(stmm, 5)},
362 {DEFINE_FPU_VECT(stmm, 6)},
363 {DEFINE_FPU_VECT(stmm, 7)},
364 {DEFINE_FPU_VECT(xmm, 0)},
365 {DEFINE_FPU_VECT(xmm, 1)},
366 {DEFINE_FPU_VECT(xmm, 2)},
367 {DEFINE_FPU_VECT(xmm, 3)},
368 {DEFINE_FPU_VECT(xmm, 4)},
369 {DEFINE_FPU_VECT(xmm, 5)},
370 {DEFINE_FPU_VECT(xmm, 6)},
371 {DEFINE_FPU_VECT(xmm, 7)},
372
373 {DEFINE_EXC(trapno),
376 nullptr,
377 nullptr,
378 nullptr,
379 },
380 {DEFINE_EXC(err),
383 nullptr,
384 nullptr,
385 nullptr,
386 },
387 {DEFINE_EXC(faultvaddr),
390 nullptr,
391 nullptr,
392 nullptr,
393 }};
394
395static size_t k_num_register_infos = std::size(g_register_infos);
396
398 Thread &thread, uint32_t concrete_frame_idx)
399 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
400 uint32_t i;
401 for (i = 0; i < kNumErrors; i++) {
402 gpr_errs[i] = -1;
403 fpu_errs[i] = -1;
404 exc_errs[i] = -1;
405 }
406}
407
409
412}
413
416 return k_num_registers;
417}
418
419const RegisterInfo *
422 if (reg < k_num_registers)
423 return &g_register_infos[reg];
424 return nullptr;
425}
426
429}
430
432 return g_register_infos;
433}
434
435// General purpose registers
436static uint32_t g_gpr_regnums[] = {
439
440// Floating point registers
441static uint32_t g_fpu_regnums[] = {
447
448// Exception registers
449
451
452// Number of registers in each register set
453const size_t k_num_gpr_registers = std::size(g_gpr_regnums);
454const size_t k_num_fpu_registers = std::size(g_fpu_regnums);
455const size_t k_num_exc_registers = std::size(g_exc_regnums);
456
457// Register set definitions. The first definitions at register set index of
458// zero is for all registers, followed by other registers sets. The register
459// information for the all register set need not be filled in.
460static const RegisterSet g_reg_sets[] = {
461 {
462 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
463 },
464 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
465 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
466
467const size_t k_num_regsets = std::size(g_reg_sets);
468
470 return k_num_regsets;
471}
472
474 if (reg_set < k_num_regsets)
475 return &g_reg_sets[reg_set];
476 return nullptr;
477}
478
479// Register information definitions for 32 bit i386.
481 if (reg_num < fpu_fcw)
482 return GPRRegSet;
483 else if (reg_num < exc_trapno)
484 return FPURegSet;
485 else if (reg_num < k_num_registers)
486 return EXCRegSet;
487 return -1;
488}
489
490void RegisterContextDarwin_i386::LogGPR(Log *log, const char *title) {
491 if (log) {
492 if (title)
493 LLDB_LOGF(log, "%s", title);
494 for (uint32_t i = 0; i < k_num_gpr_registers; i++) {
495 uint32_t reg = gpr_eax + i;
496 LLDB_LOGF(log, "%12s = 0x%8.8x", g_register_infos[reg].name,
497 (&gpr.eax)[reg]);
498 }
499 }
500}
501
503 int set = GPRRegSet;
504 if (force || !RegisterSetIsCached(set)) {
505 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
506 }
507 return GetError(set, Read);
508}
509
511 int set = FPURegSet;
512 if (force || !RegisterSetIsCached(set)) {
513 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
514 }
515 return GetError(set, Read);
516}
517
519 int set = EXCRegSet;
520 if (force || !RegisterSetIsCached(set)) {
521 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
522 }
523 return GetError(set, Read);
524}
525
527 int set = GPRRegSet;
528 if (!RegisterSetIsCached(set)) {
529 SetError(set, Write, -1);
530 return -1;
531 }
532 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
533 SetError(set, Read, -1);
534 return GetError(set, Write);
535}
536
538 int set = FPURegSet;
539 if (!RegisterSetIsCached(set)) {
540 SetError(set, Write, -1);
541 return -1;
542 }
543 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
544 SetError(set, Read, -1);
545 return GetError(set, Write);
546}
547
549 int set = EXCRegSet;
550 if (!RegisterSetIsCached(set)) {
551 SetError(set, Write, -1);
552 return -1;
553 }
554 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
555 SetError(set, Read, -1);
556 return GetError(set, Write);
557}
558
559int RegisterContextDarwin_i386::ReadRegisterSet(uint32_t set, bool force) {
560 switch (set) {
561 case GPRRegSet:
562 return ReadGPR(force);
563 case FPURegSet:
564 return ReadFPU(force);
565 case EXCRegSet:
566 return ReadEXC(force);
567 default:
568 break;
569 }
570 return -1;
571}
572
574 // Make sure we have a valid context to set.
575 if (RegisterSetIsCached(set)) {
576 switch (set) {
577 case GPRRegSet:
578 return WriteGPR();
579 case FPURegSet:
580 return WriteFPU();
581 case EXCRegSet:
582 return WriteEXC();
583 default:
584 break;
585 }
586 }
587 return -1;
588}
589
591 RegisterValue &value) {
592 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
594
595 if (set == -1)
596 return false;
597
598 if (ReadRegisterSet(set, false) != 0)
599 return false;
600
601 switch (reg) {
602 case gpr_eax:
603 case gpr_ebx:
604 case gpr_ecx:
605 case gpr_edx:
606 case gpr_edi:
607 case gpr_esi:
608 case gpr_ebp:
609 case gpr_esp:
610 case gpr_ss:
611 case gpr_eflags:
612 case gpr_eip:
613 case gpr_cs:
614 case gpr_ds:
615 case gpr_es:
616 case gpr_fs:
617 case gpr_gs:
618 value = (&gpr.eax)[reg - gpr_eax];
619 break;
620
621 case fpu_fcw:
622 value = fpu.fcw;
623 break;
624
625 case fpu_fsw:
626 value = fpu.fsw;
627 break;
628
629 case fpu_ftw:
630 value = fpu.ftw;
631 break;
632
633 case fpu_fop:
634 value = fpu.fop;
635 break;
636
637 case fpu_ip:
638 value = fpu.ip;
639 break;
640
641 case fpu_cs:
642 value = fpu.cs;
643 break;
644
645 case fpu_dp:
646 value = fpu.dp;
647 break;
648
649 case fpu_ds:
650 value = fpu.ds;
651 break;
652
653 case fpu_mxcsr:
654 value = fpu.mxcsr;
655 break;
656
657 case fpu_mxcsrmask:
658 value = fpu.mxcsrmask;
659 break;
660
661 case fpu_stmm0:
662 case fpu_stmm1:
663 case fpu_stmm2:
664 case fpu_stmm3:
665 case fpu_stmm4:
666 case fpu_stmm5:
667 case fpu_stmm6:
668 case fpu_stmm7:
669 // These values don't fit into scalar types,
670 // RegisterContext::ReadRegisterBytes() must be used for these registers
671 //::memcpy (reg_value.value.vector.uint8, fpu.stmm[reg - fpu_stmm0].bytes,
672 //10);
673 return false;
674
675 case fpu_xmm0:
676 case fpu_xmm1:
677 case fpu_xmm2:
678 case fpu_xmm3:
679 case fpu_xmm4:
680 case fpu_xmm5:
681 case fpu_xmm6:
682 case fpu_xmm7:
683 // These values don't fit into scalar types,
684 // RegisterContext::ReadRegisterBytes() must be used for these registers
685 //::memcpy (reg_value.value.vector.uint8, fpu.xmm[reg - fpu_xmm0].bytes,
686 //16);
687 return false;
688
689 case exc_trapno:
690 value = exc.trapno;
691 break;
692
693 case exc_err:
694 value = exc.err;
695 break;
696
697 case exc_faultvaddr:
698 value = exc.faultvaddr;
699 break;
700
701 default:
702 return false;
703 }
704 return true;
705}
706
708 const RegisterValue &value) {
709 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
710 int set = GetSetForNativeRegNum(reg);
711
712 if (set == -1)
713 return false;
714
715 if (ReadRegisterSet(set, false) != 0)
716 return false;
717
718 switch (reg) {
719 case gpr_eax:
720 case gpr_ebx:
721 case gpr_ecx:
722 case gpr_edx:
723 case gpr_edi:
724 case gpr_esi:
725 case gpr_ebp:
726 case gpr_esp:
727 case gpr_ss:
728 case gpr_eflags:
729 case gpr_eip:
730 case gpr_cs:
731 case gpr_ds:
732 case gpr_es:
733 case gpr_fs:
734 case gpr_gs:
735 (&gpr.eax)[reg - gpr_eax] = value.GetAsUInt32();
736 break;
737
738 case fpu_fcw:
739 fpu.fcw = value.GetAsUInt16();
740 break;
741
742 case fpu_fsw:
743 fpu.fsw = value.GetAsUInt16();
744 break;
745
746 case fpu_ftw:
747 fpu.ftw = value.GetAsUInt8();
748 break;
749
750 case fpu_fop:
751 fpu.fop = value.GetAsUInt16();
752 break;
753
754 case fpu_ip:
755 fpu.ip = value.GetAsUInt32();
756 break;
757
758 case fpu_cs:
759 fpu.cs = value.GetAsUInt16();
760 break;
761
762 case fpu_dp:
763 fpu.dp = value.GetAsUInt32();
764 break;
765
766 case fpu_ds:
767 fpu.ds = value.GetAsUInt16();
768 break;
769
770 case fpu_mxcsr:
771 fpu.mxcsr = value.GetAsUInt32();
772 break;
773
774 case fpu_mxcsrmask:
775 fpu.mxcsrmask = value.GetAsUInt32();
776 break;
777
778 case fpu_stmm0:
779 case fpu_stmm1:
780 case fpu_stmm2:
781 case fpu_stmm3:
782 case fpu_stmm4:
783 case fpu_stmm5:
784 case fpu_stmm6:
785 case fpu_stmm7:
786 // These values don't fit into scalar types,
787 // RegisterContext::ReadRegisterBytes() must be used for these registers
788 ::memcpy(fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(),
789 value.GetByteSize());
790 return false;
791
792 case fpu_xmm0:
793 case fpu_xmm1:
794 case fpu_xmm2:
795 case fpu_xmm3:
796 case fpu_xmm4:
797 case fpu_xmm5:
798 case fpu_xmm6:
799 case fpu_xmm7:
800 // These values don't fit into scalar types,
801 // RegisterContext::ReadRegisterBytes() must be used for these registers
802 ::memcpy(fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(),
803 value.GetByteSize());
804 return false;
805
806 case exc_trapno:
807 exc.trapno = value.GetAsUInt32();
808 break;
809
810 case exc_err:
811 exc.err = value.GetAsUInt32();
812 break;
813
814 case exc_faultvaddr:
815 exc.faultvaddr = value.GetAsUInt32();
816 break;
817
818 default:
819 return false;
820 }
821 return WriteRegisterSet(set) == 0;
822}
823
826 data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
827 if (ReadGPR(false) == 0 && ReadFPU(false) == 0 && ReadEXC(false) == 0) {
828 uint8_t *dst = data_sp->GetBytes();
829 ::memcpy(dst, &gpr, sizeof(gpr));
830 dst += sizeof(gpr);
831
832 ::memcpy(dst, &fpu, sizeof(fpu));
833 dst += sizeof(gpr);
834
835 ::memcpy(dst, &exc, sizeof(exc));
836 return true;
837 }
838 return false;
839}
840
842 const lldb::DataBufferSP &data_sp) {
843 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
844 const uint8_t *src = data_sp->GetBytes();
845 ::memcpy(&gpr, src, sizeof(gpr));
846 src += sizeof(gpr);
847
848 ::memcpy(&fpu, src, sizeof(fpu));
849 src += sizeof(gpr);
850
851 ::memcpy(&exc, src, sizeof(exc));
852 uint32_t success_count = 0;
853 if (WriteGPR() == 0)
854 ++success_count;
855 if (WriteFPU() == 0)
856 ++success_count;
857 if (WriteEXC() == 0)
858 ++success_count;
859 return success_count == 3;
860 }
861 return false;
862}
863
865 lldb::RegisterKind kind, uint32_t reg) {
866 if (kind == eRegisterKindGeneric) {
867 switch (reg) {
869 return gpr_eip;
871 return gpr_esp;
873 return gpr_ebp;
875 return gpr_eflags;
877 default:
878 break;
879 }
880 } else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF) {
881 switch (reg) {
882 case dwarf_eax:
883 return gpr_eax;
884 case dwarf_ecx:
885 return gpr_ecx;
886 case dwarf_edx:
887 return gpr_edx;
888 case dwarf_ebx:
889 return gpr_ebx;
890 case dwarf_esp:
891 return gpr_esp;
892 case dwarf_ebp:
893 return gpr_ebp;
894 case dwarf_esi:
895 return gpr_esi;
896 case dwarf_edi:
897 return gpr_edi;
898 case dwarf_eip:
899 return gpr_eip;
900 case dwarf_eflags:
901 return gpr_eflags;
902 case dwarf_stmm0:
903 return fpu_stmm0;
904 case dwarf_stmm1:
905 return fpu_stmm1;
906 case dwarf_stmm2:
907 return fpu_stmm2;
908 case dwarf_stmm3:
909 return fpu_stmm3;
910 case dwarf_stmm4:
911 return fpu_stmm4;
912 case dwarf_stmm5:
913 return fpu_stmm5;
914 case dwarf_stmm6:
915 return fpu_stmm6;
916 case dwarf_stmm7:
917 return fpu_stmm7;
918 case dwarf_xmm0:
919 return fpu_xmm0;
920 case dwarf_xmm1:
921 return fpu_xmm1;
922 case dwarf_xmm2:
923 return fpu_xmm2;
924 case dwarf_xmm3:
925 return fpu_xmm3;
926 case dwarf_xmm4:
927 return fpu_xmm4;
928 case dwarf_xmm5:
929 return fpu_xmm5;
930 case dwarf_xmm6:
931 return fpu_xmm6;
932 case dwarf_xmm7:
933 return fpu_xmm7;
934 default:
935 break;
936 }
937 } else if (kind == eRegisterKindLLDB) {
938 return reg;
939 }
940 return LLDB_INVALID_REGNUM;
941}
942
944 if (ReadGPR(false) != 0)
945 return false;
946
947 const uint32_t trace_bit = 0x100u;
948 if (enable) {
949 // If the trace bit is already set, there is nothing to do
950 if (gpr.eflags & trace_bit)
951 return true;
952 else
953 gpr.eflags |= trace_bit;
954 } else {
955 // If the trace bit is already cleared, there is nothing to do
956 if (gpr.eflags & trace_bit)
957 gpr.eflags &= ~trace_bit;
958 else
959 return true;
960 }
961
962 return WriteGPR() == 0;
963}
static const uint32_t k_num_register_infos
static const RegisterInfo g_register_infos[]
@ dwarf_edx
@ dwarf_ecx
@ dwarf_eip
@ dwarf_eax
@ dwarf_esi
@ dwarf_edi
@ dwarf_esp
@ dwarf_ebx
@ dwarf_ebp
@ dwarf_stmm0
@ dwarf_xmm0
@ dwarf_xmm4
@ dwarf_xmm7
@ dwarf_stmm5
@ dwarf_stmm3
@ dwarf_xmm6
@ dwarf_xmm5
@ dwarf_stmm7
@ dwarf_stmm2
@ dwarf_xmm3
@ dwarf_stmm6
@ dwarf_xmm2
@ dwarf_xmm1
@ dwarf_stmm1
@ dwarf_stmm4
#define LLDB_LOGF(log,...)
Definition: Log.h:366
const size_t k_num_regsets
const size_t k_num_gpr_registers
#define REG_CONTEXT_SIZE
const size_t k_num_regsets
static uint32_t g_fpu_regnums[]
static uint32_t g_gpr_regnums[]
static RegisterInfo g_register_infos[]
static uint32_t g_exc_regnums[]
const size_t k_num_gpr_registers
const size_t k_num_fpu_registers
#define DEFINE_EXC(reg)
#define DEFINE_FPU_VECT(reg, i)
#define DEFINE_FPU_UINT(reg)
static const RegisterSet g_reg_sets[]
const size_t k_num_exc_registers
#define DEFINE_GPR(reg, alt)
static size_t k_num_register_infos
static RegisterSet g_reg_sets[]
bool WriteRegister(const lldb_private::RegisterInfo *reg_info, const lldb_private::RegisterValue &value) override
const lldb_private::RegisterSet * GetRegisterSet(size_t set) override
static int GetSetForNativeRegNum(int reg_num)
bool HardwareSingleStep(bool enable) override
virtual int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr)=0
int GetError(int flavor, uint32_t err_idx) const
bool SetError(int flavor, uint32_t err_idx, int err)
const lldb_private::RegisterInfo * GetRegisterInfoAtIndex(size_t reg) override
int ReadRegisterSet(uint32_t set, bool force)
static const lldb_private::RegisterInfo * GetRegisterInfos()
~RegisterContextDarwin_i386() override
virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu)=0
bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override
void LogGPR(lldb_private::Log *log, const char *title)
virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu)=0
uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, uint32_t num) override
Convert from a given register numbering scheme to the lldb register numbering scheme.
virtual int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr)=0
bool ReadRegister(const lldb_private::RegisterInfo *reg_info, lldb_private::RegisterValue &value) override
virtual int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc)=0
RegisterContextDarwin_i386(lldb_private::Thread &thread, uint32_t concrete_frame_idx)
virtual int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc)=0
bool ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override
virtual lldb::tid_t GetThreadID() const
uint16_t GetAsUInt16(uint16_t fail_value=UINT16_MAX, bool *success_ptr=nullptr) const
uint8_t GetAsUInt8(uint8_t fail_value=UINT8_MAX, bool *success_ptr=nullptr) const
const void * GetBytes() const
uint32_t GetAsUInt32(uint32_t fail_value=UINT32_MAX, bool *success_ptr=nullptr) const
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:59
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:57
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:60
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:87
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:56
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:58
A class that represents a running process on the host machine.
Definition: SBAddress.h:15
std::shared_ptr< lldb_private::DataBuffer > DataBufferSP
Definition: lldb-forward.h:332
std::shared_ptr< lldb_private::WritableDataBuffer > WritableDataBufferSP
Definition: lldb-forward.h:333
RegisterKind
Register numbering types.
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target
@ eRegisterKindLLDB
lldb's internal register numbers
@ eRegisterKindDWARF
the register numbers seen DWARF
@ eRegisterKindEHFrame
the register numbers seen in eh_frame
Every register is described in detail including its name, alternate name (optional),...
uint32_t kinds[lldb::kNumRegisterKinds]
Holds all of the various register numbers for all register kinds.
Registers are grouped into register sets.