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RegisterContextDarwin_x86_64.cpp
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1 //===-- RegisterContextDarwin_x86_64.cpp ------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include <inttypes.h>
10 #include <stdarg.h>
11 #include <stddef.h>
12 
13 #include <memory>
14 
17 #include "lldb/Utility/Endian.h"
18 #include "lldb/Utility/Log.h"
20 #include "lldb/Utility/Scalar.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Compiler.h"
23 
24 // Support building against older versions of LLVM, this macro was added
25 // recently.
26 #ifndef LLVM_EXTENSION
27 #define LLVM_EXTENSION
28 #endif
29 
31 
32 using namespace lldb;
33 using namespace lldb_private;
34 
35 enum {
36  gpr_rax = 0,
57 
92 
96 
98 
99  // Aliases
107 };
108 
151 
152 };
153 
154 #define GPR_OFFSET(reg) \
155  (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::GPR, reg))
156 #define FPU_OFFSET(reg) \
157  (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::FPU, reg) + \
158  sizeof(RegisterContextDarwin_x86_64::GPR))
159 #define EXC_OFFSET(reg) \
160  (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::EXC, reg) + \
161  sizeof(RegisterContextDarwin_x86_64::GPR) + \
162  sizeof(RegisterContextDarwin_x86_64::FPU))
163 
164 // These macros will auto define the register name, alt name, register size,
165 // register offset, encoding, format and native register. This ensures that the
166 // register state structures are defined correctly and have the correct sizes
167 // and offsets.
168 #define DEFINE_GPR(reg, alt) \
169  #reg, alt, sizeof(((RegisterContextDarwin_x86_64::GPR *) NULL)->reg), \
170  GPR_OFFSET(reg), eEncodingUint, eFormatHex
171 #define DEFINE_FPU_UINT(reg) \
172  #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg), \
173  FPU_OFFSET(reg), eEncodingUint, eFormatHex
174 #define DEFINE_FPU_VECT(reg, i) \
175  #reg #i, NULL, \
176  sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg[i].bytes), \
177  FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8, \
178  {ehframe_dwarf_fpu_##reg##i, \
179  ehframe_dwarf_fpu_##reg##i, LLDB_INVALID_REGNUM, \
180  LLDB_INVALID_REGNUM, fpu_##reg##i }, \
181  nullptr, nullptr, nullptr, 0
182 #define DEFINE_EXC(reg) \
183  #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::EXC *) NULL)->reg), \
184  EXC_OFFSET(reg), eEncodingUint, eFormatHex
185 
186 #define REG_CONTEXT_SIZE \
187  (sizeof(RegisterContextDarwin_x86_64::GPR) + \
188  sizeof(RegisterContextDarwin_x86_64::FPU) + \
189  sizeof(RegisterContextDarwin_x86_64::EXC))
190 
191 // General purpose registers for 64 bit
192 static RegisterInfo g_register_infos[] = {
193  // Macro auto defines most stuff EH_FRAME DWARF
194  // GENERIC PROCESS PLUGIN LLDB
195  // =============================== ======================
196  // =================== ========================== ====================
197  // ===================
198  {DEFINE_GPR(rax, NULL),
201  nullptr,
202  nullptr,
203  nullptr,
204  0},
205  {DEFINE_GPR(rbx, NULL),
208  nullptr,
209  nullptr,
210  nullptr,
211  0},
212  {DEFINE_GPR(rcx, NULL),
215  nullptr,
216  nullptr,
217  nullptr,
218  0},
219  {DEFINE_GPR(rdx, NULL),
222  nullptr,
223  nullptr,
224  nullptr,
225  0},
226  {DEFINE_GPR(rdi, NULL),
229  nullptr,
230  nullptr,
231  nullptr,
232  0},
233  {DEFINE_GPR(rsi, NULL),
236  nullptr,
237  nullptr,
238  nullptr,
239  0},
240  {DEFINE_GPR(rbp, "fp"),
243  nullptr,
244  nullptr,
245  nullptr,
246  0},
247  {DEFINE_GPR(rsp, "sp"),
250  nullptr,
251  nullptr,
252  nullptr,
253  0},
254  {DEFINE_GPR(r8, NULL),
257  nullptr,
258  nullptr,
259  nullptr,
260  0},
261  {DEFINE_GPR(r9, NULL),
264  nullptr,
265  nullptr,
266  nullptr,
267  0},
268  {DEFINE_GPR(r10, NULL),
271  nullptr,
272  nullptr,
273  nullptr,
274  0},
275  {DEFINE_GPR(r11, NULL),
278  nullptr,
279  nullptr,
280  nullptr,
281  0},
282  {DEFINE_GPR(r12, NULL),
285  nullptr,
286  nullptr,
287  nullptr,
288  0},
289  {DEFINE_GPR(r13, NULL),
292  nullptr,
293  nullptr,
294  nullptr,
295  0},
296  {DEFINE_GPR(r14, NULL),
299  nullptr,
300  nullptr,
301  nullptr,
302  0},
303  {DEFINE_GPR(r15, NULL),
306  nullptr,
307  nullptr,
308  nullptr,
309  0},
310  {DEFINE_GPR(rip, "pc"),
313  nullptr,
314  nullptr,
315  nullptr,
316  0},
317  {DEFINE_GPR(rflags, "flags"),
320  nullptr,
321  nullptr,
322  nullptr,
323  0},
324  {DEFINE_GPR(cs, NULL),
327  nullptr,
328  nullptr,
329  nullptr,
330  0},
331  {DEFINE_GPR(fs, NULL),
334  nullptr,
335  nullptr,
336  nullptr,
337  0},
338  {DEFINE_GPR(gs, NULL),
341  nullptr,
342  nullptr,
343  nullptr,
344  0},
345 
346  {DEFINE_FPU_UINT(fcw),
349  nullptr,
350  nullptr,
351  nullptr,
352  0},
353  {DEFINE_FPU_UINT(fsw),
356  nullptr,
357  nullptr,
358  nullptr,
359  0},
360  {DEFINE_FPU_UINT(ftw),
363  nullptr,
364  nullptr,
365  nullptr,
366  0},
367  {DEFINE_FPU_UINT(fop),
370  nullptr,
371  nullptr,
372  nullptr,
373  0},
374  {DEFINE_FPU_UINT(ip),
377  nullptr,
378  nullptr,
379  nullptr,
380  0},
381  {DEFINE_FPU_UINT(cs),
384  nullptr,
385  nullptr,
386  nullptr,
387  0},
388  {DEFINE_FPU_UINT(dp),
391  nullptr,
392  nullptr,
393  nullptr,
394  0},
395  {DEFINE_FPU_UINT(ds),
398  nullptr,
399  nullptr,
400  nullptr,
401  0},
402  {DEFINE_FPU_UINT(mxcsr),
405  nullptr,
406  nullptr,
407  nullptr,
408  0},
409  {DEFINE_FPU_UINT(mxcsrmask),
412  nullptr,
413  nullptr,
414  nullptr,
415  0},
416  {DEFINE_FPU_VECT(stmm, 0)},
417  {DEFINE_FPU_VECT(stmm, 1)},
418  {DEFINE_FPU_VECT(stmm, 2)},
419  {DEFINE_FPU_VECT(stmm, 3)},
420  {DEFINE_FPU_VECT(stmm, 4)},
421  {DEFINE_FPU_VECT(stmm, 5)},
422  {DEFINE_FPU_VECT(stmm, 6)},
423  {DEFINE_FPU_VECT(stmm, 7)},
424  {DEFINE_FPU_VECT(xmm, 0)},
425  {DEFINE_FPU_VECT(xmm, 1)},
426  {DEFINE_FPU_VECT(xmm, 2)},
427  {DEFINE_FPU_VECT(xmm, 3)},
428  {DEFINE_FPU_VECT(xmm, 4)},
429  {DEFINE_FPU_VECT(xmm, 5)},
430  {DEFINE_FPU_VECT(xmm, 6)},
431  {DEFINE_FPU_VECT(xmm, 7)},
432  {DEFINE_FPU_VECT(xmm, 8)},
433  {DEFINE_FPU_VECT(xmm, 9)},
434  {DEFINE_FPU_VECT(xmm, 10)},
435  {DEFINE_FPU_VECT(xmm, 11)},
436  {DEFINE_FPU_VECT(xmm, 12)},
437  {DEFINE_FPU_VECT(xmm, 13)},
438  {DEFINE_FPU_VECT(xmm, 14)},
439  {DEFINE_FPU_VECT(xmm, 15)},
440 
441  {DEFINE_EXC(trapno),
444  nullptr,
445  nullptr,
446  nullptr,
447  0},
448  {DEFINE_EXC(err),
451  nullptr,
452  nullptr,
453  nullptr,
454  0},
455  {DEFINE_EXC(faultvaddr),
458  nullptr,
459  nullptr,
460  nullptr,
461  0}};
462 
463 static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
464 
466  Thread &thread, uint32_t concrete_frame_idx)
467  : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
468  uint32_t i;
469  for (i = 0; i < kNumErrors; i++) {
470  gpr_errs[i] = -1;
471  fpu_errs[i] = -1;
472  exc_errs[i] = -1;
473  }
474 }
475 
477 
480 }
481 
484  return k_num_registers;
485 }
486 
487 const RegisterInfo *
490  if (reg < k_num_registers)
491  return &g_register_infos[reg];
492  return NULL;
493 }
494 
496  return k_num_register_infos;
497 }
498 
499 const lldb_private::RegisterInfo *
501  return g_register_infos;
502 }
503 
508 
516 
518 
519 // Number of registers in each register set
520 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
521 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
522 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
523 
524 // Register set definitions. The first definitions at register set index of
525 // zero is for all registers, followed by other registers sets. The register
526 // information for the all register set need not be filled in.
527 static const RegisterSet g_reg_sets[] = {
528  {
529  "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
530  },
531  {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
532  {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
533 
534 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
535 
537  return k_num_regsets;
538 }
539 
540 const RegisterSet *
542  if (reg_set < k_num_regsets)
543  return &g_reg_sets[reg_set];
544  return NULL;
545 }
546 
548  if (reg_num < fpu_fcw)
549  return GPRRegSet;
550  else if (reg_num < exc_trapno)
551  return FPURegSet;
552  else if (reg_num < k_num_registers)
553  return EXCRegSet;
554  return -1;
555 }
556 
557 void RegisterContextDarwin_x86_64::LogGPR(Log *log, const char *format, ...) {
558  if (log) {
559  if (format) {
560  va_list args;
561  va_start(args, format);
562  log->VAPrintf(format, args);
563  va_end(args);
564  }
565  for (uint32_t i = 0; i < k_num_gpr_registers; i++) {
566  uint32_t reg = gpr_rax + i;
567  log->Printf("%12s = 0x%16.16" PRIx64, g_register_infos[reg].name,
568  (&gpr.rax)[reg]);
569  }
570  }
571 }
572 
574  int set = GPRRegSet;
575  if (force || !RegisterSetIsCached(set)) {
576  SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
577  }
578  return GetError(GPRRegSet, Read);
579 }
580 
582  int set = FPURegSet;
583  if (force || !RegisterSetIsCached(set)) {
584  SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
585  }
586  return GetError(FPURegSet, Read);
587 }
588 
590  int set = EXCRegSet;
591  if (force || !RegisterSetIsCached(set)) {
592  SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
593  }
594  return GetError(EXCRegSet, Read);
595 }
596 
598  int set = GPRRegSet;
599  if (!RegisterSetIsCached(set)) {
600  SetError(set, Write, -1);
601  return -1;
602  }
603  SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
604  SetError(set, Read, -1);
605  return GetError(set, Write);
606 }
607 
609  int set = FPURegSet;
610  if (!RegisterSetIsCached(set)) {
611  SetError(set, Write, -1);
612  return -1;
613  }
614  SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
615  SetError(set, Read, -1);
616  return GetError(set, Write);
617 }
618 
620  int set = EXCRegSet;
621  if (!RegisterSetIsCached(set)) {
622  SetError(set, Write, -1);
623  return -1;
624  }
625  SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
626  SetError(set, Read, -1);
627  return GetError(set, Write);
628 }
629 
631  switch (set) {
632  case GPRRegSet:
633  return ReadGPR(force);
634  case FPURegSet:
635  return ReadFPU(force);
636  case EXCRegSet:
637  return ReadEXC(force);
638  default:
639  break;
640  }
641  return -1;
642 }
643 
645  // Make sure we have a valid context to set.
646  switch (set) {
647  case GPRRegSet:
648  return WriteGPR();
649  case FPURegSet:
650  return WriteFPU();
651  case EXCRegSet:
652  return WriteEXC();
653  default:
654  break;
655  }
656  return -1;
657 }
658 
659 bool RegisterContextDarwin_x86_64::ReadRegister(const RegisterInfo *reg_info,
660  RegisterValue &value) {
661  const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
663  if (set == -1)
664  return false;
665 
666  if (ReadRegisterSet(set, false) != 0)
667  return false;
668 
669  switch (reg) {
670  case gpr_rax:
671  case gpr_rbx:
672  case gpr_rcx:
673  case gpr_rdx:
674  case gpr_rdi:
675  case gpr_rsi:
676  case gpr_rbp:
677  case gpr_rsp:
678  case gpr_r8:
679  case gpr_r9:
680  case gpr_r10:
681  case gpr_r11:
682  case gpr_r12:
683  case gpr_r13:
684  case gpr_r14:
685  case gpr_r15:
686  case gpr_rip:
687  case gpr_rflags:
688  case gpr_cs:
689  case gpr_fs:
690  case gpr_gs:
691  value = (&gpr.rax)[reg - gpr_rax];
692  break;
693 
694  case fpu_fcw:
695  value = fpu.fcw;
696  break;
697 
698  case fpu_fsw:
699  value = fpu.fsw;
700  break;
701 
702  case fpu_ftw:
703  value = fpu.ftw;
704  break;
705 
706  case fpu_fop:
707  value = fpu.fop;
708  break;
709 
710  case fpu_ip:
711  value = fpu.ip;
712  break;
713 
714  case fpu_cs:
715  value = fpu.cs;
716  break;
717 
718  case fpu_dp:
719  value = fpu.dp;
720  break;
721 
722  case fpu_ds:
723  value = fpu.ds;
724  break;
725 
726  case fpu_mxcsr:
727  value = fpu.mxcsr;
728  break;
729 
730  case fpu_mxcsrmask:
731  value = fpu.mxcsrmask;
732  break;
733 
734  case fpu_stmm0:
735  case fpu_stmm1:
736  case fpu_stmm2:
737  case fpu_stmm3:
738  case fpu_stmm4:
739  case fpu_stmm5:
740  case fpu_stmm6:
741  case fpu_stmm7:
742  value.SetBytes(fpu.stmm[reg - fpu_stmm0].bytes, reg_info->byte_size,
744  break;
745 
746  case fpu_xmm0:
747  case fpu_xmm1:
748  case fpu_xmm2:
749  case fpu_xmm3:
750  case fpu_xmm4:
751  case fpu_xmm5:
752  case fpu_xmm6:
753  case fpu_xmm7:
754  case fpu_xmm8:
755  case fpu_xmm9:
756  case fpu_xmm10:
757  case fpu_xmm11:
758  case fpu_xmm12:
759  case fpu_xmm13:
760  case fpu_xmm14:
761  case fpu_xmm15:
762  value.SetBytes(fpu.xmm[reg - fpu_xmm0].bytes, reg_info->byte_size,
764  break;
765 
766  case exc_trapno:
767  value = exc.trapno;
768  break;
769 
770  case exc_err:
771  value = exc.err;
772  break;
773 
774  case exc_faultvaddr:
775  value = exc.faultvaddr;
776  break;
777 
778  default:
779  return false;
780  }
781  return true;
782 }
783 
784 bool RegisterContextDarwin_x86_64::WriteRegister(const RegisterInfo *reg_info,
785  const RegisterValue &value) {
786  const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
788 
789  if (set == -1)
790  return false;
791 
792  if (ReadRegisterSet(set, false) != 0)
793  return false;
794 
795  switch (reg) {
796  case gpr_rax:
797  case gpr_rbx:
798  case gpr_rcx:
799  case gpr_rdx:
800  case gpr_rdi:
801  case gpr_rsi:
802  case gpr_rbp:
803  case gpr_rsp:
804  case gpr_r8:
805  case gpr_r9:
806  case gpr_r10:
807  case gpr_r11:
808  case gpr_r12:
809  case gpr_r13:
810  case gpr_r14:
811  case gpr_r15:
812  case gpr_rip:
813  case gpr_rflags:
814  case gpr_cs:
815  case gpr_fs:
816  case gpr_gs:
817  (&gpr.rax)[reg - gpr_rax] = value.GetAsUInt64();
818  break;
819 
820  case fpu_fcw:
821  fpu.fcw = value.GetAsUInt16();
822  break;
823 
824  case fpu_fsw:
825  fpu.fsw = value.GetAsUInt16();
826  break;
827 
828  case fpu_ftw:
829  fpu.ftw = value.GetAsUInt8();
830  break;
831 
832  case fpu_fop:
833  fpu.fop = value.GetAsUInt16();
834  break;
835 
836  case fpu_ip:
837  fpu.ip = value.GetAsUInt32();
838  break;
839 
840  case fpu_cs:
841  fpu.cs = value.GetAsUInt16();
842  break;
843 
844  case fpu_dp:
845  fpu.dp = value.GetAsUInt32();
846  break;
847 
848  case fpu_ds:
849  fpu.ds = value.GetAsUInt16();
850  break;
851 
852  case fpu_mxcsr:
853  fpu.mxcsr = value.GetAsUInt32();
854  break;
855 
856  case fpu_mxcsrmask:
857  fpu.mxcsrmask = value.GetAsUInt32();
858  break;
859 
860  case fpu_stmm0:
861  case fpu_stmm1:
862  case fpu_stmm2:
863  case fpu_stmm3:
864  case fpu_stmm4:
865  case fpu_stmm5:
866  case fpu_stmm6:
867  case fpu_stmm7:
868  ::memcpy(fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(),
869  value.GetByteSize());
870  break;
871 
872  case fpu_xmm0:
873  case fpu_xmm1:
874  case fpu_xmm2:
875  case fpu_xmm3:
876  case fpu_xmm4:
877  case fpu_xmm5:
878  case fpu_xmm6:
879  case fpu_xmm7:
880  case fpu_xmm8:
881  case fpu_xmm9:
882  case fpu_xmm10:
883  case fpu_xmm11:
884  case fpu_xmm12:
885  case fpu_xmm13:
886  case fpu_xmm14:
887  case fpu_xmm15:
888  ::memcpy(fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(),
889  value.GetByteSize());
890  return false;
891 
892  case exc_trapno:
893  exc.trapno = value.GetAsUInt32();
894  break;
895 
896  case exc_err:
897  exc.err = value.GetAsUInt32();
898  break;
899 
900  case exc_faultvaddr:
901  exc.faultvaddr = value.GetAsUInt64();
902  break;
903 
904  default:
905  return false;
906  }
907  return WriteRegisterSet(set) == 0;
908 }
909 
911  lldb::DataBufferSP &data_sp) {
912  data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
913  if (data_sp && ReadGPR(false) == 0 && ReadFPU(false) == 0 &&
914  ReadEXC(false) == 0) {
915  uint8_t *dst = data_sp->GetBytes();
916  ::memcpy(dst, &gpr, sizeof(gpr));
917  dst += sizeof(gpr);
918 
919  ::memcpy(dst, &fpu, sizeof(fpu));
920  dst += sizeof(gpr);
921 
922  ::memcpy(dst, &exc, sizeof(exc));
923  return true;
924  }
925  return false;
926 }
927 
929  const lldb::DataBufferSP &data_sp) {
930  if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
931  const uint8_t *src = data_sp->GetBytes();
932  ::memcpy(&gpr, src, sizeof(gpr));
933  src += sizeof(gpr);
934 
935  ::memcpy(&fpu, src, sizeof(fpu));
936  src += sizeof(gpr);
937 
938  ::memcpy(&exc, src, sizeof(exc));
939  uint32_t success_count = 0;
940  if (WriteGPR() == 0)
941  ++success_count;
942  if (WriteFPU() == 0)
943  ++success_count;
944  if (WriteEXC() == 0)
945  ++success_count;
946  return success_count == 3;
947  }
948  return false;
949 }
950 
952  lldb::RegisterKind kind, uint32_t reg) {
953  if (kind == eRegisterKindGeneric) {
954  switch (reg) {
956  return gpr_rip;
958  return gpr_rsp;
960  return gpr_rbp;
962  return gpr_rflags;
964  default:
965  break;
966  }
967  } else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF) {
968  switch (reg) {
970  return gpr_rax;
972  return gpr_rdx;
974  return gpr_rcx;
976  return gpr_rbx;
978  return gpr_rsi;
980  return gpr_rdi;
982  return gpr_rbp;
984  return gpr_rsp;
986  return gpr_r8;
988  return gpr_r9;
990  return gpr_r10;
992  return gpr_r11;
994  return gpr_r12;
996  return gpr_r13;
998  return gpr_r14;
1000  return gpr_r15;
1001  case ehframe_dwarf_gpr_rip:
1002  return gpr_rip;
1004  return fpu_xmm0;
1006  return fpu_xmm1;
1008  return fpu_xmm2;
1010  return fpu_xmm3;
1012  return fpu_xmm4;
1014  return fpu_xmm5;
1016  return fpu_xmm6;
1018  return fpu_xmm7;
1020  return fpu_xmm8;
1022  return fpu_xmm9;
1024  return fpu_xmm10;
1026  return fpu_xmm11;
1028  return fpu_xmm12;
1030  return fpu_xmm13;
1032  return fpu_xmm14;
1034  return fpu_xmm15;
1036  return fpu_stmm0;
1038  return fpu_stmm1;
1040  return fpu_stmm2;
1042  return fpu_stmm3;
1044  return fpu_stmm4;
1046  return fpu_stmm5;
1048  return fpu_stmm6;
1050  return fpu_stmm7;
1051  default:
1052  break;
1053  }
1054  } else if (kind == eRegisterKindLLDB) {
1055  return reg;
1056  }
1057  return LLDB_INVALID_REGNUM;
1058 }
1059 
1061  if (ReadGPR(true) != 0)
1062  return false;
1063 
1064  const uint64_t trace_bit = 0x100ull;
1065  if (enable) {
1066 
1067  if (gpr.rflags & trace_bit)
1068  return true; // trace bit is already set, there is nothing to do
1069  else
1070  gpr.rflags |= trace_bit;
1071  } else {
1072  if (gpr.rflags & trace_bit)
1073  gpr.rflags &= ~trace_bit;
1074  else
1075  return true; // trace bit is clear, there is nothing to do
1076  }
1077 
1078  return WriteGPR() == 0;
1079 }
const size_t k_num_fpu_registers
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:63
#define DEFINE_FPU_UINT(reg)
Enumerations for broadcasting.
Definition: SBLaunchInfo.h:14
const lldb_private::RegisterSet * GetRegisterSet(size_t set) override
virtual int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr)=0
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:66
virtual int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc)=0
int GetError(int flavor, uint32_t err_idx) const
#define DEFINE_FPU_VECT(reg, i)
bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override
virtual int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr)=0
virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu)=0
static size_t k_num_register_infos
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:64
static const RegisterSet g_reg_sets[]
uint64_t GetAsUInt64(uint64_t fail_value=UINT64_MAX, bool *success_ptr=nullptr) const
#define REG_CONTEXT_SIZE
const size_t k_num_gpr_registers
const size_t k_num_regsets
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:65
static uint32_t g_exc_regnums[]
uint16_t GetAsUInt16(uint16_t fail_value=UINT16_MAX, bool *success_ptr=nullptr) const
bool ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override
uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, uint32_t num) override
Convert from a given register numbering scheme to the lldb register numbering scheme.
virtual lldb::tid_t GetThreadID() const
const void * GetBytes() const
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:67
const lldb_private::RegisterInfo * GetRegisterInfoAtIndex(size_t reg) override
#define DEFINE_GPR(reg, alt)
virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu)=0
#define DEFINE_EXC(reg)
void LogGPR(lldb_private::Log *log, const char *format,...)
uint32_t GetAsUInt32(uint32_t fail_value=UINT32_MAX, bool *success_ptr=nullptr) const
static RegisterInfo g_register_infos[]
bool SetError(int flavor, uint32_t err_idx, int err)
const size_t k_num_exc_registers
bool WriteRegister(const lldb_private::RegisterInfo *reg_info, const lldb_private::RegisterValue &value) override
Definition: SBAddress.h:15
bool ReadRegister(const lldb_private::RegisterInfo *reg_info, lldb_private::RegisterValue &value) override
virtual int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc)=0
void SetBytes(const void *bytes, size_t length, lldb::ByteOrder byte_order)
uint8_t GetAsUInt8(uint8_t fail_value=UINT8_MAX, bool *success_ptr=nullptr) const
static uint32_t g_gpr_regnums[]
lldb::ByteOrder InlHostByteOrder()
Definition: Endian.h:25
static uint32_t g_fpu_regnums[]
static const lldb_private::RegisterInfo * GetRegisterInfos()
void Printf(const char *format,...) __attribute__((format(printf
Definition: Log.cpp:113
int ReadRegisterSet(uint32_t set, bool force)
bool HardwareSingleStep(bool enable) override
RegisterContextDarwin_x86_64(lldb_private::Thread &thread, uint32_t concrete_frame_idx)
void void VAPrintf(const char *format, va_list args)
Definition: Log.cpp:123
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:90