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RegisterContextDarwin_x86_64.cpp
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1//===-- RegisterContextDarwin_x86_64.cpp ----------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include <cinttypes>
10#include <cstdarg>
11#include <cstddef>
12
13#include <memory>
14
17#include "lldb/Utility/Endian.h"
18#include "lldb/Utility/Log.h"
20#include "lldb/Utility/Scalar.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/Support/Compiler.h"
23
25
26using namespace lldb;
27using namespace lldb_private;
28
29enum {
51
86
90
92
93 // Aliases
102
145
147
148#define GPR_OFFSET(reg) \
149 (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::GPR, reg))
150#define FPU_OFFSET(reg) \
151 (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::FPU, reg) + \
152 sizeof(RegisterContextDarwin_x86_64::GPR))
153#define EXC_OFFSET(reg) \
154 (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::EXC, reg) + \
155 sizeof(RegisterContextDarwin_x86_64::GPR) + \
156 sizeof(RegisterContextDarwin_x86_64::FPU))
157
158// These macros will auto define the register name, alt name, register size,
159// register offset, encoding, format and native register. This ensures that the
160// register state structures are defined correctly and have the correct sizes
161// and offsets.
162#define DEFINE_GPR(reg, alt) \
163 #reg, alt, sizeof(((RegisterContextDarwin_x86_64::GPR *) NULL)->reg), \
164 GPR_OFFSET(reg), eEncodingUint, eFormatHex
165#define DEFINE_FPU_UINT(reg) \
166 #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg), \
167 FPU_OFFSET(reg), eEncodingUint, eFormatHex
168#define DEFINE_FPU_VECT(reg, i) \
169 #reg #i, NULL, \
170 sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg[i].bytes), \
171 FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8, \
172 {ehframe_dwarf_fpu_##reg##i, \
173 ehframe_dwarf_fpu_##reg##i, LLDB_INVALID_REGNUM, \
174 LLDB_INVALID_REGNUM, fpu_##reg##i }, \
175 nullptr, nullptr,
176#define DEFINE_EXC(reg) \
177 #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::EXC *) NULL)->reg), \
178 EXC_OFFSET(reg), eEncodingUint, eFormatHex
179
180#define REG_CONTEXT_SIZE \
181 (sizeof(RegisterContextDarwin_x86_64::GPR) + \
182 sizeof(RegisterContextDarwin_x86_64::FPU) + \
183 sizeof(RegisterContextDarwin_x86_64::EXC))
184
185// General purpose registers for 64 bit
186static RegisterInfo g_register_infos[] = {
187 // Macro auto defines most stuff EH_FRAME DWARF
188 // GENERIC PROCESS PLUGIN LLDB
189 // =============================== ======================
190 // =================== ========================== ====================
191 // ===================
192 {DEFINE_GPR(rax, nullptr),
195 nullptr,
196 nullptr,
197 },
198 {DEFINE_GPR(rbx, nullptr),
201 nullptr,
202 nullptr,
203 },
204 {DEFINE_GPR(rcx, nullptr),
207 nullptr,
208 nullptr,
209 },
210 {DEFINE_GPR(rdx, nullptr),
213 nullptr,
214 nullptr,
215 },
216 {DEFINE_GPR(rdi, nullptr),
219 nullptr,
220 nullptr,
221 },
222 {DEFINE_GPR(rsi, nullptr),
225 nullptr,
226 nullptr,
227 },
228 {DEFINE_GPR(rbp, "fp"),
231 nullptr,
232 nullptr,
233 },
234 {DEFINE_GPR(rsp, "sp"),
237 nullptr,
238 nullptr,
239 },
240 {DEFINE_GPR(r8, nullptr),
243 nullptr,
244 nullptr,
245 },
246 {DEFINE_GPR(r9, nullptr),
249 nullptr,
250 nullptr,
251 },
252 {DEFINE_GPR(r10, nullptr),
255 nullptr,
256 nullptr,
257 },
258 {DEFINE_GPR(r11, nullptr),
261 nullptr,
262 nullptr,
263 },
264 {DEFINE_GPR(r12, nullptr),
267 nullptr,
268 nullptr,
269 },
270 {DEFINE_GPR(r13, nullptr),
273 nullptr,
274 nullptr,
275 },
276 {DEFINE_GPR(r14, nullptr),
279 nullptr,
280 nullptr,
281 },
282 {DEFINE_GPR(r15, nullptr),
285 nullptr,
286 nullptr,
287 },
288 {DEFINE_GPR(rip, "pc"),
291 nullptr,
292 nullptr,
293 },
294 {DEFINE_GPR(rflags, "flags"),
297 nullptr,
298 nullptr,
299 },
300 {DEFINE_GPR(cs, nullptr),
303 nullptr,
304 nullptr,
305 },
306 {DEFINE_GPR(fs, nullptr),
309 nullptr,
310 nullptr,
311 },
312 {DEFINE_GPR(gs, nullptr),
315 nullptr,
316 nullptr,
317 },
318
319 {DEFINE_FPU_UINT(fcw),
322 nullptr,
323 nullptr,
324 },
325 {DEFINE_FPU_UINT(fsw),
328 nullptr,
329 nullptr,
330 },
331 {DEFINE_FPU_UINT(ftw),
334 nullptr,
335 nullptr,
336 },
337 {DEFINE_FPU_UINT(fop),
340 nullptr,
341 nullptr,
342 },
343 {DEFINE_FPU_UINT(ip),
346 nullptr,
347 nullptr,
348 },
349 {DEFINE_FPU_UINT(cs),
352 nullptr,
353 nullptr,
354 },
355 {DEFINE_FPU_UINT(dp),
358 nullptr,
359 nullptr,
360 },
361 {DEFINE_FPU_UINT(ds),
364 nullptr,
365 nullptr,
366 },
367 {DEFINE_FPU_UINT(mxcsr),
370 nullptr,
371 nullptr,
372 },
373 {DEFINE_FPU_UINT(mxcsrmask),
376 nullptr,
377 nullptr,
378 },
379 {DEFINE_FPU_VECT(stmm, 0)},
380 {DEFINE_FPU_VECT(stmm, 1)},
381 {DEFINE_FPU_VECT(stmm, 2)},
382 {DEFINE_FPU_VECT(stmm, 3)},
383 {DEFINE_FPU_VECT(stmm, 4)},
384 {DEFINE_FPU_VECT(stmm, 5)},
385 {DEFINE_FPU_VECT(stmm, 6)},
386 {DEFINE_FPU_VECT(stmm, 7)},
387 {DEFINE_FPU_VECT(xmm, 0)},
388 {DEFINE_FPU_VECT(xmm, 1)},
389 {DEFINE_FPU_VECT(xmm, 2)},
390 {DEFINE_FPU_VECT(xmm, 3)},
391 {DEFINE_FPU_VECT(xmm, 4)},
392 {DEFINE_FPU_VECT(xmm, 5)},
393 {DEFINE_FPU_VECT(xmm, 6)},
394 {DEFINE_FPU_VECT(xmm, 7)},
395 {DEFINE_FPU_VECT(xmm, 8)},
396 {DEFINE_FPU_VECT(xmm, 9)},
397 {DEFINE_FPU_VECT(xmm, 10)},
398 {DEFINE_FPU_VECT(xmm, 11)},
399 {DEFINE_FPU_VECT(xmm, 12)},
400 {DEFINE_FPU_VECT(xmm, 13)},
401 {DEFINE_FPU_VECT(xmm, 14)},
402 {DEFINE_FPU_VECT(xmm, 15)},
403
404 {DEFINE_EXC(trapno),
407 nullptr,
408 nullptr,
409 },
410 {DEFINE_EXC(err),
413 nullptr,
414 nullptr,
415 },
416 {DEFINE_EXC(faultvaddr),
419 nullptr,
420 nullptr,
421 }};
422
423static size_t k_num_register_infos = std::size(g_register_infos);
424
426 Thread &thread, uint32_t concrete_frame_idx)
427 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
428 uint32_t i;
429 for (i = 0; i < kNumErrors; i++) {
430 gpr_errs[i] = -1;
431 fpu_errs[i] = -1;
432 exc_errs[i] = -1;
433 }
434}
435
437
440}
441
444 return k_num_registers;
445}
446
447const RegisterInfo *
450 if (reg < k_num_registers)
451 return &g_register_infos[reg];
452 return nullptr;
453}
454
457}
458
459const lldb_private::RegisterInfo *
461 return g_register_infos;
462}
463
468
476
478
479// Number of registers in each register set
480const size_t k_num_gpr_registers = std::size(g_gpr_regnums);
481const size_t k_num_fpu_registers = std::size(g_fpu_regnums);
482const size_t k_num_exc_registers = std::size(g_exc_regnums);
483
484// Register set definitions. The first definitions at register set index of
485// zero is for all registers, followed by other registers sets. The register
486// information for the all register set need not be filled in.
487static const RegisterSet g_reg_sets[] = {
488 {
489 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
490 },
491 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
492 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
493
494const size_t k_num_regsets = std::size(g_reg_sets);
495
497 return k_num_regsets;
498}
499
500const RegisterSet *
502 if (reg_set < k_num_regsets)
503 return &g_reg_sets[reg_set];
504 return nullptr;
505}
506
508 if (reg_num < fpu_fcw)
509 return GPRRegSet;
510 else if (reg_num < exc_trapno)
511 return FPURegSet;
512 else if (reg_num < k_num_registers)
513 return EXCRegSet;
514 return -1;
515}
516
518 int set = GPRRegSet;
519 if (force || !RegisterSetIsCached(set)) {
520 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
521 }
522 return GetError(GPRRegSet, Read);
523}
524
526 int set = FPURegSet;
527 if (force || !RegisterSetIsCached(set)) {
528 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
529 }
530 return GetError(FPURegSet, Read);
531}
532
534 int set = EXCRegSet;
535 if (force || !RegisterSetIsCached(set)) {
536 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
537 }
538 return GetError(EXCRegSet, Read);
539}
540
542 int set = GPRRegSet;
543 if (!RegisterSetIsCached(set)) {
544 SetError(set, Write, -1);
545 return -1;
546 }
547 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
548 SetError(set, Read, -1);
549 return GetError(set, Write);
550}
551
553 int set = FPURegSet;
554 if (!RegisterSetIsCached(set)) {
555 SetError(set, Write, -1);
556 return -1;
557 }
558 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
559 SetError(set, Read, -1);
560 return GetError(set, Write);
561}
562
564 int set = EXCRegSet;
565 if (!RegisterSetIsCached(set)) {
566 SetError(set, Write, -1);
567 return -1;
568 }
569 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
570 SetError(set, Read, -1);
571 return GetError(set, Write);
572}
573
575 switch (set) {
576 case GPRRegSet:
577 return ReadGPR(force);
578 case FPURegSet:
579 return ReadFPU(force);
580 case EXCRegSet:
581 return ReadEXC(force);
582 default:
583 break;
584 }
585 return -1;
586}
587
589 // Make sure we have a valid context to set.
590 switch (set) {
591 case GPRRegSet:
592 return WriteGPR();
593 case FPURegSet:
594 return WriteFPU();
595 case EXCRegSet:
596 return WriteEXC();
597 default:
598 break;
599 }
600 return -1;
601}
602
603bool RegisterContextDarwin_x86_64::ReadRegister(const RegisterInfo *reg_info,
604 RegisterValue &value) {
605 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
607 if (set == -1)
608 return false;
609
610 if (ReadRegisterSet(set, false) != 0)
611 return false;
612
613 switch (reg) {
614 case gpr_rax:
615 case gpr_rbx:
616 case gpr_rcx:
617 case gpr_rdx:
618 case gpr_rdi:
619 case gpr_rsi:
620 case gpr_rbp:
621 case gpr_rsp:
622 case gpr_r8:
623 case gpr_r9:
624 case gpr_r10:
625 case gpr_r11:
626 case gpr_r12:
627 case gpr_r13:
628 case gpr_r14:
629 case gpr_r15:
630 case gpr_rip:
631 case gpr_rflags:
632 case gpr_cs:
633 case gpr_fs:
634 case gpr_gs:
635 value = (&gpr.rax)[reg - gpr_rax];
636 break;
637
638 case fpu_fcw:
639 value = fpu.fcw;
640 break;
641
642 case fpu_fsw:
643 value = fpu.fsw;
644 break;
645
646 case fpu_ftw:
647 value = fpu.ftw;
648 break;
649
650 case fpu_fop:
651 value = fpu.fop;
652 break;
653
654 case fpu_ip:
655 value = fpu.ip;
656 break;
657
658 case fpu_cs:
659 value = fpu.cs;
660 break;
661
662 case fpu_dp:
663 value = fpu.dp;
664 break;
665
666 case fpu_ds:
667 value = fpu.ds;
668 break;
669
670 case fpu_mxcsr:
671 value = fpu.mxcsr;
672 break;
673
674 case fpu_mxcsrmask:
675 value = fpu.mxcsrmask;
676 break;
677
678 case fpu_stmm0:
679 case fpu_stmm1:
680 case fpu_stmm2:
681 case fpu_stmm3:
682 case fpu_stmm4:
683 case fpu_stmm5:
684 case fpu_stmm6:
685 case fpu_stmm7:
686 value.SetBytes(fpu.stmm[reg - fpu_stmm0].bytes, reg_info->byte_size,
688 break;
689
690 case fpu_xmm0:
691 case fpu_xmm1:
692 case fpu_xmm2:
693 case fpu_xmm3:
694 case fpu_xmm4:
695 case fpu_xmm5:
696 case fpu_xmm6:
697 case fpu_xmm7:
698 case fpu_xmm8:
699 case fpu_xmm9:
700 case fpu_xmm10:
701 case fpu_xmm11:
702 case fpu_xmm12:
703 case fpu_xmm13:
704 case fpu_xmm14:
705 case fpu_xmm15:
706 value.SetBytes(fpu.xmm[reg - fpu_xmm0].bytes, reg_info->byte_size,
708 break;
709
710 case exc_trapno:
711 value = exc.trapno;
712 break;
713
714 case exc_err:
715 value = exc.err;
716 break;
717
718 case exc_faultvaddr:
719 value = exc.faultvaddr;
720 break;
721
722 default:
723 return false;
724 }
725 return true;
726}
727
728bool RegisterContextDarwin_x86_64::WriteRegister(const RegisterInfo *reg_info,
729 const RegisterValue &value) {
730 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
732
733 if (set == -1)
734 return false;
735
736 if (ReadRegisterSet(set, false) != 0)
737 return false;
738
739 switch (reg) {
740 case gpr_rax:
741 case gpr_rbx:
742 case gpr_rcx:
743 case gpr_rdx:
744 case gpr_rdi:
745 case gpr_rsi:
746 case gpr_rbp:
747 case gpr_rsp:
748 case gpr_r8:
749 case gpr_r9:
750 case gpr_r10:
751 case gpr_r11:
752 case gpr_r12:
753 case gpr_r13:
754 case gpr_r14:
755 case gpr_r15:
756 case gpr_rip:
757 case gpr_rflags:
758 case gpr_cs:
759 case gpr_fs:
760 case gpr_gs:
761 (&gpr.rax)[reg - gpr_rax] = value.GetAsUInt64();
762 break;
763
764 case fpu_fcw:
765 fpu.fcw = value.GetAsUInt16();
766 break;
767
768 case fpu_fsw:
769 fpu.fsw = value.GetAsUInt16();
770 break;
771
772 case fpu_ftw:
773 fpu.ftw = value.GetAsUInt8();
774 break;
775
776 case fpu_fop:
777 fpu.fop = value.GetAsUInt16();
778 break;
779
780 case fpu_ip:
781 fpu.ip = value.GetAsUInt32();
782 break;
783
784 case fpu_cs:
785 fpu.cs = value.GetAsUInt16();
786 break;
787
788 case fpu_dp:
789 fpu.dp = value.GetAsUInt32();
790 break;
791
792 case fpu_ds:
793 fpu.ds = value.GetAsUInt16();
794 break;
795
796 case fpu_mxcsr:
797 fpu.mxcsr = value.GetAsUInt32();
798 break;
799
800 case fpu_mxcsrmask:
801 fpu.mxcsrmask = value.GetAsUInt32();
802 break;
803
804 case fpu_stmm0:
805 case fpu_stmm1:
806 case fpu_stmm2:
807 case fpu_stmm3:
808 case fpu_stmm4:
809 case fpu_stmm5:
810 case fpu_stmm6:
811 case fpu_stmm7:
812 ::memcpy(fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(),
813 value.GetByteSize());
814 break;
815
816 case fpu_xmm0:
817 case fpu_xmm1:
818 case fpu_xmm2:
819 case fpu_xmm3:
820 case fpu_xmm4:
821 case fpu_xmm5:
822 case fpu_xmm6:
823 case fpu_xmm7:
824 case fpu_xmm8:
825 case fpu_xmm9:
826 case fpu_xmm10:
827 case fpu_xmm11:
828 case fpu_xmm12:
829 case fpu_xmm13:
830 case fpu_xmm14:
831 case fpu_xmm15:
832 ::memcpy(fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(),
833 value.GetByteSize());
834 return false;
835
836 case exc_trapno:
837 exc.trapno = value.GetAsUInt32();
838 break;
839
840 case exc_err:
841 exc.err = value.GetAsUInt32();
842 break;
843
844 case exc_faultvaddr:
845 exc.faultvaddr = value.GetAsUInt64();
846 break;
847
848 default:
849 return false;
850 }
851 return WriteRegisterSet(set) == 0;
852}
853
855 lldb::WritableDataBufferSP &data_sp) {
856 data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
857 if (ReadGPR(false) == 0 && ReadFPU(false) == 0 && ReadEXC(false) == 0) {
858 uint8_t *dst = data_sp->GetBytes();
859 ::memcpy(dst, &gpr, sizeof(gpr));
860 dst += sizeof(gpr);
861
862 ::memcpy(dst, &fpu, sizeof(fpu));
863 dst += sizeof(gpr);
864
865 ::memcpy(dst, &exc, sizeof(exc));
866 return true;
867 }
868 return false;
869}
870
872 const lldb::DataBufferSP &data_sp) {
873 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
874 const uint8_t *src = data_sp->GetBytes();
875 ::memcpy(&gpr, src, sizeof(gpr));
876 src += sizeof(gpr);
877
878 ::memcpy(&fpu, src, sizeof(fpu));
879 src += sizeof(gpr);
880
881 ::memcpy(&exc, src, sizeof(exc));
882 uint32_t success_count = 0;
883 if (WriteGPR() == 0)
884 ++success_count;
885 if (WriteFPU() == 0)
886 ++success_count;
887 if (WriteEXC() == 0)
888 ++success_count;
889 return success_count == 3;
890 }
891 return false;
892}
893
895 lldb::RegisterKind kind, uint32_t reg) {
896 if (kind == eRegisterKindGeneric) {
897 switch (reg) {
899 return gpr_rip;
901 return gpr_rsp;
903 return gpr_rbp;
905 return gpr_rflags;
907 default:
908 break;
909 }
910 } else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF) {
911 switch (reg) {
913 return gpr_rax;
915 return gpr_rdx;
917 return gpr_rcx;
919 return gpr_rbx;
921 return gpr_rsi;
923 return gpr_rdi;
925 return gpr_rbp;
927 return gpr_rsp;
929 return gpr_r8;
931 return gpr_r9;
933 return gpr_r10;
935 return gpr_r11;
937 return gpr_r12;
939 return gpr_r13;
941 return gpr_r14;
943 return gpr_r15;
945 return gpr_rip;
947 return fpu_xmm0;
949 return fpu_xmm1;
951 return fpu_xmm2;
953 return fpu_xmm3;
955 return fpu_xmm4;
957 return fpu_xmm5;
959 return fpu_xmm6;
961 return fpu_xmm7;
963 return fpu_xmm8;
965 return fpu_xmm9;
967 return fpu_xmm10;
969 return fpu_xmm11;
971 return fpu_xmm12;
973 return fpu_xmm13;
975 return fpu_xmm14;
977 return fpu_xmm15;
979 return fpu_stmm0;
981 return fpu_stmm1;
983 return fpu_stmm2;
985 return fpu_stmm3;
987 return fpu_stmm4;
989 return fpu_stmm5;
991 return fpu_stmm6;
993 return fpu_stmm7;
994 default:
995 break;
996 }
997 } else if (kind == eRegisterKindLLDB) {
998 return reg;
999 }
1000 return LLDB_INVALID_REGNUM;
1001}
1002
1004 if (ReadGPR(true) != 0)
1005 return false;
1006
1007 const uint64_t trace_bit = 0x100ull;
1008 if (enable) {
1009
1010 if (gpr.rflags & trace_bit)
1011 return true; // trace bit is already set, there is nothing to do
1012 else
1013 gpr.rflags |= trace_bit;
1014 } else {
1015 if (gpr.rflags & trace_bit)
1016 gpr.rflags &= ~trace_bit;
1017 else
1018 return true; // trace bit is clear, there is nothing to do
1019 }
1020
1021 return WriteGPR() == 0;
1022}
static const uint32_t k_num_register_infos
static const RegisterInfo g_register_infos[]
const size_t k_num_regsets
#define REG_CONTEXT_SIZE
const size_t k_num_regsets
static uint32_t g_fpu_regnums[]
static uint32_t g_gpr_regnums[]
static RegisterInfo g_register_infos[]
static uint32_t g_exc_regnums[]
const size_t k_num_gpr_registers
const size_t k_num_fpu_registers
#define DEFINE_EXC(reg)
#define DEFINE_FPU_VECT(reg, i)
#define DEFINE_FPU_UINT(reg)
static const RegisterSet g_reg_sets[]
const size_t k_num_exc_registers
#define DEFINE_GPR(reg, alt)
static size_t k_num_register_infos
static RegisterSet g_reg_sets[]
virtual int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc)=0
virtual int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc)=0
virtual int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr)=0
const lldb_private::RegisterInfo * GetRegisterInfoAtIndex(size_t reg) override
RegisterContextDarwin_x86_64(lldb_private::Thread &thread, uint32_t concrete_frame_idx)
virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu)=0
bool WriteRegister(const lldb_private::RegisterInfo *reg_info, const lldb_private::RegisterValue &value) override
virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu)=0
const lldb_private::RegisterSet * GetRegisterSet(size_t set) override
uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, uint32_t num) override
Convert from a given register numbering scheme to the lldb register numbering scheme.
bool ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override
int GetError(int flavor, uint32_t err_idx) const
bool SetError(int flavor, uint32_t err_idx, int err)
bool ReadRegister(const lldb_private::RegisterInfo *reg_info, lldb_private::RegisterValue &value) override
virtual int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr)=0
int ReadRegisterSet(uint32_t set, bool force)
static const lldb_private::RegisterInfo * GetRegisterInfos()
~RegisterContextDarwin_x86_64() override
bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override
bool HardwareSingleStep(bool enable) override
virtual lldb::tid_t GetThreadID() const
uint16_t GetAsUInt16(uint16_t fail_value=UINT16_MAX, bool *success_ptr=nullptr) const
uint8_t GetAsUInt8(uint8_t fail_value=UINT8_MAX, bool *success_ptr=nullptr) const
uint64_t GetAsUInt64(uint64_t fail_value=UINT64_MAX, bool *success_ptr=nullptr) const
void SetBytes(const void *bytes, size_t length, lldb::ByteOrder byte_order)
const void * GetBytes() const
uint32_t GetAsUInt32(uint32_t fail_value=UINT32_MAX, bool *success_ptr=nullptr) const
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:54
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:52
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:55
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:79
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:51
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:53
lldb::ByteOrder InlHostByteOrder()
Definition: Endian.h:25
A class that represents a running process on the host machine.
Definition: SBAttachInfo.h:14
Definition: SBAddress.h:15
RegisterKind
Register numbering types.
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target
@ eRegisterKindLLDB
lldb's internal register numbers
@ eRegisterKindDWARF
the register numbers seen DWARF
@ eRegisterKindEHFrame
the register numbers seen in eh_frame