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RegisterContextDarwin_x86_64.cpp
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1//===-- RegisterContextDarwin_x86_64.cpp ----------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include <cinttypes>
10#include <cstdarg>
11#include <cstddef>
12
13#include <memory>
14
17#include "lldb/Utility/Endian.h"
18#include "lldb/Utility/Log.h"
20#include "lldb/Utility/Scalar.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/Support/Compiler.h"
23
25
26using namespace lldb;
27using namespace lldb_private;
28
29enum {
51
86
90
92
93 // Aliases
102
145
147
148#define GPR_OFFSET(reg) \
149 (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::GPR, reg))
150#define FPU_OFFSET(reg) \
151 (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::FPU, reg) + \
152 sizeof(RegisterContextDarwin_x86_64::GPR))
153#define EXC_OFFSET(reg) \
154 (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::EXC, reg) + \
155 sizeof(RegisterContextDarwin_x86_64::GPR) + \
156 sizeof(RegisterContextDarwin_x86_64::FPU))
157
158// These macros will auto define the register name, alt name, register size,
159// register offset, encoding, format and native register. This ensures that the
160// register state structures are defined correctly and have the correct sizes
161// and offsets.
162#define DEFINE_GPR(reg, alt) \
163 #reg, alt, sizeof(((RegisterContextDarwin_x86_64::GPR *) NULL)->reg), \
164 GPR_OFFSET(reg), eEncodingUint, eFormatHex
165#define DEFINE_FPU_UINT(reg) \
166 #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg), \
167 FPU_OFFSET(reg), eEncodingUint, eFormatHex
168#define DEFINE_FPU_VECT(reg, i) \
169 #reg #i, NULL, \
170 sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg[i].bytes), \
171 FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8, \
172 {ehframe_dwarf_fpu_##reg##i, \
173 ehframe_dwarf_fpu_##reg##i, LLDB_INVALID_REGNUM, \
174 LLDB_INVALID_REGNUM, fpu_##reg##i }, \
175 nullptr, nullptr, nullptr,
176#define DEFINE_EXC(reg) \
177 #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::EXC *) NULL)->reg), \
178 EXC_OFFSET(reg), eEncodingUint, eFormatHex
179
180#define REG_CONTEXT_SIZE \
181 (sizeof(RegisterContextDarwin_x86_64::GPR) + \
182 sizeof(RegisterContextDarwin_x86_64::FPU) + \
183 sizeof(RegisterContextDarwin_x86_64::EXC))
184
185// General purpose registers for 64 bit
187 // Macro auto defines most stuff EH_FRAME DWARF
188 // GENERIC PROCESS PLUGIN LLDB
189 // =============================== ======================
190 // =================== ========================== ====================
191 // ===================
192 {DEFINE_GPR(rax, nullptr),
195 nullptr,
196 nullptr,
197 nullptr,
198 },
199 {DEFINE_GPR(rbx, nullptr),
202 nullptr,
203 nullptr,
204 nullptr,
205 },
206 {DEFINE_GPR(rcx, nullptr),
209 nullptr,
210 nullptr,
211 nullptr,
212 },
213 {DEFINE_GPR(rdx, nullptr),
216 nullptr,
217 nullptr,
218 nullptr,
219 },
220 {DEFINE_GPR(rdi, nullptr),
223 nullptr,
224 nullptr,
225 nullptr,
226 },
227 {DEFINE_GPR(rsi, nullptr),
230 nullptr,
231 nullptr,
232 nullptr,
233 },
234 {DEFINE_GPR(rbp, "fp"),
237 nullptr,
238 nullptr,
239 nullptr,
240 },
241 {DEFINE_GPR(rsp, "sp"),
244 nullptr,
245 nullptr,
246 nullptr,
247 },
248 {DEFINE_GPR(r8, nullptr),
251 nullptr,
252 nullptr,
253 nullptr,
254 },
255 {DEFINE_GPR(r9, nullptr),
258 nullptr,
259 nullptr,
260 nullptr,
261 },
262 {DEFINE_GPR(r10, nullptr),
265 nullptr,
266 nullptr,
267 nullptr,
268 },
269 {DEFINE_GPR(r11, nullptr),
272 nullptr,
273 nullptr,
274 nullptr,
275 },
276 {DEFINE_GPR(r12, nullptr),
279 nullptr,
280 nullptr,
281 nullptr,
282 },
283 {DEFINE_GPR(r13, nullptr),
286 nullptr,
287 nullptr,
288 nullptr,
289 },
290 {DEFINE_GPR(r14, nullptr),
293 nullptr,
294 nullptr,
295 nullptr,
296 },
297 {DEFINE_GPR(r15, nullptr),
300 nullptr,
301 nullptr,
302 nullptr,
303 },
304 {DEFINE_GPR(rip, "pc"),
307 nullptr,
308 nullptr,
309 nullptr,
310 },
311 {DEFINE_GPR(rflags, "flags"),
314 nullptr,
315 nullptr,
316 nullptr,
317 },
318 {DEFINE_GPR(cs, nullptr),
321 nullptr,
322 nullptr,
323 nullptr,
324 },
325 {DEFINE_GPR(fs, nullptr),
328 nullptr,
329 nullptr,
330 nullptr,
331 },
332 {DEFINE_GPR(gs, nullptr),
335 nullptr,
336 nullptr,
337 nullptr,
338 },
339
340 {DEFINE_FPU_UINT(fcw),
343 nullptr,
344 nullptr,
345 nullptr,
346 },
347 {DEFINE_FPU_UINT(fsw),
350 nullptr,
351 nullptr,
352 nullptr,
353 },
354 {DEFINE_FPU_UINT(ftw),
357 nullptr,
358 nullptr,
359 nullptr,
360 },
361 {DEFINE_FPU_UINT(fop),
364 nullptr,
365 nullptr,
366 nullptr,
367 },
368 {DEFINE_FPU_UINT(ip),
371 nullptr,
372 nullptr,
373 nullptr,
374 },
375 {DEFINE_FPU_UINT(cs),
378 nullptr,
379 nullptr,
380 nullptr,
381 },
382 {DEFINE_FPU_UINT(dp),
385 nullptr,
386 nullptr,
387 nullptr,
388 },
389 {DEFINE_FPU_UINT(ds),
392 nullptr,
393 nullptr,
394 nullptr,
395 },
396 {DEFINE_FPU_UINT(mxcsr),
399 nullptr,
400 nullptr,
401 nullptr,
402 },
403 {DEFINE_FPU_UINT(mxcsrmask),
406 nullptr,
407 nullptr,
408 nullptr,
409 },
410 {DEFINE_FPU_VECT(stmm, 0)},
411 {DEFINE_FPU_VECT(stmm, 1)},
412 {DEFINE_FPU_VECT(stmm, 2)},
413 {DEFINE_FPU_VECT(stmm, 3)},
414 {DEFINE_FPU_VECT(stmm, 4)},
415 {DEFINE_FPU_VECT(stmm, 5)},
416 {DEFINE_FPU_VECT(stmm, 6)},
417 {DEFINE_FPU_VECT(stmm, 7)},
418 {DEFINE_FPU_VECT(xmm, 0)},
419 {DEFINE_FPU_VECT(xmm, 1)},
420 {DEFINE_FPU_VECT(xmm, 2)},
421 {DEFINE_FPU_VECT(xmm, 3)},
422 {DEFINE_FPU_VECT(xmm, 4)},
423 {DEFINE_FPU_VECT(xmm, 5)},
424 {DEFINE_FPU_VECT(xmm, 6)},
425 {DEFINE_FPU_VECT(xmm, 7)},
426 {DEFINE_FPU_VECT(xmm, 8)},
427 {DEFINE_FPU_VECT(xmm, 9)},
428 {DEFINE_FPU_VECT(xmm, 10)},
429 {DEFINE_FPU_VECT(xmm, 11)},
430 {DEFINE_FPU_VECT(xmm, 12)},
431 {DEFINE_FPU_VECT(xmm, 13)},
432 {DEFINE_FPU_VECT(xmm, 14)},
433 {DEFINE_FPU_VECT(xmm, 15)},
434
435 {DEFINE_EXC(trapno),
438 nullptr,
439 nullptr,
440 nullptr,
441 },
442 {DEFINE_EXC(err),
445 nullptr,
446 nullptr,
447 nullptr,
448 },
449 {DEFINE_EXC(faultvaddr),
452 nullptr,
453 nullptr,
454 nullptr,
455 }};
456
457static size_t k_num_register_infos = std::size(g_register_infos);
458
460 Thread &thread, uint32_t concrete_frame_idx)
461 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
462 uint32_t i;
463 for (i = 0; i < kNumErrors; i++) {
464 gpr_errs[i] = -1;
465 fpu_errs[i] = -1;
466 exc_errs[i] = -1;
467 }
468}
469
471
474}
475
478 return k_num_registers;
479}
480
481const RegisterInfo *
484 if (reg < k_num_registers)
485 return &g_register_infos[reg];
486 return nullptr;
487}
488
491}
492
495 return g_register_infos;
496}
497
498static uint32_t g_gpr_regnums[] = {
502
503static uint32_t g_fpu_regnums[] = {
510
512
513// Number of registers in each register set
514const size_t k_num_gpr_registers = std::size(g_gpr_regnums);
515const size_t k_num_fpu_registers = std::size(g_fpu_regnums);
516const size_t k_num_exc_registers = std::size(g_exc_regnums);
517
518// Register set definitions. The first definitions at register set index of
519// zero is for all registers, followed by other registers sets. The register
520// information for the all register set need not be filled in.
521static const RegisterSet g_reg_sets[] = {
522 {
523 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
524 },
525 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
526 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
527
528const size_t k_num_regsets = std::size(g_reg_sets);
529
531 return k_num_regsets;
532}
533
534const RegisterSet *
536 if (reg_set < k_num_regsets)
537 return &g_reg_sets[reg_set];
538 return nullptr;
539}
540
542 if (reg_num < fpu_fcw)
543 return GPRRegSet;
544 else if (reg_num < exc_trapno)
545 return FPURegSet;
546 else if (reg_num < k_num_registers)
547 return EXCRegSet;
548 return -1;
549}
550
552 int set = GPRRegSet;
553 if (force || !RegisterSetIsCached(set)) {
554 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
555 }
556 return GetError(GPRRegSet, Read);
557}
558
560 int set = FPURegSet;
561 if (force || !RegisterSetIsCached(set)) {
562 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
563 }
564 return GetError(FPURegSet, Read);
565}
566
568 int set = EXCRegSet;
569 if (force || !RegisterSetIsCached(set)) {
570 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
571 }
572 return GetError(EXCRegSet, Read);
573}
574
576 int set = GPRRegSet;
577 if (!RegisterSetIsCached(set)) {
578 SetError(set, Write, -1);
579 return -1;
580 }
581 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
582 SetError(set, Read, -1);
583 return GetError(set, Write);
584}
585
587 int set = FPURegSet;
588 if (!RegisterSetIsCached(set)) {
589 SetError(set, Write, -1);
590 return -1;
591 }
592 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
593 SetError(set, Read, -1);
594 return GetError(set, Write);
595}
596
598 int set = EXCRegSet;
599 if (!RegisterSetIsCached(set)) {
600 SetError(set, Write, -1);
601 return -1;
602 }
603 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
604 SetError(set, Read, -1);
605 return GetError(set, Write);
606}
607
609 switch (set) {
610 case GPRRegSet:
611 return ReadGPR(force);
612 case FPURegSet:
613 return ReadFPU(force);
614 case EXCRegSet:
615 return ReadEXC(force);
616 default:
617 break;
618 }
619 return -1;
620}
621
623 // Make sure we have a valid context to set.
624 switch (set) {
625 case GPRRegSet:
626 return WriteGPR();
627 case FPURegSet:
628 return WriteFPU();
629 case EXCRegSet:
630 return WriteEXC();
631 default:
632 break;
633 }
634 return -1;
635}
636
638 RegisterValue &value) {
639 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
641 if (set == -1)
642 return false;
643
644 if (ReadRegisterSet(set, false) != 0)
645 return false;
646
647 switch (reg) {
648 case gpr_rax:
649 case gpr_rbx:
650 case gpr_rcx:
651 case gpr_rdx:
652 case gpr_rdi:
653 case gpr_rsi:
654 case gpr_rbp:
655 case gpr_rsp:
656 case gpr_r8:
657 case gpr_r9:
658 case gpr_r10:
659 case gpr_r11:
660 case gpr_r12:
661 case gpr_r13:
662 case gpr_r14:
663 case gpr_r15:
664 case gpr_rip:
665 case gpr_rflags:
666 case gpr_cs:
667 case gpr_fs:
668 case gpr_gs:
669 value = (&gpr.rax)[reg - gpr_rax];
670 break;
671
672 case fpu_fcw:
673 value = fpu.fcw;
674 break;
675
676 case fpu_fsw:
677 value = fpu.fsw;
678 break;
679
680 case fpu_ftw:
681 value = fpu.ftw;
682 break;
683
684 case fpu_fop:
685 value = fpu.fop;
686 break;
687
688 case fpu_ip:
689 value = fpu.ip;
690 break;
691
692 case fpu_cs:
693 value = fpu.cs;
694 break;
695
696 case fpu_dp:
697 value = fpu.dp;
698 break;
699
700 case fpu_ds:
701 value = fpu.ds;
702 break;
703
704 case fpu_mxcsr:
705 value = fpu.mxcsr;
706 break;
707
708 case fpu_mxcsrmask:
709 value = fpu.mxcsrmask;
710 break;
711
712 case fpu_stmm0:
713 case fpu_stmm1:
714 case fpu_stmm2:
715 case fpu_stmm3:
716 case fpu_stmm4:
717 case fpu_stmm5:
718 case fpu_stmm6:
719 case fpu_stmm7:
720 value.SetBytes(fpu.stmm[reg - fpu_stmm0].bytes, reg_info->byte_size,
722 break;
723
724 case fpu_xmm0:
725 case fpu_xmm1:
726 case fpu_xmm2:
727 case fpu_xmm3:
728 case fpu_xmm4:
729 case fpu_xmm5:
730 case fpu_xmm6:
731 case fpu_xmm7:
732 case fpu_xmm8:
733 case fpu_xmm9:
734 case fpu_xmm10:
735 case fpu_xmm11:
736 case fpu_xmm12:
737 case fpu_xmm13:
738 case fpu_xmm14:
739 case fpu_xmm15:
740 value.SetBytes(fpu.xmm[reg - fpu_xmm0].bytes, reg_info->byte_size,
742 break;
743
744 case exc_trapno:
745 value = exc.trapno;
746 break;
747
748 case exc_err:
749 value = exc.err;
750 break;
751
752 case exc_faultvaddr:
753 value = exc.faultvaddr;
754 break;
755
756 default:
757 return false;
758 }
759 return true;
760}
761
763 const RegisterValue &value) {
764 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
766
767 if (set == -1)
768 return false;
769
770 if (ReadRegisterSet(set, false) != 0)
771 return false;
772
773 switch (reg) {
774 case gpr_rax:
775 case gpr_rbx:
776 case gpr_rcx:
777 case gpr_rdx:
778 case gpr_rdi:
779 case gpr_rsi:
780 case gpr_rbp:
781 case gpr_rsp:
782 case gpr_r8:
783 case gpr_r9:
784 case gpr_r10:
785 case gpr_r11:
786 case gpr_r12:
787 case gpr_r13:
788 case gpr_r14:
789 case gpr_r15:
790 case gpr_rip:
791 case gpr_rflags:
792 case gpr_cs:
793 case gpr_fs:
794 case gpr_gs:
795 (&gpr.rax)[reg - gpr_rax] = value.GetAsUInt64();
796 break;
797
798 case fpu_fcw:
799 fpu.fcw = value.GetAsUInt16();
800 break;
801
802 case fpu_fsw:
803 fpu.fsw = value.GetAsUInt16();
804 break;
805
806 case fpu_ftw:
807 fpu.ftw = value.GetAsUInt8();
808 break;
809
810 case fpu_fop:
811 fpu.fop = value.GetAsUInt16();
812 break;
813
814 case fpu_ip:
815 fpu.ip = value.GetAsUInt32();
816 break;
817
818 case fpu_cs:
819 fpu.cs = value.GetAsUInt16();
820 break;
821
822 case fpu_dp:
823 fpu.dp = value.GetAsUInt32();
824 break;
825
826 case fpu_ds:
827 fpu.ds = value.GetAsUInt16();
828 break;
829
830 case fpu_mxcsr:
831 fpu.mxcsr = value.GetAsUInt32();
832 break;
833
834 case fpu_mxcsrmask:
835 fpu.mxcsrmask = value.GetAsUInt32();
836 break;
837
838 case fpu_stmm0:
839 case fpu_stmm1:
840 case fpu_stmm2:
841 case fpu_stmm3:
842 case fpu_stmm4:
843 case fpu_stmm5:
844 case fpu_stmm6:
845 case fpu_stmm7:
846 ::memcpy(fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(),
847 value.GetByteSize());
848 break;
849
850 case fpu_xmm0:
851 case fpu_xmm1:
852 case fpu_xmm2:
853 case fpu_xmm3:
854 case fpu_xmm4:
855 case fpu_xmm5:
856 case fpu_xmm6:
857 case fpu_xmm7:
858 case fpu_xmm8:
859 case fpu_xmm9:
860 case fpu_xmm10:
861 case fpu_xmm11:
862 case fpu_xmm12:
863 case fpu_xmm13:
864 case fpu_xmm14:
865 case fpu_xmm15:
866 ::memcpy(fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(),
867 value.GetByteSize());
868 return false;
869
870 case exc_trapno:
871 exc.trapno = value.GetAsUInt32();
872 break;
873
874 case exc_err:
875 exc.err = value.GetAsUInt32();
876 break;
877
878 case exc_faultvaddr:
879 exc.faultvaddr = value.GetAsUInt64();
880 break;
881
882 default:
883 return false;
884 }
885 return WriteRegisterSet(set) == 0;
886}
887
890 data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
891 if (ReadGPR(false) == 0 && ReadFPU(false) == 0 && ReadEXC(false) == 0) {
892 uint8_t *dst = data_sp->GetBytes();
893 ::memcpy(dst, &gpr, sizeof(gpr));
894 dst += sizeof(gpr);
895
896 ::memcpy(dst, &fpu, sizeof(fpu));
897 dst += sizeof(gpr);
898
899 ::memcpy(dst, &exc, sizeof(exc));
900 return true;
901 }
902 return false;
903}
904
906 const lldb::DataBufferSP &data_sp) {
907 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
908 const uint8_t *src = data_sp->GetBytes();
909 ::memcpy(&gpr, src, sizeof(gpr));
910 src += sizeof(gpr);
911
912 ::memcpy(&fpu, src, sizeof(fpu));
913 src += sizeof(gpr);
914
915 ::memcpy(&exc, src, sizeof(exc));
916 uint32_t success_count = 0;
917 if (WriteGPR() == 0)
918 ++success_count;
919 if (WriteFPU() == 0)
920 ++success_count;
921 if (WriteEXC() == 0)
922 ++success_count;
923 return success_count == 3;
924 }
925 return false;
926}
927
929 lldb::RegisterKind kind, uint32_t reg) {
930 if (kind == eRegisterKindGeneric) {
931 switch (reg) {
933 return gpr_rip;
935 return gpr_rsp;
937 return gpr_rbp;
939 return gpr_rflags;
941 default:
942 break;
943 }
944 } else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF) {
945 switch (reg) {
947 return gpr_rax;
949 return gpr_rdx;
951 return gpr_rcx;
953 return gpr_rbx;
955 return gpr_rsi;
957 return gpr_rdi;
959 return gpr_rbp;
961 return gpr_rsp;
963 return gpr_r8;
965 return gpr_r9;
967 return gpr_r10;
969 return gpr_r11;
971 return gpr_r12;
973 return gpr_r13;
975 return gpr_r14;
977 return gpr_r15;
979 return gpr_rip;
981 return fpu_xmm0;
983 return fpu_xmm1;
985 return fpu_xmm2;
987 return fpu_xmm3;
989 return fpu_xmm4;
991 return fpu_xmm5;
993 return fpu_xmm6;
995 return fpu_xmm7;
997 return fpu_xmm8;
999 return fpu_xmm9;
1001 return fpu_xmm10;
1003 return fpu_xmm11;
1005 return fpu_xmm12;
1007 return fpu_xmm13;
1009 return fpu_xmm14;
1011 return fpu_xmm15;
1013 return fpu_stmm0;
1015 return fpu_stmm1;
1017 return fpu_stmm2;
1019 return fpu_stmm3;
1021 return fpu_stmm4;
1023 return fpu_stmm5;
1025 return fpu_stmm6;
1027 return fpu_stmm7;
1028 default:
1029 break;
1030 }
1031 } else if (kind == eRegisterKindLLDB) {
1032 return reg;
1033 }
1034 return LLDB_INVALID_REGNUM;
1035}
1036
1038 if (ReadGPR(true) != 0)
1039 return false;
1040
1041 const uint64_t trace_bit = 0x100ull;
1042 if (enable) {
1043
1044 if (gpr.rflags & trace_bit)
1045 return true; // trace bit is already set, there is nothing to do
1046 else
1047 gpr.rflags |= trace_bit;
1048 } else {
1049 if (gpr.rflags & trace_bit)
1050 gpr.rflags &= ~trace_bit;
1051 else
1052 return true; // trace bit is clear, there is nothing to do
1053 }
1054
1055 return WriteGPR() == 0;
1056}
static const uint32_t k_num_register_infos
static const RegisterInfo g_register_infos[]
const size_t k_num_regsets
#define REG_CONTEXT_SIZE
const size_t k_num_regsets
static uint32_t g_fpu_regnums[]
static uint32_t g_gpr_regnums[]
static RegisterInfo g_register_infos[]
static uint32_t g_exc_regnums[]
const size_t k_num_gpr_registers
const size_t k_num_fpu_registers
#define DEFINE_EXC(reg)
#define DEFINE_FPU_VECT(reg, i)
#define DEFINE_FPU_UINT(reg)
static const RegisterSet g_reg_sets[]
const size_t k_num_exc_registers
#define DEFINE_GPR(reg, alt)
static size_t k_num_register_infos
static RegisterSet g_reg_sets[]
virtual int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc)=0
virtual int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc)=0
virtual int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr)=0
const lldb_private::RegisterInfo * GetRegisterInfoAtIndex(size_t reg) override
RegisterContextDarwin_x86_64(lldb_private::Thread &thread, uint32_t concrete_frame_idx)
virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu)=0
bool WriteRegister(const lldb_private::RegisterInfo *reg_info, const lldb_private::RegisterValue &value) override
virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu)=0
const lldb_private::RegisterSet * GetRegisterSet(size_t set) override
uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, uint32_t num) override
Convert from a given register numbering scheme to the lldb register numbering scheme.
bool ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override
int GetError(int flavor, uint32_t err_idx) const
bool SetError(int flavor, uint32_t err_idx, int err)
bool ReadRegister(const lldb_private::RegisterInfo *reg_info, lldb_private::RegisterValue &value) override
virtual int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr)=0
int ReadRegisterSet(uint32_t set, bool force)
static const lldb_private::RegisterInfo * GetRegisterInfos()
~RegisterContextDarwin_x86_64() override
bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override
bool HardwareSingleStep(bool enable) override
virtual lldb::tid_t GetThreadID() const
uint16_t GetAsUInt16(uint16_t fail_value=UINT16_MAX, bool *success_ptr=nullptr) const
uint8_t GetAsUInt8(uint8_t fail_value=UINT8_MAX, bool *success_ptr=nullptr) const
uint64_t GetAsUInt64(uint64_t fail_value=UINT64_MAX, bool *success_ptr=nullptr) const
void SetBytes(const void *bytes, size_t length, lldb::ByteOrder byte_order)
const void * GetBytes() const
uint32_t GetAsUInt32(uint32_t fail_value=UINT32_MAX, bool *success_ptr=nullptr) const
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:59
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:57
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:60
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:87
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:56
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:58
lldb::ByteOrder InlHostByteOrder()
Definition: Endian.h:25
A class that represents a running process on the host machine.
Definition: SBAddress.h:15
std::shared_ptr< lldb_private::DataBuffer > DataBufferSP
Definition: lldb-forward.h:334
std::shared_ptr< lldb_private::WritableDataBuffer > WritableDataBufferSP
Definition: lldb-forward.h:335
RegisterKind
Register numbering types.
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target
@ eRegisterKindLLDB
lldb's internal register numbers
@ eRegisterKindDWARF
the register numbers seen DWARF
@ eRegisterKindEHFrame
the register numbers seen in eh_frame
Every register is described in detail including its name, alternate name (optional),...
uint32_t byte_size
Size in bytes of the register.
uint32_t kinds[lldb::kNumRegisterKinds]
Holds all of the various register numbers for all register kinds.
Registers are grouped into register sets.