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RegisterInfoPOSIX_arm64.cpp
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1//===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===---------------------------------------------------------------------===//
8
9#include <cassert>
10#include <cstddef>
11#include <vector>
12
13#include "lldb/lldb-defines.h"
14#include "llvm/Support/Compiler.h"
15
17
18// Based on RegisterContextDarwin_arm64.cpp
19#define GPR_OFFSET(idx) ((idx)*8)
20#define GPR_OFFSET_NAME(reg) \
21 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
22
23#define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
24#define FPU_OFFSET_NAME(reg) \
25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
26 sizeof(RegisterInfoPOSIX_arm64::GPR))
27
28// This information is based on AArch64 with SVE architecture reference manual.
29// AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
30// (First Fault) register and a VG (Vector Granule) pseudo register.
31
32// SVE 16-byte quad word is the basic unit of expansion in vector length.
33#define SVE_QUAD_WORD_BYTES 16
34
35// Vector length is the multiplier which decides the no of quad words,
36// (multiples of 128-bits or 16-bytes) present in a Z register. Vector length
37// is decided during execution and can change at runtime. SVE AArch64 register
38// infos have modes one for each valid value of vector length. A change in
39// vector length requires register context to update sizes of SVE Z, P and FFR.
40// Also register context needs to update byte offsets of all registers affected
41// by the change in vector length.
42#define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR)
43
44#define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
45
46#define EXC_OFFSET_NAME(reg) \
47 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \
48 sizeof(RegisterInfoPOSIX_arm64::GPR) + \
49 sizeof(RegisterInfoPOSIX_arm64::FPU))
50#define DBG_OFFSET_NAME(reg) \
51 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \
52 sizeof(RegisterInfoPOSIX_arm64::GPR) + \
53 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
54 sizeof(RegisterInfoPOSIX_arm64::EXC))
55
56#define DEFINE_DBG(reg, i) \
57 #reg, NULL, \
58 sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \
59 DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
60 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
61 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
62 dbg_##reg##i }, \
63 NULL, NULL, NULL,
64#define REG_CONTEXT_SIZE \
65 (sizeof(RegisterInfoPOSIX_arm64::GPR) + \
66 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
67 sizeof(RegisterInfoPOSIX_arm64::EXC))
68
69// Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
70#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
71#include "RegisterInfos_arm64.h"
73#undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
74
76 DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)};
77
79 DEFINE_EXTENSION_REG(mte_ctrl)};
80
82 DEFINE_EXTENSION_REG(tpidr),
83 // Only present when SME is present
84 DEFINE_EXTENSION_REG(tpidr2)};
85
87 DEFINE_EXTENSION_REG(svcr),
88 DEFINE_EXTENSION_REG(svg),
89 // 16 is a default size we will change later.
91 KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
92
93// Number of register sets provided by this context.
94enum {
95 k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
96 k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
97 k_num_sve_registers = sve_ffr - sve_vg + 1,
99 // Number of TLS registers is dynamic so it is not listed here.
105
106// ARM64 general purpose registers.
107static const uint32_t g_gpr_regnums_arm64[] = {
108 gpr_x0, gpr_x1, gpr_x2, gpr_x3,
109 gpr_x4, gpr_x5, gpr_x6, gpr_x7,
110 gpr_x8, gpr_x9, gpr_x10, gpr_x11,
111 gpr_x12, gpr_x13, gpr_x14, gpr_x15,
112 gpr_x16, gpr_x17, gpr_x18, gpr_x19,
113 gpr_x20, gpr_x21, gpr_x22, gpr_x23,
114 gpr_x24, gpr_x25, gpr_x26, gpr_x27,
115 gpr_x28, gpr_fp, gpr_lr, gpr_sp,
116 gpr_pc, gpr_cpsr, gpr_w0, gpr_w1,
117 gpr_w2, gpr_w3, gpr_w4, gpr_w5,
118 gpr_w6, gpr_w7, gpr_w8, gpr_w9,
119 gpr_w10, gpr_w11, gpr_w12, gpr_w13,
120 gpr_w14, gpr_w15, gpr_w16, gpr_w17,
121 gpr_w18, gpr_w19, gpr_w20, gpr_w21,
122 gpr_w22, gpr_w23, gpr_w24, gpr_w25,
123 gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM};
124
125static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) -
127 "g_gpr_regnums_arm64 has wrong number of register infos");
128
129// ARM64 floating point registers.
130static const uint32_t g_fpu_regnums_arm64[] = {
131 fpu_v0, fpu_v1, fpu_v2,
132 fpu_v3, fpu_v4, fpu_v5,
133 fpu_v6, fpu_v7, fpu_v8,
134 fpu_v9, fpu_v10, fpu_v11,
135 fpu_v12, fpu_v13, fpu_v14,
136 fpu_v15, fpu_v16, fpu_v17,
137 fpu_v18, fpu_v19, fpu_v20,
138 fpu_v21, fpu_v22, fpu_v23,
139 fpu_v24, fpu_v25, fpu_v26,
140 fpu_v27, fpu_v28, fpu_v29,
141 fpu_v30, fpu_v31, fpu_s0,
152 fpu_s31, fpu_d0, fpu_d1,
153 fpu_d2, fpu_d3, fpu_d4,
154 fpu_d5, fpu_d6, fpu_d7,
155 fpu_d8, fpu_d9, fpu_d10,
156 fpu_d11, fpu_d12, fpu_d13,
157 fpu_d14, fpu_d15, fpu_d16,
158 fpu_d17, fpu_d18, fpu_d19,
159 fpu_d20, fpu_d21, fpu_d22,
160 fpu_d23, fpu_d24, fpu_d25,
161 fpu_d26, fpu_d27, fpu_d28,
162 fpu_d29, fpu_d30, fpu_d31,
163 fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM};
164static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) -
166 "g_fpu_regnums_arm64 has wrong number of register infos");
167
168// ARM64 SVE registers.
169static const uint32_t g_sve_regnums_arm64[] = {
170 sve_vg, sve_z0, sve_z1,
171 sve_z2, sve_z3, sve_z4,
172 sve_z5, sve_z6, sve_z7,
173 sve_z8, sve_z9, sve_z10,
174 sve_z11, sve_z12, sve_z13,
175 sve_z14, sve_z15, sve_z16,
176 sve_z17, sve_z18, sve_z19,
177 sve_z20, sve_z21, sve_z22,
178 sve_z23, sve_z24, sve_z25,
179 sve_z26, sve_z27, sve_z28,
180 sve_z29, sve_z30, sve_z31,
181 sve_p0, sve_p1, sve_p2,
182 sve_p3, sve_p4, sve_p5,
183 sve_p6, sve_p7, sve_p8,
184 sve_p9, sve_p10, sve_p11,
185 sve_p12, sve_p13, sve_p14,
186 sve_p15, sve_ffr, LLDB_INVALID_REGNUM};
187static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) -
189 "g_sve_regnums_arm64 has wrong number of register infos");
190
191// Register sets for ARM64.
193 {"General Purpose Registers", "gpr", k_num_gpr_registers,
195 {"Floating Point Registers", "fpu", k_num_fpr_registers,
197 {"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
199
201 "Pointer Authentication Registers", "pauth", k_num_pauth_register, nullptr};
202
204 "MTE Control Register", "mte", k_num_mte_register, nullptr};
205
206// The size of the TLS set is dynamic, so not listed here.
207
209 "Scalable Matrix Extension Registers", "sme", k_num_sme_register, nullptr};
210
212 const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
213 : lldb_private::RegisterInfoAndSetInterface(target_arch),
214 m_opt_regsets(opt_regsets) {
215 switch (target_arch.GetMachine()) {
216 case llvm::Triple::aarch64:
217 case llvm::Triple::aarch64_32: {
220 m_per_regset_regnum_range[GPRegSet] = std::make_pair(gpr_x0, gpr_w28 + 1);
221 m_per_regset_regnum_range[FPRegSet] = std::make_pair(fpu_v0, fpu_fpcr + 1);
222
223 // Now configure register sets supported by current target. If we have a
224 // dynamic register set like MTE, Pointer Authentication regset then we need
225 // to create dynamic register infos and regset array. Push back all optional
226 // register infos and regset and calculate register offsets accordingly.
228 m_register_info_p = g_register_infos_arm64_sve_le;
229 m_register_info_count = sve_ffr + 1;
231 std::make_pair(sve_vg, sve_ffr + 1);
232 } else {
233 m_register_info_p = g_register_infos_arm64_le;
234 m_register_info_count = fpu_fpcr + 1;
235 }
236
238 llvm::ArrayRef<lldb_private::RegisterInfo> reg_infos_ref =
240 llvm::ArrayRef<lldb_private::RegisterSet> reg_sets_ref =
241 llvm::ArrayRef(m_register_set_p, m_register_set_count);
242 llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos));
243 llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets));
244
247
249 AddRegSetMTE();
250
251 // The TLS set always contains tpidr but only has tpidr2 when SME is
252 // present.
254
256 AddRegSetSME();
257
262 }
263 break;
264 }
265 default:
266 assert(false && "Unhandled target architecture.");
267 }
268}
269
272}
273
275 return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
276}
277
279 return sizeof(struct RegisterInfoPOSIX_arm64::FPU);
280}
281
284 return m_register_info_p;
285}
286
289}
290
292 uint32_t reg_index) const {
293 for (const auto &regset_range : m_per_regset_regnum_range) {
294 if (reg_index >= regset_range.second.first &&
295 reg_index < regset_range.second.second)
296 return regset_range.first;
297 }
298 return LLDB_INVALID_REGNUM;
299}
300
303 if (set_index < GetRegisterSetCount())
304 return &m_register_set_p[set_index];
305 return nullptr;
306}
307
309 uint32_t pa_regnum = m_dynamic_reg_infos.size();
310 for (uint32_t i = 0; i < k_num_pauth_register; i++) {
311 pauth_regnum_collection.push_back(pa_regnum + i);
313 m_dynamic_reg_infos[pa_regnum + i].byte_offset =
314 m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset +
315 m_dynamic_reg_infos[pa_regnum + i - 1].byte_size;
316 m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] =
317 pa_regnum + i;
318 }
319
321 std::make_pair(pa_regnum, m_dynamic_reg_infos.size());
323 m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
324}
325
327 uint32_t mte_regnum = m_dynamic_reg_infos.size();
328 m_mte_regnum_collection.push_back(mte_regnum);
330 m_dynamic_reg_infos[mte_regnum].byte_offset =
331 m_dynamic_reg_infos[mte_regnum - 1].byte_offset +
332 m_dynamic_reg_infos[mte_regnum - 1].byte_size;
333 m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum;
334
336 std::make_pair(mte_regnum, mte_regnum + 1);
338 m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
339}
340
342 uint32_t tls_regnum = m_dynamic_reg_infos.size();
343 uint32_t num_regs = has_tpidr2 ? 2 : 1;
344 for (uint32_t i = 0; i < num_regs; i++) {
345 m_tls_regnum_collection.push_back(tls_regnum + i);
347 m_dynamic_reg_infos[tls_regnum + i].byte_offset =
348 m_dynamic_reg_infos[tls_regnum + i - 1].byte_offset +
349 m_dynamic_reg_infos[tls_regnum + i - 1].byte_size;
350 m_dynamic_reg_infos[tls_regnum + i].kinds[lldb::eRegisterKindLLDB] =
351 tls_regnum + i;
352 }
353
355 std::make_pair(tls_regnum, m_dynamic_reg_infos.size());
356 m_dynamic_reg_sets.push_back(
357 {"Thread Local Storage Registers", "tls", num_regs, nullptr});
358 m_dynamic_reg_sets.back().registers = m_tls_regnum_collection.data();
359}
360
362 uint32_t sme_regnum = m_dynamic_reg_infos.size();
363 for (uint32_t i = 0; i < k_num_sme_register; i++) {
364 m_sme_regnum_collection.push_back(sme_regnum + i);
366 m_dynamic_reg_infos[sme_regnum + i].byte_offset =
367 m_dynamic_reg_infos[sme_regnum + i - 1].byte_offset +
368 m_dynamic_reg_infos[sme_regnum + i - 1].byte_size;
369 m_dynamic_reg_infos[sme_regnum + i].kinds[lldb::eRegisterKindLLDB] =
370 sme_regnum + i;
371 }
372
374 std::make_pair(sme_regnum, m_dynamic_reg_infos.size());
376 m_dynamic_reg_sets.back().registers = m_sme_regnum_collection.data();
377}
378
380 // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
381 // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
382 // Also if an invalid or previously set vector length is passed to this
383 // function then it will exit immediately with previously set vector length.
384 if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
385 return m_vector_reg_vq;
386
387 // We cannot enable AArch64 only mode if SVE was enabled.
388 if (sve_vq == eVectorQuadwordAArch64 &&
391
392 m_vector_reg_vq = sve_vq;
393
394 if (sve_vq == eVectorQuadwordAArch64)
395 return m_vector_reg_vq;
396 std::vector<lldb_private::RegisterInfo> &reg_info_ref =
397 m_per_vq_reg_infos[sve_vq];
398
399 if (reg_info_ref.empty()) {
400 reg_info_ref = llvm::ArrayRef(m_register_info_p, m_register_info_count);
401
402 uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX;
403 reg_info_ref[fpu_fpsr].byte_offset = offset;
404 reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
405 reg_info_ref[sve_vg].byte_offset = offset + 8;
406 offset += 16;
407
408 // Update Z registers size and offset
409 uint32_t s_reg_base = fpu_s0;
410 uint32_t d_reg_base = fpu_d0;
411 uint32_t v_reg_base = fpu_v0;
412 uint32_t z_reg_base = sve_z0;
413
414 for (uint32_t index = 0; index < 32; index++) {
415 reg_info_ref[s_reg_base + index].byte_offset = offset;
416 reg_info_ref[d_reg_base + index].byte_offset = offset;
417 reg_info_ref[v_reg_base + index].byte_offset = offset;
418 reg_info_ref[z_reg_base + index].byte_offset = offset;
419
420 reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES;
421 offset += reg_info_ref[z_reg_base + index].byte_size;
422 }
423
424 // Update P registers and FFR size and offset
425 for (uint32_t it = sve_p0; it <= sve_ffr; it++) {
426 reg_info_ref[it].byte_offset = offset;
427 reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8;
428 offset += reg_info_ref[it].byte_size;
429 }
430
431 for (uint32_t it = sve_ffr + 1; it < m_register_info_count; it++) {
432 reg_info_ref[it].byte_offset = offset;
433 offset += reg_info_ref[it].byte_size;
434 }
435
436 m_per_vq_reg_infos[sve_vq] = reg_info_ref;
437 }
438
439 m_register_info_p = m_per_vq_reg_infos[sve_vq].data();
440 return m_vector_reg_vq;
441}
442
444 if (!VectorSizeIsValid(za_vq) || m_za_reg_vq == za_vq)
445 return;
446
447 m_za_reg_vq = za_vq;
448
449 // For SVE changes, we replace m_register_info_p completely. ZA is in a
450 // dynamic set and is just 1 register so we make an exception to const here.
451 lldb_private::RegisterInfo *non_const_reginfo =
453 non_const_reginfo[m_sme_regnum_collection[2]].byte_size =
454 (za_vq * 16) * (za_vq * 16);
455}
456
457bool RegisterInfoPOSIX_arm64::IsSVEReg(unsigned reg) const {
459 return (sve_vg <= reg && reg <= sve_ffr);
460 else
461 return false;
462}
463
464bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const {
465 return (sve_z0 <= reg && reg <= sve_z31);
466}
467
468bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const {
469 return (sve_p0 <= reg && reg <= sve_p15);
470}
471
472bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
473 return sve_vg == reg;
474}
475
476bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
477 return reg == m_sme_regnum_collection[2];
478}
479
480bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
481 return llvm::is_contained(pauth_regnum_collection, reg);
482}
483
484bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
485 return llvm::is_contained(m_mte_regnum_collection, reg);
486}
487
488bool RegisterInfoPOSIX_arm64::IsTLSReg(unsigned reg) const {
489 return llvm::is_contained(m_tls_regnum_collection, reg);
490}
491
492bool RegisterInfoPOSIX_arm64::IsSMEReg(unsigned reg) const {
493 return llvm::is_contained(m_sme_regnum_collection, reg);
494}
495
496uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
497
498uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
499
500uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
501
502uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
503
504uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
505
507 return m_sme_regnum_collection[1];
508}
509
512}
513
516}
517
520}
521
524}
static lldb_private::RegisterInfo g_register_infos_tls[]
static const uint32_t g_fpu_regnums_arm64[]
static lldb_private::RegisterInfo g_register_infos_mte[]
#define SVE_QUAD_WORD_BYTES
static const lldb_private::RegisterSet g_reg_set_mte_arm64
static const lldb_private::RegisterSet g_reg_set_pauth_arm64
static const lldb_private::RegisterSet g_reg_set_sme_arm64
#define SVE_REGS_DEFAULT_OFFSET_LINUX
@ k_num_fpr_registers
@ k_num_gpr_registers
@ k_num_pauth_register
@ k_num_sve_registers
@ k_num_mte_register
@ k_num_register_sets_default
static const uint32_t g_gpr_regnums_arm64[]
static const uint32_t g_sve_regnums_arm64[]
static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets]
static lldb_private::RegisterInfo g_register_infos_pauth[]
static lldb_private::RegisterInfo g_register_infos_sme[]
std::map< uint32_t, std::pair< uint32_t, uint32_t > > m_per_regset_regnum_range
std::vector< lldb_private::RegisterInfo > m_dynamic_reg_infos
bool IsSVERegVG(unsigned reg) const
lldb_private::Flags m_opt_regsets
void AddRegSetTLS(bool has_tpidr2)
const lldb_private::RegisterInfo * m_register_info_p
uint32_t ConfigureVectorLengthSVE(uint32_t sve_vq)
std::vector< uint32_t > m_tls_regnum_collection
void ConfigureVectorLengthZA(uint32_t za_vq)
std::vector< lldb_private::RegisterSet > m_dynamic_reg_sets
std::vector< uint32_t > m_mte_regnum_collection
const lldb_private::RegisterInfo * GetRegisterInfo() const override
bool IsSVEZReg(unsigned reg) const
bool IsPAuthReg(unsigned reg) const
bool IsSMERegZA(unsigned reg) const
size_t GetRegisterSetCount() const override
const lldb_private::RegisterSet * m_register_set_p
std::vector< uint32_t > pauth_regnum_collection
bool IsSVEReg(unsigned reg) const
bool IsSVEPReg(unsigned reg) const
bool IsTLSReg(unsigned reg) const
bool IsMTEReg(unsigned reg) const
size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override
RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
per_vq_register_infos m_per_vq_reg_infos
uint32_t GetRegisterCount() const override
size_t GetFPRSize() const override
const lldb_private::RegisterSet * GetRegisterSet(size_t reg_set) const override
std::vector< uint32_t > m_sme_regnum_collection
bool IsSMEReg(unsigned reg) const
An architecture specification class.
Definition: ArchSpec.h:31
llvm::Triple::ArchType GetMachine() const
Returns a machine family for the current architecture.
Definition: ArchSpec.cpp:683
A class to manage flags.
Definition: Flags.h:22
bool AllSet(ValueType mask) const
Test if all bits in mask are 1 in the current flags.
Definition: Flags.h:83
bool AnySet(ValueType mask) const
Test one or more flags.
Definition: Flags.h:90
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:81
A class that represents a running process on the host machine.
Definition: SBAttachInfo.h:14
@ eFormatVectorOfUInt8
@ eEncodingVector
vector registers
@ eRegisterKindLLDB
lldb's internal register numbers
Every register is described in detail including its name, alternate name (optional),...
uint32_t byte_offset
The byte offset in the register context data where this register's value is found.
uint32_t byte_size
Size in bytes of the register.
Registers are grouped into register sets.