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RegisterInfoPOSIX_arm64.cpp
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1 //===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8 
9 #include <cassert>
10 #include <cstddef>
11 #include <vector>
12 
13 #include "lldb/lldb-defines.h"
14 #include "llvm/Support/Compiler.h"
15 
17 
18 // Based on RegisterContextDarwin_arm64.cpp
19 #define GPR_OFFSET(idx) ((idx)*8)
20 #define GPR_OFFSET_NAME(reg) \
21  (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
22 
23 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
24 #define FPU_OFFSET_NAME(reg) \
25  (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
26  sizeof(RegisterInfoPOSIX_arm64::GPR))
27 
28 // This information is based on AArch64 with SVE architecture reference manual.
29 // AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
30 // (First Fault) register and a VG (Vector Granule) pseudo register.
31 
32 // SVE 16-byte quad word is the basic unit of expansion in vector length.
33 #define SVE_QUAD_WORD_BYTES 16
34 
35 // Vector length is the multiplier which decides the no of quad words,
36 // (multiples of 128-bits or 16-bytes) present in a Z register. Vector length
37 // is decided during execution and can change at runtime. SVE AArch64 register
38 // infos have modes one for each valid value of vector length. A change in
39 // vector length requires register context to update sizes of SVE Z, P and FFR.
40 // Also register context needs to update byte offsets of all registers affected
41 // by the change in vector length.
42 #define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR)
43 
44 #define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
45 
46 #define EXC_OFFSET_NAME(reg) \
47  (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \
48  sizeof(RegisterInfoPOSIX_arm64::GPR) + \
49  sizeof(RegisterInfoPOSIX_arm64::FPU))
50 #define DBG_OFFSET_NAME(reg) \
51  (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \
52  sizeof(RegisterInfoPOSIX_arm64::GPR) + \
53  sizeof(RegisterInfoPOSIX_arm64::FPU) + \
54  sizeof(RegisterInfoPOSIX_arm64::EXC))
55 
56 #define DEFINE_DBG(reg, i) \
57  #reg, NULL, \
58  sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \
59  DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
60  {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
61  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
62  dbg_##reg##i }, \
63  NULL, NULL,
64 #define REG_CONTEXT_SIZE \
65  (sizeof(RegisterInfoPOSIX_arm64::GPR) + \
66  sizeof(RegisterInfoPOSIX_arm64::FPU) + \
67  sizeof(RegisterInfoPOSIX_arm64::EXC))
68 
69 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
70 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
71 #include "RegisterInfos_arm64.h"
73 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
74 
75 static lldb_private::RegisterInfo g_register_infos_pauth[] = {
76  DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)};
77 
78 static lldb_private::RegisterInfo g_register_infos_mte[] = {
79  DEFINE_EXTENSION_REG(mte_ctrl)};
80 
81 // Number of register sets provided by this context.
82 enum {
83  k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
84  k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
85  k_num_sve_registers = sve_ffr - sve_vg + 1,
90 };
91 
92 // ARM64 general purpose registers.
93 static const uint32_t g_gpr_regnums_arm64[] = {
94  gpr_x0, gpr_x1, gpr_x2, gpr_x3,
95  gpr_x4, gpr_x5, gpr_x6, gpr_x7,
96  gpr_x8, gpr_x9, gpr_x10, gpr_x11,
97  gpr_x12, gpr_x13, gpr_x14, gpr_x15,
98  gpr_x16, gpr_x17, gpr_x18, gpr_x19,
99  gpr_x20, gpr_x21, gpr_x22, gpr_x23,
100  gpr_x24, gpr_x25, gpr_x26, gpr_x27,
101  gpr_x28, gpr_fp, gpr_lr, gpr_sp,
102  gpr_pc, gpr_cpsr, gpr_w0, gpr_w1,
103  gpr_w2, gpr_w3, gpr_w4, gpr_w5,
104  gpr_w6, gpr_w7, gpr_w8, gpr_w9,
105  gpr_w10, gpr_w11, gpr_w12, gpr_w13,
106  gpr_w14, gpr_w15, gpr_w16, gpr_w17,
107  gpr_w18, gpr_w19, gpr_w20, gpr_w21,
108  gpr_w22, gpr_w23, gpr_w24, gpr_w25,
109  gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM};
110 
111 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) -
112  1) == k_num_gpr_registers,
113  "g_gpr_regnums_arm64 has wrong number of register infos");
114 
115 // ARM64 floating point registers.
116 static const uint32_t g_fpu_regnums_arm64[] = {
117  fpu_v0, fpu_v1, fpu_v2,
118  fpu_v3, fpu_v4, fpu_v5,
119  fpu_v6, fpu_v7, fpu_v8,
120  fpu_v9, fpu_v10, fpu_v11,
121  fpu_v12, fpu_v13, fpu_v14,
122  fpu_v15, fpu_v16, fpu_v17,
123  fpu_v18, fpu_v19, fpu_v20,
124  fpu_v21, fpu_v22, fpu_v23,
125  fpu_v24, fpu_v25, fpu_v26,
126  fpu_v27, fpu_v28, fpu_v29,
127  fpu_v30, fpu_v31, fpu_s0,
128  fpu_s1, fpu_s2, fpu_s3,
129  fpu_s4, fpu_s5, fpu_s6,
130  fpu_s7, fpu_s8, fpu_s9,
138  fpu_s31, fpu_d0, fpu_d1,
139  fpu_d2, fpu_d3, fpu_d4,
140  fpu_d5, fpu_d6, fpu_d7,
141  fpu_d8, fpu_d9, fpu_d10,
142  fpu_d11, fpu_d12, fpu_d13,
143  fpu_d14, fpu_d15, fpu_d16,
144  fpu_d17, fpu_d18, fpu_d19,
145  fpu_d20, fpu_d21, fpu_d22,
146  fpu_d23, fpu_d24, fpu_d25,
147  fpu_d26, fpu_d27, fpu_d28,
148  fpu_d29, fpu_d30, fpu_d31,
149  fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM};
150 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) -
151  1) == k_num_fpr_registers,
152  "g_fpu_regnums_arm64 has wrong number of register infos");
153 
154 // ARM64 SVE registers.
155 static const uint32_t g_sve_regnums_arm64[] = {
156  sve_vg, sve_z0, sve_z1,
157  sve_z2, sve_z3, sve_z4,
158  sve_z5, sve_z6, sve_z7,
159  sve_z8, sve_z9, sve_z10,
160  sve_z11, sve_z12, sve_z13,
161  sve_z14, sve_z15, sve_z16,
162  sve_z17, sve_z18, sve_z19,
163  sve_z20, sve_z21, sve_z22,
164  sve_z23, sve_z24, sve_z25,
165  sve_z26, sve_z27, sve_z28,
166  sve_z29, sve_z30, sve_z31,
167  sve_p0, sve_p1, sve_p2,
168  sve_p3, sve_p4, sve_p5,
169  sve_p6, sve_p7, sve_p8,
170  sve_p9, sve_p10, sve_p11,
171  sve_p12, sve_p13, sve_p14,
172  sve_p15, sve_ffr, LLDB_INVALID_REGNUM};
173 static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) -
174  1) == k_num_sve_registers,
175  "g_sve_regnums_arm64 has wrong number of register infos");
176 
177 // Register sets for ARM64.
178 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
179  {"General Purpose Registers", "gpr", k_num_gpr_registers,
181  {"Floating Point Registers", "fpu", k_num_fpr_registers,
183  {"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
185 
186 static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = {
187  "Pointer Authentication Registers", "pauth", k_num_pauth_register, nullptr};
188 
189 static const lldb_private::RegisterSet g_reg_set_mte_arm64 = {
190  "MTE Control Register", "mte", k_num_mte_register, nullptr};
191 
193  const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
194  : lldb_private::RegisterInfoAndSetInterface(target_arch),
195  m_opt_regsets(opt_regsets) {
196  switch (target_arch.GetMachine()) {
197  case llvm::Triple::aarch64:
198  case llvm::Triple::aarch64_32: {
201  m_per_regset_regnum_range[GPRegSet] = std::make_pair(gpr_x0, gpr_w28 + 1);
202  m_per_regset_regnum_range[FPRegSet] = std::make_pair(fpu_v0, fpu_fpcr + 1);
203 
204  // Now configure register sets supported by current target. If we have a
205  // dynamic register set like MTE, Pointer Authentication regset then we need
206  // to create dynamic register infos and regset array. Push back all optional
207  // register infos and regset and calculate register offsets accordingly.
209  m_register_info_p = g_register_infos_arm64_sve_le;
210  m_register_info_count = sve_ffr + 1;
212  std::make_pair(sve_vg, sve_ffr + 1);
213  } else {
214  m_register_info_p = g_register_infos_arm64_le;
215  m_register_info_count = fpu_fpcr + 1;
216  }
217 
219  llvm::ArrayRef<lldb_private::RegisterInfo> reg_infos_ref =
220  llvm::makeArrayRef(m_register_info_p, m_register_info_count);
221  llvm::ArrayRef<lldb_private::RegisterSet> reg_sets_ref =
222  llvm::makeArrayRef(m_register_set_p, m_register_set_count);
223  llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos));
224  llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets));
225 
227  AddRegSetPAuth();
228 
230  AddRegSetMTE();
231 
236  }
237  break;
238  }
239  default:
240  assert(false && "Unhandled target architecture.");
241  }
242 }
243 
245  return m_register_info_count;
246 }
247 
249  return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
250 }
251 
253  return sizeof(struct RegisterInfoPOSIX_arm64::FPU);
254 }
255 
256 const lldb_private::RegisterInfo *
258  return m_register_info_p;
259 }
260 
262  return m_register_set_count;
263 }
264 
266  uint32_t reg_index) const {
267  for (const auto &regset_range : m_per_regset_regnum_range) {
268  if (reg_index >= regset_range.second.first &&
269  reg_index < regset_range.second.second)
270  return regset_range.first;
271  }
272  return LLDB_INVALID_REGNUM;
273 }
274 
275 const lldb_private::RegisterSet *
277  if (set_index < GetRegisterSetCount())
278  return &m_register_set_p[set_index];
279  return nullptr;
280 }
281 
283  uint32_t pa_regnum = m_dynamic_reg_infos.size();
284  for (uint32_t i = 0; i < k_num_pauth_register; i++) {
285  pauth_regnum_collection.push_back(pa_regnum + i);
287  m_dynamic_reg_infos[pa_regnum + i].byte_offset =
288  m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset +
289  m_dynamic_reg_infos[pa_regnum + i - 1].byte_size;
290  m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] =
291  pa_regnum + i;
292  }
293 
295  std::make_pair(pa_regnum, m_dynamic_reg_infos.size());
297  m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
298 }
299 
301  uint32_t mte_regnum = m_dynamic_reg_infos.size();
302  m_mte_regnum_collection.push_back(mte_regnum);
304  m_dynamic_reg_infos[mte_regnum].byte_offset =
305  m_dynamic_reg_infos[mte_regnum - 1].byte_offset +
306  m_dynamic_reg_infos[mte_regnum - 1].byte_size;
307  m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum;
308 
310  std::make_pair(mte_regnum, mte_regnum + 1);
312  m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
313 }
314 
316  // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
317  // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
318  // Also if an invalid or previously set vector length is passed to this
319  // function then it will exit immediately with previously set vector length.
320  if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
321  return m_vector_reg_vq;
322 
323  // We cannot enable AArch64 only mode if SVE was enabled.
324  if (sve_vq == eVectorQuadwordAArch64 &&
326  sve_vq = eVectorQuadwordAArch64SVE;
327 
328  m_vector_reg_vq = sve_vq;
329 
330  if (sve_vq == eVectorQuadwordAArch64)
331  return m_vector_reg_vq;
332  std::vector<lldb_private::RegisterInfo> &reg_info_ref =
333  m_per_vq_reg_infos[sve_vq];
334 
335  if (reg_info_ref.empty()) {
336  reg_info_ref = llvm::makeArrayRef(m_register_info_p, m_register_info_count);
337 
339  reg_info_ref[fpu_fpsr].byte_offset = offset;
340  reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
341  reg_info_ref[sve_vg].byte_offset = offset + 8;
342  offset += 16;
343 
344  // Update Z registers size and offset
345  uint32_t s_reg_base = fpu_s0;
346  uint32_t d_reg_base = fpu_d0;
347  uint32_t v_reg_base = fpu_v0;
348  uint32_t z_reg_base = sve_z0;
349 
350  for (uint32_t index = 0; index < 32; index++) {
351  reg_info_ref[s_reg_base + index].byte_offset = offset;
352  reg_info_ref[d_reg_base + index].byte_offset = offset;
353  reg_info_ref[v_reg_base + index].byte_offset = offset;
354  reg_info_ref[z_reg_base + index].byte_offset = offset;
355 
356  reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES;
357  offset += reg_info_ref[z_reg_base + index].byte_size;
358  }
359 
360  // Update P registers and FFR size and offset
361  for (uint32_t it = sve_p0; it <= sve_ffr; it++) {
362  reg_info_ref[it].byte_offset = offset;
363  reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8;
364  offset += reg_info_ref[it].byte_size;
365  }
366 
367  for (uint32_t it = sve_ffr + 1; it < m_register_info_count; it++) {
368  reg_info_ref[it].byte_offset = offset;
369  offset += reg_info_ref[it].byte_size;
370  }
371 
372  m_per_vq_reg_infos[sve_vq] = reg_info_ref;
373  }
374 
375  m_register_info_p = m_per_vq_reg_infos[sve_vq].data();
376  return m_vector_reg_vq;
377 }
378 
379 bool RegisterInfoPOSIX_arm64::IsSVEReg(unsigned reg) const {
381  return (sve_vg <= reg && reg <= sve_ffr);
382  else
383  return false;
384 }
385 
386 bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const {
387  return (sve_z0 <= reg && reg <= sve_z31);
388 }
389 
390 bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const {
391  return (sve_p0 <= reg && reg <= sve_p15);
392 }
393 
394 bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
395  return sve_vg == reg;
396 }
397 
398 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
399  return llvm::is_contained(pauth_regnum_collection, reg);
400 }
401 
402 bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
403  return llvm::is_contained(m_mte_regnum_collection, reg);
404 }
405 
407 
409 
411 
413 
415 
417  return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
418 }
419 
421  return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
422 }
RegisterInfoPOSIX_arm64::GetRegisterInfo
const lldb_private::RegisterInfo * GetRegisterInfo() const override
Definition: RegisterInfoPOSIX_arm64.cpp:257
g_reg_set_mte_arm64
static const lldb_private::RegisterSet g_reg_set_mte_arm64
Definition: RegisterInfoPOSIX_arm64.cpp:189
fpu_s24
@ fpu_s24
Definition: RegisterContextDarwin_arm.cpp:78
RegisterInfoPOSIX_arm64::m_dynamic_reg_sets
std::vector< lldb_private::RegisterSet > m_dynamic_reg_sets
Definition: RegisterInfoPOSIX_arm64.h:151
k_num_register_sets
@ k_num_register_sets
Definition: RegisterInfoPOSIX_arm64.cpp:89
RegisterInfoPOSIX_arm64::IsSVERegVG
bool IsSVERegVG(unsigned reg) const
Definition: RegisterInfoPOSIX_arm64.cpp:394
lldb_private::ArchSpec
Definition: ArchSpec.h:33
RegisterInfoPOSIX_arm64::IsMTEReg
bool IsMTEReg(unsigned reg) const
Definition: RegisterInfoPOSIX_arm64.cpp:402
g_register_infos_mte
static lldb_private::RegisterInfo g_register_infos_mte[]
Definition: RegisterInfoPOSIX_arm64.cpp:78
fpu_s19
@ fpu_s19
Definition: RegisterContextDarwin_arm.cpp:73
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:79
RegisterInfoPOSIX_arm64::m_per_vq_reg_infos
per_vq_register_infos m_per_vq_reg_infos
Definition: RegisterInfoPOSIX_arm64.h:134
fpu_s12
@ fpu_s12
Definition: RegisterContextDarwin_arm.cpp:66
lldb_private::Flags::AnySet
bool AnySet(ValueType mask) const
Test one or more flags.
Definition: Flags.h:90
lldb_private::ArchSpec::GetMachine
llvm::Triple::ArchType GetMachine() const
Returns a machine family for the current architecture.
Definition: ArchSpec.cpp:668
fpu_s5
@ fpu_s5
Definition: RegisterContextDarwin_arm.cpp:59
RegisterInfoPOSIX_arm64::GPR
Definition: RegisterInfoPOSIX_arm64.h:43
RegisterInfoPOSIX_arm64::m_register_info_p
const lldb_private::RegisterInfo * m_register_info_p
Definition: RegisterInfoPOSIX_arm64.h:138
fpu_s2
@ fpu_s2
Definition: RegisterContextDarwin_arm.cpp:56
lldb-defines.h
fpu_s23
@ fpu_s23
Definition: RegisterContextDarwin_arm.cpp:77
fpu_s17
@ fpu_s17
Definition: RegisterContextDarwin_arm.cpp:71
fpu_s22
@ fpu_s22
Definition: RegisterContextDarwin_arm.cpp:76
RegisterInfoPOSIX_arm64::GetRegisterSetCount
size_t GetRegisterSetCount() const override
Definition: RegisterInfoPOSIX_arm64.cpp:261
gpr_lr
@ gpr_lr
Definition: RegisterContextDarwin_arm.cpp:49
k_num_sve_registers
@ k_num_sve_registers
Definition: RegisterInfoPOSIX_arm64.cpp:85
gpr_cpsr
@ gpr_cpsr
Definition: RegisterContextDarwin_arm.cpp:52
RegisterInfoPOSIX_arm64::FPU
Definition: RegisterInfoPOSIX_arm64.h:59
lldb_private::Flags
Definition: Flags.h:22
fpu_s6
@ fpu_s6
Definition: RegisterContextDarwin_arm.cpp:60
RegisterInfoPOSIX_arm64::m_register_info_count
uint32_t m_register_info_count
Definition: RegisterInfoPOSIX_arm64.h:139
RegisterInfoPOSIX_arm64::AddRegSetPAuth
void AddRegSetPAuth()
Definition: RegisterInfoPOSIX_arm64.cpp:282
k_num_register_sets_default
@ k_num_register_sets_default
Definition: RegisterInfoPOSIX_arm64.cpp:88
fpu_s0
@ fpu_s0
Definition: RegisterContextDarwin_arm.cpp:54
RegisterInfoPOSIX_arm64::GetFPRSize
size_t GetFPRSize() const override
Definition: RegisterInfoPOSIX_arm64.cpp:252
fpu_s26
@ fpu_s26
Definition: RegisterContextDarwin_arm.cpp:80
g_reg_sets_arm64
static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets]
Definition: RegisterInfoPOSIX_arm64.cpp:178
g_fpu_regnums_arm64
static const uint32_t g_fpu_regnums_arm64[]
Definition: RegisterInfoPOSIX_arm64.cpp:116
RegisterInfoPOSIX_arm64::m_per_regset_regnum_range
std::map< uint32_t, std::pair< uint32_t, uint32_t > > m_per_regset_regnum_range
Definition: RegisterInfoPOSIX_arm64.h:146
RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64
@ eVectorQuadwordAArch64
Definition: RegisterInfoPOSIX_arm64.h:36
RegisterInfos_arm64_sve.h
RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex
size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override
Definition: RegisterInfoPOSIX_arm64.cpp:265
lldb::eRegisterKindLLDB
@ eRegisterKindLLDB
lldb's internal register numbers
Definition: lldb-enumerations.h:234
RegisterInfoPOSIX_arm64::ConfigureVectorLength
uint32_t ConfigureVectorLength(uint32_t sve_vq)
Definition: RegisterInfoPOSIX_arm64.cpp:315
RegisterInfoPOSIX_arm64::eRegsetMaskPAuth
@ eRegsetMaskPAuth
Definition: RegisterInfoPOSIX_arm64.h:29
RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64
RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
Definition: RegisterInfoPOSIX_arm64.cpp:192
RegisterInfoPOSIX_arm64::m_opt_regsets
lldb_private::Flags m_opt_regsets
Definition: RegisterInfoPOSIX_arm64.h:148
fpu_s3
@ fpu_s3
Definition: RegisterContextDarwin_arm.cpp:57
fpu_s10
@ fpu_s10
Definition: RegisterContextDarwin_arm.cpp:64
RegisterInfoPOSIX_arm64::FPRegSet
@ FPRegSet
Definition: RegisterInfoPOSIX_arm64.h:23
fpu_s29
@ fpu_s29
Definition: RegisterContextDarwin_arm.cpp:83
RegisterInfoPOSIX_arm64::GetRegNumFPCR
uint32_t GetRegNumFPCR() const
Definition: RegisterInfoPOSIX_arm64.cpp:410
RegisterInfoPOSIX_arm64::IsSVEZReg
bool IsSVEZReg(unsigned reg) const
Definition: RegisterInfoPOSIX_arm64.cpp:386
gpr_sp
@ gpr_sp
Definition: RegisterContextDarwin_arm.cpp:47
g_register_infos_pauth
static lldb_private::RegisterInfo g_register_infos_pauth[]
Definition: RegisterInfoPOSIX_arm64.cpp:75
fpu_s31
@ fpu_s31
Definition: RegisterContextDarwin_arm.cpp:85
fpu_s15
@ fpu_s15
Definition: RegisterContextDarwin_arm.cpp:69
RegisterInfoPOSIX_arm64::AddRegSetMTE
void AddRegSetMTE()
Definition: RegisterInfoPOSIX_arm64.cpp:300
RegisterInfoPOSIX_arm64::m_vector_reg_vq
uint32_t m_vector_reg_vq
Definition: RegisterInfoPOSIX_arm64.h:136
RegisterInfos_arm64.h
SVE_REGS_DEFAULT_OFFSET_LINUX
#define SVE_REGS_DEFAULT_OFFSET_LINUX
Definition: RegisterInfoPOSIX_arm64.cpp:42
RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64SVE
@ eVectorQuadwordAArch64SVE
Definition: RegisterInfoPOSIX_arm64.h:37
fpu_s18
@ fpu_s18
Definition: RegisterContextDarwin_arm.cpp:72
RegisterInfoPOSIX_arm64.h
lldb_private::Flags::AllSet
bool AllSet(ValueType mask) const
Test if all bits in mask are 1 in the current flags.
Definition: Flags.h:83
RegisterInfoPOSIX_arm64::eRegsetMaskMTE
@ eRegsetMaskMTE
Definition: RegisterInfoPOSIX_arm64.h:30
RegisterInfoPOSIX_arm64::pauth_regnum_collection
std::vector< uint32_t > pauth_regnum_collection
Definition: RegisterInfoPOSIX_arm64.h:153
g_reg_set_pauth_arm64
static const lldb_private::RegisterSet g_reg_set_pauth_arm64
Definition: RegisterInfoPOSIX_arm64.cpp:186
fpu_s20
@ fpu_s20
Definition: RegisterContextDarwin_arm.cpp:74
fpu_s16
@ fpu_s16
Definition: RegisterContextDarwin_arm.cpp:70
RegisterInfoPOSIX_arm64::m_dynamic_reg_infos
std::vector< lldb_private::RegisterInfo > m_dynamic_reg_infos
Definition: RegisterInfoPOSIX_arm64.h:150
k_num_mte_register
@ k_num_mte_register
Definition: RegisterInfoPOSIX_arm64.cpp:86
fpu_s7
@ fpu_s7
Definition: RegisterContextDarwin_arm.cpp:61
g_gpr_regnums_arm64
static const uint32_t g_gpr_regnums_arm64[]
Definition: RegisterInfoPOSIX_arm64.cpp:93
RegisterInfoPOSIX_arm64::GetRegNumSVEFFR
uint32_t GetRegNumSVEFFR() const
Definition: RegisterInfoPOSIX_arm64.cpp:408
RegisterInfoPOSIX_arm64::m_register_set_count
uint32_t m_register_set_count
Definition: RegisterInfoPOSIX_arm64.h:142
fpu_s25
@ fpu_s25
Definition: RegisterContextDarwin_arm.cpp:79
RegisterInfoPOSIX_arm64::GetMTEOffset
uint32_t GetMTEOffset() const
Definition: RegisterInfoPOSIX_arm64.cpp:420
fpu_s13
@ fpu_s13
Definition: RegisterContextDarwin_arm.cpp:67
RegisterInfoPOSIX_arm64::GetRegisterSet
const lldb_private::RegisterSet * GetRegisterSet(size_t reg_set) const override
Definition: RegisterInfoPOSIX_arm64.cpp:276
RegisterInfoPOSIX_arm64::GetRegNumSVEZ0
uint32_t GetRegNumSVEZ0() const
Definition: RegisterInfoPOSIX_arm64.cpp:406
fpu_s4
@ fpu_s4
Definition: RegisterContextDarwin_arm.cpp:58
RegisterInfoPOSIX_arm64::eRegsetMaskDynamic
@ eRegsetMaskDynamic
Definition: RegisterInfoPOSIX_arm64.h:31
RegisterInfoPOSIX_arm64::GetPAuthOffset
uint32_t GetPAuthOffset() const
Definition: RegisterInfoPOSIX_arm64.cpp:416
uint32_t
g_sve_regnums_arm64
static const uint32_t g_sve_regnums_arm64[]
Definition: RegisterInfoPOSIX_arm64.cpp:155
SVE_QUAD_WORD_BYTES
#define SVE_QUAD_WORD_BYTES
Definition: RegisterInfoPOSIX_arm64.cpp:33
fpu_s9
@ fpu_s9
Definition: RegisterContextDarwin_arm.cpp:63
fpu_s11
@ fpu_s11
Definition: RegisterContextDarwin_arm.cpp:65
fpu_s21
@ fpu_s21
Definition: RegisterContextDarwin_arm.cpp:75
RegisterInfoPOSIX_arm64::GetGPRSize
size_t GetGPRSize() const override
Definition: RegisterInfoPOSIX_arm64.cpp:248
RegisterInfoPOSIX_arm64::IsSVEPReg
bool IsSVEPReg(unsigned reg) const
Definition: RegisterInfoPOSIX_arm64.cpp:390
RegisterInfoPOSIX_arm64::IsSVEReg
bool IsSVEReg(unsigned reg) const
Definition: RegisterInfoPOSIX_arm64.cpp:379
RegisterInfoPOSIX_arm64::GPRegSet
@ GPRegSet
Definition: RegisterInfoPOSIX_arm64.h:23
lldb_private
A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
k_num_gpr_registers
@ k_num_gpr_registers
Definition: RegisterInfoPOSIX_arm64.cpp:83
fpu_s30
@ fpu_s30
Definition: RegisterContextDarwin_arm.cpp:84
RegisterInfoPOSIX_arm64::GetRegNumSVEVG
uint32_t GetRegNumSVEVG() const
Definition: RegisterInfoPOSIX_arm64.cpp:414
fpu_s1
@ fpu_s1
Definition: RegisterContextDarwin_arm.cpp:55
RegisterInfoPOSIX_arm64::VectorSizeIsValid
bool VectorSizeIsValid(uint32_t vq)
Definition: RegisterInfoPOSIX_arm64.h:105
fpu_s14
@ fpu_s14
Definition: RegisterContextDarwin_arm.cpp:68
k_num_fpr_registers
@ k_num_fpr_registers
Definition: RegisterInfoPOSIX_arm64.cpp:84
RegisterInfoPOSIX_arm64::IsPAuthReg
bool IsPAuthReg(unsigned reg) const
Definition: RegisterInfoPOSIX_arm64.cpp:398
RegisterInfoPOSIX_arm64::m_register_set_p
const lldb_private::RegisterSet * m_register_set_p
Definition: RegisterInfoPOSIX_arm64.h:141
k_num_pauth_register
@ k_num_pauth_register
Definition: RegisterInfoPOSIX_arm64.cpp:87
RegisterInfoPOSIX_arm64::m_mte_regnum_collection
std::vector< uint32_t > m_mte_regnum_collection
Definition: RegisterInfoPOSIX_arm64.h:154
RegisterInfoPOSIX_arm64::eRegsetMaskSVE
@ eRegsetMaskSVE
Definition: RegisterInfoPOSIX_arm64.h:28
fpu_s28
@ fpu_s28
Definition: RegisterContextDarwin_arm.cpp:82
RegisterInfoPOSIX_arm64::GetRegisterCount
uint32_t GetRegisterCount() const override
Definition: RegisterInfoPOSIX_arm64.cpp:244
gpr_pc
@ gpr_pc
Definition: RegisterContextDarwin_arm.cpp:51
fpu_s8
@ fpu_s8
Definition: RegisterContextDarwin_arm.cpp:62
RegisterInfoPOSIX_arm64::GetRegNumFPSR
uint32_t GetRegNumFPSR() const
Definition: RegisterInfoPOSIX_arm64.cpp:412
fpu_s27
@ fpu_s27
Definition: RegisterContextDarwin_arm.cpp:81