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RegisterInfoPOSIX_arm64.cpp
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1//===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===---------------------------------------------------------------------===//
8
9#include <cassert>
10#include <cstddef>
11#include <vector>
12
13#include "lldb/lldb-defines.h"
14#include "llvm/Support/Compiler.h"
15
17
18// Based on RegisterContextDarwin_arm64.cpp
19#define GPR_OFFSET(idx) ((idx)*8)
20#define GPR_OFFSET_NAME(reg) \
21 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
22
23#define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
24#define FPU_OFFSET_NAME(reg) \
25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
26 sizeof(RegisterInfoPOSIX_arm64::GPR))
27
28// This information is based on AArch64 with SVE architecture reference manual.
29// AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
30// (First Fault) register and a VG (Vector Granule) pseudo register.
31
32// SVE 16-byte quad word is the basic unit of expansion in vector length.
33#define SVE_QUAD_WORD_BYTES 16
34
35// Vector length is the multiplier which decides the no of quad words,
36// (multiples of 128-bits or 16-bytes) present in a Z register. Vector length
37// is decided during execution and can change at runtime. SVE AArch64 register
38// infos have modes one for each valid value of vector length. A change in
39// vector length requires register context to update sizes of SVE Z, P and FFR.
40// Also register context needs to update byte offsets of all registers affected
41// by the change in vector length.
42#define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR)
43
44#define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
45
46#define EXC_OFFSET_NAME(reg) \
47 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \
48 sizeof(RegisterInfoPOSIX_arm64::GPR) + \
49 sizeof(RegisterInfoPOSIX_arm64::FPU))
50#define DBG_OFFSET_NAME(reg) \
51 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \
52 sizeof(RegisterInfoPOSIX_arm64::GPR) + \
53 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
54 sizeof(RegisterInfoPOSIX_arm64::EXC))
55
56#define DEFINE_DBG(reg, i) \
57 #reg, NULL, \
58 sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \
59 DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
60 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
61 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
62 dbg_##reg##i }, \
63 NULL, NULL,
64#define REG_CONTEXT_SIZE \
65 (sizeof(RegisterInfoPOSIX_arm64::GPR) + \
66 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
67 sizeof(RegisterInfoPOSIX_arm64::EXC))
68
69// Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
70#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
71#include "RegisterInfos_arm64.h"
73#undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
74
75static lldb_private::RegisterInfo g_register_infos_pauth[] = {
76 DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)};
77
78static lldb_private::RegisterInfo g_register_infos_mte[] = {
79 DEFINE_EXTENSION_REG(mte_ctrl)};
80
81// Number of register sets provided by this context.
82enum {
83 k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
84 k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
85 k_num_sve_registers = sve_ffr - sve_vg + 1,
90};
91
92// ARM64 general purpose registers.
93static const uint32_t g_gpr_regnums_arm64[] = {
94 gpr_x0, gpr_x1, gpr_x2, gpr_x3,
95 gpr_x4, gpr_x5, gpr_x6, gpr_x7,
96 gpr_x8, gpr_x9, gpr_x10, gpr_x11,
97 gpr_x12, gpr_x13, gpr_x14, gpr_x15,
98 gpr_x16, gpr_x17, gpr_x18, gpr_x19,
99 gpr_x20, gpr_x21, gpr_x22, gpr_x23,
100 gpr_x24, gpr_x25, gpr_x26, gpr_x27,
101 gpr_x28, gpr_fp, gpr_lr, gpr_sp,
102 gpr_pc, gpr_cpsr, gpr_w0, gpr_w1,
103 gpr_w2, gpr_w3, gpr_w4, gpr_w5,
104 gpr_w6, gpr_w7, gpr_w8, gpr_w9,
105 gpr_w10, gpr_w11, gpr_w12, gpr_w13,
106 gpr_w14, gpr_w15, gpr_w16, gpr_w17,
107 gpr_w18, gpr_w19, gpr_w20, gpr_w21,
108 gpr_w22, gpr_w23, gpr_w24, gpr_w25,
109 gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM};
110
111static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) -
113 "g_gpr_regnums_arm64 has wrong number of register infos");
114
115// ARM64 floating point registers.
117 fpu_v0, fpu_v1, fpu_v2,
118 fpu_v3, fpu_v4, fpu_v5,
119 fpu_v6, fpu_v7, fpu_v8,
120 fpu_v9, fpu_v10, fpu_v11,
121 fpu_v12, fpu_v13, fpu_v14,
122 fpu_v15, fpu_v16, fpu_v17,
123 fpu_v18, fpu_v19, fpu_v20,
124 fpu_v21, fpu_v22, fpu_v23,
125 fpu_v24, fpu_v25, fpu_v26,
126 fpu_v27, fpu_v28, fpu_v29,
127 fpu_v30, fpu_v31, fpu_s0,
138 fpu_s31, fpu_d0, fpu_d1,
139 fpu_d2, fpu_d3, fpu_d4,
140 fpu_d5, fpu_d6, fpu_d7,
141 fpu_d8, fpu_d9, fpu_d10,
142 fpu_d11, fpu_d12, fpu_d13,
143 fpu_d14, fpu_d15, fpu_d16,
144 fpu_d17, fpu_d18, fpu_d19,
145 fpu_d20, fpu_d21, fpu_d22,
146 fpu_d23, fpu_d24, fpu_d25,
147 fpu_d26, fpu_d27, fpu_d28,
148 fpu_d29, fpu_d30, fpu_d31,
149 fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM};
150static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) -
152 "g_fpu_regnums_arm64 has wrong number of register infos");
153
154// ARM64 SVE registers.
156 sve_vg, sve_z0, sve_z1,
157 sve_z2, sve_z3, sve_z4,
158 sve_z5, sve_z6, sve_z7,
159 sve_z8, sve_z9, sve_z10,
160 sve_z11, sve_z12, sve_z13,
161 sve_z14, sve_z15, sve_z16,
162 sve_z17, sve_z18, sve_z19,
163 sve_z20, sve_z21, sve_z22,
164 sve_z23, sve_z24, sve_z25,
165 sve_z26, sve_z27, sve_z28,
166 sve_z29, sve_z30, sve_z31,
167 sve_p0, sve_p1, sve_p2,
168 sve_p3, sve_p4, sve_p5,
169 sve_p6, sve_p7, sve_p8,
170 sve_p9, sve_p10, sve_p11,
171 sve_p12, sve_p13, sve_p14,
172 sve_p15, sve_ffr, LLDB_INVALID_REGNUM};
173static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) -
175 "g_sve_regnums_arm64 has wrong number of register infos");
176
177// Register sets for ARM64.
178static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
179 {"General Purpose Registers", "gpr", k_num_gpr_registers,
181 {"Floating Point Registers", "fpu", k_num_fpr_registers,
183 {"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
185
186static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = {
187 "Pointer Authentication Registers", "pauth", k_num_pauth_register, nullptr};
188
189static const lldb_private::RegisterSet g_reg_set_mte_arm64 = {
190 "MTE Control Register", "mte", k_num_mte_register, nullptr};
191
193 const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
194 : lldb_private::RegisterInfoAndSetInterface(target_arch),
195 m_opt_regsets(opt_regsets) {
196 switch (target_arch.GetMachine()) {
197 case llvm::Triple::aarch64:
198 case llvm::Triple::aarch64_32: {
201 m_per_regset_regnum_range[GPRegSet] = std::make_pair(gpr_x0, gpr_w28 + 1);
202 m_per_regset_regnum_range[FPRegSet] = std::make_pair(fpu_v0, fpu_fpcr + 1);
203
204 // Now configure register sets supported by current target. If we have a
205 // dynamic register set like MTE, Pointer Authentication regset then we need
206 // to create dynamic register infos and regset array. Push back all optional
207 // register infos and regset and calculate register offsets accordingly.
209 m_register_info_p = g_register_infos_arm64_sve_le;
210 m_register_info_count = sve_ffr + 1;
212 std::make_pair(sve_vg, sve_ffr + 1);
213 } else {
214 m_register_info_p = g_register_infos_arm64_le;
215 m_register_info_count = fpu_fpcr + 1;
216 }
217
219 llvm::ArrayRef<lldb_private::RegisterInfo> reg_infos_ref =
221 llvm::ArrayRef<lldb_private::RegisterSet> reg_sets_ref =
222 llvm::ArrayRef(m_register_set_p, m_register_set_count);
223 llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos));
224 llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets));
225
228
230 AddRegSetMTE();
231
236 }
237 break;
238 }
239 default:
240 assert(false && "Unhandled target architecture.");
241 }
242}
243
246}
247
249 return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
250}
251
253 return sizeof(struct RegisterInfoPOSIX_arm64::FPU);
254}
255
256const lldb_private::RegisterInfo *
258 return m_register_info_p;
259}
260
263}
264
266 uint32_t reg_index) const {
267 for (const auto &regset_range : m_per_regset_regnum_range) {
268 if (reg_index >= regset_range.second.first &&
269 reg_index < regset_range.second.second)
270 return regset_range.first;
271 }
272 return LLDB_INVALID_REGNUM;
273}
274
275const lldb_private::RegisterSet *
277 if (set_index < GetRegisterSetCount())
278 return &m_register_set_p[set_index];
279 return nullptr;
280}
281
283 uint32_t pa_regnum = m_dynamic_reg_infos.size();
284 for (uint32_t i = 0; i < k_num_pauth_register; i++) {
285 pauth_regnum_collection.push_back(pa_regnum + i);
287 m_dynamic_reg_infos[pa_regnum + i].byte_offset =
288 m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset +
289 m_dynamic_reg_infos[pa_regnum + i - 1].byte_size;
290 m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] =
291 pa_regnum + i;
292 }
293
295 std::make_pair(pa_regnum, m_dynamic_reg_infos.size());
297 m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
298}
299
301 uint32_t mte_regnum = m_dynamic_reg_infos.size();
302 m_mte_regnum_collection.push_back(mte_regnum);
304 m_dynamic_reg_infos[mte_regnum].byte_offset =
305 m_dynamic_reg_infos[mte_regnum - 1].byte_offset +
306 m_dynamic_reg_infos[mte_regnum - 1].byte_size;
307 m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum;
308
310 std::make_pair(mte_regnum, mte_regnum + 1);
312 m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
313}
314
316 // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
317 // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
318 // Also if an invalid or previously set vector length is passed to this
319 // function then it will exit immediately with previously set vector length.
320 if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
321 return m_vector_reg_vq;
322
323 // We cannot enable AArch64 only mode if SVE was enabled.
324 if (sve_vq == eVectorQuadwordAArch64 &&
327
328 m_vector_reg_vq = sve_vq;
329
330 if (sve_vq == eVectorQuadwordAArch64)
331 return m_vector_reg_vq;
332 std::vector<lldb_private::RegisterInfo> &reg_info_ref =
333 m_per_vq_reg_infos[sve_vq];
334
335 if (reg_info_ref.empty()) {
336 reg_info_ref = llvm::ArrayRef(m_register_info_p, m_register_info_count);
337
339 reg_info_ref[fpu_fpsr].byte_offset = offset;
340 reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
341 reg_info_ref[sve_vg].byte_offset = offset + 8;
342 offset += 16;
343
344 // Update Z registers size and offset
345 uint32_t s_reg_base = fpu_s0;
346 uint32_t d_reg_base = fpu_d0;
347 uint32_t v_reg_base = fpu_v0;
348 uint32_t z_reg_base = sve_z0;
349
350 for (uint32_t index = 0; index < 32; index++) {
351 reg_info_ref[s_reg_base + index].byte_offset = offset;
352 reg_info_ref[d_reg_base + index].byte_offset = offset;
353 reg_info_ref[v_reg_base + index].byte_offset = offset;
354 reg_info_ref[z_reg_base + index].byte_offset = offset;
355
356 reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES;
357 offset += reg_info_ref[z_reg_base + index].byte_size;
358 }
359
360 // Update P registers and FFR size and offset
361 for (uint32_t it = sve_p0; it <= sve_ffr; it++) {
362 reg_info_ref[it].byte_offset = offset;
363 reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8;
364 offset += reg_info_ref[it].byte_size;
365 }
366
367 for (uint32_t it = sve_ffr + 1; it < m_register_info_count; it++) {
368 reg_info_ref[it].byte_offset = offset;
369 offset += reg_info_ref[it].byte_size;
370 }
371
372 m_per_vq_reg_infos[sve_vq] = reg_info_ref;
373 }
374
375 m_register_info_p = m_per_vq_reg_infos[sve_vq].data();
376 return m_vector_reg_vq;
377}
378
379bool RegisterInfoPOSIX_arm64::IsSVEReg(unsigned reg) const {
381 return (sve_vg <= reg && reg <= sve_ffr);
382 else
383 return false;
384}
385
386bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const {
387 return (sve_z0 <= reg && reg <= sve_z31);
388}
389
390bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const {
391 return (sve_p0 <= reg && reg <= sve_p15);
392}
393
394bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
395 return sve_vg == reg;
396}
397
398bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
399 return llvm::is_contained(pauth_regnum_collection, reg);
400}
401
402bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
403 return llvm::is_contained(m_mte_regnum_collection, reg);
404}
405
407
409
411
413
415
417 return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
418}
419
421 return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
422}
static const uint32_t g_fpu_regnums_arm64[]
static lldb_private::RegisterInfo g_register_infos_mte[]
#define SVE_QUAD_WORD_BYTES
static const lldb_private::RegisterSet g_reg_set_mte_arm64
static const lldb_private::RegisterSet g_reg_set_pauth_arm64
#define SVE_REGS_DEFAULT_OFFSET_LINUX
@ k_num_fpr_registers
@ k_num_gpr_registers
@ k_num_pauth_register
@ k_num_sve_registers
@ k_num_mte_register
@ k_num_register_sets_default
@ k_num_register_sets
static const uint32_t g_gpr_regnums_arm64[]
static const uint32_t g_sve_regnums_arm64[]
static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets]
static lldb_private::RegisterInfo g_register_infos_pauth[]
std::map< uint32_t, std::pair< uint32_t, uint32_t > > m_per_regset_regnum_range
std::vector< lldb_private::RegisterInfo > m_dynamic_reg_infos
bool IsSVERegVG(unsigned reg) const
lldb_private::Flags m_opt_regsets
const lldb_private::RegisterInfo * m_register_info_p
std::vector< lldb_private::RegisterSet > m_dynamic_reg_sets
std::vector< uint32_t > m_mte_regnum_collection
const lldb_private::RegisterInfo * GetRegisterInfo() const override
bool IsSVEZReg(unsigned reg) const
bool IsPAuthReg(unsigned reg) const
size_t GetRegisterSetCount() const override
uint32_t ConfigureVectorLength(uint32_t sve_vq)
const lldb_private::RegisterSet * m_register_set_p
std::vector< uint32_t > pauth_regnum_collection
bool IsSVEReg(unsigned reg) const
bool IsSVEPReg(unsigned reg) const
bool IsMTEReg(unsigned reg) const
size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override
RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
per_vq_register_infos m_per_vq_reg_infos
uint32_t GetRegisterCount() const override
size_t GetFPRSize() const override
const lldb_private::RegisterSet * GetRegisterSet(size_t reg_set) const override
An architecture specification class.
Definition: ArchSpec.h:32
llvm::Triple::ArchType GetMachine() const
Returns a machine family for the current architecture.
Definition: ArchSpec.cpp:678
A class to manage flags.
Definition: Flags.h:22
bool AllSet(ValueType mask) const
Test if all bits in mask are 1 in the current flags.
Definition: Flags.h:83
bool AnySet(ValueType mask) const
Test one or more flags.
Definition: Flags.h:90
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:79
A class that represents a running process on the host machine.
@ eRegisterKindLLDB
lldb's internal register numbers