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RegisterInfoPOSIX_arm.cpp
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1 //===-- RegisterInfoPOSIX_arm.cpp -----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8 
9 #include <cassert>
10 #include <cstddef>
11 #include <vector>
12 
13 #include "lldb/lldb-defines.h"
14 #include "llvm/Support/Compiler.h"
15 
16 #include "RegisterInfoPOSIX_arm.h"
17 
18 using namespace lldb;
19 using namespace lldb_private;
20 
21 // Based on RegisterContextDarwin_arm.cpp
22 #define GPR_OFFSET(idx) ((idx)*4)
23 #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterInfoPOSIX_arm::GPR))
24 #define FPSCR_OFFSET \
25  (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm::FPU, fpscr) + \
26  sizeof(RegisterInfoPOSIX_arm::GPR))
27 #define EXC_OFFSET(idx) \
28  ((idx)*4 + sizeof(RegisterInfoPOSIX_arm::GPR) + \
29  sizeof(RegisterInfoPOSIX_arm::FPU))
30 #define DBG_OFFSET(reg) \
31  ((LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm::DBG, reg) + \
32  sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
33  sizeof(RegisterInfoPOSIX_arm::EXC)))
34 
35 #define DEFINE_DBG(reg, i) \
36  #reg, NULL, sizeof(((RegisterInfoPOSIX_arm::DBG *) NULL)->reg[i]), \
37  DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \
38  {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
39  LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
40  dbg_##reg##i }, \
41  NULL, NULL, NULL, 0
42 #define REG_CONTEXT_SIZE \
43  (sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
44  sizeof(RegisterInfoPOSIX_arm::EXC))
45 
46 // Include RegisterInfos_arm to declare our g_register_infos_arm structure.
47 #define DECLARE_REGISTER_INFOS_ARM_STRUCT
48 #include "RegisterInfos_arm.h"
49 #undef DECLARE_REGISTER_INFOS_ARM_STRUCT
50 
51 static const lldb_private::RegisterInfo *
53  switch (target_arch.GetMachine()) {
54  case llvm::Triple::arm:
55  return g_register_infos_arm;
56  default:
57  assert(false && "Unhandled target architecture.");
58  return nullptr;
59  }
60 }
61 
62 static uint32_t
64  switch (target_arch.GetMachine()) {
65  case llvm::Triple::arm:
66  return static_cast<uint32_t>(sizeof(g_register_infos_arm) /
67  sizeof(g_register_infos_arm[0]));
68  default:
69  assert(false && "Unhandled target architecture.");
70  return 0;
71  }
72 }
73 
74 // Number of register sets provided by this context.
75 enum {
77  k_num_fpr_registers = fpu_q15 - fpu_s0 + 1,
79 };
80 
81 // arm general purpose registers.
82 static const uint32_t g_gpr_regnums_arm[] = {
83  gpr_r0, gpr_r1,
84  gpr_r2, gpr_r3,
85  gpr_r4, gpr_r5,
86  gpr_r6, gpr_r7,
87  gpr_r8, gpr_r9,
89  gpr_r12, gpr_sp,
90  gpr_lr, gpr_pc,
91  gpr_cpsr, LLDB_INVALID_REGNUM // register sets need to end with this flag
92 };
93 static_assert(((sizeof g_gpr_regnums_arm / sizeof g_gpr_regnums_arm[0]) - 1) ==
95  "g_gpr_regnums_arm has wrong number of register infos");
96 
97 // arm floating point registers.
98 static const uint32_t g_fpu_regnums_arm[] = {
99  fpu_s0, fpu_s1,
100  fpu_s2, fpu_s3,
101  fpu_s4, fpu_s5,
102  fpu_s6, fpu_s7,
103  fpu_s8, fpu_s9,
104  fpu_s10, fpu_s11,
105  fpu_s12, fpu_s13,
106  fpu_s14, fpu_s15,
107  fpu_s16, fpu_s17,
108  fpu_s18, fpu_s19,
109  fpu_s20, fpu_s21,
110  fpu_s22, fpu_s23,
111  fpu_s24, fpu_s25,
112  fpu_s26, fpu_s27,
113  fpu_s28, fpu_s29,
114  fpu_s30, fpu_s31,
115  fpu_fpscr, fpu_d0,
116  fpu_d1, fpu_d2,
117  fpu_d3, fpu_d4,
118  fpu_d5, fpu_d6,
119  fpu_d7, fpu_d8,
120  fpu_d9, fpu_d10,
121  fpu_d11, fpu_d12,
122  fpu_d13, fpu_d14,
123  fpu_d15, fpu_d16,
124  fpu_d17, fpu_d18,
125  fpu_d19, fpu_d20,
126  fpu_d21, fpu_d22,
127  fpu_d23, fpu_d24,
128  fpu_d25, fpu_d26,
129  fpu_d27, fpu_d28,
130  fpu_d29, fpu_d30,
131  fpu_d31, fpu_q0,
132  fpu_q1, fpu_q2,
133  fpu_q3, fpu_q4,
134  fpu_q5, fpu_q6,
135  fpu_q7, fpu_q8,
136  fpu_q9, fpu_q10,
137  fpu_q11, fpu_q12,
138  fpu_q13, fpu_q14,
139  fpu_q15, LLDB_INVALID_REGNUM // register sets need to end with this flag
140 };
141 static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) ==
143  "g_fpu_regnums_arm has wrong number of register infos");
144 
145 // Register sets for arm.
146 static const RegisterSet g_reg_sets_arm[k_num_register_sets] = {
147  {"General Purpose Registers", "gpr", k_num_gpr_registers,
149  {"Floating Point Registers", "fpu", k_num_fpr_registers,
151 
153  const lldb_private::ArchSpec &target_arch)
155  m_register_info_p(GetRegisterInfoPtr(target_arch)),
156  m_register_info_count(GetRegisterInfoCount(target_arch)) {}
157 
159  return sizeof(struct RegisterInfoPOSIX_arm::GPR);
160 }
161 
163  return sizeof(struct RegisterInfoPOSIX_arm::FPU);
164 }
165 
166 const lldb_private::RegisterInfo *
168  return m_register_info_p;
169 }
170 
172  return k_num_register_sets;
173 }
174 
176  uint32_t reg_index) const {
177  if (reg_index <= gpr_cpsr)
178  return GPRegSet;
179  if (reg_index <= fpu_q15)
180  return FPRegSet;
181  return LLDB_INVALID_REGNUM;
182 }
183 
184 const lldb_private::RegisterSet *
185 RegisterInfoPOSIX_arm::GetRegisterSet(size_t set_index) const {
186  if (set_index < GetRegisterSetCount())
187  return &g_reg_sets_arm[set_index];
188  return nullptr;
189 }
190 
192  return m_register_info_count;
193 }
gpr_r0
@ gpr_r0
Definition: RegisterContextDarwin_arm.cpp:33
fpu_s3
@ fpu_s3
Definition: RegisterContextDarwin_arm.cpp:57
gpr_r12
@ gpr_r12
Definition: RegisterContextDarwin_arm.cpp:45
lldb_private::ArchSpec
Definition: ArchSpec.h:33
gpr_pc
@ gpr_pc
Definition: RegisterContextDarwin_arm.cpp:51
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:91
fpu_s0
@ fpu_s0
Definition: RegisterContextDarwin_arm.cpp:54
lldb_private::ArchSpec::GetMachine
llvm::Triple::ArchType GetMachine() const
Returns a machine family for the current architecture.
Definition: ArchSpec.cpp:667
fpu_s10
@ fpu_s10
Definition: RegisterContextDarwin_arm.cpp:64
fpu_s9
@ fpu_s9
Definition: RegisterContextDarwin_arm.cpp:63
fpu_s4
@ fpu_s4
Definition: RegisterContextDarwin_arm.cpp:58
lldb-defines.h
fpu_s5
@ fpu_s5
Definition: RegisterContextDarwin_arm.cpp:59
gpr_cpsr
@ gpr_cpsr
Definition: RegisterContextDarwin_arm.cpp:52
RegisterInfoPOSIX_arm::FPU
Definition: RegisterInfoPOSIX_arm.h:29
fpu_s12
@ fpu_s12
Definition: RegisterContextDarwin_arm.cpp:66
fpu_s19
@ fpu_s19
Definition: RegisterContextDarwin_arm.cpp:73
k_num_fpr_registers
@ k_num_fpr_registers
Definition: RegisterInfoPOSIX_arm.cpp:77
RegisterInfoPOSIX_arm.h
fpu_s8
@ fpu_s8
Definition: RegisterContextDarwin_arm.cpp:62
gpr_r10
@ gpr_r10
Definition: RegisterContextDarwin_arm.cpp:43
RegisterInfoPOSIX_arm::GetRegisterSetFromRegisterIndex
size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override
Definition: RegisterInfoPOSIX_arm.cpp:175
fpu_s30
@ fpu_s30
Definition: RegisterContextDarwin_arm.cpp:84
GetRegisterInfoCount
static uint32_t GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch)
Definition: RegisterInfoPOSIX_arm.cpp:63
fpu_s23
@ fpu_s23
Definition: RegisterContextDarwin_arm.cpp:77
lldb_private::RegisterInfoAndSetInterface
Definition: RegisterInfoAndSetInterface.h:20
gpr_r7
@ gpr_r7
Definition: RegisterContextDarwin_arm.cpp:40
fpu_s2
@ fpu_s2
Definition: RegisterContextDarwin_arm.cpp:56
gpr_r6
@ gpr_r6
Definition: RegisterContextDarwin_arm.cpp:39
fpu_s20
@ fpu_s20
Definition: RegisterContextDarwin_arm.cpp:74
fpu_s25
@ fpu_s25
Definition: RegisterContextDarwin_arm.cpp:79
RegisterInfoPOSIX_arm::RegisterInfoPOSIX_arm
RegisterInfoPOSIX_arm(const lldb_private::ArchSpec &target_arch)
Definition: RegisterInfoPOSIX_arm.cpp:152
gpr_lr
@ gpr_lr
Definition: RegisterContextDarwin_arm.cpp:49
gpr_r2
@ gpr_r2
Definition: RegisterContextDarwin_arm.cpp:35
gpr_r1
@ gpr_r1
Definition: RegisterContextDarwin_arm.cpp:34
RegisterInfoPOSIX_arm::GetGPRSize
size_t GetGPRSize() const override
Definition: RegisterInfoPOSIX_arm.cpp:158
RegisterInfoPOSIX_arm::FPRegSet
@ FPRegSet
Definition: RegisterInfoPOSIX_arm.h:18
fpu_s15
@ fpu_s15
Definition: RegisterContextDarwin_arm.cpp:69
g_reg_sets_arm
static const RegisterSet g_reg_sets_arm[k_num_register_sets]
Definition: RegisterInfoPOSIX_arm.cpp:146
fpu_fpscr
@ fpu_fpscr
Definition: RegisterContextDarwin_arm.cpp:86
fpu_s28
@ fpu_s28
Definition: RegisterContextDarwin_arm.cpp:82
RegisterInfoPOSIX_arm::m_register_info_count
uint32_t m_register_info_count
Definition: RegisterInfoPOSIX_arm.h:69
fpu_s11
@ fpu_s11
Definition: RegisterContextDarwin_arm.cpp:65
RegisterInfoPOSIX_arm::GetRegisterCount
uint32_t GetRegisterCount() const override
Definition: RegisterInfoPOSIX_arm.cpp:191
fpu_s21
@ fpu_s21
Definition: RegisterContextDarwin_arm.cpp:75
fpu_s6
@ fpu_s6
Definition: RegisterContextDarwin_arm.cpp:60
fpu_s31
@ fpu_s31
Definition: RegisterContextDarwin_arm.cpp:85
g_fpu_regnums_arm
static const uint32_t g_fpu_regnums_arm[]
Definition: RegisterInfoPOSIX_arm.cpp:98
fpu_s24
@ fpu_s24
Definition: RegisterContextDarwin_arm.cpp:78
fpu_s27
@ fpu_s27
Definition: RegisterContextDarwin_arm.cpp:81
RegisterInfoPOSIX_arm::GetFPRSize
size_t GetFPRSize() const override
Definition: RegisterInfoPOSIX_arm.cpp:162
RegisterInfoPOSIX_arm::GetRegisterSet
const lldb_private::RegisterSet * GetRegisterSet(size_t reg_set) const override
Definition: RegisterInfoPOSIX_arm.cpp:185
gpr_r5
@ gpr_r5
Definition: RegisterContextDarwin_arm.cpp:38
uint32_t
fpu_s1
@ fpu_s1
Definition: RegisterContextDarwin_arm.cpp:55
fpu_s18
@ fpu_s18
Definition: RegisterContextDarwin_arm.cpp:72
RegisterInfoPOSIX_arm::GetRegisterInfo
const lldb_private::RegisterInfo * GetRegisterInfo() const override
Definition: RegisterInfoPOSIX_arm.cpp:167
fpu_s17
@ fpu_s17
Definition: RegisterContextDarwin_arm.cpp:71
fpu_s7
@ fpu_s7
Definition: RegisterContextDarwin_arm.cpp:61
fpu_s14
@ fpu_s14
Definition: RegisterContextDarwin_arm.cpp:68
gpr_r9
@ gpr_r9
Definition: RegisterContextDarwin_arm.cpp:42
gpr_sp
@ gpr_sp
Definition: RegisterContextDarwin_arm.cpp:47
gpr_r8
@ gpr_r8
Definition: RegisterContextDarwin_arm.cpp:41
fpu_s13
@ fpu_s13
Definition: RegisterContextDarwin_arm.cpp:67
RegisterInfoPOSIX_arm::GPRegSet
@ GPRegSet
Definition: RegisterInfoPOSIX_arm.h:18
fpu_s22
@ fpu_s22
Definition: RegisterContextDarwin_arm.cpp:76
lldb_private
A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
k_num_register_sets
@ k_num_register_sets
Definition: RegisterInfoPOSIX_arm.cpp:78
fpu_s29
@ fpu_s29
Definition: RegisterContextDarwin_arm.cpp:83
fpu_s26
@ fpu_s26
Definition: RegisterContextDarwin_arm.cpp:80
g_gpr_regnums_arm
static const uint32_t g_gpr_regnums_arm[]
Definition: RegisterInfoPOSIX_arm.cpp:82
fpu_s16
@ fpu_s16
Definition: RegisterContextDarwin_arm.cpp:70
RegisterInfos_arm.h
gpr_r3
@ gpr_r3
Definition: RegisterContextDarwin_arm.cpp:36
lldb
Definition: SBAddress.h:15
RegisterInfoPOSIX_arm::m_register_info_p
const lldb_private::RegisterInfo * m_register_info_p
Definition: RegisterInfoPOSIX_arm.h:68
GetRegisterInfoPtr
static const lldb_private::RegisterInfo * GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch)
Definition: RegisterInfoPOSIX_arm.cpp:52
k_num_gpr_registers
@ k_num_gpr_registers
Definition: RegisterInfoPOSIX_arm.cpp:76
gpr_r11
@ gpr_r11
Definition: RegisterContextDarwin_arm.cpp:44
RegisterInfoPOSIX_arm::GetRegisterSetCount
size_t GetRegisterSetCount() const override
Definition: RegisterInfoPOSIX_arm.cpp:171
gpr_r4
@ gpr_r4
Definition: RegisterContextDarwin_arm.cpp:37
RegisterInfoPOSIX_arm::GPR
Definition: RegisterInfoPOSIX_arm.h:20