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EmulateInstructionMIPS.cpp
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1 //===-- EmulateInstructionMIPS.cpp ----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "EmulateInstructionMIPS.h"
10 
11 #include <cstdlib>
12 
13 #include "lldb/Core/Address.h"
14 #include "lldb/Core/Opcode.h"
15 #include "lldb/Core/PluginManager.h"
16 #include "lldb/Symbol/UnwindPlan.h"
17 #include "lldb/Target/Target.h"
18 #include "lldb/Utility/ArchSpec.h"
19 #include "lldb/Utility/ConstString.h"
20 #include "lldb/Utility/DataExtractor.h"
21 #include "lldb/Utility/RegisterValue.h"
22 #include "lldb/Utility/Stream.h"
23 #include "llvm-c/Disassembler.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/MC/MCTargetOptions.h"
32 #include "llvm/MC/TargetRegistry.h"
33 #include "llvm/Support/TargetSelect.h"
34 
35 #include "llvm/ADT/STLExtras.h"
36 
37 #include "Plugins/Process/Utility/InstructionUtils.h"
38 #include "Plugins/Process/Utility/RegisterContext_mips.h"
39 
40 using namespace lldb;
41 using namespace lldb_private;
42 
43 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionMIPS, InstructionMIPS)
44 
45 #define UInt(x) ((uint64_t)x)
46 #define integer int64_t
47 
48 //
49 // EmulateInstructionMIPS implementation
50 //
51 
52 #ifdef __mips__
53 extern "C" {
54 void LLVMInitializeMipsTargetInfo();
55 void LLVMInitializeMipsTarget();
56 void LLVMInitializeMipsAsmPrinter();
57 void LLVMInitializeMipsTargetMC();
58 void LLVMInitializeMipsDisassembler();
59 }
60 #endif
61 
62 EmulateInstructionMIPS::EmulateInstructionMIPS(
63  const lldb_private::ArchSpec &arch)
64  : EmulateInstruction(arch) {
65  /* Create instance of llvm::MCDisassembler */
66  std::string Status;
67  llvm::Triple triple = arch.GetTriple();
68  const llvm::Target *target =
69  llvm::TargetRegistry::lookupTarget(triple.getTriple(), Status);
70 
71 /*
72  * If we fail to get the target then we haven't registered it. The
73  * SystemInitializerCommon
74  * does not initialize targets, MCs and disassemblers. However we need the
75  * MCDisassembler
76  * to decode the instructions so that the decoding complexity stays with LLVM.
77  * Initialize the MIPS targets and disassemblers.
78 */
79 #ifdef __mips__
80  if (!target) {
81  LLVMInitializeMipsTargetInfo();
82  LLVMInitializeMipsTarget();
83  LLVMInitializeMipsAsmPrinter();
84  LLVMInitializeMipsTargetMC();
85  LLVMInitializeMipsDisassembler();
86  target = llvm::TargetRegistry::lookupTarget(triple.getTriple(), Status);
87  }
88 #endif
89 
90  assert(target);
91 
92  llvm::StringRef cpu;
93 
94  switch (arch.GetCore()) {
95  case ArchSpec::eCore_mips32:
96  case ArchSpec::eCore_mips32el:
97  cpu = "mips32";
98  break;
99  case ArchSpec::eCore_mips32r2:
100  case ArchSpec::eCore_mips32r2el:
101  cpu = "mips32r2";
102  break;
103  case ArchSpec::eCore_mips32r3:
104  case ArchSpec::eCore_mips32r3el:
105  cpu = "mips32r3";
106  break;
107  case ArchSpec::eCore_mips32r5:
108  case ArchSpec::eCore_mips32r5el:
109  cpu = "mips32r5";
110  break;
111  case ArchSpec::eCore_mips32r6:
112  case ArchSpec::eCore_mips32r6el:
113  cpu = "mips32r6";
114  break;
115  case ArchSpec::eCore_mips64:
116  case ArchSpec::eCore_mips64el:
117  cpu = "mips64";
118  break;
119  case ArchSpec::eCore_mips64r2:
120  case ArchSpec::eCore_mips64r2el:
121  cpu = "mips64r2";
122  break;
123  case ArchSpec::eCore_mips64r3:
124  case ArchSpec::eCore_mips64r3el:
125  cpu = "mips64r3";
126  break;
127  case ArchSpec::eCore_mips64r5:
128  case ArchSpec::eCore_mips64r5el:
129  cpu = "mips64r5";
130  break;
131  case ArchSpec::eCore_mips64r6:
132  case ArchSpec::eCore_mips64r6el:
133  cpu = "mips64r6";
134  break;
135  default:
136  cpu = "generic";
137  break;
138  }
139 
140  std::string features;
141  uint32_t arch_flags = arch.GetFlags();
142  if (arch_flags & ArchSpec::eMIPSAse_msa)
143  features += "+msa,";
144  if (arch_flags & ArchSpec::eMIPSAse_dsp)
145  features += "+dsp,";
146  if (arch_flags & ArchSpec::eMIPSAse_dspr2)
147  features += "+dspr2,";
148 
149  m_reg_info.reset(target->createMCRegInfo(triple.getTriple()));
150  assert(m_reg_info.get());
151 
152  m_insn_info.reset(target->createMCInstrInfo());
153  assert(m_insn_info.get());
154 
155  llvm::MCTargetOptions MCOptions;
156  m_asm_info.reset(
157  target->createMCAsmInfo(*m_reg_info, triple.getTriple(), MCOptions));
158  m_subtype_info.reset(
159  target->createMCSubtargetInfo(triple.getTriple(), cpu, features));
160  assert(m_asm_info.get() && m_subtype_info.get());
161 
162  m_context = std::make_unique<llvm::MCContext>(
163  triple, m_asm_info.get(), m_reg_info.get(), m_subtype_info.get());
164  assert(m_context.get());
165 
166  m_disasm.reset(target->createMCDisassembler(*m_subtype_info, *m_context));
167  assert(m_disasm.get());
168 
169  /* Create alternate disassembler for microMIPS */
170  if (arch_flags & ArchSpec::eMIPSAse_mips16)
171  features += "+mips16,";
172  else if (arch_flags & ArchSpec::eMIPSAse_micromips)
173  features += "+micromips,";
174 
175  m_alt_subtype_info.reset(
176  target->createMCSubtargetInfo(triple.getTriple(), cpu, features));
177  assert(m_alt_subtype_info.get());
178 
179  m_alt_disasm.reset(
180  target->createMCDisassembler(*m_alt_subtype_info, *m_context));
181  assert(m_alt_disasm.get());
182 
183  m_next_inst_size = 0;
184  m_use_alt_disaasm = false;
185 }
186 
187 void EmulateInstructionMIPS::Initialize() {
188  PluginManager::RegisterPlugin(GetPluginNameStatic(),
189  GetPluginDescriptionStatic(), CreateInstance);
190 }
191 
192 void EmulateInstructionMIPS::Terminate() {
193  PluginManager::UnregisterPlugin(CreateInstance);
194 }
195 
196 llvm::StringRef EmulateInstructionMIPS::GetPluginDescriptionStatic() {
197  return "Emulate instructions for the MIPS32 architecture.";
198 }
199 
200 EmulateInstruction *
201 EmulateInstructionMIPS::CreateInstance(const ArchSpec &arch,
202  InstructionType inst_type) {
203  if (EmulateInstructionMIPS::SupportsEmulatingInstructionsOfTypeStatic(
204  inst_type)) {
205  if (arch.GetTriple().getArch() == llvm::Triple::mips ||
206  arch.GetTriple().getArch() == llvm::Triple::mipsel) {
207  return new EmulateInstructionMIPS(arch);
208  }
209  }
210 
211  return nullptr;
212 }
213 
214 bool EmulateInstructionMIPS::SetTargetTriple(const ArchSpec &arch) {
215  return arch.GetTriple().getArch() == llvm::Triple::mips ||
216  arch.GetTriple().getArch() == llvm::Triple::mipsel;
217 }
218 
219 const char *EmulateInstructionMIPS::GetRegisterName(unsigned reg_num,
220  bool alternate_name) {
221  if (alternate_name) {
222  switch (reg_num) {
223  case dwarf_sp_mips:
224  return "r29";
225  case dwarf_r30_mips:
226  return "r30";
227  case dwarf_ra_mips:
228  return "r31";
229  case dwarf_f0_mips:
230  return "f0";
231  case dwarf_f1_mips:
232  return "f1";
233  case dwarf_f2_mips:
234  return "f2";
235  case dwarf_f3_mips:
236  return "f3";
237  case dwarf_f4_mips:
238  return "f4";
239  case dwarf_f5_mips:
240  return "f5";
241  case dwarf_f6_mips:
242  return "f6";
243  case dwarf_f7_mips:
244  return "f7";
245  case dwarf_f8_mips:
246  return "f8";
247  case dwarf_f9_mips:
248  return "f9";
249  case dwarf_f10_mips:
250  return "f10";
251  case dwarf_f11_mips:
252  return "f11";
253  case dwarf_f12_mips:
254  return "f12";
255  case dwarf_f13_mips:
256  return "f13";
257  case dwarf_f14_mips:
258  return "f14";
259  case dwarf_f15_mips:
260  return "f15";
261  case dwarf_f16_mips:
262  return "f16";
263  case dwarf_f17_mips:
264  return "f17";
265  case dwarf_f18_mips:
266  return "f18";
267  case dwarf_f19_mips:
268  return "f19";
269  case dwarf_f20_mips:
270  return "f20";
271  case dwarf_f21_mips:
272  return "f21";
273  case dwarf_f22_mips:
274  return "f22";
275  case dwarf_f23_mips:
276  return "f23";
277  case dwarf_f24_mips:
278  return "f24";
279  case dwarf_f25_mips:
280  return "f25";
281  case dwarf_f26_mips:
282  return "f26";
283  case dwarf_f27_mips:
284  return "f27";
285  case dwarf_f28_mips:
286  return "f28";
287  case dwarf_f29_mips:
288  return "f29";
289  case dwarf_f30_mips:
290  return "f30";
291  case dwarf_f31_mips:
292  return "f31";
293  case dwarf_w0_mips:
294  return "w0";
295  case dwarf_w1_mips:
296  return "w1";
297  case dwarf_w2_mips:
298  return "w2";
299  case dwarf_w3_mips:
300  return "w3";
301  case dwarf_w4_mips:
302  return "w4";
303  case dwarf_w5_mips:
304  return "w5";
305  case dwarf_w6_mips:
306  return "w6";
307  case dwarf_w7_mips:
308  return "w7";
309  case dwarf_w8_mips:
310  return "w8";
311  case dwarf_w9_mips:
312  return "w9";
313  case dwarf_w10_mips:
314  return "w10";
315  case dwarf_w11_mips:
316  return "w11";
317  case dwarf_w12_mips:
318  return "w12";
319  case dwarf_w13_mips:
320  return "w13";
321  case dwarf_w14_mips:
322  return "w14";
323  case dwarf_w15_mips:
324  return "w15";
325  case dwarf_w16_mips:
326  return "w16";
327  case dwarf_w17_mips:
328  return "w17";
329  case dwarf_w18_mips:
330  return "w18";
331  case dwarf_w19_mips:
332  return "w19";
333  case dwarf_w20_mips:
334  return "w20";
335  case dwarf_w21_mips:
336  return "w21";
337  case dwarf_w22_mips:
338  return "w22";
339  case dwarf_w23_mips:
340  return "w23";
341  case dwarf_w24_mips:
342  return "w24";
343  case dwarf_w25_mips:
344  return "w25";
345  case dwarf_w26_mips:
346  return "w26";
347  case dwarf_w27_mips:
348  return "w27";
349  case dwarf_w28_mips:
350  return "w28";
351  case dwarf_w29_mips:
352  return "w29";
353  case dwarf_w30_mips:
354  return "w30";
355  case dwarf_w31_mips:
356  return "w31";
357  case dwarf_mir_mips:
358  return "mir";
359  case dwarf_mcsr_mips:
360  return "mcsr";
361  case dwarf_config5_mips:
362  return "config5";
363  default:
364  break;
365  }
366  return nullptr;
367  }
368 
369  switch (reg_num) {
370  case dwarf_zero_mips:
371  return "r0";
372  case dwarf_r1_mips:
373  return "r1";
374  case dwarf_r2_mips:
375  return "r2";
376  case dwarf_r3_mips:
377  return "r3";
378  case dwarf_r4_mips:
379  return "r4";
380  case dwarf_r5_mips:
381  return "r5";
382  case dwarf_r6_mips:
383  return "r6";
384  case dwarf_r7_mips:
385  return "r7";
386  case dwarf_r8_mips:
387  return "r8";
388  case dwarf_r9_mips:
389  return "r9";
390  case dwarf_r10_mips:
391  return "r10";
392  case dwarf_r11_mips:
393  return "r11";
394  case dwarf_r12_mips:
395  return "r12";
396  case dwarf_r13_mips:
397  return "r13";
398  case dwarf_r14_mips:
399  return "r14";
400  case dwarf_r15_mips:
401  return "r15";
402  case dwarf_r16_mips:
403  return "r16";
404  case dwarf_r17_mips:
405  return "r17";
406  case dwarf_r18_mips:
407  return "r18";
408  case dwarf_r19_mips:
409  return "r19";
410  case dwarf_r20_mips:
411  return "r20";
412  case dwarf_r21_mips:
413  return "r21";
414  case dwarf_r22_mips:
415  return "r22";
416  case dwarf_r23_mips:
417  return "r23";
418  case dwarf_r24_mips:
419  return "r24";
420  case dwarf_r25_mips:
421  return "r25";
422  case dwarf_r26_mips:
423  return "r26";
424  case dwarf_r27_mips:
425  return "r27";
426  case dwarf_gp_mips:
427  return "gp";
428  case dwarf_sp_mips:
429  return "sp";
430  case dwarf_r30_mips:
431  return "fp";
432  case dwarf_ra_mips:
433  return "ra";
434  case dwarf_sr_mips:
435  return "sr";
436  case dwarf_lo_mips:
437  return "lo";
438  case dwarf_hi_mips:
439  return "hi";
440  case dwarf_bad_mips:
441  return "bad";
442  case dwarf_cause_mips:
443  return "cause";
444  case dwarf_pc_mips:
445  return "pc";
446  case dwarf_f0_mips:
447  return "f0";
448  case dwarf_f1_mips:
449  return "f1";
450  case dwarf_f2_mips:
451  return "f2";
452  case dwarf_f3_mips:
453  return "f3";
454  case dwarf_f4_mips:
455  return "f4";
456  case dwarf_f5_mips:
457  return "f5";
458  case dwarf_f6_mips:
459  return "f6";
460  case dwarf_f7_mips:
461  return "f7";
462  case dwarf_f8_mips:
463  return "f8";
464  case dwarf_f9_mips:
465  return "f9";
466  case dwarf_f10_mips:
467  return "f10";
468  case dwarf_f11_mips:
469  return "f11";
470  case dwarf_f12_mips:
471  return "f12";
472  case dwarf_f13_mips:
473  return "f13";
474  case dwarf_f14_mips:
475  return "f14";
476  case dwarf_f15_mips:
477  return "f15";
478  case dwarf_f16_mips:
479  return "f16";
480  case dwarf_f17_mips:
481  return "f17";
482  case dwarf_f18_mips:
483  return "f18";
484  case dwarf_f19_mips:
485  return "f19";
486  case dwarf_f20_mips:
487  return "f20";
488  case dwarf_f21_mips:
489  return "f21";
490  case dwarf_f22_mips:
491  return "f22";
492  case dwarf_f23_mips:
493  return "f23";
494  case dwarf_f24_mips:
495  return "f24";
496  case dwarf_f25_mips:
497  return "f25";
498  case dwarf_f26_mips:
499  return "f26";
500  case dwarf_f27_mips:
501  return "f27";
502  case dwarf_f28_mips:
503  return "f28";
504  case dwarf_f29_mips:
505  return "f29";
506  case dwarf_f30_mips:
507  return "f30";
508  case dwarf_f31_mips:
509  return "f31";
510  case dwarf_fcsr_mips:
511  return "fcsr";
512  case dwarf_fir_mips:
513  return "fir";
514  case dwarf_w0_mips:
515  return "w0";
516  case dwarf_w1_mips:
517  return "w1";
518  case dwarf_w2_mips:
519  return "w2";
520  case dwarf_w3_mips:
521  return "w3";
522  case dwarf_w4_mips:
523  return "w4";
524  case dwarf_w5_mips:
525  return "w5";
526  case dwarf_w6_mips:
527  return "w6";
528  case dwarf_w7_mips:
529  return "w7";
530  case dwarf_w8_mips:
531  return "w8";
532  case dwarf_w9_mips:
533  return "w9";
534  case dwarf_w10_mips:
535  return "w10";
536  case dwarf_w11_mips:
537  return "w11";
538  case dwarf_w12_mips:
539  return "w12";
540  case dwarf_w13_mips:
541  return "w13";
542  case dwarf_w14_mips:
543  return "w14";
544  case dwarf_w15_mips:
545  return "w15";
546  case dwarf_w16_mips:
547  return "w16";
548  case dwarf_w17_mips:
549  return "w17";
550  case dwarf_w18_mips:
551  return "w18";
552  case dwarf_w19_mips:
553  return "w19";
554  case dwarf_w20_mips:
555  return "w20";
556  case dwarf_w21_mips:
557  return "w21";
558  case dwarf_w22_mips:
559  return "w22";
560  case dwarf_w23_mips:
561  return "w23";
562  case dwarf_w24_mips:
563  return "w24";
564  case dwarf_w25_mips:
565  return "w25";
566  case dwarf_w26_mips:
567  return "w26";
568  case dwarf_w27_mips:
569  return "w27";
570  case dwarf_w28_mips:
571  return "w28";
572  case dwarf_w29_mips:
573  return "w29";
574  case dwarf_w30_mips:
575  return "w30";
576  case dwarf_w31_mips:
577  return "w31";
578  case dwarf_mcsr_mips:
579  return "mcsr";
580  case dwarf_mir_mips:
581  return "mir";
582  case dwarf_config5_mips:
583  return "config5";
584  }
585  return nullptr;
586 }
587 
588 llvm::Optional<RegisterInfo>
589 EmulateInstructionMIPS::GetRegisterInfo(RegisterKind reg_kind,
590  uint32_t reg_num) {
591  if (reg_kind == eRegisterKindGeneric) {
592  switch (reg_num) {
593  case LLDB_REGNUM_GENERIC_PC:
594  reg_kind = eRegisterKindDWARF;
595  reg_num = dwarf_pc_mips;
596  break;
597  case LLDB_REGNUM_GENERIC_SP:
598  reg_kind = eRegisterKindDWARF;
599  reg_num = dwarf_sp_mips;
600  break;
601  case LLDB_REGNUM_GENERIC_FP:
602  reg_kind = eRegisterKindDWARF;
603  reg_num = dwarf_r30_mips;
604  break;
605  case LLDB_REGNUM_GENERIC_RA:
606  reg_kind = eRegisterKindDWARF;
607  reg_num = dwarf_ra_mips;
608  break;
609  case LLDB_REGNUM_GENERIC_FLAGS:
610  reg_kind = eRegisterKindDWARF;
611  reg_num = dwarf_sr_mips;
612  break;
613  default:
614  return {};
615  }
616  }
617 
618  if (reg_kind == eRegisterKindDWARF) {
619  RegisterInfo reg_info;
620  ::memset(&reg_info, 0, sizeof(RegisterInfo));
621  ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
622 
623  if (reg_num == dwarf_sr_mips || reg_num == dwarf_fcsr_mips ||
624  reg_num == dwarf_fir_mips || reg_num == dwarf_mcsr_mips ||
625  reg_num == dwarf_mir_mips || reg_num == dwarf_config5_mips) {
626  reg_info.byte_size = 4;
627  reg_info.format = eFormatHex;
628  reg_info.encoding = eEncodingUint;
629  } else if ((int)reg_num >= dwarf_zero_mips &&
630  (int)reg_num <= dwarf_f31_mips) {
631  reg_info.byte_size = 4;
632  reg_info.format = eFormatHex;
633  reg_info.encoding = eEncodingUint;
634  } else if ((int)reg_num >= dwarf_w0_mips &&
635  (int)reg_num <= dwarf_w31_mips) {
636  reg_info.byte_size = 16;
637  reg_info.format = eFormatVectorOfUInt8;
638  reg_info.encoding = eEncodingVector;
639  } else {
640  return {};
641  }
642 
643  reg_info.name = GetRegisterName(reg_num, false);
644  reg_info.alt_name = GetRegisterName(reg_num, true);
645  reg_info.kinds[eRegisterKindDWARF] = reg_num;
646 
647  switch (reg_num) {
648  case dwarf_r30_mips:
649  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
650  break;
651  case dwarf_ra_mips:
652  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
653  break;
654  case dwarf_sp_mips:
655  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
656  break;
657  case dwarf_pc_mips:
658  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
659  break;
660  case dwarf_sr_mips:
661  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
662  break;
663  default:
664  break;
665  }
666  return reg_info;
667  }
668  return {};
669 }
670 
671 EmulateInstructionMIPS::MipsOpcode *
672 EmulateInstructionMIPS::GetOpcodeForInstruction(llvm::StringRef name) {
673  static EmulateInstructionMIPS::MipsOpcode g_opcodes[] = {
674  // Prologue/Epilogue instructions
675  {"ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu,
676  "ADDIU rt, rs, immediate"},
677  {"SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt, offset(rs)"},
678  {"LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt, offset(base)"},
679  {"SUBU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "SUBU rd, rs, rt"},
680  {"ADDU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "ADDU rd, rs, rt"},
681  {"LUI", &EmulateInstructionMIPS::Emulate_LUI, "LUI rt, immediate"},
682 
683  // MicroMIPS Prologue/Epilogue instructions
684  {"ADDIUSP_MM", &EmulateInstructionMIPS::Emulate_ADDIUSP,
685  "ADDIU immediate"},
686  {"ADDIUS5_MM", &EmulateInstructionMIPS::Emulate_ADDIUS5,
687  "ADDIUS5 rd,immediate"},
688  {"SWSP_MM", &EmulateInstructionMIPS::Emulate_SWSP, "SWSP rt,offset(sp)"},
689  {"SWM16_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,
690  "SWM16 reglist,offset(sp)"},
691  {"SWM32_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,
692  "SWM32 reglist,offset(base)"},
693  {"SWP_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,
694  "SWP rs1,offset(base)"},
695  {"LWSP_MM", &EmulateInstructionMIPS::Emulate_LWSP, "LWSP rt,offset(sp)"},
696  {"LWM16_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,
697  "LWM16 reglist,offset(sp)"},
698  {"LWM32_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,
699  "LWM32 reglist,offset(base)"},
700  {"LWP_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,
701  "LWP rd,offset(base)"},
702  {"JRADDIUSP", &EmulateInstructionMIPS::Emulate_JRADDIUSP,
703  "JRADDIUSP immediate"},
704 
705  // Load/Store instructions
706  /* Following list of emulated instructions are required by implementation
707  of hardware watchpoint
708  for MIPS in lldb. As we just need the address accessed by instructions,
709  we have generalised
710  all these instructions in 2 functions depending on their addressing
711  modes */
712 
713  {"LB", &EmulateInstructionMIPS::Emulate_LDST_Imm,
714  "LB rt, offset(base)"},
715  {"LBE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
716  "LBE rt, offset(base)"},
717  {"LBU", &EmulateInstructionMIPS::Emulate_LDST_Imm,
718  "LBU rt, offset(base)"},
719  {"LBUE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
720  "LBUE rt, offset(base)"},
721  {"LDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,
722  "LDC1 ft, offset(base)"},
723  {"LD", &EmulateInstructionMIPS::Emulate_LDST_Imm,
724  "LD rt, offset(base)"},
725  {"LDL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
726  "LDL rt, offset(base)"},
727  {"LDR", &EmulateInstructionMIPS::Emulate_LDST_Imm,
728  "LDR rt, offset(base)"},
729  {"LLD", &EmulateInstructionMIPS::Emulate_LDST_Imm,
730  "LLD rt, offset(base)"},
731  {"LDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,
732  "LDC2 rt, offset(base)"},
733  {"LDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
734  "LDXC1 fd, index (base)"},
735  {"LH", &EmulateInstructionMIPS::Emulate_LDST_Imm,
736  "LH rt, offset(base)"},
737  {"LHE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
738  "LHE rt, offset(base)"},
739  {"LHU", &EmulateInstructionMIPS::Emulate_LDST_Imm,
740  "LHU rt, offset(base)"},
741  {"LHUE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
742  "LHUE rt, offset(base)"},
743  {"LL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
744  "LL rt, offset(base)"},
745  {"LLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
746  "LLE rt, offset(base)"},
747  {"LUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
748  "LUXC1 fd, index (base)"},
749  {"LW", &EmulateInstructionMIPS::Emulate_LDST_Imm,
750  "LW rt, offset(base)"},
751  {"LWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,
752  "LWC1 ft, offset(base)"},
753  {"LWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,
754  "LWC2 rt, offset(base)"},
755  {"LWE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
756  "LWE rt, offset(base)"},
757  {"LWL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
758  "LWL rt, offset(base)"},
759  {"LWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
760  "LWLE rt, offset(base)"},
761  {"LWR", &EmulateInstructionMIPS::Emulate_LDST_Imm,
762  "LWR rt, offset(base)"},
763  {"LWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
764  "LWRE rt, offset(base)"},
765  {"LWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
766  "LWXC1 fd, index (base)"},
767  {"LLX", &EmulateInstructionMIPS::Emulate_LDST_Imm,
768  "LLX rt, offset(base)"},
769  {"LLXE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
770  "LLXE rt, offset(base)"},
771  {"LLDX", &EmulateInstructionMIPS::Emulate_LDST_Imm,
772  "LLDX rt, offset(base)"},
773 
774  {"SB", &EmulateInstructionMIPS::Emulate_LDST_Imm,
775  "SB rt, offset(base)"},
776  {"SBE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
777  "SBE rt, offset(base)"},
778  {"SC", &EmulateInstructionMIPS::Emulate_LDST_Imm,
779  "SC rt, offset(base)"},
780  {"SCE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
781  "SCE rt, offset(base)"},
782  {"SCD", &EmulateInstructionMIPS::Emulate_LDST_Imm,
783  "SCD rt, offset(base)"},
784  {"SD", &EmulateInstructionMIPS::Emulate_LDST_Imm,
785  "SD rt, offset(base)"},
786  {"SDL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
787  "SDL rt, offset(base)"},
788  {"SDR", &EmulateInstructionMIPS::Emulate_LDST_Imm,
789  "SDR rt, offset(base)"},
790  {"SDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,
791  "SDC1 ft, offset(base)"},
792  {"SDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,
793  "SDC2 rt, offset(base)"},
794  {"SDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
795  "SDXC1 fs, index(base)"},
796  {"SH", &EmulateInstructionMIPS::Emulate_LDST_Imm,
797  "SH rt, offset(base)"},
798  {"SHE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
799  "SHE rt, offset(base)"},
800  {"SUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
801  "SUXC1 fs, index (base)"},
802  {"SWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,
803  "SWC1 ft, offset(base)"},
804  {"SWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,
805  "SWC2 rt, offset(base)"},
806  {"SWE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
807  "SWE rt, offset(base)"},
808  {"SWL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
809  "SWL rt, offset(base)"},
810  {"SWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
811  "SWLE rt, offset(base)"},
812  {"SWR", &EmulateInstructionMIPS::Emulate_LDST_Imm,
813  "SWR rt, offset(base)"},
814  {"SWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
815  "SWRE rt, offset(base)"},
816  {"SWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
817  "SWXC1 fs, index (base)"},
818  {"SCX", &EmulateInstructionMIPS::Emulate_LDST_Imm,
819  "SCX rt, offset(base)"},
820  {"SCXE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
821  "SCXE rt, offset(base)"},
822  {"SCDX", &EmulateInstructionMIPS::Emulate_LDST_Imm,
823  "SCDX rt, offset(base)"},
824 
825  // MicroMIPS Load/Store instructions
826  {"LBU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
827  "LBU16 rt, decoded_offset(base)"},
828  {"LHU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
829  "LHU16 rt, left_shifted_offset(base)"},
830  {"LW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
831  "LW16 rt, left_shifted_offset(base)"},
832  {"LWGP_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
833  "LWGP rt, left_shifted_offset(gp)"},
834  {"SH16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
835  "SH16 rt, left_shifted_offset(base)"},
836  {"SW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
837  "SW16 rt, left_shifted_offset(base)"},
838  {"SW_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
839  "SWSP rt, left_shifted_offset(base)"},
840  {"SB16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
841  "SB16 rt, offset(base)"},
842 
843  // Branch instructions
844  {"BEQ", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
845  {"BNE", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BNE rs,rt,offset"},
846  {"BEQL", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BEQL rs,rt,offset"},
847  {"BNEL", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BNEL rs,rt,offset"},
848  {"BGEZALL", &EmulateInstructionMIPS::Emulate_Bcond_Link,
849  "BGEZALL rt,offset"},
850  {"BAL", &EmulateInstructionMIPS::Emulate_BAL, "BAL offset"},
851  {"BGEZAL", &EmulateInstructionMIPS::Emulate_Bcond_Link,
852  "BGEZAL rs,offset"},
853  {"BALC", &EmulateInstructionMIPS::Emulate_BALC, "BALC offset"},
854  {"BC", &EmulateInstructionMIPS::Emulate_BC, "BC offset"},
855  {"BGEZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGEZ rs,offset"},
856  {"BLEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
857  "BLEZALC rs,offset"},
858  {"BGEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
859  "BGEZALC rs,offset"},
860  {"BLTZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
861  "BLTZALC rs,offset"},
862  {"BGTZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
863  "BGTZALC rs,offset"},
864  {"BEQZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
865  "BEQZALC rs,offset"},
866  {"BNEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
867  "BNEZALC rs,offset"},
868  {"BEQC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
869  "BEQC rs,rt,offset"},
870  {"BNEC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
871  "BNEC rs,rt,offset"},
872  {"BLTC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
873  "BLTC rs,rt,offset"},
874  {"BGEC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
875  "BGEC rs,rt,offset"},
876  {"BLTUC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
877  "BLTUC rs,rt,offset"},
878  {"BGEUC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
879  "BGEUC rs,rt,offset"},
880  {"BLTZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BLTZC rt,offset"},
881  {"BLEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BLEZC rt,offset"},
882  {"BGEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BGEZC rt,offset"},
883  {"BGTZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BGTZC rt,offset"},
884  {"BEQZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BEQZC rt,offset"},
885  {"BNEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BNEZC rt,offset"},
886  {"BGEZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGEZL rt,offset"},
887  {"BGTZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGTZ rt,offset"},
888  {"BGTZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGTZL rt,offset"},
889  {"BLEZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLEZ rt,offset"},
890  {"BLEZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLEZL rt,offset"},
891  {"BLTZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLTZ rt,offset"},
892  {"BLTZAL", &EmulateInstructionMIPS::Emulate_Bcond_Link,
893  "BLTZAL rt,offset"},
894  {"BLTZALL", &EmulateInstructionMIPS::Emulate_Bcond_Link,
895  "BLTZALL rt,offset"},
896  {"BLTZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLTZL rt,offset"},
897  {"BOVC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
898  "BOVC rs,rt,offset"},
899  {"BNVC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
900  "BNVC rs,rt,offset"},
901  {"J", &EmulateInstructionMIPS::Emulate_J, "J target"},
902  {"JAL", &EmulateInstructionMIPS::Emulate_JAL, "JAL target"},
903  {"JALX", &EmulateInstructionMIPS::Emulate_JAL, "JALX target"},
904  {"JALR", &EmulateInstructionMIPS::Emulate_JALR, "JALR target"},
905  {"JALR_HB", &EmulateInstructionMIPS::Emulate_JALR, "JALR.HB target"},
906  {"JIALC", &EmulateInstructionMIPS::Emulate_JIALC, "JIALC rt,offset"},
907  {"JIC", &EmulateInstructionMIPS::Emulate_JIC, "JIC rt,offset"},
908  {"JR", &EmulateInstructionMIPS::Emulate_JR, "JR target"},
909  {"JR_HB", &EmulateInstructionMIPS::Emulate_JR, "JR.HB target"},
910  {"BC1F", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1F cc, offset"},
911  {"BC1T", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1T cc, offset"},
912  {"BC1FL", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1FL cc, offset"},
913  {"BC1TL", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1TL cc, offset"},
914  {"BC1EQZ", &EmulateInstructionMIPS::Emulate_BC1EQZ, "BC1EQZ ft, offset"},
915  {"BC1NEZ", &EmulateInstructionMIPS::Emulate_BC1NEZ, "BC1NEZ ft, offset"},
916  {"BC1ANY2F", &EmulateInstructionMIPS::Emulate_3D_branch,
917  "BC1ANY2F cc, offset"},
918  {"BC1ANY2T", &EmulateInstructionMIPS::Emulate_3D_branch,
919  "BC1ANY2T cc, offset"},
920  {"BC1ANY4F", &EmulateInstructionMIPS::Emulate_3D_branch,
921  "BC1ANY4F cc, offset"},
922  {"BC1ANY4T", &EmulateInstructionMIPS::Emulate_3D_branch,
923  "BC1ANY4T cc, offset"},
924  {"BNZ_B", &EmulateInstructionMIPS::Emulate_BNZB, "BNZ.b wt,s16"},
925  {"BNZ_H", &EmulateInstructionMIPS::Emulate_BNZH, "BNZ.h wt,s16"},
926  {"BNZ_W", &EmulateInstructionMIPS::Emulate_BNZW, "BNZ.w wt,s16"},
927  {"BNZ_D", &EmulateInstructionMIPS::Emulate_BNZD, "BNZ.d wt,s16"},
928  {"BZ_B", &EmulateInstructionMIPS::Emulate_BZB, "BZ.b wt,s16"},
929  {"BZ_H", &EmulateInstructionMIPS::Emulate_BZH, "BZ.h wt,s16"},
930  {"BZ_W", &EmulateInstructionMIPS::Emulate_BZW, "BZ.w wt,s16"},
931  {"BZ_D", &EmulateInstructionMIPS::Emulate_BZD, "BZ.d wt,s16"},
932  {"BNZ_V", &EmulateInstructionMIPS::Emulate_BNZV, "BNZ.V wt,s16"},
933  {"BZ_V", &EmulateInstructionMIPS::Emulate_BZV, "BZ.V wt,s16"},
934 
935  // MicroMIPS Branch instructions
936  {"B16_MM", &EmulateInstructionMIPS::Emulate_B16_MM, "B16 offset"},
937  {"BEQZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
938  "BEQZ16 rs, offset"},
939  {"BNEZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
940  "BNEZ16 rs, offset"},
941  {"BEQZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
942  "BEQZC rs, offset"},
943  {"BNEZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
944  "BNEZC rs, offset"},
945  {"BGEZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
946  "BGEZALS rs, offset"},
947  {"BLTZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
948  "BLTZALS rs, offset"},
949  {"JALR16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALR16 rs"},
950  {"JALRS16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALRS16 rs"},
951  {"JR16_MM", &EmulateInstructionMIPS::Emulate_JR, "JR16 rs rs"},
952  {"JRC16_MM", &EmulateInstructionMIPS::Emulate_JR, "JRC16 rs rs"},
953  {"JALS_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALS target"},
954  {"JALX_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALX target"},
955  {"JALRS_MM", &EmulateInstructionMIPS::Emulate_JALRS, "JALRS rt, rs"},
956  };
957 
958  for (MipsOpcode &opcode : g_opcodes) {
959  if (name.equals_insensitive(opcode.op_name))
960  return &opcode;
961  }
962  return nullptr;
963 }
964 
965 uint32_t
966 EmulateInstructionMIPS::GetSizeOfInstruction(lldb_private::DataExtractor &data,
967  uint64_t inst_addr) {
968  uint64_t next_inst_size = 0;
969  llvm::MCInst mc_insn;
970  llvm::MCDisassembler::DecodeStatus decode_status;
971  llvm::ArrayRef<uint8_t> raw_insn(data.GetDataStart(), data.GetByteSize());
972 
973  if (m_use_alt_disaasm)
974  decode_status = m_alt_disasm->getInstruction(
975  mc_insn, next_inst_size, raw_insn, inst_addr, llvm::nulls());
976  else
977  decode_status = m_disasm->getInstruction(mc_insn, next_inst_size, raw_insn,
978  inst_addr, llvm::nulls());
979 
980  if (decode_status != llvm::MCDisassembler::Success)
981  return false;
982 
983  return m_insn_info->get(mc_insn.getOpcode()).getSize();
984 }
985 
986 bool EmulateInstructionMIPS::SetInstruction(const Opcode &insn_opcode,
987  const Address &inst_addr,
988  Target *target) {
989  m_use_alt_disaasm = false;
990 
991  if (EmulateInstruction::SetInstruction(insn_opcode, inst_addr, target)) {
992  if (inst_addr.GetAddressClass() == AddressClass::eCodeAlternateISA) {
993  Status error;
994  lldb::addr_t load_addr = LLDB_INVALID_ADDRESS;
995 
996  /*
997  * The address belongs to microMIPS function. To find the size of
998  * next instruction use microMIPS disassembler.
999  */
1000  m_use_alt_disaasm = true;
1001 
1002  uint32_t current_inst_size = insn_opcode.GetByteSize();
1003  uint8_t buf[sizeof(uint32_t)];
1004  uint64_t next_inst_addr = (m_addr & (~1ull)) + current_inst_size;
1005  Address next_addr(next_inst_addr);
1006 
1007  const size_t bytes_read =
1008  target->ReadMemory(next_addr, /* Address of next instruction */
1009  buf, sizeof(uint32_t), error,
1010  false, /* force_live_memory */
1011  &load_addr);
1012 
1013  if (bytes_read == 0)
1014  return true;
1015 
1016  DataExtractor data(buf, sizeof(uint32_t), GetByteOrder(),
1017  GetAddressByteSize());
1018  m_next_inst_size = GetSizeOfInstruction(data, next_inst_addr);
1019  return true;
1020  } else {
1021  /*
1022  * If the address class is not AddressClass::eCodeAlternateISA then
1023  * the function is not microMIPS. In this case instruction size is
1024  * always 4 bytes.
1025  */
1026  m_next_inst_size = 4;
1027  return true;
1028  }
1029  }
1030  return false;
1031 }
1032 
1033 bool EmulateInstructionMIPS::ReadInstruction() {
1034  bool success = false;
1035  m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
1036  LLDB_INVALID_ADDRESS, &success);
1037  if (success) {
1038  Context read_inst_context;
1039  read_inst_context.type = eContextReadOpcode;
1040  read_inst_context.SetNoArgs();
1041  m_opcode.SetOpcode32(
1042  ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success),
1043  GetByteOrder());
1044  }
1045  if (!success)
1046  m_addr = LLDB_INVALID_ADDRESS;
1047  return success;
1048 }
1049 
1050 bool EmulateInstructionMIPS::EvaluateInstruction(uint32_t evaluate_options) {
1051  bool success = false;
1052  llvm::MCInst mc_insn;
1053  uint64_t insn_size;
1054  DataExtractor data;
1055 
1056  /* Keep the complexity of the decode logic with the llvm::MCDisassembler
1057  * class. */
1058  if (m_opcode.GetData(data)) {
1059  llvm::MCDisassembler::DecodeStatus decode_status;
1060  llvm::ArrayRef<uint8_t> raw_insn(data.GetDataStart(), data.GetByteSize());
1061  if (m_use_alt_disaasm)
1062  decode_status = m_alt_disasm->getInstruction(mc_insn, insn_size, raw_insn,
1063  m_addr, llvm::nulls());
1064  else
1065  decode_status = m_disasm->getInstruction(mc_insn, insn_size, raw_insn,
1066  m_addr, llvm::nulls());
1067 
1068  if (decode_status != llvm::MCDisassembler::Success)
1069  return false;
1070  }
1071 
1072  /*
1073  * mc_insn.getOpcode() returns decoded opcode. However to make use
1074  * of llvm::Mips::<insn> we would need "MipsGenInstrInfo.inc".
1075  */
1076  const char *op_name = m_insn_info->getName(mc_insn.getOpcode()).data();
1077 
1078  if (op_name == nullptr)
1079  return false;
1080 
1081  /*
1082  * Decoding has been done already. Just get the call-back function
1083  * and emulate the instruction.
1084  */
1085  MipsOpcode *opcode_data = GetOpcodeForInstruction(op_name);
1086 
1087  if (opcode_data == nullptr)
1088  return false;
1089 
1090  uint64_t old_pc = 0, new_pc = 0;
1091  const bool auto_advance_pc =
1092  evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
1093 
1094  if (auto_advance_pc) {
1095  old_pc =
1096  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
1097  if (!success)
1098  return false;
1099  }
1100 
1101  /* emulate instruction */
1102  success = (this->*opcode_data->callback)(mc_insn);
1103  if (!success)
1104  return false;
1105 
1106  if (auto_advance_pc) {
1107  new_pc =
1108  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
1109  if (!success)
1110  return false;
1111 
1112  /* If we haven't changed the PC, change it here */
1113  if (old_pc == new_pc) {
1114  new_pc += 4;
1115  Context context;
1116  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
1117  new_pc))
1118  return false;
1119  }
1120  }
1121 
1122  return true;
1123 }
1124 
1125 bool EmulateInstructionMIPS::CreateFunctionEntryUnwind(
1126  UnwindPlan &unwind_plan) {
1127  unwind_plan.Clear();
1128  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
1129 
1130  UnwindPlan::RowSP row(new UnwindPlan::Row);
1131  const bool can_replace = false;
1132 
1133  // Our previous Call Frame Address is the stack pointer
1134  row->GetCFAValue().SetIsRegisterPlusOffset(dwarf_sp_mips, 0);
1135 
1136  // Our previous PC is in the RA
1137  row->SetRegisterLocationToRegister(dwarf_pc_mips, dwarf_ra_mips, can_replace);
1138 
1139  unwind_plan.AppendRow(row);
1140 
1141  // All other registers are the same.
1142  unwind_plan.SetSourceName("EmulateInstructionMIPS");
1143  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1144  unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
1145  unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo);
1146  unwind_plan.SetReturnAddressRegister(dwarf_ra_mips);
1147 
1148  return true;
1149 }
1150 
1151 bool EmulateInstructionMIPS::nonvolatile_reg_p(uint32_t regnum) {
1152  switch (regnum) {
1153  case dwarf_r16_mips:
1154  case dwarf_r17_mips:
1155  case dwarf_r18_mips:
1156  case dwarf_r19_mips:
1157  case dwarf_r20_mips:
1158  case dwarf_r21_mips:
1159  case dwarf_r22_mips:
1160  case dwarf_r23_mips:
1161  case dwarf_gp_mips:
1162  case dwarf_sp_mips:
1163  case dwarf_r30_mips:
1164  case dwarf_ra_mips:
1165  return true;
1166  default:
1167  return false;
1168  }
1169  return false;
1170 }
1171 
1172 bool EmulateInstructionMIPS::Emulate_ADDiu(llvm::MCInst &insn) {
1173  // ADDIU rt, rs, immediate
1174  // GPR[rt] <- GPR[rs] + sign_extend(immediate)
1175 
1176  uint8_t dst, src;
1177  bool success = false;
1178  const uint32_t imm16 = insn.getOperand(2).getImm();
1179  int64_t imm = SignedBits(imm16, 15, 0);
1180 
1181  dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1182  src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1183 
1184  // If immediate value is greater then 2^16 - 1 then clang generate LUI,
1185  // ADDIU, SUBU instructions in prolog. Example lui $1, 0x2 addiu $1, $1,
1186  // -0x5920 subu $sp, $sp, $1 In this case, ADDIU dst and src will be same
1187  // and not equal to sp
1188  if (dst == src) {
1189  Context context;
1190 
1191  /* read <src> register */
1192  const int64_t src_opd_val = ReadRegisterUnsigned(
1193  eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success);
1194  if (!success)
1195  return false;
1196 
1197  /* Check if this is daddiu sp, sp, imm16 */
1198  if (dst == dwarf_sp_mips) {
1199  uint64_t result = src_opd_val + imm;
1200  llvm::Optional<RegisterInfo> reg_info_sp =
1201  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
1202  if (reg_info_sp)
1203  context.SetRegisterPlusOffset(*reg_info_sp, imm);
1204 
1205  /* We are allocating bytes on stack */
1206  context.type = eContextAdjustStackPointer;
1207 
1208  WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips, result);
1209  return true;
1210  }
1211 
1212  imm += src_opd_val;
1213  context.SetImmediateSigned(imm);
1214  context.type = eContextImmediate;
1215 
1216  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF,
1217  dwarf_zero_mips + dst, imm))
1218  return false;
1219  }
1220 
1221  return true;
1222 }
1223 
1224 bool EmulateInstructionMIPS::Emulate_SW(llvm::MCInst &insn) {
1225  bool success = false;
1226  uint32_t imm16 = insn.getOperand(2).getImm();
1227  uint32_t imm = SignedBits(imm16, 15, 0);
1228  uint32_t src, base;
1229  int32_t address;
1230  Context bad_vaddr_context;
1231 
1232  src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1233  base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1234 
1235  llvm::Optional<RegisterInfo> reg_info_base =
1236  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base);
1237  if (!reg_info_base)
1238  return false;
1239 
1240  /* read base register */
1241  address = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1242  dwarf_zero_mips + base, 0, &success);
1243  if (!success)
1244  return false;
1245 
1246  /* destination address */
1247  address = address + imm;
1248 
1249  /* Set the bad_vaddr register with base address used in the instruction */
1250  bad_vaddr_context.type = eContextInvalid;
1251  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
1252  address);
1253 
1254  /* We look for sp based non-volatile register stores */
1255  if (nonvolatile_reg_p(src)) {
1256  llvm::Optional<RegisterInfo> reg_info_src =
1257  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src);
1258  if (!reg_info_src)
1259  return false;
1260 
1261  Context context;
1262  context.type = eContextPushRegisterOnStack;
1263  context.SetRegisterToRegisterPlusOffset(*reg_info_src, *reg_info_base, 0);
1264 
1265  uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
1266  Status error;
1267 
1268  llvm::Optional<RegisterValue> data_src = ReadRegister(*reg_info_base);
1269  if (!data_src)
1270  return false;
1271 
1272  if (data_src->GetAsMemoryData(*reg_info_src, buffer,
1273  reg_info_src->byte_size, eByteOrderLittle,
1274  error) == 0)
1275  return false;
1276 
1277  if (!WriteMemory(context, address, buffer, reg_info_src->byte_size))
1278  return false;
1279 
1280  return true;
1281  }
1282 
1283  return false;
1284 }
1285 
1286 bool EmulateInstructionMIPS::Emulate_LW(llvm::MCInst &insn) {
1287  bool success = false;
1288  uint32_t src, base;
1289  int32_t imm, address;
1290  Context bad_vaddr_context;
1291 
1292  src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1293  base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1294  imm = insn.getOperand(2).getImm();
1295 
1296  if (GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
1297  return false;
1298 
1299  /* read base register */
1300  address = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1301  dwarf_zero_mips + base, 0, &success);
1302  if (!success)
1303  return false;
1304 
1305  /* destination address */
1306  address = address + imm;
1307 
1308  /* Set the bad_vaddr register with base address used in the instruction */
1309  bad_vaddr_context.type = eContextInvalid;
1310  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
1311  address);
1312 
1313  if (nonvolatile_reg_p(src)) {
1314  RegisterValue data_src;
1315  llvm::Optional<RegisterInfo> reg_info_src =
1316  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src);
1317  if (!reg_info_src)
1318  return false;
1319 
1320  Context context;
1321  context.type = eContextPopRegisterOffStack;
1322  context.SetAddress(address);
1323 
1324  return WriteRegister(context, *reg_info_src, data_src);
1325  }
1326 
1327  return false;
1328 }
1329 
1330 bool EmulateInstructionMIPS::Emulate_SUBU_ADDU(llvm::MCInst &insn) {
1331  // SUBU sp, <src>, <rt>
1332  // ADDU sp, <src>, <rt>
1333  // ADDU dst, sp, <rt>
1334 
1335  bool success = false;
1336  uint64_t result;
1337  uint8_t src, dst, rt;
1338  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1339 
1340  dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1341  src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1342 
1343  /* Check if sp is destination register */
1344  if (dst == dwarf_sp_mips) {
1345  rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg());
1346 
1347  /* read <src> register */
1348  uint64_t src_opd_val = ReadRegisterUnsigned(
1349  eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success);
1350  if (!success)
1351  return false;
1352 
1353  /* read <rt > register */
1354  uint64_t rt_opd_val = ReadRegisterUnsigned(
1355  eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success);
1356  if (!success)
1357  return false;
1358 
1359  if (op_name.equals_insensitive("SUBU"))
1360  result = src_opd_val - rt_opd_val;
1361  else
1362  result = src_opd_val + rt_opd_val;
1363 
1364  Context context;
1365  llvm::Optional<RegisterInfo> reg_info_sp =
1366  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
1367  if (reg_info_sp)
1368  context.SetRegisterPlusOffset(*reg_info_sp, rt_opd_val);
1369 
1370  /* We are allocating bytes on stack */
1371  context.type = eContextAdjustStackPointer;
1372 
1373  WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips, result);
1374 
1375  return true;
1376  } else if (src == dwarf_sp_mips) {
1377  rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg());
1378 
1379  /* read <src> register */
1380  uint64_t src_opd_val = ReadRegisterUnsigned(
1381  eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success);
1382  if (!success)
1383  return false;
1384 
1385  /* read <rt> register */
1386  uint64_t rt_opd_val = ReadRegisterUnsigned(
1387  eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success);
1388  if (!success)
1389  return false;
1390 
1391  Context context;
1392 
1393  if (op_name.equals_insensitive("SUBU"))
1394  result = src_opd_val - rt_opd_val;
1395  else
1396  result = src_opd_val + rt_opd_val;
1397 
1398  context.SetImmediateSigned(result);
1399  context.type = eContextImmediate;
1400 
1401  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF,
1402  dwarf_zero_mips + dst, result))
1403  return false;
1404  }
1405 
1406  return true;
1407 }
1408 
1409 bool EmulateInstructionMIPS::Emulate_LUI(llvm::MCInst &insn) {
1410  // LUI rt, immediate
1411  // GPR[rt] <- sign_extend(immediate << 16)
1412 
1413  const uint32_t imm32 = insn.getOperand(1).getImm() << 16;
1414  int64_t imm = SignedBits(imm32, 31, 0);
1415  uint8_t rt;
1416  Context context;
1417 
1418  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1419  context.SetImmediateSigned(imm);
1420  context.type = eContextImmediate;
1421 
1422  return WriteRegisterUnsigned(context, eRegisterKindDWARF,
1423  dwarf_zero_mips + rt, imm);
1424 }
1425 
1426 bool EmulateInstructionMIPS::Emulate_ADDIUSP(llvm::MCInst &insn) {
1427  bool success = false;
1428  const uint32_t imm9 = insn.getOperand(0).getImm();
1429  uint64_t result;
1430 
1431  // This instruction operates implicitly on stack pointer, so read <sp>
1432  // register.
1433  uint64_t src_opd_val =
1434  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_sp_mips, 0, &success);
1435  if (!success)
1436  return false;
1437 
1438  result = src_opd_val + imm9;
1439 
1440  Context context;
1441  llvm::Optional<RegisterInfo> reg_info_sp =
1442  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
1443  if (reg_info_sp)
1444  context.SetRegisterPlusOffset(*reg_info_sp, imm9);
1445 
1446  // We are adjusting the stack.
1447  context.type = eContextAdjustStackPointer;
1448 
1449  WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips, result);
1450  return true;
1451 }
1452 
1453 bool EmulateInstructionMIPS::Emulate_ADDIUS5(llvm::MCInst &insn) {
1454  bool success = false;
1455  uint32_t base;
1456  const uint32_t imm4 = insn.getOperand(2).getImm();
1457  uint64_t result;
1458 
1459  // The source and destination register is same for this instruction.
1460  base = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1461 
1462  // We are looking for stack adjustment only
1463  if (base == dwarf_sp_mips) {
1464  // Read stack pointer register
1465  uint64_t src_opd_val = ReadRegisterUnsigned(
1466  eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
1467  if (!success)
1468  return false;
1469 
1470  result = src_opd_val + imm4;
1471 
1472  Context context;
1473  llvm::Optional<RegisterInfo> reg_info_sp =
1474  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
1475  if (reg_info_sp)
1476  context.SetRegisterPlusOffset(*reg_info_sp, imm4);
1477 
1478  // We are adjusting the stack.
1479  context.type = eContextAdjustStackPointer;
1480 
1481  WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips, result);
1482  }
1483 
1484  return true;
1485 }
1486 
1487 bool EmulateInstructionMIPS::Emulate_SWSP(llvm::MCInst &insn) {
1488  bool success = false;
1489  uint32_t imm5 = insn.getOperand(2).getImm();
1490  uint32_t src, base;
1491  Context bad_vaddr_context;
1492  uint32_t address;
1493 
1494  src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1495  base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1496 
1497  llvm::Optional<RegisterInfo> reg_info_base =
1498  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base);
1499  if (!reg_info_base)
1500  return false;
1501 
1502  // read base register
1503  address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + base, 0,
1504  &success);
1505  if (!success)
1506  return false;
1507 
1508  // destination address
1509  address = address + imm5;
1510 
1511  // We use bad_vaddr_context to store base address which is used by H/W
1512  // watchpoint Set the bad_vaddr register with base address used in the
1513  // instruction
1514  bad_vaddr_context.type = eContextInvalid;
1515  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
1516  address);
1517 
1518  // We look for sp based non-volatile register stores.
1519  if (base == dwarf_sp_mips && nonvolatile_reg_p(src)) {
1520  RegisterInfo reg_info_src = {};
1521  Context context;
1522  context.type = eContextPushRegisterOnStack;
1523  context.SetRegisterToRegisterPlusOffset(reg_info_src, *reg_info_base, 0);
1524 
1525  uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
1526  Status error;
1527 
1528  llvm::Optional<RegisterValue> data_src = ReadRegister(*reg_info_base);
1529  if (!data_src)
1530  return false;
1531 
1532  if (data_src->GetAsMemoryData(reg_info_src, buffer, reg_info_src.byte_size,
1533  eByteOrderLittle, error) == 0)
1534  return false;
1535 
1536  if (!WriteMemory(context, address, buffer, reg_info_src.byte_size))
1537  return false;
1538 
1539  return true;
1540  }
1541 
1542  return false;
1543 }
1544 
1545 /* Emulate SWM16,SWM32 and SWP instruction.
1546 
1547  SWM16 always has stack pointer as a base register (but it is still available
1548  in MCInst as an operand).
1549  SWM32 and SWP can have base register other than stack pointer.
1550 */
1551 bool EmulateInstructionMIPS::Emulate_SWM16_32(llvm::MCInst &insn) {
1552  bool success = false;
1553  uint32_t src, base;
1554  uint32_t num_operands = insn.getNumOperands(); // No of operands vary based on
1555  // no of regs to store.
1556 
1557  // Base register is second last operand of the instruction.
1558  base =
1559  m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
1560 
1561  // We are looking for sp based stores so if base is not a stack pointer then
1562  // don't proceed.
1563  if (base != dwarf_sp_mips)
1564  return false;
1565 
1566  // offset is always the last operand.
1567  uint32_t offset = insn.getOperand(num_operands - 1).getImm();
1568 
1569  llvm::Optional<RegisterInfo> reg_info_base =
1570  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base);
1571  if (!reg_info_base)
1572  return false;
1573 
1574  // read SP
1575  uint32_t base_address = ReadRegisterUnsigned(
1576  eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
1577  if (!success)
1578  return false;
1579 
1580  // Resulting base addrss
1581  base_address = base_address + offset;
1582 
1583  // Total no of registers to be stored are num_operands-2.
1584  for (uint32_t i = 0; i < num_operands - 2; i++) {
1585  // Get the register number to be stored.
1586  src = m_reg_info->getEncodingValue(insn.getOperand(i).getReg());
1587 
1588  /*
1589  Record only non-volatile stores.
1590  This check is required for SWP instruction because source operand could
1591  be any register.
1592  SWM16 and SWM32 instruction always has saved registers as source
1593  operands.
1594  */
1595  if (!nonvolatile_reg_p(src))
1596  return false;
1597 
1598  llvm::Optional<RegisterInfo> reg_info_src =
1599  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src);
1600  if (!reg_info_src)
1601  return false;
1602 
1603  Context context;
1604  context.type = eContextPushRegisterOnStack;
1605  context.SetRegisterToRegisterPlusOffset(*reg_info_src, *reg_info_base, 0);
1606 
1607  uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
1608  Status error;
1609 
1610  llvm::Optional<RegisterValue> data_src = ReadRegister(*reg_info_base);
1611  if (!data_src)
1612  return false;
1613 
1614  if (data_src->GetAsMemoryData(*reg_info_src, buffer,
1615  reg_info_src->byte_size, eByteOrderLittle,
1616  error) == 0)
1617  return false;
1618 
1619  if (!WriteMemory(context, base_address, buffer, reg_info_src->byte_size))
1620  return false;
1621 
1622  // Stack address for next register
1623  base_address = base_address + reg_info_src->byte_size;
1624  }
1625  return true;
1626 }
1627 
1628 bool EmulateInstructionMIPS::Emulate_LWSP(llvm::MCInst &insn) {
1629  bool success = false;
1630  uint32_t src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1631  uint32_t base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1632  uint32_t imm5 = insn.getOperand(2).getImm();
1633  Context bad_vaddr_context;
1634 
1635  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
1636  return false;
1637 
1638  // read base register
1639  uint32_t base_address = ReadRegisterUnsigned(
1640  eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
1641  if (!success)
1642  return false;
1643 
1644  base_address = base_address + imm5;
1645 
1646  // We use bad_vaddr_context to store base address which is used by H/W
1647  // watchpoint Set the bad_vaddr register with base address used in the
1648  // instruction
1649  bad_vaddr_context.type = eContextInvalid;
1650  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
1651  base_address);
1652 
1653  if (base == dwarf_sp_mips && nonvolatile_reg_p(src)) {
1654  RegisterValue data_src;
1655  llvm::Optional<RegisterInfo> reg_info_src =
1656  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src);
1657  if (!reg_info_src)
1658  return false;
1659 
1660  Context context;
1661  context.type = eContextPopRegisterOffStack;
1662  context.SetAddress(base_address);
1663 
1664  return WriteRegister(context, *reg_info_src, data_src);
1665  }
1666 
1667  return false;
1668 }
1669 
1670 /* Emulate LWM16, LWM32 and LWP instructions.
1671 
1672  LWM16 always has stack pointer as a base register (but it is still available
1673  in MCInst as an operand).
1674  LWM32 and LWP can have base register other than stack pointer.
1675 */
1676 bool EmulateInstructionMIPS::Emulate_LWM16_32(llvm::MCInst &insn) {
1677  bool success = false;
1678  uint32_t dst, base;
1679  uint32_t num_operands = insn.getNumOperands(); // No of operands vary based on
1680  // no of regs to store.
1681  uint32_t imm = insn.getOperand(num_operands - 1)
1682  .getImm(); // imm is the last operand in the instruction.
1683 
1684  // Base register is second last operand of the instruction.
1685  base =
1686  m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
1687 
1688  // We are looking for sp based loads so if base is not a stack pointer then
1689  // don't proceed.
1690  if (base != dwarf_sp_mips)
1691  return false;
1692 
1693  uint32_t base_address = ReadRegisterUnsigned(
1694  eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
1695  if (!success)
1696  return false;
1697 
1698  base_address = base_address + imm;
1699 
1700  RegisterValue data_dst;
1701 
1702  // Total no of registers to be re-stored are num_operands-2.
1703  for (uint32_t i = 0; i < num_operands - 2; i++) {
1704  // Get the register number to be re-stored.
1705  dst = m_reg_info->getEncodingValue(insn.getOperand(i).getReg());
1706 
1707  /*
1708  Record only non-volatile loads.
1709  This check is required for LWP instruction because destination operand
1710  could be any register.
1711  LWM16 and LWM32 instruction always has saved registers as destination
1712  operands.
1713  */
1714  if (!nonvolatile_reg_p(dst))
1715  return false;
1716 
1717  llvm::Optional<RegisterInfo> reg_info_dst =
1718  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + dst);
1719  if (!reg_info_dst)
1720  return false;
1721 
1722  Context context;
1723  context.type = eContextPopRegisterOffStack;
1724  context.SetAddress(base_address + (i * 4));
1725 
1726  if (!WriteRegister(context, *reg_info_dst, data_dst))
1727  return false;
1728  }
1729 
1730  return true;
1731 }
1732 
1733 bool EmulateInstructionMIPS::Emulate_JRADDIUSP(llvm::MCInst &insn) {
1734  bool success = false;
1735  int32_t imm5 = insn.getOperand(0).getImm();
1736 
1737  /* JRADDIUSP immediate
1738  * PC <- RA
1739  * SP <- SP + zero_extend(Immediate << 2)
1740  */
1741 
1742  // This instruction operates implicitly on stack pointer, so read <sp>
1743  // register.
1744  int32_t src_opd_val =
1745  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_sp_mips, 0, &success);
1746  if (!success)
1747  return false;
1748 
1749  int32_t ra_val =
1750  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_ra_mips, 0, &success);
1751  if (!success)
1752  return false;
1753 
1754  int32_t result = src_opd_val + imm5;
1755 
1756  Context context;
1757 
1758  // Update the PC
1759  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
1760  ra_val))
1761  return false;
1762 
1763  llvm::Optional<RegisterInfo> reg_info_sp =
1764  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
1765  if (reg_info_sp)
1766  context.SetRegisterPlusOffset(*reg_info_sp, imm5);
1767 
1768  // We are adjusting stack
1769  context.type = eContextAdjustStackPointer;
1770 
1771  // update SP
1772  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips,
1773  result);
1774 }
1775 
1776 static int IsAdd64bitOverflow(int32_t a, int32_t b) {
1777  int32_t r = (uint32_t)a + (uint32_t)b;
1778  return (a < 0 && b < 0 && r >= 0) || (a >= 0 && b >= 0 && r < 0);
1779 }
1780 
1781 /*
1782  Emulate below MIPS branch instructions.
1783  BEQ, BNE : Branch on condition
1784  BEQL, BNEL : Branch likely
1785 */
1786 bool EmulateInstructionMIPS::Emulate_BXX_3ops(llvm::MCInst &insn) {
1787  bool success = false;
1788  uint32_t rs, rt;
1789  int32_t offset, pc, target = 0, rs_val, rt_val;
1790  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1791 
1792  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1793  rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1794  offset = insn.getOperand(2).getImm();
1795 
1796  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
1797  if (!success)
1798  return false;
1799 
1800  rs_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1801  dwarf_zero_mips + rs, 0, &success);
1802  if (!success)
1803  return false;
1804 
1805  rt_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1806  dwarf_zero_mips + rt, 0, &success);
1807  if (!success)
1808  return false;
1809 
1810  if (op_name.equals_insensitive("BEQ") || op_name.equals_insensitive("BEQL")) {
1811  if (rs_val == rt_val)
1812  target = pc + offset;
1813  else
1814  target = pc + 8;
1815  } else if (op_name.equals_insensitive("BNE") ||
1816  op_name.equals_insensitive("BNEL")) {
1817  if (rs_val != rt_val)
1818  target = pc + offset;
1819  else
1820  target = pc + 8;
1821  }
1822 
1823  Context context;
1824  context.type = eContextRelativeBranchImmediate;
1825  context.SetImmediate(offset);
1826 
1827  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
1828  target);
1829 }
1830 
1831 /*
1832  Emulate below MIPS branch instructions.
1833  BEQC, BNEC, BLTC, BGEC, BLTUC, BGEUC, BOVC, BNVC: Compact branch
1834  instructions with no delay slot
1835 */
1836 bool EmulateInstructionMIPS::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
1837  bool success = false;
1838  uint32_t rs, rt;
1839  int32_t offset, pc, target = 0, rs_val, rt_val;
1840  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1841  uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
1842 
1843  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1844  rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1845  offset = insn.getOperand(2).getImm();
1846 
1847  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
1848  if (!success)
1849  return false;
1850 
1851  rs_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1852  dwarf_zero_mips + rs, 0, &success);
1853  if (!success)
1854  return false;
1855 
1856  rt_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1857  dwarf_zero_mips + rt, 0, &success);
1858  if (!success)
1859  return false;
1860 
1861  if (op_name.equals_insensitive("BEQC")) {
1862  if (rs_val == rt_val)
1863  target = pc + offset;
1864  else
1865  target = pc + 4;
1866  } else if (op_name.equals_insensitive("BNEC")) {
1867  if (rs_val != rt_val)
1868  target = pc + offset;
1869  else
1870  target = pc + 4;
1871  } else if (op_name.equals_insensitive("BLTC")) {
1872  if (rs_val < rt_val)
1873  target = pc + offset;
1874  else
1875  target = pc + 4;
1876  } else if (op_name.equals_insensitive("BGEC")) {
1877  if (rs_val >= rt_val)
1878  target = pc + offset;
1879  else
1880  target = pc + 4;
1881  } else if (op_name.equals_insensitive("BLTUC")) {
1882  if (rs_val < rt_val)
1883  target = pc + offset;
1884  else
1885  target = pc + 4;
1886  } else if (op_name.equals_insensitive("BGEUC")) {
1887  if ((uint32_t)rs_val >= (uint32_t)rt_val)
1888  target = pc + offset;
1889  else
1890  target = pc + 4;
1891  } else if (op_name.equals_insensitive("BOVC")) {
1892  if (IsAdd64bitOverflow(rs_val, rt_val))
1893  target = pc + offset;
1894  else
1895  target = pc + 4;
1896  } else if (op_name.equals_insensitive("BNVC")) {
1897  if (!IsAdd64bitOverflow(rs_val, rt_val))
1898  target = pc + offset;
1899  else
1900  target = pc + 4;
1901  }
1902 
1903  Context context;
1904  context.type = eContextRelativeBranchImmediate;
1905  context.SetImmediate(current_inst_size + offset);
1906 
1907  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
1908  target);
1909 }
1910 
1911 /*
1912  Emulate below MIPS conditional branch and link instructions.
1913  BLEZALC, BGEZALC, BLTZALC, BGTZALC, BEQZALC, BNEZALC : Compact branches
1914 */
1915 bool EmulateInstructionMIPS::Emulate_Bcond_Link_C(llvm::MCInst &insn) {
1916  bool success = false;
1917  uint32_t rs;
1918  int32_t offset, pc, target = 0;
1919  int32_t rs_val;
1920  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1921 
1922  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1923  offset = insn.getOperand(1).getImm();
1924 
1925  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
1926  if (!success)
1927  return false;
1928 
1929  rs_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1930  dwarf_zero_mips + rs, 0, &success);
1931  if (!success)
1932  return false;
1933 
1934  if (op_name.equals_insensitive("BLEZALC")) {
1935  if (rs_val <= 0)
1936  target = pc + offset;
1937  else
1938  target = pc + 4;
1939  } else if (op_name.equals_insensitive("BGEZALC")) {
1940  if (rs_val >= 0)
1941  target = pc + offset;
1942  else
1943  target = pc + 4;
1944  } else if (op_name.equals_insensitive("BLTZALC")) {
1945  if (rs_val < 0)
1946  target = pc + offset;
1947  else
1948  target = pc + 4;
1949  } else if (op_name.equals_insensitive("BGTZALC")) {
1950  if (rs_val > 0)
1951  target = pc + offset;
1952  else
1953  target = pc + 4;
1954  } else if (op_name.equals_insensitive("BEQZALC")) {
1955  if (rs_val == 0)
1956  target = pc + offset;
1957  else
1958  target = pc + 4;
1959  } else if (op_name.equals_insensitive("BNEZALC")) {
1960  if (rs_val != 0)
1961  target = pc + offset;
1962  else
1963  target = pc + 4;
1964  }
1965 
1966  Context context;
1967 
1968  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
1969  target))
1970  return false;
1971 
1972  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
1973  pc + 4))
1974  return false;
1975 
1976  return true;
1977 }
1978 
1979 /*
1980  Emulate below MIPS Non-Compact conditional branch and link instructions.
1981  BLTZAL, BGEZAL :
1982  BLTZALL, BGEZALL : Branch likely
1983 */
1984 bool EmulateInstructionMIPS::Emulate_Bcond_Link(llvm::MCInst &insn) {
1985  bool success = false;
1986  uint32_t rs;
1987  int32_t offset, pc, target = 0;
1988  int32_t rs_val;
1989  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1990 
1991  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1992  offset = insn.getOperand(1).getImm();
1993 
1994  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
1995  if (!success)
1996  return false;
1997 
1998  rs_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1999  dwarf_zero_mips + rs, 0, &success);
2000  if (!success)
2001  return false;
2002 
2003  if (op_name.equals_insensitive("BLTZAL") ||
2004  op_name.equals_insensitive("BLTZALL")) {
2005  if ((int32_t)rs_val < 0)
2006  target = pc + offset;
2007  else
2008  target = pc + 8;
2009  } else if (op_name.equals_insensitive("BGEZAL") ||
2010  op_name.equals_insensitive("BGEZALL")) {
2011  if ((int32_t)rs_val >= 0)
2012  target = pc + offset;
2013  else
2014  target = pc + 8;
2015  }
2016 
2017  Context context;
2018 
2019  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2020  target))
2021  return false;
2022 
2023  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
2024  pc + 8))
2025  return false;
2026 
2027  return true;
2028 }
2029 
2030 /*
2031  Emulate below MIPS branch instructions.
2032  BLTZL, BGEZL, BGTZL, BLEZL : Branch likely
2033  BLTZ, BGEZ, BGTZ, BLEZ : Non-compact branches
2034 */
2035 bool EmulateInstructionMIPS::Emulate_BXX_2ops(llvm::MCInst &insn) {
2036  bool success = false;
2037  uint32_t rs;
2038  int32_t offset, pc, target = 0;
2039  int32_t rs_val;
2040  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
2041 
2042  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2043  offset = insn.getOperand(1).getImm();
2044 
2045  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2046  if (!success)
2047  return false;
2048 
2049  rs_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
2050  dwarf_zero_mips + rs, 0, &success);
2051  if (!success)
2052  return false;
2053 
2054  if (op_name.equals_insensitive("BLTZL") ||
2055  op_name.equals_insensitive("BLTZ")) {
2056  if (rs_val < 0)
2057  target = pc + offset;
2058  else
2059  target = pc + 8;
2060  } else if (op_name.equals_insensitive("BGEZL") ||
2061  op_name.equals_insensitive("BGEZ")) {
2062  if (rs_val >= 0)
2063  target = pc + offset;
2064  else
2065  target = pc + 8;
2066  } else if (op_name.equals_insensitive("BGTZL") ||
2067  op_name.equals_insensitive("BGTZ")) {
2068  if (rs_val > 0)
2069  target = pc + offset;
2070  else
2071  target = pc + 8;
2072  } else if (op_name.equals_insensitive("BLEZL") ||
2073  op_name.equals_insensitive("BLEZ")) {
2074  if (rs_val <= 0)
2075  target = pc + offset;
2076  else
2077  target = pc + 8;
2078  }
2079 
2080  Context context;
2081  context.type = eContextRelativeBranchImmediate;
2082  context.SetImmediate(offset);
2083 
2084  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2085  target);
2086 }
2087 
2088 /*
2089  Emulate below MIPS branch instructions.
2090  BLTZC, BLEZC, BGEZC, BGTZC, BEQZC, BNEZC : Compact Branches
2091 */
2092 bool EmulateInstructionMIPS::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
2093  bool success = false;
2094  uint32_t rs;
2095  int32_t offset, pc, target = 0;
2096  int32_t rs_val;
2097  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
2098  uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2099 
2100  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2101  offset = insn.getOperand(1).getImm();
2102 
2103  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2104  if (!success)
2105  return false;
2106 
2107  rs_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
2108  dwarf_zero_mips + rs, 0, &success);
2109  if (!success)
2110  return false;
2111 
2112  if (op_name.equals_insensitive("BLTZC")) {
2113  if (rs_val < 0)
2114  target = pc + offset;
2115  else
2116  target = pc + 4;
2117  } else if (op_name.equals_insensitive("BLEZC")) {
2118  if (rs_val <= 0)
2119  target = pc + offset;
2120  else
2121  target = pc + 4;
2122  } else if (op_name.equals_insensitive("BGEZC")) {
2123  if (rs_val >= 0)
2124  target = pc + offset;
2125  else
2126  target = pc + 4;
2127  } else if (op_name.equals_insensitive("BGTZC")) {
2128  if (rs_val > 0)
2129  target = pc + offset;
2130  else
2131  target = pc + 4;
2132  } else if (op_name.equals_insensitive("BEQZC")) {
2133  if (rs_val == 0)
2134  target = pc + offset;
2135  else
2136  target = pc + 4;
2137  } else if (op_name.equals_insensitive("BNEZC")) {
2138  if (rs_val != 0)
2139  target = pc + offset;
2140  else
2141  target = pc + 4;
2142  }
2143 
2144  Context context;
2145  context.type = eContextRelativeBranchImmediate;
2146  context.SetImmediate(current_inst_size + offset);
2147 
2148  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2149  target);
2150 }
2151 
2152 bool EmulateInstructionMIPS::Emulate_B16_MM(llvm::MCInst &insn) {
2153  bool success = false;
2154  int32_t offset, pc, target;
2155  uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2156 
2157  offset = insn.getOperand(0).getImm();
2158 
2159  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2160  if (!success)
2161  return false;
2162 
2163  // unconditional branch
2164  target = pc + offset;
2165 
2166  Context context;
2167  context.type = eContextRelativeBranchImmediate;
2168  context.SetImmediate(current_inst_size + offset);
2169 
2170  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2171  target);
2172 }
2173 
2174 /*
2175  BEQZC, BNEZC are 32 bit compact instructions without a delay slot.
2176  BEQZ16, BNEZ16 are 16 bit instructions with delay slot.
2177  BGEZALS, BLTZALS are 16 bit instructions with short (2-byte) delay slot.
2178 */
2179 bool EmulateInstructionMIPS::Emulate_Branch_MM(llvm::MCInst &insn) {
2180  bool success = false;
2181  int32_t target = 0;
2182  uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2183  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
2184  bool update_ra = false;
2185  uint32_t ra_offset = 0;
2186 
2187  /*
2188  * BEQZ16 rs, offset
2189  * condition <- (GPR[rs] = 0)
2190  * if condition then
2191  * PC = PC + sign_ext (offset || 0)
2192  *
2193  * BNEZ16 rs, offset
2194  * condition <- (GPR[rs] != 0)
2195  * if condition then
2196  * PC = PC + sign_ext (offset || 0)
2197  *
2198  * BEQZC rs, offset (compact instruction: No delay slot)
2199  * condition <- (GPR[rs] == 0)
2200  * if condition then
2201  * PC = PC + 4 + sign_ext (offset || 0)
2202  */
2203 
2204  uint32_t rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2205  int32_t offset = insn.getOperand(1).getImm();
2206 
2207  int32_t pc =
2208  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2209  if (!success)
2210  return false;
2211 
2212  int32_t rs_val = (int32_t)ReadRegisterUnsigned(
2213  eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success);
2214  if (!success)
2215  return false;
2216 
2217  if (op_name.equals_insensitive("BEQZ16_MM")) {
2218  if (rs_val == 0)
2219  target = pc + offset;
2220  else
2221  target = pc + current_inst_size +
2222  m_next_inst_size; // Skip delay slot instruction.
2223  } else if (op_name.equals_insensitive("BNEZ16_MM")) {
2224  if (rs_val != 0)
2225  target = pc + offset;
2226  else
2227  target = pc + current_inst_size +
2228  m_next_inst_size; // Skip delay slot instruction.
2229  } else if (op_name.equals_insensitive("BEQZC_MM")) {
2230  if (rs_val == 0)
2231  target = pc + 4 + offset;
2232  else
2233  target =
2234  pc +
2235  4; // 32 bit instruction and does not have delay slot instruction.
2236  } else if (op_name.equals_insensitive("BNEZC_MM")) {
2237  if (rs_val != 0)
2238  target = pc + 4 + offset;
2239  else
2240  target =
2241  pc +
2242  4; // 32 bit instruction and does not have delay slot instruction.
2243  } else if (op_name.equals_insensitive("BGEZALS_MM")) {
2244  if (rs_val >= 0)
2245  target = pc + offset;
2246  else
2247  target = pc + 6; // 32 bit instruction with short (2-byte) delay slot
2248 
2249  update_ra = true;
2250  ra_offset = 6;
2251  } else if (op_name.equals_insensitive("BLTZALS_MM")) {
2252  if (rs_val >= 0)
2253  target = pc + offset;
2254  else
2255  target = pc + 6; // 32 bit instruction with short (2-byte) delay slot
2256 
2257  update_ra = true;
2258  ra_offset = 6;
2259  }
2260 
2261  Context context;
2262  context.type = eContextRelativeBranchImmediate;
2263  context.SetImmediate(current_inst_size + offset);
2264 
2265  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2266  target))
2267  return false;
2268 
2269  if (update_ra) {
2270  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
2271  pc + ra_offset))
2272  return false;
2273  }
2274  return true;
2275 }
2276 
2277 /* Emulate micromips jump instructions.
2278  JALR16,JALRS16
2279 */
2280 bool EmulateInstructionMIPS::Emulate_JALRx16_MM(llvm::MCInst &insn) {
2281  bool success = false;
2282  uint32_t ra_offset = 0;
2283  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
2284 
2285  uint32_t rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2286 
2287  uint32_t pc =
2288  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2289  if (!success)
2290  return false;
2291 
2292  uint32_t rs_val = ReadRegisterUnsigned(eRegisterKindDWARF,
2293  dwarf_zero_mips + rs, 0, &success);
2294  if (!success)
2295  return false;
2296 
2297  if (op_name.equals_insensitive("JALR16_MM"))
2298  ra_offset = 6; // 2-byte instruction with 4-byte delay slot.
2299  else if (op_name.equals_insensitive("JALRS16_MM"))
2300  ra_offset = 4; // 2-byte instruction with 2-byte delay slot.
2301 
2302  Context context;
2303 
2304  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2305  rs_val))
2306  return false;
2307 
2308  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
2309  pc + ra_offset))
2310  return false;
2311 
2312  return true;
2313 }
2314 
2315 /* Emulate JALS and JALX instructions.
2316  JALS 32 bit instruction with short (2-byte) delay slot.
2317  JALX 32 bit instruction with 4-byte delay slot.
2318 */
2319 bool EmulateInstructionMIPS::Emulate_JALx(llvm::MCInst &insn) {
2320  bool success = false;
2321  uint32_t offset = 0, target = 0, pc = 0, ra_offset = 0;
2322  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
2323 
2324  /*
2325  * JALS target
2326  * RA = PC + 6
2327  * offset = sign_ext (offset << 1)
2328  * PC = PC[31-27] | offset
2329  * JALX target
2330  * RA = PC + 8
2331  * offset = sign_ext (offset << 2)
2332  * PC = PC[31-28] | offset
2333  */
2334  offset = insn.getOperand(0).getImm();
2335 
2336  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2337  if (!success)
2338  return false;
2339 
2340  // These are PC-region branches and not PC-relative.
2341  if (op_name.equals_insensitive("JALS_MM")) {
2342  // target address is in the “current” 128 MB-aligned region
2343  target = (pc & 0xF8000000UL) | offset;
2344  ra_offset = 6;
2345  } else if (op_name.equals_insensitive("JALX_MM")) {
2346  // target address is in the “current” 256 MB-aligned region
2347  target = (pc & 0xF0000000UL) | offset;
2348  ra_offset = 8;
2349  }
2350 
2351  Context context;
2352 
2353  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2354  target))
2355  return false;
2356 
2357  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
2358  pc + ra_offset))
2359  return false;
2360 
2361  return true;
2362 }
2363 
2364 bool EmulateInstructionMIPS::Emulate_JALRS(llvm::MCInst &insn) {
2365  bool success = false;
2366  uint32_t rs = 0, rt = 0;
2367  int32_t pc = 0, rs_val = 0;
2368 
2369  /*
2370  JALRS rt, rs
2371  GPR[rt] <- PC + 6
2372  PC <- GPR[rs]
2373  */
2374 
2375  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2376  rs = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
2377 
2378  rs_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
2379  dwarf_zero_mips + rs, 0, &success);
2380  if (!success)
2381  return false;
2382 
2383  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2384  if (!success)
2385  return false;
2386 
2387  Context context;
2388 
2389  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2390  rs_val))
2391  return false;
2392 
2393  // This is 4-byte instruction with 2-byte delay slot.
2394  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_zero_mips + rt,
2395  pc + 6))
2396  return false;
2397 
2398  return true;
2399 }
2400 
2401 bool EmulateInstructionMIPS::Emulate_BAL(llvm::MCInst &insn) {
2402  bool success = false;
2403  int32_t offset, pc, target;
2404 
2405  /*
2406  * BAL offset
2407  * offset = sign_ext (offset << 2)
2408  * RA = PC + 8
2409  * PC = PC + offset
2410  */
2411  offset = insn.getOperand(0).getImm();
2412 
2413  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2414  if (!success)
2415  return false;
2416 
2417  target = pc + offset;
2418 
2419  Context context;
2420 
2421  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2422  target))
2423  return false;
2424 
2425  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
2426  pc + 8))
2427  return false;
2428 
2429  return true;
2430 }
2431 
2432 bool EmulateInstructionMIPS::Emulate_BALC(llvm::MCInst &insn) {
2433  bool success = false;
2434  int32_t offset, pc, target;
2435 
2436  /*
2437  * BALC offset
2438  * offset = sign_ext (offset << 2)
2439  * RA = PC + 4
2440  * PC = PC + 4 + offset
2441  */
2442  offset = insn.getOperand(0).getImm();
2443 
2444  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2445  if (!success)
2446  return false;
2447 
2448  target = pc + offset;
2449 
2450  Context context;
2451 
2452  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2453  target))
2454  return false;
2455 
2456  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
2457  pc + 4))
2458  return false;
2459 
2460  return true;
2461 }
2462 
2463 bool EmulateInstructionMIPS::Emulate_BC(llvm::MCInst &insn) {
2464  bool success = false;
2465  int32_t offset, pc, target;
2466 
2467  /*
2468  * BC offset
2469  * offset = sign_ext (offset << 2)
2470  * PC = PC + 4 + offset
2471  */
2472  offset = insn.getOperand(0).getImm();
2473 
2474  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2475  if (!success)
2476  return false;
2477 
2478  target = pc + offset;
2479 
2480  Context context;
2481 
2482  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2483  target);
2484 }
2485 
2486 bool EmulateInstructionMIPS::Emulate_J(llvm::MCInst &insn) {
2487  bool success = false;
2488  uint32_t offset, pc;
2489 
2490  /*
2491  * J offset
2492  * offset = sign_ext (offset << 2)
2493  * PC = PC[63-28] | offset
2494  */
2495  offset = insn.getOperand(0).getImm();
2496 
2497  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2498  if (!success)
2499  return false;
2500 
2501  /* This is a PC-region branch and not PC-relative */
2502  pc = (pc & 0xF0000000UL) | offset;
2503 
2504  Context context;
2505 
2506  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips, pc);
2507 }
2508 
2509 bool EmulateInstructionMIPS::Emulate_JAL(llvm::MCInst &insn) {
2510  bool success = false;
2511  uint32_t offset, target, pc;
2512 
2513  /*
2514  * JAL offset
2515  * offset = sign_ext (offset << 2)
2516  * PC = PC[63-28] | offset
2517  */
2518  offset = insn.getOperand(0).getImm();
2519 
2520  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2521  if (!success)
2522  return false;
2523 
2524  /* This is a PC-region branch and not PC-relative */
2525  target = (pc & 0xF0000000UL) | offset;
2526 
2527  Context context;
2528 
2529  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2530  target))
2531  return false;
2532 
2533  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
2534  pc + 8))
2535  return false;
2536 
2537  return true;
2538 }
2539 
2540 bool EmulateInstructionMIPS::Emulate_JALR(llvm::MCInst &insn) {
2541  bool success = false;
2542  uint32_t rs, rt;
2543  uint32_t pc, rs_val;
2544 
2545  /*
2546  * JALR rt, rs
2547  * GPR[rt] = PC + 8
2548  * PC = GPR[rs]
2549  */
2550  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2551  rs = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
2552 
2553  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2554  if (!success)
2555  return false;
2556 
2557  rs_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + rs, 0,
2558  &success);
2559  if (!success)
2560  return false;
2561 
2562  Context context;
2563 
2564  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2565  rs_val))
2566  return false;
2567 
2568  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_zero_mips + rt,
2569  pc + 8))
2570  return false;
2571 
2572  return true;
2573 }
2574 
2575 bool EmulateInstructionMIPS::Emulate_JIALC(llvm::MCInst &insn) {
2576  bool success = false;
2577  uint32_t rt;
2578  int32_t target, offset, pc, rt_val;
2579 
2580  /*
2581  * JIALC rt, offset
2582  * offset = sign_ext (offset)
2583  * PC = GPR[rt] + offset
2584  * RA = PC + 4
2585  */
2586  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2587  offset = insn.getOperand(1).getImm();
2588 
2589  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2590  if (!success)
2591  return false;
2592 
2593  rt_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
2594  dwarf_zero_mips + rt, 0, &success);
2595  if (!success)
2596  return false;
2597 
2598  target = rt_val + offset;
2599 
2600  Context context;
2601 
2602  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2603  target))
2604  return false;
2605 
2606  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips,
2607  pc + 4))
2608  return false;
2609 
2610  return true;
2611 }
2612 
2613 bool EmulateInstructionMIPS::Emulate_JIC(llvm::MCInst &insn) {
2614  bool success = false;
2615  uint32_t rt;
2616  int32_t target, offset, rt_val;
2617 
2618  /*
2619  * JIC rt, offset
2620  * offset = sign_ext (offset)
2621  * PC = GPR[rt] + offset
2622  */
2623  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2624  offset = insn.getOperand(1).getImm();
2625 
2626  rt_val = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
2627  dwarf_zero_mips + rt, 0, &success);
2628  if (!success)
2629  return false;
2630 
2631  target = rt_val + offset;
2632 
2633  Context context;
2634 
2635  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2636  target);
2637 }
2638 
2639 bool EmulateInstructionMIPS::Emulate_JR(llvm::MCInst &insn) {
2640  bool success = false;
2641  uint32_t rs;
2642  uint32_t rs_val;
2643 
2644  /*
2645  * JR rs
2646  * PC = GPR[rs]
2647  */
2648  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2649 
2650  rs_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + rs, 0,
2651  &success);
2652  if (!success)
2653  return false;
2654 
2655  Context context;
2656 
2657  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2658  rs_val);
2659 }
2660 
2661 /*
2662  Emulate Branch on FP True/False
2663  BC1F, BC1FL : Branch on FP False (L stands for branch likely)
2664  BC1T, BC1TL : Branch on FP True (L stands for branch likely)
2665 */
2666 bool EmulateInstructionMIPS::Emulate_FP_branch(llvm::MCInst &insn) {
2667  bool success = false;
2668  uint32_t cc, fcsr;
2669  int32_t pc, offset, target = 0;
2670  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
2671 
2672  cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2673  offset = insn.getOperand(1).getImm();
2674 
2675  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2676  if (!success)
2677  return false;
2678 
2679  fcsr = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success);
2680  if (!success)
2681  return false;
2682 
2683  /* fcsr[23], fcsr[25-31] are vaild condition bits */
2684  fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
2685 
2686  if (op_name.equals_insensitive("BC1F") ||
2687  op_name.equals_insensitive("BC1FL")) {
2688  if ((fcsr & (1 << cc)) == 0)
2689  target = pc + offset;
2690  else
2691  target = pc + 8;
2692  } else if (op_name.equals_insensitive("BC1T") ||
2693  op_name.equals_insensitive("BC1TL")) {
2694  if ((fcsr & (1 << cc)) != 0)
2695  target = pc + offset;
2696  else
2697  target = pc + 8;
2698  }
2699  Context context;
2700 
2701  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2702  target);
2703 }
2704 
2705 bool EmulateInstructionMIPS::Emulate_BC1EQZ(llvm::MCInst &insn) {
2706  bool success = false;
2707  uint32_t ft;
2708  uint32_t ft_val;
2709  int32_t target, pc, offset;
2710 
2711  /*
2712  * BC1EQZ ft, offset
2713  * condition <- (FPR[ft].bit0 == 0)
2714  * if condition then
2715  * offset = sign_ext (offset)
2716  * PC = PC + 4 + offset
2717  */
2718  ft = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2719  offset = insn.getOperand(1).getImm();
2720 
2721  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2722  if (!success)
2723  return false;
2724 
2725  ft_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + ft, 0,
2726  &success);
2727  if (!success)
2728  return false;
2729 
2730  if ((ft_val & 1) == 0)
2731  target = pc + 4 + offset;
2732  else
2733  target = pc + 8;
2734 
2735  Context context;
2736 
2737  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2738  target);
2739 }
2740 
2741 bool EmulateInstructionMIPS::Emulate_BC1NEZ(llvm::MCInst &insn) {
2742  bool success = false;
2743  uint32_t ft;
2744  uint32_t ft_val;
2745  int32_t target, pc, offset;
2746 
2747  /*
2748  * BC1NEZ ft, offset
2749  * condition <- (FPR[ft].bit0 != 0)
2750  * if condition then
2751  * offset = sign_ext (offset)
2752  * PC = PC + 4 + offset
2753  */
2754  ft = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2755  offset = insn.getOperand(1).getImm();
2756 
2757  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2758  if (!success)
2759  return false;
2760 
2761  ft_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + ft, 0,
2762  &success);
2763  if (!success)
2764  return false;
2765 
2766  if ((ft_val & 1) != 0)
2767  target = pc + 4 + offset;
2768  else
2769  target = pc + 8;
2770 
2771  Context context;
2772 
2773  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2774  target);
2775 }
2776 
2777 /*
2778  Emulate MIPS-3D Branch instructions
2779  BC1ANY2F, BC1ANY2T : Branch on Any of Two Floating Point Condition Codes
2780  False/True
2781  BC1ANY4F, BC1ANY4T : Branch on Any of Four Floating Point Condition Codes
2782  False/True
2783 */
2784 bool EmulateInstructionMIPS::Emulate_3D_branch(llvm::MCInst &insn) {
2785  bool success = false;
2786  uint32_t cc, fcsr;
2787  int32_t pc, offset, target = 0;
2788  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
2789 
2790  cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2791  offset = insn.getOperand(1).getImm();
2792 
2793  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2794  if (!success)
2795  return false;
2796 
2797  fcsr = (uint32_t)ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips, 0,
2798  &success);
2799  if (!success)
2800  return false;
2801 
2802  /* fcsr[23], fcsr[25-31] are vaild condition bits */
2803  fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
2804 
2805  if (op_name.equals_insensitive("BC1ANY2F")) {
2806  /* if any one bit is 0 */
2807  if (((fcsr >> cc) & 3) != 3)
2808  target = pc + offset;
2809  else
2810  target = pc + 8;
2811  } else if (op_name.equals_insensitive("BC1ANY2T")) {
2812  /* if any one bit is 1 */
2813  if (((fcsr >> cc) & 3) != 0)
2814  target = pc + offset;
2815  else
2816  target = pc + 8;
2817  } else if (op_name.equals_insensitive("BC1ANY4F")) {
2818  /* if any one bit is 0 */
2819  if (((fcsr >> cc) & 0xf) != 0xf)
2820  target = pc + offset;
2821  else
2822  target = pc + 8;
2823  } else if (op_name.equals_insensitive("BC1ANY4T")) {
2824  /* if any one bit is 1 */
2825  if (((fcsr >> cc) & 0xf) != 0)
2826  target = pc + offset;
2827  else
2828  target = pc + 8;
2829  }
2830  Context context;
2831 
2832  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2833  target);
2834 }
2835 
2836 bool EmulateInstructionMIPS::Emulate_BNZB(llvm::MCInst &insn) {
2837  return Emulate_MSA_Branch_DF(insn, 1, true);
2838 }
2839 
2840 bool EmulateInstructionMIPS::Emulate_BNZH(llvm::MCInst &insn) {
2841  return Emulate_MSA_Branch_DF(insn, 2, true);
2842 }
2843 
2844 bool EmulateInstructionMIPS::Emulate_BNZW(llvm::MCInst &insn) {
2845  return Emulate_MSA_Branch_DF(insn, 4, true);
2846 }
2847 
2848 bool EmulateInstructionMIPS::Emulate_BNZD(llvm::MCInst &insn) {
2849  return Emulate_MSA_Branch_DF(insn, 8, true);
2850 }
2851 
2852 bool EmulateInstructionMIPS::Emulate_BZB(llvm::MCInst &insn) {
2853  return Emulate_MSA_Branch_DF(insn, 1, false);
2854 }
2855 
2856 bool EmulateInstructionMIPS::Emulate_BZH(llvm::MCInst &insn) {
2857  return Emulate_MSA_Branch_DF(insn, 2, false);
2858 }
2859 
2860 bool EmulateInstructionMIPS::Emulate_BZW(llvm::MCInst &insn) {
2861  return Emulate_MSA_Branch_DF(insn, 4, false);
2862 }
2863 
2864 bool EmulateInstructionMIPS::Emulate_BZD(llvm::MCInst &insn) {
2865  return Emulate_MSA_Branch_DF(insn, 8, false);
2866 }
2867 
2868 bool EmulateInstructionMIPS::Emulate_MSA_Branch_DF(llvm::MCInst &insn,
2869  int element_byte_size,
2870  bool bnz) {
2871  bool success = false, branch_hit = true;
2872  int32_t target = 0;
2873  RegisterValue reg_value;
2874  const uint8_t *ptr = nullptr;
2875 
2876  uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2877  int32_t offset = insn.getOperand(1).getImm();
2878 
2879  int32_t pc =
2880  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2881  if (!success)
2882  return false;
2883 
2884  if (ReadRegister(eRegisterKindDWARF, dwarf_w0_mips + wt, reg_value))
2885  ptr = (const uint8_t *)reg_value.GetBytes();
2886  else
2887  return false;
2888 
2889  for (int i = 0; i < 16 / element_byte_size; i++) {
2890  switch (element_byte_size) {
2891  case 1:
2892  if ((*ptr == 0 && bnz) || (*ptr != 0 && !bnz))
2893  branch_hit = false;
2894  break;
2895  case 2:
2896  if ((*(const uint16_t *)ptr == 0 && bnz) ||
2897  (*(const uint16_t *)ptr != 0 && !bnz))
2898  branch_hit = false;
2899  break;
2900  case 4:
2901  if ((*(const uint32_t *)ptr == 0 && bnz) ||
2902  (*(const uint32_t *)ptr != 0 && !bnz))
2903  branch_hit = false;
2904  break;
2905  case 8:
2906  if ((*(const uint64_t *)ptr == 0 && bnz) ||
2907  (*(const uint64_t *)ptr != 0 && !bnz))
2908  branch_hit = false;
2909  break;
2910  }
2911  if (!branch_hit)
2912  break;
2913  ptr = ptr + element_byte_size;
2914  }
2915 
2916  if (branch_hit)
2917  target = pc + offset;
2918  else
2919  target = pc + 8;
2920 
2921  Context context;
2922  context.type = eContextRelativeBranchImmediate;
2923 
2924  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2925  target);
2926 }
2927 
2928 bool EmulateInstructionMIPS::Emulate_BNZV(llvm::MCInst &insn) {
2929  return Emulate_MSA_Branch_V(insn, true);
2930 }
2931 
2932 bool EmulateInstructionMIPS::Emulate_BZV(llvm::MCInst &insn) {
2933  return Emulate_MSA_Branch_V(insn, false);
2934 }
2935 
2936 bool EmulateInstructionMIPS::Emulate_MSA_Branch_V(llvm::MCInst &insn,
2937  bool bnz) {
2938  bool success = false;
2939  int32_t target = 0;
2940  llvm::APInt wr_val = llvm::APInt::getZero(128);
2941  llvm::APInt fail_value = llvm::APInt::getMaxValue(128);
2942  llvm::APInt zero_value = llvm::APInt::getZero(128);
2943  RegisterValue reg_value;
2944 
2945  uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2946  int32_t offset = insn.getOperand(1).getImm();
2947 
2948  int32_t pc =
2949  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
2950  if (!success)
2951  return false;
2952 
2953  if (ReadRegister(eRegisterKindDWARF, dwarf_w0_mips + wt, reg_value))
2954  wr_val = reg_value.GetAsUInt128(fail_value);
2955  else
2956  return false;
2957 
2958  if ((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) ||
2959  (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz))
2960  target = pc + offset;
2961  else
2962  target = pc + 8;
2963 
2964  Context context;
2965  context.type = eContextRelativeBranchImmediate;
2966 
2967  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
2968  target);
2969 }
2970 
2971 bool EmulateInstructionMIPS::Emulate_LDST_Imm(llvm::MCInst &insn) {
2972  bool success = false;
2973  uint32_t base;
2974  int32_t imm, address;
2975  Context bad_vaddr_context;
2976 
2977  uint32_t num_operands = insn.getNumOperands();
2978  base =
2979  m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
2980  imm = insn.getOperand(num_operands - 1).getImm();
2981 
2982  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
2983  return false;
2984 
2985  /* read base register */
2986  address = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
2987  dwarf_zero_mips + base, 0, &success);
2988  if (!success)
2989  return false;
2990 
2991  /* destination address */
2992  address = address + imm;
2993 
2994  /* Set the bad_vaddr register with base address used in the instruction */
2995  bad_vaddr_context.type = eContextInvalid;
2996  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
2997  address);
2998 
2999  return true;
3000 }
3001 
3002 bool EmulateInstructionMIPS::Emulate_LDST_Reg(llvm::MCInst &insn) {
3003  bool success = false;
3004  uint32_t base, index;
3005  int32_t address, index_address;
3006  Context bad_vaddr_context;
3007 
3008  uint32_t num_operands = insn.getNumOperands();
3009  base =
3010  m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
3011  index =
3012  m_reg_info->getEncodingValue(insn.getOperand(num_operands - 1).getReg());
3013 
3014  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
3015  return false;
3016 
3017  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + index))
3018  return false;
3019 
3020  /* read base register */
3021  address = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
3022  dwarf_zero_mips + base, 0, &success);
3023  if (!success)
3024  return false;
3025 
3026  /* read index register */
3027  index_address = (int32_t)ReadRegisterUnsigned(
3028  eRegisterKindDWARF, dwarf_zero_mips + index, 0, &success);
3029  if (!success)
3030  return false;
3031 
3032  /* destination address */
3033  address = address + index_address;
3034 
3035  /* Set the bad_vaddr register with base address used in the instruction */
3036  bad_vaddr_context.type = eContextInvalid;
3037  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
3038  address);
3039 
3040  return true;
3041 }
EmulateInstructionMIPS::Emulate_ADDiu
bool Emulate_ADDiu(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1172
EmulateInstructionMIPS::Emulate_BZV
bool Emulate_BZV(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2932
EmulateInstructionMIPS::Emulate_JR
bool Emulate_JR(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2639
EmulateInstructionMIPS::nonvolatile_reg_p
bool nonvolatile_reg_p(uint32_t regnum)
Definition: EmulateInstructionMIPS.cpp:1151
dwarf_f12_mips
@ dwarf_f12_mips
Definition: RegisterContext_mips.h:70
EmulateInstructionMIPS::Emulate_BALC
bool Emulate_BALC(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2432
lldb_private::UnwindPlan::AppendRow
void AppendRow(const RowSP &row_sp)
Definition: UnwindPlan.cpp:362
IsAdd64bitOverflow
static int IsAdd64bitOverflow(int32_t a, int32_t b)
Definition: EmulateInstructionMIPS.cpp:1776
dwarf_f9_mips
@ dwarf_f9_mips
Definition: RegisterContext_mips.h:67
EmulateInstructionMIPS::Emulate_J
bool Emulate_J(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2486
lldb_private::ArchSpec
Definition: ArchSpec.h:32
EmulateInstructionMIPS::m_insn_info
std::unique_ptr< llvm::MCInstrInfo > m_insn_info
Definition: EmulateInstructionMIPS.h:214
EmulateInstructionMIPS::SetTargetTriple
bool SetTargetTriple(const lldb_private::ArchSpec &arch) override
Definition: EmulateInstructionMIPS.cpp:214
dwarf_f27_mips
@ dwarf_f27_mips
Definition: RegisterContext_mips.h:85
dwarf_f26_mips
@ dwarf_f26_mips
Definition: RegisterContext_mips.h:84
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:79
dwarf_w8_mips
@ dwarf_w8_mips
Definition: RegisterContext_mips.h:100
lldb_private::Opcode
Definition: Opcode.h:29
EmulateInstructionMIPS::Emulate_BC1EQZ
bool Emulate_BC1EQZ(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2705
dwarf_w12_mips
@ dwarf_w12_mips
Definition: RegisterContext_mips.h:104
lldb_private::RegisterValue
Definition: RegisterValue.h:28
dwarf_f0_mips
@ dwarf_f0_mips
Definition: RegisterContext_mips.h:58
EmulateInstructionMIPS::EvaluateInstruction
bool EvaluateInstruction(uint32_t evaluate_options) override
Definition: EmulateInstructionMIPS.cpp:1050
lldb_private::UnwindPlan::SetRegisterKind
void SetRegisterKind(lldb::RegisterKind kind)
Definition: UnwindPlan.h:437
lldb_private::SignedBits
static int64_t SignedBits(const uint64_t value, const uint64_t msbit, const uint64_t lsbit)
Definition: InstructionUtils.h:104
lldb::eRegisterKindDWARF
@ eRegisterKindDWARF
the register numbers seen DWARF
Definition: lldb-enumerations.h:230
EmulateInstructionMIPS::GetSizeOfInstruction
uint32_t GetSizeOfInstruction(lldb_private::DataExtractor &data, uint64_t inst_addr)
Definition: EmulateInstructionMIPS.cpp:966
Opcode.h
EmulateInstructionMIPS::EmulateInstructionMIPS
EmulateInstructionMIPS(const lldb_private::ArchSpec &arch)
Definition: EmulateInstructionMIPS.cpp:62
lldb_private::EmulateInstruction::GetAddressByteSize
uint32_t GetAddressByteSize() const
Definition: EmulateInstruction.h:431
EmulateInstructionMIPS::m_next_inst_size
uint32_t m_next_inst_size
Definition: EmulateInstructionMIPS.h:215
lldb::eRegisterKindGeneric
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target
Definition: lldb-enumerations.h:231
dwarf_r8_mips
@ dwarf_r8_mips
Definition: RegisterContext_mips.h:28
dwarf_w6_mips
@ dwarf_w6_mips
Definition: RegisterContext_mips.h:98
dwarf_f11_mips
@ dwarf_f11_mips
Definition: RegisterContext_mips.h:69
dwarf_w20_mips
@ dwarf_w20_mips
Definition: RegisterContext_mips.h:112
lldb_private::ArchSpec::GetCore
Core GetCore() const
Definition: ArchSpec.h:442
dwarf_r21_mips
@ dwarf_r21_mips
Definition: RegisterContext_mips.h:41
dwarf_r11_mips
@ dwarf_r11_mips
Definition: RegisterContext_mips.h:31
lldb_private::UnwindPlan::SetUnwindPlanValidAtAllInstructions
void SetUnwindPlanValidAtAllInstructions(lldb_private::LazyBool valid_at_all_insn)
Definition: UnwindPlan.h:490
EmulateInstructionMIPS::Initialize
static void Initialize()
Definition: EmulateInstructionMIPS.cpp:187
dwarf_f18_mips
@ dwarf_f18_mips
Definition: RegisterContext_mips.h:76
dwarf_lo_mips
@ dwarf_lo_mips
Definition: RegisterContext_mips.h:53
lldb_private::eLazyBoolYes
@ eLazyBoolYes
Definition: lldb-private-enumerations.h:115
dwarf_f1_mips
@ dwarf_f1_mips
Definition: RegisterContext_mips.h:59
lldb_private::EmulateInstruction::Context
Definition: EmulateInstruction.h:184
dwarf_r12_mips
@ dwarf_r12_mips
Definition: RegisterContext_mips.h:32
EmulateInstructionMIPS::Emulate_MSA_Branch_V
bool Emulate_MSA_Branch_V(llvm::MCInst &insn, bool bnz)
Definition: EmulateInstructionMIPS.cpp:2936
dwarf_f14_mips
@ dwarf_f14_mips
Definition: RegisterContext_mips.h:72
EmulateInstructionMIPS::SupportsEmulatingInstructionsOfTypeStatic
static bool SupportsEmulatingInstructionsOfTypeStatic(lldb_private::InstructionType inst_type)
Definition: EmulateInstructionMIPS.h:44
lldb_private::RegisterValue::GetAsUInt128
llvm::APInt GetAsUInt128(const llvm::APInt &fail_value, bool *success_ptr=nullptr) const
Definition: RegisterValue.cpp:591
EmulateInstructionMIPS::Emulate_LDST_Imm
bool Emulate_LDST_Imm(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2971
dwarf_f4_mips
@ dwarf_f4_mips
Definition: RegisterContext_mips.h:62
lldb_private::ArchSpec::GetFlags
uint32_t GetFlags() const
Definition: ArchSpec.h:539
EmulateInstructionMIPS::Emulate_ADDIUS5
bool Emulate_ADDIUS5(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1453
dwarf_r20_mips
@ dwarf_r20_mips
Definition: RegisterContext_mips.h:40
lldb_private::UnwindPlan::SetUnwindPlanForSignalTrap
void SetUnwindPlanForSignalTrap(lldb_private::LazyBool is_for_signal_trap)
Definition: UnwindPlan.h:502
EmulateInstructionMIPS::ReadInstruction
bool ReadInstruction() override
Definition: EmulateInstructionMIPS.cpp:1033
RegisterValue.h
EmulateInstructionMIPS::Emulate_BZD
bool Emulate_BZD(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2864
dwarf_w31_mips
@ dwarf_w31_mips
Definition: RegisterContext_mips.h:123
dwarf_w30_mips
@ dwarf_w30_mips
Definition: RegisterContext_mips.h:122
lldb_private::ArchSpec::GetTriple
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:463
lldb::addr_t
uint64_t addr_t
Definition: lldb-types.h:83
pc
@ pc
Definition: CompactUnwindInfo.cpp:1251
dwarf_r22_mips
@ dwarf_r22_mips
Definition: RegisterContext_mips.h:42
dwarf_w15_mips
@ dwarf_w15_mips
Definition: RegisterContext_mips.h:107
lldb_private::Opcode::SetOpcode32
void SetOpcode32(uint32_t inst, lldb::ByteOrder order)
Definition: Opcode.h:171
dwarf_f2_mips
@ dwarf_f2_mips
Definition: RegisterContext_mips.h:60
dwarf_r10_mips
@ dwarf_r10_mips
Definition: RegisterContext_mips.h:30
dwarf_w18_mips
@ dwarf_w18_mips
Definition: RegisterContext_mips.h:110
dwarf_r5_mips
@ dwarf_r5_mips
Definition: RegisterContext_mips.h:25
lldb_private::Target
Definition: Target.h:469
lldb_private::UnwindPlan::SetSourceName
void SetSourceName(const char *)
Definition: UnwindPlan.cpp:564
LLDB_PLUGIN_DEFINE_ADV
LLDB_PLUGIN_DEFINE_ADV(ObjectContainerUniversalMachO, ObjectContainerMachOArchive) void ObjectContainerUniversalMachO
Definition: ObjectContainerUniversalMachO.cpp:23
dwarf_w9_mips
@ dwarf_w9_mips
Definition: RegisterContext_mips.h:101
EmulateInstructionMIPS::Emulate_FP_branch
bool Emulate_FP_branch(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2666
EmulateInstructionMIPS::Emulate_JALRx16_MM
bool Emulate_JALRx16_MM(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2280
lldb_private::EmulateInstruction::eContextReadOpcode
@ eContextReadOpcode
Definition: EmulateInstruction.h:102
dwarf_f24_mips
@ dwarf_f24_mips
Definition: RegisterContext_mips.h:82
EmulateInstructionMIPS::Emulate_B16_MM
bool Emulate_B16_MM(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2152
dwarf_w28_mips
@ dwarf_w28_mips
Definition: RegisterContext_mips.h:120
dwarf_f30_mips
@ dwarf_f30_mips
Definition: RegisterContext_mips.h:88
Target.h
EmulateInstructionMIPS::m_context
std::unique_ptr< llvm::MCContext > m_context
Definition: EmulateInstructionMIPS.h:213
dwarf_w25_mips
@ dwarf_w25_mips
Definition: RegisterContext_mips.h:117
EmulateInstructionMIPS::m_disasm
std::unique_ptr< llvm::MCDisassembler > m_disasm
Definition: EmulateInstructionMIPS.h:207
dwarf_r16_mips
@ dwarf_r16_mips
Definition: RegisterContext_mips.h:36
LLDB_REGNUM_GENERIC_FLAGS
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:55
RegisterContext_mips.h
error
static llvm::raw_ostream & error(Stream &strm)
Definition: CommandReturnObject.cpp:17
dwarf_w4_mips
@ dwarf_w4_mips
Definition: RegisterContext_mips.h:96
EmulateInstructionMIPS::Emulate_BNZH
bool Emulate_BNZH(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2840
dwarf_r14_mips
@ dwarf_r14_mips
Definition: RegisterContext_mips.h:34
lldb_private::EmulateInstruction::GetByteOrder
lldb::ByteOrder GetByteOrder() const
Definition: EmulateInstruction.h:433
EmulateInstructionMIPS::Emulate_SUBU_ADDU
bool Emulate_SUBU_ADDU(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1330
EmulateInstructionMIPS::Emulate_LDST_Reg
bool Emulate_LDST_Reg(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:3002
EmulateInstructionMIPS::Emulate_BXX_3ops
bool Emulate_BXX_3ops(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1786
lldb_private::EmulateInstruction::eContextImmediate
@ eContextImmediate
Definition: EmulateInstruction.h:106
dwarf_bad_mips
@ dwarf_bad_mips
Definition: RegisterContext_mips.h:55
dwarf_r24_mips
@ dwarf_r24_mips
Definition: RegisterContext_mips.h:44
dwarf_f6_mips
@ dwarf_f6_mips
Definition: RegisterContext_mips.h:64
dwarf_f10_mips
@ dwarf_f10_mips
Definition: RegisterContext_mips.h:68
dwarf_f7_mips
@ dwarf_f7_mips
Definition: RegisterContext_mips.h:65
EmulateInstructionMIPS::Emulate_BXX_3ops_C
bool Emulate_BXX_3ops_C(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1836
lldb_private::Address::GetAddressClass
AddressClass GetAddressClass() const
Definition: Address.cpp:1026
lldb_private::DataExtractor
Definition: DataExtractor.h:48
EmulateInstructionMIPS::Emulate_LUI
bool Emulate_LUI(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1409
dwarf_r6_mips
@ dwarf_r6_mips
Definition: RegisterContext_mips.h:26
lldb_private::UnwindPlan::SetReturnAddressRegister
void SetReturnAddressRegister(uint32_t regnum)
Definition: UnwindPlan.h:439
dwarf_ra_mips
@ dwarf_ra_mips
Definition: RegisterContext_mips.h:51
dwarf_w0_mips
@ dwarf_w0_mips
Definition: RegisterContext_mips.h:92
lldb_private::EmulateInstruction::Context::type
ContextType type
Definition: EmulateInstruction.h:185
dwarf_w21_mips
@ dwarf_w21_mips
Definition: RegisterContext_mips.h:113
lldb_private::RegisterValue::GetBytes
const void * GetBytes() const
Definition: RegisterValue.cpp:686
EmulateInstructionMIPS::m_alt_subtype_info
std::unique_ptr< llvm::MCSubtargetInfo > m_alt_subtype_info
Definition: EmulateInstructionMIPS.h:210
EmulateInstructionMIPS::Emulate_Bcond_Link_C
bool Emulate_Bcond_Link_C(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1915
EmulateInstructionMIPS::CreateFunctionEntryUnwind
bool CreateFunctionEntryUnwind(lldb_private::UnwindPlan &unwind_plan) override
Definition: EmulateInstructionMIPS.cpp:1125
EmulateInstructionMIPS::GetRegisterInfo
llvm::Optional< lldb_private::RegisterInfo > GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num) override
Definition: EmulateInstructionMIPS.cpp:589
dwarf_zero_mips
@ dwarf_zero_mips
Definition: RegisterContext_mips.h:20
EmulateInstructionMIPS::Emulate_BZW
bool Emulate_BZW(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2860
EmulateInstructionMIPS::MipsOpcode::callback
bool(EmulateInstructionMIPS::* callback)(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.h:92
dwarf_cause_mips
@ dwarf_cause_mips
Definition: RegisterContext_mips.h:56
EmulateInstructionMIPS::m_subtype_info
std::unique_ptr< llvm::MCSubtargetInfo > m_subtype_info
Definition: EmulateInstructionMIPS.h:209
dwarf_w22_mips
@ dwarf_w22_mips
Definition: RegisterContext_mips.h:114
EmulateInstructionMIPS::Emulate_BZB
bool Emulate_BZB(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2852
dwarf_w5_mips
@ dwarf_w5_mips
Definition: RegisterContext_mips.h:97
dwarf_r19_mips
@ dwarf_r19_mips
Definition: RegisterContext_mips.h:39
dwarf_f5_mips
@ dwarf_f5_mips
Definition: RegisterContext_mips.h:63
lldb_private::DataExtractor::GetDataStart
const uint8_t * GetDataStart() const
Get the data start pointer.
Definition: DataExtractor.h:422
lldb_private::UnwindPlan::SetSourcedFromCompiler
void SetSourcedFromCompiler(lldb_private::LazyBool from_compiler)
Definition: UnwindPlan.h:478
lldb::eEncodingUint
@ eEncodingUint
unsigned integer
Definition: lldb-enumerations.h:149
lldb_private::EmulateInstruction::eContextInvalid
@ eContextInvalid
Definition: EmulateInstruction.h:100
dwarf_r23_mips
@ dwarf_r23_mips
Definition: RegisterContext_mips.h:43
EmulateInstructionMIPS::Emulate_JIALC
bool Emulate_JIALC(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2575
dwarf_f15_mips
@ dwarf_f15_mips
Definition: RegisterContext_mips.h:73
lldb_private::EmulateInstruction::Context::SetRegisterPlusOffset
void SetRegisterPlusOffset(RegisterInfo base_reg, int64_t signed_offset)
Definition: EmulateInstruction.h:249
dwarf_f22_mips
@ dwarf_f22_mips
Definition: RegisterContext_mips.h:80
dwarf_w3_mips
@ dwarf_w3_mips
Definition: RegisterContext_mips.h:95
lldb_private::EmulateInstruction::Context::SetRegisterToRegisterPlusOffset
void SetRegisterToRegisterPlusOffset(RegisterInfo data_reg, RegisterInfo base_reg, int64_t offset)
Definition: EmulateInstruction.h:262
EmulateInstructionMIPS::Emulate_JAL
bool Emulate_JAL(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2509
dwarf_w29_mips
@ dwarf_w29_mips
Definition: RegisterContext_mips.h:121
dwarf_r26_mips
@ dwarf_r26_mips
Definition: RegisterContext_mips.h:46
EmulateInstructionMIPS.h
lldb_private::Opcode::GetData
uint32_t GetData(DataExtractor &data) const
Definition: Opcode.cpp:81
dwarf_w17_mips
@ dwarf_w17_mips
Definition: RegisterContext_mips.h:109
EmulateInstructionMIPS::Emulate_LWM16_32
bool Emulate_LWM16_32(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1676
string
string(SUBSTRING ${p} 10 -1 pStripped) if($
Definition: Plugins/CMakeLists.txt:40
dwarf_r4_mips
@ dwarf_r4_mips
Definition: RegisterContext_mips.h:24
EmulateInstructionMIPS::GetOpcodeForInstruction
static MipsOpcode * GetOpcodeForInstruction(llvm::StringRef name)
Definition: EmulateInstructionMIPS.cpp:672
EmulateInstructionMIPS::Emulate_JRADDIUSP
bool Emulate_JRADDIUSP(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1733
dwarf_sr_mips
@ dwarf_sr_mips
Definition: RegisterContext_mips.h:52
EmulateInstructionMIPS::Emulate_MSA_Branch_DF
bool Emulate_MSA_Branch_DF(llvm::MCInst &insn, int element_byte_size, bool bnz)
Definition: EmulateInstructionMIPS.cpp:2868
EmulateInstructionMIPS::MipsOpcode
Definition: EmulateInstructionMIPS.h:90
EmulateInstructionMIPS::Emulate_BXX_2ops_C
bool Emulate_BXX_2ops_C(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2092
Address.h
EmulateInstructionMIPS::Emulate_SWM16_32
bool Emulate_SWM16_32(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1551
UnwindPlan.h
dwarf_f3_mips
@ dwarf_f3_mips
Definition: RegisterContext_mips.h:61
dwarf_fcsr_mips
@ dwarf_fcsr_mips
Definition: RegisterContext_mips.h:90
EmulateInstructionMIPS::Emulate_BC
bool Emulate_BC(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2463
dwarf_w23_mips
@ dwarf_w23_mips
Definition: RegisterContext_mips.h:115
InstructionUtils.h
EmulateInstructionMIPS::Emulate_Branch_MM
bool Emulate_Branch_MM(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2179
dwarf_r3_mips
@ dwarf_r3_mips
Definition: RegisterContext_mips.h:23
dwarf_f29_mips
@ dwarf_f29_mips
Definition: RegisterContext_mips.h:87
lldb::RegisterKind
RegisterKind
Register numbering types.
Definition: lldb-enumerations.h:228
lldb_private::EmulateInstruction::eContextAdjustStackPointer
@ eContextAdjustStackPointer
Definition: EmulateInstruction.h:117
EmulateInstructionMIPS::Emulate_BZH
bool Emulate_BZH(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2856
EmulateInstructionMIPS::Emulate_BXX_2ops
bool Emulate_BXX_2ops(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2035
dwarf_sp_mips
@ dwarf_sp_mips
Definition: RegisterContext_mips.h:49
EmulateInstructionMIPS::Emulate_JALx
bool Emulate_JALx(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2319
EmulateInstructionMIPS::Terminate
static void Terminate()
Definition: EmulateInstructionMIPS.cpp:192
lldb_private::UnwindPlan::RowSP
std::shared_ptr< Row > RowSP
Definition: UnwindPlan.h:395
EmulateInstructionMIPS::m_alt_disasm
std::unique_ptr< llvm::MCDisassembler > m_alt_disasm
Definition: EmulateInstructionMIPS.h:208
dwarf_r25_mips
@ dwarf_r25_mips
Definition: RegisterContext_mips.h:45
dwarf_f13_mips
@ dwarf_f13_mips
Definition: RegisterContext_mips.h:71
dwarf_r2_mips
@ dwarf_r2_mips
Definition: RegisterContext_mips.h:22
dwarf_w27_mips
@ dwarf_w27_mips
Definition: RegisterContext_mips.h:119
EmulateInstructionMIPS::Emulate_BNZV
bool Emulate_BNZV(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2928
dwarf_f25_mips
@ dwarf_f25_mips
Definition: RegisterContext_mips.h:83
lldb::eEncodingVector
@ eEncodingVector
vector registers
Definition: lldb-enumerations.h:152
dwarf_f28_mips
@ dwarf_f28_mips
Definition: RegisterContext_mips.h:86
dwarf_w19_mips
@ dwarf_w19_mips
Definition: RegisterContext_mips.h:111
lldb_private::UnwindPlan::Clear
void Clear()
Definition: UnwindPlan.h:508
lldb_private::Status
Definition: Status.h:44
EmulateInstructionMIPS::Emulate_BNZB
bool Emulate_BNZB(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2836
dwarf_f8_mips
@ dwarf_f8_mips
Definition: RegisterContext_mips.h:66
lldb_private::EmulateInstruction::ReadRegister
llvm::Optional< RegisterValue > ReadRegister(const RegisterInfo &reg_info)
Definition: EmulateInstruction.cpp:76
dwarf_w1_mips
@ dwarf_w1_mips
Definition: RegisterContext_mips.h:93
dwarf_r9_mips
@ dwarf_r9_mips
Definition: RegisterContext_mips.h:29
lldb_private::Target::ReadMemory
size_t ReadMemory(const Address &addr, void *dst, size_t dst_len, Status &error, bool force_live_memory=false, lldb::addr_t *load_addr_ptr=nullptr)
Definition: Target.cpp:1752
lldb_private::EmulateInstruction::Context::SetNoArgs
void SetNoArgs()
Definition: EmulateInstruction.h:328
EmulateInstructionMIPS::Emulate_LW
bool Emulate_LW(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1286
EmulateInstructionMIPS::Emulate_3D_branch
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Definition: EmulateInstructionMIPS.cpp:2784
dwarf_w14_mips
@ dwarf_w14_mips
Definition: RegisterContext_mips.h:106
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Definition: UnwindPlan.h:55
uint32_t
lldb_private::eLazyBoolNo
@ eLazyBoolNo
Definition: lldb-private-enumerations.h:115
EmulateInstructionMIPS::Emulate_BAL
bool Emulate_BAL(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2401
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Definition: EmulateInstruction.h:93
dwarf_r17_mips
@ dwarf_r17_mips
Definition: RegisterContext_mips.h:37
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static llvm::StringRef GetPluginDescriptionStatic()
Definition: EmulateInstructionMIPS.cpp:196
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Definition: Address.h:59
LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:52
EmulateInstructionMIPS::Emulate_BNZW
bool Emulate_BNZW(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2844
dwarf_r1_mips
@ dwarf_r1_mips
Definition: RegisterContext_mips.h:21
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uint32_t GetByteSize() const
Definition: Opcode.h:202
EmulateInstructionMIPS::SetInstruction
bool SetInstruction(const lldb_private::Opcode &insn_opcode, const lldb_private::Address &inst_addr, lldb_private::Target *target) override
Definition: EmulateInstructionMIPS.cpp:986
ArchSpec.h
dwarf_r7_mips
@ dwarf_r7_mips
Definition: RegisterContext_mips.h:27
dwarf_w10_mips
@ dwarf_w10_mips
Definition: RegisterContext_mips.h:102
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bool WriteMemory(const Context &context, lldb::addr_t addr, const void *src, size_t src_len)
Definition: EmulateInstruction.cpp:211
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bool Emulate_BC1NEZ(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2741
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@ dwarf_fir_mips
Definition: RegisterContext_mips.h:91
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bool Emulate_JIC(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2613
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EmulateInstructionMIPS::Emulate_BNZD
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Definition: EmulateInstructionMIPS.cpp:2848
PluginManager.h
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#define LLDB_INVALID_ADDRESS
Definition: lldb-defines.h:74
EmulateInstructionMIPS::Emulate_SWSP
bool Emulate_SWSP(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1487
DataExtractor.h
lldb_private::InstructionType
InstructionType
Instruction types.
Definition: lldb-private-enumerations.h:118
dwarf_mir_mips
@ dwarf_mir_mips
Definition: RegisterContext_mips.h:125
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Definition: EmulateInstructionMIPS.cpp:2364
dwarf_f23_mips
@ dwarf_f23_mips
Definition: RegisterContext_mips.h:81
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A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
EmulateInstructionMIPS::Emulate_Bcond_Link
bool Emulate_Bcond_Link(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1984
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@ eFormatHex
Definition: lldb-enumerations.h:170
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#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:53
dwarf_w26_mips
@ dwarf_w26_mips
Definition: RegisterContext_mips.h:118
dwarf_gp_mips
@ dwarf_gp_mips
Definition: RegisterContext_mips.h:48
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void SetAddress(lldb::addr_t address)
Definition: EmulateInstruction.h:307
dwarf_f21_mips
@ dwarf_f21_mips
Definition: RegisterContext_mips.h:79
dwarf_w2_mips
@ dwarf_w2_mips
Definition: RegisterContext_mips.h:94
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#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:51
dwarf_r13_mips
@ dwarf_r13_mips
Definition: RegisterContext_mips.h:33
dwarf_mcsr_mips
@ dwarf_mcsr_mips
Definition: RegisterContext_mips.h:124
dwarf_w11_mips
@ dwarf_w11_mips
Definition: RegisterContext_mips.h:103
ConstString.h
EmulateInstructionMIPS::m_asm_info
std::unique_ptr< llvm::MCAsmInfo > m_asm_info
Definition: EmulateInstructionMIPS.h:212
EmulateInstructionMIPS::Emulate_JALR
bool Emulate_JALR(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:2540
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const char * GetRegisterName(unsigned reg_num, bool alternate_name)
Definition: EmulateInstructionMIPS.cpp:219
dwarf_f16_mips
@ dwarf_f16_mips
Definition: RegisterContext_mips.h:74
dwarf_f20_mips
@ dwarf_f20_mips
Definition: RegisterContext_mips.h:78
EmulateInstructionMIPS::CreateInstance
static lldb_private::EmulateInstruction * CreateInstance(const lldb_private::ArchSpec &arch, lldb_private::InstructionType inst_type)
Definition: EmulateInstructionMIPS.cpp:201
lldb_private::EmulateInstruction::ReadMemoryUnsigned
uint64_t ReadMemoryUnsigned(const Context &context, lldb::addr_t addr, size_t byte_size, uint64_t fail_value, bool *success_ptr)
Definition: EmulateInstruction.cpp:173
dwarf_w13_mips
@ dwarf_w13_mips
Definition: RegisterContext_mips.h:105
dwarf_pc_mips
@ dwarf_pc_mips
Definition: RegisterContext_mips.h:57
dwarf_r30_mips
@ dwarf_r30_mips
Definition: RegisterContext_mips.h:50
Stream.h
EmulateInstructionMIPS::Emulate_LWSP
bool Emulate_LWSP(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1628
dwarf_r15_mips
@ dwarf_r15_mips
Definition: RegisterContext_mips.h:35
dwarf_f31_mips
@ dwarf_f31_mips
Definition: RegisterContext_mips.h:89
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uint64_t GetByteSize() const
Get the number of bytes contained in this object.
Definition: DataExtractor.h:270
lldb_private::EmulateInstruction::eContextPopRegisterOffStack
@ eContextPopRegisterOffStack
Definition: EmulateInstruction.h:114
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@ dwarf_f19_mips
Definition: RegisterContext_mips.h:77
dwarf_r18_mips
@ dwarf_r18_mips
Definition: RegisterContext_mips.h:38
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@ eByteOrderLittle
Definition: lldb-enumerations.h:143
dwarf_w16_mips
@ dwarf_w16_mips
Definition: RegisterContext_mips.h:108
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void SetImmediateSigned(int64_t signed_immediate)
Definition: EmulateInstruction.h:302
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uint64_t ReadRegisterUnsigned(const RegisterInfo &reg_info, uint64_t fail_value, bool *success_ptr)
Definition: EmulateInstruction.cpp:112
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Definition: EmulateInstructionMIPS.h:216
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Definition: EmulateInstruction.h:504
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Definition: UnwindPlan.h:53
lldb
Definition: SBAddress.h:15
lldb_private::EmulateInstruction::eContextPushRegisterOnStack
@ eContextPushRegisterOnStack
Definition: EmulateInstruction.h:110
EmulateInstructionMIPS::Emulate_SW
bool Emulate_SW(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1224
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static llvm::StringRef GetPluginNameStatic()
Definition: EmulateInstructionMIPS.h:36
lldb_private::EmulateInstruction::eContextRelativeBranchImmediate
@ eContextRelativeBranchImmediate
Definition: EmulateInstruction.h:141
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bool WriteRegisterUnsigned(const Context &context, const RegisterInfo &reg_info, uint64_t reg_value)
Definition: EmulateInstruction.cpp:156
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std::unique_ptr< llvm::MCRegisterInfo > m_reg_info
Definition: EmulateInstructionMIPS.h:211
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@ dwarf_hi_mips
Definition: RegisterContext_mips.h:54
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bool WriteRegister(const Context &context, const RegisterInfo &ref_info, const RegisterValue &reg_value)
Definition: EmulateInstruction.cpp:125
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@ eFormatVectorOfUInt8
Definition: lldb-enumerations.h:182
dwarf_f17_mips
@ dwarf_f17_mips
Definition: RegisterContext_mips.h:75
EmulateInstructionMIPS
Definition: EmulateInstructionMIPS.h:30
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void SetImmediate(uint64_t immediate)
Definition: EmulateInstruction.h:297
dwarf_w24_mips
@ dwarf_w24_mips
Definition: RegisterContext_mips.h:116
dwarf_config5_mips
@ dwarf_config5_mips
Definition: RegisterContext_mips.h:126
dwarf_r27_mips
@ dwarf_r27_mips
Definition: RegisterContext_mips.h:47
dwarf_w7_mips
@ dwarf_w7_mips
Definition: RegisterContext_mips.h:99
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bool Emulate_ADDIUSP(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS.cpp:1426
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Opcode m_opcode
Definition: EmulateInstruction.h:505
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#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:54
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