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RegisterInfos_arm64.h
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1//===-- RegisterInfos_arm64.h -----------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
10
11#include <cstddef>
12
13#include "lldb/lldb-defines.h"
14#include "lldb/lldb-enumerations.h"
15#include "lldb/lldb-private.h"
16
17#include "Utility/ARM64_DWARF_Registers.h"
18#include "Utility/ARM64_ehframe_Registers.h"
19
20#ifndef GPR_OFFSET
21#error GPR_OFFSET must be defined before including this header file
22#endif
23
24#ifndef GPR_OFFSET_NAME
25#error GPR_OFFSET_NAME must be defined before including this header file
26#endif
27
28#ifndef FPU_OFFSET
29#error FPU_OFFSET must be defined before including this header file
30#endif
31
32#ifndef FPU_OFFSET_NAME
33#error FPU_OFFSET_NAME must be defined before including this header file
34#endif
35
36#ifndef EXC_OFFSET_NAME
37#error EXC_OFFSET_NAME must be defined before including this header file
38#endif
39
40#ifndef DBG_OFFSET_NAME
41#error DBG_OFFSET_NAME must be defined before including this header file
42#endif
43
44#ifndef DEFINE_DBG
45#error DEFINE_DBG must be defined before including this header file
46#endif
47
48// Offsets for a little-endian layout of the register context
49#define GPR_W_PSEUDO_REG_ENDIAN_OFFSET 0
50#define FPU_S_PSEUDO_REG_ENDIAN_OFFSET 0
51#define FPU_D_PSEUDO_REG_ENDIAN_OFFSET 0
52
53enum {
54 gpr_x0 = 0,
55 gpr_x1,
56 gpr_x2,
57 gpr_x3,
58 gpr_x4,
59 gpr_x5,
60 gpr_x6,
61 gpr_x7,
62 gpr_x8,
63 gpr_x9,
64 gpr_x10,
65 gpr_x11,
66 gpr_x12,
67 gpr_x13,
68 gpr_x14,
69 gpr_x15,
70 gpr_x16,
71 gpr_x17,
72 gpr_x18,
73 gpr_x19,
74 gpr_x20,
75 gpr_x21,
76 gpr_x22,
77 gpr_x23,
78 gpr_x24,
79 gpr_x25,
80 gpr_x26,
81 gpr_x27,
82 gpr_x28,
83 gpr_x29 = 29,
84 gpr_fp = gpr_x29,
85 gpr_x30 = 30,
86 gpr_lr = gpr_x30,
87 gpr_ra = gpr_x30,
88 gpr_x31 = 31,
89 gpr_sp = gpr_x31,
90 gpr_pc = 32,
91 gpr_cpsr,
92
93 gpr_w0,
94 gpr_w1,
95 gpr_w2,
96 gpr_w3,
97 gpr_w4,
98 gpr_w5,
99 gpr_w6,
100 gpr_w7,
101 gpr_w8,
102 gpr_w9,
103 gpr_w10,
104 gpr_w11,
105 gpr_w12,
106 gpr_w13,
107 gpr_w14,
108 gpr_w15,
109 gpr_w16,
110 gpr_w17,
111 gpr_w18,
112 gpr_w19,
113 gpr_w20,
114 gpr_w21,
115 gpr_w22,
116 gpr_w23,
117 gpr_w24,
118 gpr_w25,
119 gpr_w26,
120 gpr_w27,
121 gpr_w28,
122
123 fpu_v0,
124 fpu_v1,
125 fpu_v2,
126 fpu_v3,
127 fpu_v4,
128 fpu_v5,
129 fpu_v6,
130 fpu_v7,
131 fpu_v8,
132 fpu_v9,
133 fpu_v10,
134 fpu_v11,
135 fpu_v12,
136 fpu_v13,
137 fpu_v14,
138 fpu_v15,
139 fpu_v16,
140 fpu_v17,
141 fpu_v18,
142 fpu_v19,
143 fpu_v20,
144 fpu_v21,
145 fpu_v22,
146 fpu_v23,
147 fpu_v24,
148 fpu_v25,
149 fpu_v26,
150 fpu_v27,
151 fpu_v28,
152 fpu_v29,
153 fpu_v30,
154 fpu_v31,
155
156 fpu_s0,
157 fpu_s1,
158 fpu_s2,
159 fpu_s3,
160 fpu_s4,
161 fpu_s5,
162 fpu_s6,
163 fpu_s7,
164 fpu_s8,
165 fpu_s9,
166 fpu_s10,
167 fpu_s11,
168 fpu_s12,
169 fpu_s13,
170 fpu_s14,
171 fpu_s15,
172 fpu_s16,
173 fpu_s17,
174 fpu_s18,
175 fpu_s19,
176 fpu_s20,
177 fpu_s21,
178 fpu_s22,
179 fpu_s23,
180 fpu_s24,
181 fpu_s25,
182 fpu_s26,
183 fpu_s27,
184 fpu_s28,
185 fpu_s29,
186 fpu_s30,
187 fpu_s31,
188
189 fpu_d0,
190 fpu_d1,
191 fpu_d2,
192 fpu_d3,
193 fpu_d4,
194 fpu_d5,
195 fpu_d6,
196 fpu_d7,
197 fpu_d8,
198 fpu_d9,
199 fpu_d10,
200 fpu_d11,
201 fpu_d12,
202 fpu_d13,
203 fpu_d14,
204 fpu_d15,
205 fpu_d16,
206 fpu_d17,
207 fpu_d18,
208 fpu_d19,
209 fpu_d20,
210 fpu_d21,
211 fpu_d22,
212 fpu_d23,
213 fpu_d24,
214 fpu_d25,
215 fpu_d26,
216 fpu_d27,
217 fpu_d28,
218 fpu_d29,
219 fpu_d30,
220 fpu_d31,
221
222 fpu_fpsr,
223 fpu_fpcr,
224
225 exc_far,
226 exc_esr,
227 exc_exception,
228
229 dbg_bvr0,
230 dbg_bvr1,
231 dbg_bvr2,
232 dbg_bvr3,
233 dbg_bvr4,
234 dbg_bvr5,
235 dbg_bvr6,
236 dbg_bvr7,
237 dbg_bvr8,
238 dbg_bvr9,
239 dbg_bvr10,
240 dbg_bvr11,
241 dbg_bvr12,
242 dbg_bvr13,
243 dbg_bvr14,
244 dbg_bvr15,
245
246 dbg_bcr0,
247 dbg_bcr1,
248 dbg_bcr2,
249 dbg_bcr3,
250 dbg_bcr4,
251 dbg_bcr5,
252 dbg_bcr6,
253 dbg_bcr7,
254 dbg_bcr8,
255 dbg_bcr9,
256 dbg_bcr10,
257 dbg_bcr11,
258 dbg_bcr12,
259 dbg_bcr13,
260 dbg_bcr14,
261 dbg_bcr15,
262
263 dbg_wvr0,
264 dbg_wvr1,
265 dbg_wvr2,
266 dbg_wvr3,
267 dbg_wvr4,
268 dbg_wvr5,
269 dbg_wvr6,
270 dbg_wvr7,
271 dbg_wvr8,
272 dbg_wvr9,
273 dbg_wvr10,
274 dbg_wvr11,
275 dbg_wvr12,
276 dbg_wvr13,
277 dbg_wvr14,
278 dbg_wvr15,
279
280 dbg_wcr0,
281 dbg_wcr1,
282 dbg_wcr2,
283 dbg_wcr3,
284 dbg_wcr4,
285 dbg_wcr5,
286 dbg_wcr6,
287 dbg_wcr7,
288 dbg_wcr8,
289 dbg_wcr9,
290 dbg_wcr10,
291 dbg_wcr11,
292 dbg_wcr12,
293 dbg_wcr13,
294 dbg_wcr14,
295 dbg_wcr15,
296
297 k_num_registers
298};
299
300static uint32_t g_contained_x0[] = {gpr_x0, LLDB_INVALID_REGNUM};
301static uint32_t g_contained_x1[] = {gpr_x1, LLDB_INVALID_REGNUM};
302static uint32_t g_contained_x2[] = {gpr_x2, LLDB_INVALID_REGNUM};
303static uint32_t g_contained_x3[] = {gpr_x3, LLDB_INVALID_REGNUM};
304static uint32_t g_contained_x4[] = {gpr_x4, LLDB_INVALID_REGNUM};
305static uint32_t g_contained_x5[] = {gpr_x5, LLDB_INVALID_REGNUM};
306static uint32_t g_contained_x6[] = {gpr_x6, LLDB_INVALID_REGNUM};
307static uint32_t g_contained_x7[] = {gpr_x7, LLDB_INVALID_REGNUM};
308static uint32_t g_contained_x8[] = {gpr_x8, LLDB_INVALID_REGNUM};
309static uint32_t g_contained_x9[] = {gpr_x9, LLDB_INVALID_REGNUM};
310static uint32_t g_contained_x10[] = {gpr_x10, LLDB_INVALID_REGNUM};
311static uint32_t g_contained_x11[] = {gpr_x11, LLDB_INVALID_REGNUM};
312static uint32_t g_contained_x12[] = {gpr_x12, LLDB_INVALID_REGNUM};
313static uint32_t g_contained_x13[] = {gpr_x13, LLDB_INVALID_REGNUM};
314static uint32_t g_contained_x14[] = {gpr_x14, LLDB_INVALID_REGNUM};
315static uint32_t g_contained_x15[] = {gpr_x15, LLDB_INVALID_REGNUM};
316static uint32_t g_contained_x16[] = {gpr_x16, LLDB_INVALID_REGNUM};
317static uint32_t g_contained_x17[] = {gpr_x17, LLDB_INVALID_REGNUM};
318static uint32_t g_contained_x18[] = {gpr_x18, LLDB_INVALID_REGNUM};
319static uint32_t g_contained_x19[] = {gpr_x19, LLDB_INVALID_REGNUM};
320static uint32_t g_contained_x20[] = {gpr_x20, LLDB_INVALID_REGNUM};
321static uint32_t g_contained_x21[] = {gpr_x21, LLDB_INVALID_REGNUM};
322static uint32_t g_contained_x22[] = {gpr_x22, LLDB_INVALID_REGNUM};
323static uint32_t g_contained_x23[] = {gpr_x23, LLDB_INVALID_REGNUM};
324static uint32_t g_contained_x24[] = {gpr_x24, LLDB_INVALID_REGNUM};
325static uint32_t g_contained_x25[] = {gpr_x25, LLDB_INVALID_REGNUM};
326static uint32_t g_contained_x26[] = {gpr_x26, LLDB_INVALID_REGNUM};
327static uint32_t g_contained_x27[] = {gpr_x27, LLDB_INVALID_REGNUM};
328static uint32_t g_contained_x28[] = {gpr_x28, LLDB_INVALID_REGNUM};
329
330static uint32_t g_w0_invalidates[] = {gpr_x0, LLDB_INVALID_REGNUM};
331static uint32_t g_w1_invalidates[] = {gpr_x1, LLDB_INVALID_REGNUM};
332static uint32_t g_w2_invalidates[] = {gpr_x2, LLDB_INVALID_REGNUM};
333static uint32_t g_w3_invalidates[] = {gpr_x3, LLDB_INVALID_REGNUM};
334static uint32_t g_w4_invalidates[] = {gpr_x4, LLDB_INVALID_REGNUM};
335static uint32_t g_w5_invalidates[] = {gpr_x5, LLDB_INVALID_REGNUM};
336static uint32_t g_w6_invalidates[] = {gpr_x6, LLDB_INVALID_REGNUM};
337static uint32_t g_w7_invalidates[] = {gpr_x7, LLDB_INVALID_REGNUM};
338static uint32_t g_w8_invalidates[] = {gpr_x8, LLDB_INVALID_REGNUM};
339static uint32_t g_w9_invalidates[] = {gpr_x9, LLDB_INVALID_REGNUM};
340static uint32_t g_w10_invalidates[] = {gpr_x10, LLDB_INVALID_REGNUM};
341static uint32_t g_w11_invalidates[] = {gpr_x11, LLDB_INVALID_REGNUM};
342static uint32_t g_w12_invalidates[] = {gpr_x12, LLDB_INVALID_REGNUM};
343static uint32_t g_w13_invalidates[] = {gpr_x13, LLDB_INVALID_REGNUM};
344static uint32_t g_w14_invalidates[] = {gpr_x14, LLDB_INVALID_REGNUM};
345static uint32_t g_w15_invalidates[] = {gpr_x15, LLDB_INVALID_REGNUM};
346static uint32_t g_w16_invalidates[] = {gpr_x16, LLDB_INVALID_REGNUM};
347static uint32_t g_w17_invalidates[] = {gpr_x17, LLDB_INVALID_REGNUM};
348static uint32_t g_w18_invalidates[] = {gpr_x18, LLDB_INVALID_REGNUM};
349static uint32_t g_w19_invalidates[] = {gpr_x19, LLDB_INVALID_REGNUM};
350static uint32_t g_w20_invalidates[] = {gpr_x20, LLDB_INVALID_REGNUM};
351static uint32_t g_w21_invalidates[] = {gpr_x21, LLDB_INVALID_REGNUM};
352static uint32_t g_w22_invalidates[] = {gpr_x22, LLDB_INVALID_REGNUM};
353static uint32_t g_w23_invalidates[] = {gpr_x23, LLDB_INVALID_REGNUM};
354static uint32_t g_w24_invalidates[] = {gpr_x24, LLDB_INVALID_REGNUM};
355static uint32_t g_w25_invalidates[] = {gpr_x25, LLDB_INVALID_REGNUM};
356static uint32_t g_w26_invalidates[] = {gpr_x26, LLDB_INVALID_REGNUM};
357static uint32_t g_w27_invalidates[] = {gpr_x27, LLDB_INVALID_REGNUM};
358static uint32_t g_w28_invalidates[] = {gpr_x28, LLDB_INVALID_REGNUM};
359
360static uint32_t g_contained_v0[] = {fpu_v0, LLDB_INVALID_REGNUM};
361static uint32_t g_contained_v1[] = {fpu_v1, LLDB_INVALID_REGNUM};
362static uint32_t g_contained_v2[] = {fpu_v2, LLDB_INVALID_REGNUM};
363static uint32_t g_contained_v3[] = {fpu_v3, LLDB_INVALID_REGNUM};
364static uint32_t g_contained_v4[] = {fpu_v4, LLDB_INVALID_REGNUM};
365static uint32_t g_contained_v5[] = {fpu_v5, LLDB_INVALID_REGNUM};
366static uint32_t g_contained_v6[] = {fpu_v6, LLDB_INVALID_REGNUM};
367static uint32_t g_contained_v7[] = {fpu_v7, LLDB_INVALID_REGNUM};
368static uint32_t g_contained_v8[] = {fpu_v8, LLDB_INVALID_REGNUM};
369static uint32_t g_contained_v9[] = {fpu_v9, LLDB_INVALID_REGNUM};
370static uint32_t g_contained_v10[] = {fpu_v10, LLDB_INVALID_REGNUM};
371static uint32_t g_contained_v11[] = {fpu_v11, LLDB_INVALID_REGNUM};
372static uint32_t g_contained_v12[] = {fpu_v12, LLDB_INVALID_REGNUM};
373static uint32_t g_contained_v13[] = {fpu_v13, LLDB_INVALID_REGNUM};
374static uint32_t g_contained_v14[] = {fpu_v14, LLDB_INVALID_REGNUM};
375static uint32_t g_contained_v15[] = {fpu_v15, LLDB_INVALID_REGNUM};
376static uint32_t g_contained_v16[] = {fpu_v16, LLDB_INVALID_REGNUM};
377static uint32_t g_contained_v17[] = {fpu_v17, LLDB_INVALID_REGNUM};
378static uint32_t g_contained_v18[] = {fpu_v18, LLDB_INVALID_REGNUM};
379static uint32_t g_contained_v19[] = {fpu_v19, LLDB_INVALID_REGNUM};
380static uint32_t g_contained_v20[] = {fpu_v20, LLDB_INVALID_REGNUM};
381static uint32_t g_contained_v21[] = {fpu_v21, LLDB_INVALID_REGNUM};
382static uint32_t g_contained_v22[] = {fpu_v22, LLDB_INVALID_REGNUM};
383static uint32_t g_contained_v23[] = {fpu_v23, LLDB_INVALID_REGNUM};
384static uint32_t g_contained_v24[] = {fpu_v24, LLDB_INVALID_REGNUM};
385static uint32_t g_contained_v25[] = {fpu_v25, LLDB_INVALID_REGNUM};
386static uint32_t g_contained_v26[] = {fpu_v26, LLDB_INVALID_REGNUM};
387static uint32_t g_contained_v27[] = {fpu_v27, LLDB_INVALID_REGNUM};
388static uint32_t g_contained_v28[] = {fpu_v28, LLDB_INVALID_REGNUM};
389static uint32_t g_contained_v29[] = {fpu_v29, LLDB_INVALID_REGNUM};
390static uint32_t g_contained_v30[] = {fpu_v30, LLDB_INVALID_REGNUM};
391static uint32_t g_contained_v31[] = {fpu_v31, LLDB_INVALID_REGNUM};
392
393static uint32_t g_s0_invalidates[] = {fpu_v0, fpu_d0, LLDB_INVALID_REGNUM};
394static uint32_t g_s1_invalidates[] = {fpu_v1, fpu_d1, LLDB_INVALID_REGNUM};
395static uint32_t g_s2_invalidates[] = {fpu_v2, fpu_d2, LLDB_INVALID_REGNUM};
396static uint32_t g_s3_invalidates[] = {fpu_v3, fpu_d3, LLDB_INVALID_REGNUM};
397static uint32_t g_s4_invalidates[] = {fpu_v4, fpu_d4, LLDB_INVALID_REGNUM};
398static uint32_t g_s5_invalidates[] = {fpu_v5, fpu_d5, LLDB_INVALID_REGNUM};
399static uint32_t g_s6_invalidates[] = {fpu_v6, fpu_d6, LLDB_INVALID_REGNUM};
400static uint32_t g_s7_invalidates[] = {fpu_v7, fpu_d7, LLDB_INVALID_REGNUM};
401static uint32_t g_s8_invalidates[] = {fpu_v8, fpu_d8, LLDB_INVALID_REGNUM};
402static uint32_t g_s9_invalidates[] = {fpu_v9, fpu_d9, LLDB_INVALID_REGNUM};
403static uint32_t g_s10_invalidates[] = {fpu_v10, fpu_d10, LLDB_INVALID_REGNUM};
404static uint32_t g_s11_invalidates[] = {fpu_v11, fpu_d11, LLDB_INVALID_REGNUM};
405static uint32_t g_s12_invalidates[] = {fpu_v12, fpu_d12, LLDB_INVALID_REGNUM};
406static uint32_t g_s13_invalidates[] = {fpu_v13, fpu_d13, LLDB_INVALID_REGNUM};
407static uint32_t g_s14_invalidates[] = {fpu_v14, fpu_d14, LLDB_INVALID_REGNUM};
408static uint32_t g_s15_invalidates[] = {fpu_v15, fpu_d15, LLDB_INVALID_REGNUM};
409static uint32_t g_s16_invalidates[] = {fpu_v16, fpu_d16, LLDB_INVALID_REGNUM};
410static uint32_t g_s17_invalidates[] = {fpu_v17, fpu_d17, LLDB_INVALID_REGNUM};
411static uint32_t g_s18_invalidates[] = {fpu_v18, fpu_d18, LLDB_INVALID_REGNUM};
412static uint32_t g_s19_invalidates[] = {fpu_v19, fpu_d19, LLDB_INVALID_REGNUM};
413static uint32_t g_s20_invalidates[] = {fpu_v20, fpu_d20, LLDB_INVALID_REGNUM};
414static uint32_t g_s21_invalidates[] = {fpu_v21, fpu_d21, LLDB_INVALID_REGNUM};
415static uint32_t g_s22_invalidates[] = {fpu_v22, fpu_d22, LLDB_INVALID_REGNUM};
416static uint32_t g_s23_invalidates[] = {fpu_v23, fpu_d23, LLDB_INVALID_REGNUM};
417static uint32_t g_s24_invalidates[] = {fpu_v24, fpu_d24, LLDB_INVALID_REGNUM};
418static uint32_t g_s25_invalidates[] = {fpu_v25, fpu_d25, LLDB_INVALID_REGNUM};
419static uint32_t g_s26_invalidates[] = {fpu_v26, fpu_d26, LLDB_INVALID_REGNUM};
420static uint32_t g_s27_invalidates[] = {fpu_v27, fpu_d27, LLDB_INVALID_REGNUM};
421static uint32_t g_s28_invalidates[] = {fpu_v28, fpu_d28, LLDB_INVALID_REGNUM};
422static uint32_t g_s29_invalidates[] = {fpu_v29, fpu_d29, LLDB_INVALID_REGNUM};
423static uint32_t g_s30_invalidates[] = {fpu_v30, fpu_d30, LLDB_INVALID_REGNUM};
424static uint32_t g_s31_invalidates[] = {fpu_v31, fpu_d31, LLDB_INVALID_REGNUM};
425
426static uint32_t g_d0_invalidates[] = {fpu_v0, fpu_s0, LLDB_INVALID_REGNUM};
427static uint32_t g_d1_invalidates[] = {fpu_v1, fpu_s1, LLDB_INVALID_REGNUM};
428static uint32_t g_d2_invalidates[] = {fpu_v2, fpu_s2, LLDB_INVALID_REGNUM};
429static uint32_t g_d3_invalidates[] = {fpu_v3, fpu_s3, LLDB_INVALID_REGNUM};
430static uint32_t g_d4_invalidates[] = {fpu_v4, fpu_s4, LLDB_INVALID_REGNUM};
431static uint32_t g_d5_invalidates[] = {fpu_v5, fpu_s5, LLDB_INVALID_REGNUM};
432static uint32_t g_d6_invalidates[] = {fpu_v6, fpu_s6, LLDB_INVALID_REGNUM};
433static uint32_t g_d7_invalidates[] = {fpu_v7, fpu_s7, LLDB_INVALID_REGNUM};
434static uint32_t g_d8_invalidates[] = {fpu_v8, fpu_s8, LLDB_INVALID_REGNUM};
435static uint32_t g_d9_invalidates[] = {fpu_v9, fpu_s9, LLDB_INVALID_REGNUM};
436static uint32_t g_d10_invalidates[] = {fpu_v10, fpu_s10, LLDB_INVALID_REGNUM};
437static uint32_t g_d11_invalidates[] = {fpu_v11, fpu_s11, LLDB_INVALID_REGNUM};
438static uint32_t g_d12_invalidates[] = {fpu_v12, fpu_s12, LLDB_INVALID_REGNUM};
439static uint32_t g_d13_invalidates[] = {fpu_v13, fpu_s13, LLDB_INVALID_REGNUM};
440static uint32_t g_d14_invalidates[] = {fpu_v14, fpu_s14, LLDB_INVALID_REGNUM};
441static uint32_t g_d15_invalidates[] = {fpu_v15, fpu_s15, LLDB_INVALID_REGNUM};
442static uint32_t g_d16_invalidates[] = {fpu_v16, fpu_s16, LLDB_INVALID_REGNUM};
443static uint32_t g_d17_invalidates[] = {fpu_v17, fpu_s17, LLDB_INVALID_REGNUM};
444static uint32_t g_d18_invalidates[] = {fpu_v18, fpu_s18, LLDB_INVALID_REGNUM};
445static uint32_t g_d19_invalidates[] = {fpu_v19, fpu_s19, LLDB_INVALID_REGNUM};
446static uint32_t g_d20_invalidates[] = {fpu_v20, fpu_s20, LLDB_INVALID_REGNUM};
447static uint32_t g_d21_invalidates[] = {fpu_v21, fpu_s21, LLDB_INVALID_REGNUM};
448static uint32_t g_d22_invalidates[] = {fpu_v22, fpu_s22, LLDB_INVALID_REGNUM};
449static uint32_t g_d23_invalidates[] = {fpu_v23, fpu_s23, LLDB_INVALID_REGNUM};
450static uint32_t g_d24_invalidates[] = {fpu_v24, fpu_s24, LLDB_INVALID_REGNUM};
451static uint32_t g_d25_invalidates[] = {fpu_v25, fpu_s25, LLDB_INVALID_REGNUM};
452static uint32_t g_d26_invalidates[] = {fpu_v26, fpu_s26, LLDB_INVALID_REGNUM};
453static uint32_t g_d27_invalidates[] = {fpu_v27, fpu_s27, LLDB_INVALID_REGNUM};
454static uint32_t g_d28_invalidates[] = {fpu_v28, fpu_s28, LLDB_INVALID_REGNUM};
455static uint32_t g_d29_invalidates[] = {fpu_v29, fpu_s29, LLDB_INVALID_REGNUM};
456static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
457static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
458
459// clang-format off
460// Generates register kinds array with DWARF, EH frame and generic kind
461#define MISC_KIND(reg, type, generic_kind) \
462 { \
463 arm64_ehframe::reg, arm64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM, \
464 type##_##reg \
465 }
466
467// Generates register kinds array for registers with only lldb kind
468#define LLDB_KIND(lldb_kind) \
469 { \
470 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
471 LLDB_INVALID_REGNUM, lldb_kind \
472 }
473
474#define GENERIC_KIND(genenric_kind) \
475 { \
476 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, genenric_kind, \
477 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM \
478 }
479// Generates register kinds array for registers with only lldb kind
480#define KIND_ALL_INVALID \
481 { \
482 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
483 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM \
484 }
485
486// Generates register kinds array for vector registers
487#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
488#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
489
490// Defines a 64-bit general purpose register
491#define DEFINE_GPR64(reg, generic_kind) \
492 { \
493 #reg, nullptr, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint, \
494 lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr, \
495 nullptr, \
496 }
497
498// Defines a 64-bit general purpose register
499#define DEFINE_GPR64_ALT(reg, alt, generic_kind) \
500 { \
501 #reg, #alt, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint, \
502 lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr, \
503 nullptr, \
504 }
505
506// Defines a 32-bit general purpose pseudo register
507#define DEFINE_GPR32(wreg, xreg) \
508 { \
509 #wreg, nullptr, 4, \
510 GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, \
511 lldb::eEncodingUint, lldb::eFormatHex, LLDB_KIND(gpr_##wreg), \
512 g_contained_##xreg, g_##wreg##_invalidates, nullptr, \
513 }
514
515// Defines a vector register with 16-byte size
516#define DEFINE_VREG(reg) \
517 { \
518 #reg, nullptr, 16, FPU_OFFSET(fpu_##reg - fpu_v0), lldb::eEncodingVector, \
519 lldb::eFormatVectorOfUInt8, VREG_KIND(reg), nullptr, nullptr, nullptr, \
520 }
521
522// Defines S and D pseudo registers mapping over corresponding vector register
523#define DEFINE_FPU_PSEUDO(reg, size, offset, vreg) \
524 { \
525 #reg, nullptr, size, FPU_OFFSET(fpu_##vreg - fpu_v0) + offset, \
526 lldb::eEncodingIEEE754, lldb::eFormatFloat, LLDB_KIND(fpu_##reg), \
527 g_contained_##vreg, g_##reg##_invalidates, nullptr, \
528 }
529
530// Define cpsr
531#define DEFINE_GPR_CPSR \
532 { \
533 "cpsr", nullptr, 4, GPR_OFFSET_NAME(cpsr), lldb::eEncodingUint, \
534 lldb::eFormatHex, \
535 { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_REGNUM_GENERIC_FLAGS, \
536 LLDB_INVALID_REGNUM, gpr_cpsr }, \
537 nullptr, nullptr, nullptr, \
538 }
539
540// Defines miscellaneous registers that have DWARF/eh_frame numbers, like vg.
541#define DEFINE_MISC_REGS(reg, size, TYPE, lldb_kind) \
542 { \
543 #reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint, \
544 lldb::eFormatHex, MISC_##TYPE##_KIND(lldb_kind), nullptr, nullptr, \
545 nullptr, \
546 }
547
548// Defines miscellaneous status and control registers like fpcr, fpsr etc
549// that have no DWARF/eh_frame register numbers.
550#define DEFINE_MISC_LLDB_REGS(reg, size, TYPE, lldb_kind) \
551 { \
552 #reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint, \
553 lldb::eFormatHex, LLDB_KIND(lldb_kind), nullptr, nullptr, \
554 nullptr, \
555 }
556
557// Defines pointer authentication mask registers
558#define DEFINE_EXTENSION_REG(reg) \
559 { \
560 #reg, nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
561 KIND_ALL_INVALID, nullptr, nullptr, nullptr, \
562 }
563
564#define DEFINE_EXTENSION_REG_GENERIC(reg, generic_kind) \
565 { \
566 #reg, nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
567 GENERIC_KIND(generic_kind), nullptr, nullptr, nullptr, \
568 }
569
570static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
571 // DEFINE_GPR64(name, GENERIC KIND)
572 DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
573 DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2),
574 DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3),
575 DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4),
576 DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5),
577 DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6),
578 DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7),
579 DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8),
580 DEFINE_GPR64(x8, LLDB_INVALID_REGNUM),
581 DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
582 DEFINE_GPR64(x10, LLDB_INVALID_REGNUM),
583 DEFINE_GPR64(x11, LLDB_INVALID_REGNUM),
584 DEFINE_GPR64(x12, LLDB_INVALID_REGNUM),
585 DEFINE_GPR64(x13, LLDB_INVALID_REGNUM),
586 DEFINE_GPR64(x14, LLDB_INVALID_REGNUM),
587 DEFINE_GPR64(x15, LLDB_INVALID_REGNUM),
588 DEFINE_GPR64(x16, LLDB_INVALID_REGNUM),
589 DEFINE_GPR64(x17, LLDB_INVALID_REGNUM),
590 DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
591 DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
592 DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
593 DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
594 DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
595 DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
596 DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
597 DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
598 DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
599 DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
600 DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
601 // DEFINE_GPR64(name, GENERIC KIND)
602 DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP),
603 DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA),
604 DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
605 DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
606
607 DEFINE_GPR_CPSR,
608
609 // DEFINE_GPR32(name, parent name)
610 DEFINE_GPR32(w0, x0),
611 DEFINE_GPR32(w1, x1),
612 DEFINE_GPR32(w2, x2),
613 DEFINE_GPR32(w3, x3),
614 DEFINE_GPR32(w4, x4),
615 DEFINE_GPR32(w5, x5),
616 DEFINE_GPR32(w6, x6),
617 DEFINE_GPR32(w7, x7),
618 DEFINE_GPR32(w8, x8),
619 DEFINE_GPR32(w9, x9),
620 DEFINE_GPR32(w10, x10),
621 DEFINE_GPR32(w11, x11),
622 DEFINE_GPR32(w12, x12),
623 DEFINE_GPR32(w13, x13),
624 DEFINE_GPR32(w14, x14),
625 DEFINE_GPR32(w15, x15),
626 DEFINE_GPR32(w16, x16),
627 DEFINE_GPR32(w17, x17),
628 DEFINE_GPR32(w18, x18),
629 DEFINE_GPR32(w19, x19),
630 DEFINE_GPR32(w20, x20),
631 DEFINE_GPR32(w21, x21),
632 DEFINE_GPR32(w22, x22),
633 DEFINE_GPR32(w23, x23),
634 DEFINE_GPR32(w24, x24),
635 DEFINE_GPR32(w25, x25),
636 DEFINE_GPR32(w26, x26),
637 DEFINE_GPR32(w27, x27),
638 DEFINE_GPR32(w28, x28),
639
640 // DEFINE_VREG(name)
641 DEFINE_VREG(v0),
642 DEFINE_VREG(v1),
643 DEFINE_VREG(v2),
644 DEFINE_VREG(v3),
645 DEFINE_VREG(v4),
646 DEFINE_VREG(v5),
647 DEFINE_VREG(v6),
648 DEFINE_VREG(v7),
649 DEFINE_VREG(v8),
650 DEFINE_VREG(v9),
651 DEFINE_VREG(v10),
652 DEFINE_VREG(v11),
653 DEFINE_VREG(v12),
654 DEFINE_VREG(v13),
655 DEFINE_VREG(v14),
656 DEFINE_VREG(v15),
657 DEFINE_VREG(v16),
658 DEFINE_VREG(v17),
659 DEFINE_VREG(v18),
660 DEFINE_VREG(v19),
661 DEFINE_VREG(v20),
662 DEFINE_VREG(v21),
663 DEFINE_VREG(v22),
664 DEFINE_VREG(v23),
665 DEFINE_VREG(v24),
666 DEFINE_VREG(v25),
667 DEFINE_VREG(v26),
668 DEFINE_VREG(v27),
669 DEFINE_VREG(v28),
670 DEFINE_VREG(v29),
671 DEFINE_VREG(v30),
672 DEFINE_VREG(v31),
673
674 // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register)
675 DEFINE_FPU_PSEUDO(s0, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v0),
676 DEFINE_FPU_PSEUDO(s1, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v1),
677 DEFINE_FPU_PSEUDO(s2, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v2),
678 DEFINE_FPU_PSEUDO(s3, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v3),
679 DEFINE_FPU_PSEUDO(s4, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v4),
680 DEFINE_FPU_PSEUDO(s5, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v5),
681 DEFINE_FPU_PSEUDO(s6, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v6),
682 DEFINE_FPU_PSEUDO(s7, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v7),
683 DEFINE_FPU_PSEUDO(s8, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v8),
684 DEFINE_FPU_PSEUDO(s9, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v9),
685 DEFINE_FPU_PSEUDO(s10, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v10),
686 DEFINE_FPU_PSEUDO(s11, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v11),
687 DEFINE_FPU_PSEUDO(s12, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v12),
688 DEFINE_FPU_PSEUDO(s13, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v13),
689 DEFINE_FPU_PSEUDO(s14, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v14),
690 DEFINE_FPU_PSEUDO(s15, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v15),
691 DEFINE_FPU_PSEUDO(s16, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v16),
692 DEFINE_FPU_PSEUDO(s17, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v17),
693 DEFINE_FPU_PSEUDO(s18, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v18),
694 DEFINE_FPU_PSEUDO(s19, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v19),
695 DEFINE_FPU_PSEUDO(s20, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v20),
696 DEFINE_FPU_PSEUDO(s21, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v21),
697 DEFINE_FPU_PSEUDO(s22, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v22),
698 DEFINE_FPU_PSEUDO(s23, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v23),
699 DEFINE_FPU_PSEUDO(s24, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v24),
700 DEFINE_FPU_PSEUDO(s25, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v25),
701 DEFINE_FPU_PSEUDO(s26, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v26),
702 DEFINE_FPU_PSEUDO(s27, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v27),
703 DEFINE_FPU_PSEUDO(s28, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v28),
704 DEFINE_FPU_PSEUDO(s29, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v29),
705 DEFINE_FPU_PSEUDO(s30, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v30),
706 DEFINE_FPU_PSEUDO(s31, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v31),
707
708 DEFINE_FPU_PSEUDO(d0, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v0),
709 DEFINE_FPU_PSEUDO(d1, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v1),
710 DEFINE_FPU_PSEUDO(d2, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v2),
711 DEFINE_FPU_PSEUDO(d3, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v3),
712 DEFINE_FPU_PSEUDO(d4, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v4),
713 DEFINE_FPU_PSEUDO(d5, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v5),
714 DEFINE_FPU_PSEUDO(d6, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v6),
715 DEFINE_FPU_PSEUDO(d7, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v7),
716 DEFINE_FPU_PSEUDO(d8, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v8),
717 DEFINE_FPU_PSEUDO(d9, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v9),
718 DEFINE_FPU_PSEUDO(d10, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v10),
719 DEFINE_FPU_PSEUDO(d11, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v11),
720 DEFINE_FPU_PSEUDO(d12, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v12),
721 DEFINE_FPU_PSEUDO(d13, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v13),
722 DEFINE_FPU_PSEUDO(d14, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v14),
723 DEFINE_FPU_PSEUDO(d15, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v15),
724 DEFINE_FPU_PSEUDO(d16, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v16),
725 DEFINE_FPU_PSEUDO(d17, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v17),
726 DEFINE_FPU_PSEUDO(d18, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v18),
727 DEFINE_FPU_PSEUDO(d19, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v19),
728 DEFINE_FPU_PSEUDO(d20, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v20),
729 DEFINE_FPU_PSEUDO(d21, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v21),
730 DEFINE_FPU_PSEUDO(d22, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v22),
731 DEFINE_FPU_PSEUDO(d23, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v23),
732 DEFINE_FPU_PSEUDO(d24, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v24),
733 DEFINE_FPU_PSEUDO(d25, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v25),
734 DEFINE_FPU_PSEUDO(d26, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v26),
735 DEFINE_FPU_PSEUDO(d27, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v27),
736 DEFINE_FPU_PSEUDO(d28, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v28),
737 DEFINE_FPU_PSEUDO(d29, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v29),
738 DEFINE_FPU_PSEUDO(d30, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v30),
739 DEFINE_FPU_PSEUDO(d31, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v31),
740
741 // DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
742 DEFINE_MISC_LLDB_REGS(fpsr, 4, FPU, fpu_fpsr),
743 DEFINE_MISC_LLDB_REGS(fpcr, 4, FPU, fpu_fpcr),
744 DEFINE_MISC_LLDB_REGS(far, 8, EXC, exc_far),
745 DEFINE_MISC_LLDB_REGS(esr, 4, EXC, exc_esr),
746 DEFINE_MISC_LLDB_REGS(exception, 4, EXC, exc_exception),
747
748 {DEFINE_DBG(bvr, 0)},
749 {DEFINE_DBG(bvr, 1)},
750 {DEFINE_DBG(bvr, 2)},
751 {DEFINE_DBG(bvr, 3)},
752 {DEFINE_DBG(bvr, 4)},
753 {DEFINE_DBG(bvr, 5)},
754 {DEFINE_DBG(bvr, 6)},
755 {DEFINE_DBG(bvr, 7)},
756 {DEFINE_DBG(bvr, 8)},
757 {DEFINE_DBG(bvr, 9)},
758 {DEFINE_DBG(bvr, 10)},
759 {DEFINE_DBG(bvr, 11)},
760 {DEFINE_DBG(bvr, 12)},
761 {DEFINE_DBG(bvr, 13)},
762 {DEFINE_DBG(bvr, 14)},
763 {DEFINE_DBG(bvr, 15)},
764
765 {DEFINE_DBG(bcr, 0)},
766 {DEFINE_DBG(bcr, 1)},
767 {DEFINE_DBG(bcr, 2)},
768 {DEFINE_DBG(bcr, 3)},
769 {DEFINE_DBG(bcr, 4)},
770 {DEFINE_DBG(bcr, 5)},
771 {DEFINE_DBG(bcr, 6)},
772 {DEFINE_DBG(bcr, 7)},
773 {DEFINE_DBG(bcr, 8)},
774 {DEFINE_DBG(bcr, 9)},
775 {DEFINE_DBG(bcr, 10)},
776 {DEFINE_DBG(bcr, 11)},
777 {DEFINE_DBG(bcr, 12)},
778 {DEFINE_DBG(bcr, 13)},
779 {DEFINE_DBG(bcr, 14)},
780 {DEFINE_DBG(bcr, 15)},
781
782 {DEFINE_DBG(wvr, 0)},
783 {DEFINE_DBG(wvr, 1)},
784 {DEFINE_DBG(wvr, 2)},
785 {DEFINE_DBG(wvr, 3)},
786 {DEFINE_DBG(wvr, 4)},
787 {DEFINE_DBG(wvr, 5)},
788 {DEFINE_DBG(wvr, 6)},
789 {DEFINE_DBG(wvr, 7)},
790 {DEFINE_DBG(wvr, 8)},
791 {DEFINE_DBG(wvr, 9)},
792 {DEFINE_DBG(wvr, 10)},
793 {DEFINE_DBG(wvr, 11)},
794 {DEFINE_DBG(wvr, 12)},
795 {DEFINE_DBG(wvr, 13)},
796 {DEFINE_DBG(wvr, 14)},
797 {DEFINE_DBG(wvr, 15)},
798
799 {DEFINE_DBG(wcr, 0)},
800 {DEFINE_DBG(wcr, 1)},
801 {DEFINE_DBG(wcr, 2)},
802 {DEFINE_DBG(wcr, 3)},
803 {DEFINE_DBG(wcr, 4)},
804 {DEFINE_DBG(wcr, 5)},
805 {DEFINE_DBG(wcr, 6)},
806 {DEFINE_DBG(wcr, 7)},
807 {DEFINE_DBG(wcr, 8)},
808 {DEFINE_DBG(wcr, 9)},
809 {DEFINE_DBG(wcr, 10)},
810 {DEFINE_DBG(wcr, 11)},
811 {DEFINE_DBG(wcr, 12)},
812 {DEFINE_DBG(wcr, 13)},
813 {DEFINE_DBG(wcr, 14)},
814 {DEFINE_DBG(wcr, 15)}
815};
816// clang-format on
817
818#endif // DECLARE_REGISTER_INFOS_ARM64_STRUCT
ARM64_DWARF_Registers.h
ARM64_ehframe_Registers.h
DEFINE_DBG
#define DEFINE_DBG(re, y)
Definition EmulateInstructionARM64.cpp:35
dbg_bvr5
@ dbg_bvr5
Definition RegisterContextDarwin_arm.cpp:97
dbg_wvr4
@ dbg_wvr4
Definition RegisterContextDarwin_arm.cpp:130
dbg_wvr9
@ dbg_wvr9
Definition RegisterContextDarwin_arm.cpp:135
dbg_wvr15
@ dbg_wvr15
Definition RegisterContextDarwin_arm.cpp:141
dbg_wvr0
@ dbg_wvr0
Definition RegisterContextDarwin_arm.cpp:126
dbg_wvr10
@ dbg_wvr10
Definition RegisterContextDarwin_arm.cpp:136
dbg_wvr8
@ dbg_wvr8
Definition RegisterContextDarwin_arm.cpp:134
dbg_bcr1
@ dbg_bcr1
Definition RegisterContextDarwin_arm.cpp:110
fpu_s7
@ fpu_s7
Definition RegisterContextDarwin_arm.cpp:61
dbg_wvr7
@ dbg_wvr7
Definition RegisterContextDarwin_arm.cpp:133
fpu_s4
@ fpu_s4
Definition RegisterContextDarwin_arm.cpp:58
fpu_s13
@ fpu_s13
Definition RegisterContextDarwin_arm.cpp:67
dbg_wcr4
@ dbg_wcr4
Definition RegisterContextDarwin_arm.cpp:147
dbg_wcr0
@ dbg_wcr0
Definition RegisterContextDarwin_arm.cpp:143
dbg_bvr11
@ dbg_bvr11
Definition RegisterContextDarwin_arm.cpp:103
dbg_bvr3
@ dbg_bvr3
Definition RegisterContextDarwin_arm.cpp:95
dbg_bcr6
@ dbg_bcr6
Definition RegisterContextDarwin_arm.cpp:115
dbg_wcr12
@ dbg_wcr12
Definition RegisterContextDarwin_arm.cpp:155
dbg_bcr10
@ dbg_bcr10
Definition RegisterContextDarwin_arm.cpp:119
dbg_bcr0
@ dbg_bcr0
Definition RegisterContextDarwin_arm.cpp:109
fpu_s5
@ fpu_s5
Definition RegisterContextDarwin_arm.cpp:59
dbg_bvr14
@ dbg_bvr14
Definition RegisterContextDarwin_arm.cpp:106
fpu_s20
@ fpu_s20
Definition RegisterContextDarwin_arm.cpp:74
dbg_wvr14
@ dbg_wvr14
Definition RegisterContextDarwin_arm.cpp:140
dbg_bcr14
@ dbg_bcr14
Definition RegisterContextDarwin_arm.cpp:123
fpu_s3
@ fpu_s3
Definition RegisterContextDarwin_arm.cpp:57
fpu_s26
@ fpu_s26
Definition RegisterContextDarwin_arm.cpp:80
dbg_wvr2
@ dbg_wvr2
Definition RegisterContextDarwin_arm.cpp:128
dbg_bvr1
@ dbg_bvr1
Definition RegisterContextDarwin_arm.cpp:93
fpu_s14
@ fpu_s14
Definition RegisterContextDarwin_arm.cpp:68
dbg_bvr8
@ dbg_bvr8
Definition RegisterContextDarwin_arm.cpp:100
exc_exception
@ exc_exception
Definition RegisterContextDarwin_arm.cpp:88
fpu_s23
@ fpu_s23
Definition RegisterContextDarwin_arm.cpp:77
dbg_wvr13
@ dbg_wvr13
Definition RegisterContextDarwin_arm.cpp:139
fpu_s30
@ fpu_s30
Definition RegisterContextDarwin_arm.cpp:84
dbg_bcr15
@ dbg_bcr15
Definition RegisterContextDarwin_arm.cpp:124
dbg_bvr12
@ dbg_bvr12
Definition RegisterContextDarwin_arm.cpp:104
dbg_wcr11
@ dbg_wcr11
Definition RegisterContextDarwin_arm.cpp:154
fpu_s6
@ fpu_s6
Definition RegisterContextDarwin_arm.cpp:60
fpu_s11
@ fpu_s11
Definition RegisterContextDarwin_arm.cpp:65
dbg_bcr5
@ dbg_bcr5
Definition RegisterContextDarwin_arm.cpp:114
dbg_bvr15
@ dbg_bvr15
Definition RegisterContextDarwin_arm.cpp:107
dbg_wvr12
@ dbg_wvr12
Definition RegisterContextDarwin_arm.cpp:138
dbg_bcr8
@ dbg_bcr8
Definition RegisterContextDarwin_arm.cpp:117
dbg_wcr2
@ dbg_wcr2
Definition RegisterContextDarwin_arm.cpp:145
fpu_s10
@ fpu_s10
Definition RegisterContextDarwin_arm.cpp:64
dbg_bcr9
@ dbg_bcr9
Definition RegisterContextDarwin_arm.cpp:118
fpu_s1
@ fpu_s1
Definition RegisterContextDarwin_arm.cpp:55
dbg_wvr3
@ dbg_wvr3
Definition RegisterContextDarwin_arm.cpp:129
dbg_wcr5
@ dbg_wcr5
Definition RegisterContextDarwin_arm.cpp:148
fpu_s0
@ fpu_s0
Definition RegisterContextDarwin_arm.cpp:54
dbg_bcr2
@ dbg_bcr2
Definition RegisterContextDarwin_arm.cpp:111
gpr_sp
@ gpr_sp
Definition RegisterContextDarwin_arm.cpp:47
fpu_s18
@ fpu_s18
Definition RegisterContextDarwin_arm.cpp:72
dbg_bcr13
@ dbg_bcr13
Definition RegisterContextDarwin_arm.cpp:122
dbg_bvr2
@ dbg_bvr2
Definition RegisterContextDarwin_arm.cpp:94
k_num_registers
@ k_num_registers
Definition RegisterContextDarwin_arm.cpp:160
gpr_cpsr
@ gpr_cpsr
Definition RegisterContextDarwin_arm.cpp:52
fpu_s25
@ fpu_s25
Definition RegisterContextDarwin_arm.cpp:79
fpu_s16
@ fpu_s16
Definition RegisterContextDarwin_arm.cpp:70
fpu_s19
@ fpu_s19
Definition RegisterContextDarwin_arm.cpp:73
fpu_s31
@ fpu_s31
Definition RegisterContextDarwin_arm.cpp:85
dbg_wvr11
@ dbg_wvr11
Definition RegisterContextDarwin_arm.cpp:137
fpu_s24
@ fpu_s24
Definition RegisterContextDarwin_arm.cpp:78
dbg_bcr12
@ dbg_bcr12
Definition RegisterContextDarwin_arm.cpp:121
dbg_wcr14
@ dbg_wcr14
Definition RegisterContextDarwin_arm.cpp:157
fpu_s9
@ fpu_s9
Definition RegisterContextDarwin_arm.cpp:63
dbg_wvr5
@ dbg_wvr5
Definition RegisterContextDarwin_arm.cpp:131
fpu_s8
@ fpu_s8
Definition RegisterContextDarwin_arm.cpp:62
dbg_wcr8
@ dbg_wcr8
Definition RegisterContextDarwin_arm.cpp:151
dbg_wcr7
@ dbg_wcr7
Definition RegisterContextDarwin_arm.cpp:150
fpu_s21
@ fpu_s21
Definition RegisterContextDarwin_arm.cpp:75
dbg_bvr6
@ dbg_bvr6
Definition RegisterContextDarwin_arm.cpp:98
dbg_bvr4
@ dbg_bvr4
Definition RegisterContextDarwin_arm.cpp:96
fpu_s17
@ fpu_s17
Definition RegisterContextDarwin_arm.cpp:71
dbg_bvr9
@ dbg_bvr9
Definition RegisterContextDarwin_arm.cpp:101
dbg_wcr6
@ dbg_wcr6
Definition RegisterContextDarwin_arm.cpp:149
fpu_s12
@ fpu_s12
Definition RegisterContextDarwin_arm.cpp:66
gpr_pc
@ gpr_pc
Definition RegisterContextDarwin_arm.cpp:51
fpu_s22
@ fpu_s22
Definition RegisterContextDarwin_arm.cpp:76
fpu_s28
@ fpu_s28
Definition RegisterContextDarwin_arm.cpp:82
gpr_lr
@ gpr_lr
Definition RegisterContextDarwin_arm.cpp:49
dbg_bcr7
@ dbg_bcr7
Definition RegisterContextDarwin_arm.cpp:116
fpu_s15
@ fpu_s15
Definition RegisterContextDarwin_arm.cpp:69
dbg_bvr0
@ dbg_bvr0
Definition RegisterContextDarwin_arm.cpp:92
dbg_bvr10
@ dbg_bvr10
Definition RegisterContextDarwin_arm.cpp:102
dbg_wvr6
@ dbg_wvr6
Definition RegisterContextDarwin_arm.cpp:132
fpu_s29
@ fpu_s29
Definition RegisterContextDarwin_arm.cpp:83
dbg_wcr10
@ dbg_wcr10
Definition RegisterContextDarwin_arm.cpp:153
dbg_bcr11
@ dbg_bcr11
Definition RegisterContextDarwin_arm.cpp:120
dbg_bcr4
@ dbg_bcr4
Definition RegisterContextDarwin_arm.cpp:113
dbg_wcr13
@ dbg_wcr13
Definition RegisterContextDarwin_arm.cpp:156
dbg_bvr7
@ dbg_bvr7
Definition RegisterContextDarwin_arm.cpp:99
dbg_bcr3
@ dbg_bcr3
Definition RegisterContextDarwin_arm.cpp:112
fpu_s2
@ fpu_s2
Definition RegisterContextDarwin_arm.cpp:56
fpu_s27
@ fpu_s27
Definition RegisterContextDarwin_arm.cpp:81
dbg_bvr13
@ dbg_bvr13
Definition RegisterContextDarwin_arm.cpp:105
dbg_wvr1
@ dbg_wvr1
Definition RegisterContextDarwin_arm.cpp:127
dbg_wcr15
@ dbg_wcr15
Definition RegisterContextDarwin_arm.cpp:158
exc_far
@ exc_far
Definition RegisterContextDarwin_arm.cpp:90
dbg_wcr9
@ dbg_wcr9
Definition RegisterContextDarwin_arm.cpp:152
dbg_wcr1
@ dbg_wcr1
Definition RegisterContextDarwin_arm.cpp:144
dbg_wcr3
@ dbg_wcr3
Definition RegisterContextDarwin_arm.cpp:146
gpr_x3
@ gpr_x3
Definition RegisterContextDarwin_riscv32.cpp:33
gpr_x20
@ gpr_x20
Definition RegisterContextDarwin_riscv32.cpp:50
gpr_x27
@ gpr_x27
Definition RegisterContextDarwin_riscv32.cpp:57
gpr_x28
@ gpr_x28
Definition RegisterContextDarwin_riscv32.cpp:58
gpr_x8
@ gpr_x8
Definition RegisterContextDarwin_riscv32.cpp:38
gpr_x11
@ gpr_x11
Definition RegisterContextDarwin_riscv32.cpp:41
gpr_x5
@ gpr_x5
Definition RegisterContextDarwin_riscv32.cpp:35
gpr_x24
@ gpr_x24
Definition RegisterContextDarwin_riscv32.cpp:54
gpr_x29
@ gpr_x29
Definition RegisterContextDarwin_riscv32.cpp:59
gpr_x16
@ gpr_x16
Definition RegisterContextDarwin_riscv32.cpp:46
gpr_x13
@ gpr_x13
Definition RegisterContextDarwin_riscv32.cpp:43
gpr_x9
@ gpr_x9
Definition RegisterContextDarwin_riscv32.cpp:39
gpr_x0
@ gpr_x0
Definition RegisterContextDarwin_riscv32.cpp:30
gpr_x15
@ gpr_x15
Definition RegisterContextDarwin_riscv32.cpp:45
gpr_x6
@ gpr_x6
Definition RegisterContextDarwin_riscv32.cpp:36
gpr_x26
@ gpr_x26
Definition RegisterContextDarwin_riscv32.cpp:56
gpr_x4
@ gpr_x4
Definition RegisterContextDarwin_riscv32.cpp:34
gpr_x12
@ gpr_x12
Definition RegisterContextDarwin_riscv32.cpp:42
gpr_x2
@ gpr_x2
Definition RegisterContextDarwin_riscv32.cpp:32
gpr_x30
@ gpr_x30
Definition RegisterContextDarwin_riscv32.cpp:60
gpr_x1
@ gpr_x1
Definition RegisterContextDarwin_riscv32.cpp:31
gpr_x23
@ gpr_x23
Definition RegisterContextDarwin_riscv32.cpp:53
gpr_x7
@ gpr_x7
Definition RegisterContextDarwin_riscv32.cpp:37
gpr_x22
@ gpr_x22
Definition RegisterContextDarwin_riscv32.cpp:52
gpr_x14
@ gpr_x14
Definition RegisterContextDarwin_riscv32.cpp:44
gpr_x21
@ gpr_x21
Definition RegisterContextDarwin_riscv32.cpp:51
gpr_x17
@ gpr_x17
Definition RegisterContextDarwin_riscv32.cpp:47
gpr_x31
@ gpr_x31
Definition RegisterContextDarwin_riscv32.cpp:61
gpr_x18
@ gpr_x18
Definition RegisterContextDarwin_riscv32.cpp:48
gpr_x25
@ gpr_x25
Definition RegisterContextDarwin_riscv32.cpp:55
gpr_x19
@ gpr_x19
Definition RegisterContextDarwin_riscv32.cpp:49
gpr_x10
@ gpr_x10
Definition RegisterContextDarwin_riscv32.cpp:40
LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_RA
Definition lldb-defines.h:59
LLDB_REGNUM_GENERIC_ARG8
#define LLDB_REGNUM_GENERIC_ARG8
Definition lldb-defines.h:75
LLDB_REGNUM_GENERIC_ARG6
#define LLDB_REGNUM_GENERIC_ARG6
Definition lldb-defines.h:71
LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_SP
Definition lldb-defines.h:57
LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG4
Definition lldb-defines.h:67
LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG3
Definition lldb-defines.h:65
LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG1
Definition lldb-defines.h:61
LLDB_REGNUM_GENERIC_ARG7
#define LLDB_REGNUM_GENERIC_ARG7
Definition lldb-defines.h:73
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition lldb-defines.h:87
LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_ARG2
Definition lldb-defines.h:63
LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_PC
Definition lldb-defines.h:56
LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_FP
Definition lldb-defines.h:58
LLDB_REGNUM_GENERIC_ARG5
#define LLDB_REGNUM_GENERIC_ARG5
Definition lldb-defines.h:69
lldb_private::RegisterInfo
Every register is described in detail including its name, alternate name (optional),...
Definition lldb-private-types.h:37
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