9#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
21#error GPR_OFFSET must be defined before including this header file
24#ifndef GPR_OFFSET_NAME
25#error GPR_OFFSET_NAME must be defined before including this header file
29#error FPU_OFFSET must be defined before including this header file
32#ifndef FPU_OFFSET_NAME
33#error FPU_OFFSET_NAME must be defined before including this header file
36#ifndef EXC_OFFSET_NAME
37#error EXC_OFFSET_NAME must be defined before including this header file
40#ifndef DBG_OFFSET_NAME
41#error DBG_OFFSET_NAME must be defined before including this header file
45#error DEFINE_DBG must be defined before including this header file
49#define GPR_W_PSEUDO_REG_ENDIAN_OFFSET 0
50#define FPU_S_PSEUDO_REG_ENDIAN_OFFSET 0
51#define FPU_D_PSEUDO_REG_ENDIAN_OFFSET 0
460#define MISC_KIND(reg, type, generic_kind) \
462 arm64_ehframe::reg, arm64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM, \
467#define LLDB_KIND(lldb_kind) \
469 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
470 LLDB_INVALID_REGNUM, lldb_kind \
474#define KIND_ALL_INVALID \
476 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
477 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM \
481#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
482#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
483#define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, LLDB_REGNUM_GENERIC_FLAGS)
484#define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
485#define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
490#define DEFINE_GPR64(reg, generic_kind) \
492 #reg, nullptr, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint, \
493 lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr, \
498#define DEFINE_GPR64_ALT(reg, alt, generic_kind) \
500 #reg, #alt, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint, \
501 lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr, \
506#define DEFINE_GPR32(wreg, xreg) \
509 GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, \
510 lldb::eEncodingUint, lldb::eFormatHex, LLDB_KIND(gpr_##wreg), \
511 g_contained_##xreg, g_##wreg##_invalidates, nullptr, \
515#define DEFINE_VREG(reg) \
517 #reg, nullptr, 16, FPU_OFFSET(fpu_##reg - fpu_v0), lldb::eEncodingVector, \
518 lldb::eFormatVectorOfUInt8, VREG_KIND(reg), nullptr, nullptr, nullptr, \
522#define DEFINE_FPU_PSEUDO(reg, size, offset, vreg) \
524 #reg, nullptr, size, FPU_OFFSET(fpu_##vreg - fpu_v0) + offset, \
525 lldb::eEncodingIEEE754, lldb::eFormatFloat, LLDB_KIND(fpu_##reg), \
526 g_contained_##vreg, g_##reg##_invalidates, nullptr, \
530#define DEFINE_MISC_REGS(reg, size, TYPE, lldb_kind) \
532 #reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint, \
533 lldb::eFormatHex, MISC_##TYPE##_KIND(lldb_kind), nullptr, nullptr, \
538#define DEFINE_EXTENSION_REG(reg) \
540 #reg, nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
541 KIND_ALL_INVALID, nullptr, nullptr, nullptr, \
585 DEFINE_GPR32(w0, x0),
586 DEFINE_GPR32(w1, x1),
587 DEFINE_GPR32(w2, x2),
588 DEFINE_GPR32(w3, x3),
589 DEFINE_GPR32(w4, x4),
590 DEFINE_GPR32(w5, x5),
591 DEFINE_GPR32(w6, x6),
592 DEFINE_GPR32(w7, x7),
593 DEFINE_GPR32(w8, x8),
594 DEFINE_GPR32(w9, x9),
595 DEFINE_GPR32(w10, x10),
596 DEFINE_GPR32(w11, x11),
597 DEFINE_GPR32(w12, x12),
598 DEFINE_GPR32(w13, x13),
599 DEFINE_GPR32(w14, x14),
600 DEFINE_GPR32(w15, x15),
601 DEFINE_GPR32(w16, x16),
602 DEFINE_GPR32(w17, x17),
603 DEFINE_GPR32(w18, x18),
604 DEFINE_GPR32(w19,
x19),
605 DEFINE_GPR32(w20,
x20),
606 DEFINE_GPR32(w21,
x21),
607 DEFINE_GPR32(w22,
x22),
608 DEFINE_GPR32(w23,
x23),
609 DEFINE_GPR32(w24,
x24),
610 DEFINE_GPR32(w25,
x25),
611 DEFINE_GPR32(w26,
x26),
612 DEFINE_GPR32(w27,
x27),
613 DEFINE_GPR32(w28,
x28),
650 DEFINE_FPU_PSEUDO(s0, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v0),
651 DEFINE_FPU_PSEUDO(s1, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v1),
652 DEFINE_FPU_PSEUDO(s2, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v2),
653 DEFINE_FPU_PSEUDO(s3, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v3),
654 DEFINE_FPU_PSEUDO(s4, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v4),
655 DEFINE_FPU_PSEUDO(s5, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v5),
656 DEFINE_FPU_PSEUDO(s6, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v6),
657 DEFINE_FPU_PSEUDO(s7, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v7),
658 DEFINE_FPU_PSEUDO(s8, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
v8),
659 DEFINE_FPU_PSEUDO(s9, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
v9),
660 DEFINE_FPU_PSEUDO(s10, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
v10),
661 DEFINE_FPU_PSEUDO(s11, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
v11),
662 DEFINE_FPU_PSEUDO(s12, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
v12),
663 DEFINE_FPU_PSEUDO(s13, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
v13),
664 DEFINE_FPU_PSEUDO(s14, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
v14),
665 DEFINE_FPU_PSEUDO(s15, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
v15),
666 DEFINE_FPU_PSEUDO(s16, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v16),
667 DEFINE_FPU_PSEUDO(s17, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v17),
668 DEFINE_FPU_PSEUDO(s18, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v18),
669 DEFINE_FPU_PSEUDO(s19, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v19),
670 DEFINE_FPU_PSEUDO(s20, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v20),
671 DEFINE_FPU_PSEUDO(s21, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v21),
672 DEFINE_FPU_PSEUDO(s22, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v22),
673 DEFINE_FPU_PSEUDO(s23, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v23),
674 DEFINE_FPU_PSEUDO(s24, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v24),
675 DEFINE_FPU_PSEUDO(s25, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v25),
676 DEFINE_FPU_PSEUDO(s26, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v26),
677 DEFINE_FPU_PSEUDO(s27, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v27),
678 DEFINE_FPU_PSEUDO(s28, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v28),
679 DEFINE_FPU_PSEUDO(s29, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v29),
680 DEFINE_FPU_PSEUDO(s30, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v30),
681 DEFINE_FPU_PSEUDO(s31, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v31),
683 DEFINE_FPU_PSEUDO(d0, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v0),
684 DEFINE_FPU_PSEUDO(d1, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v1),
685 DEFINE_FPU_PSEUDO(d2, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v2),
686 DEFINE_FPU_PSEUDO(d3, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v3),
687 DEFINE_FPU_PSEUDO(d4, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v4),
688 DEFINE_FPU_PSEUDO(d5, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v5),
689 DEFINE_FPU_PSEUDO(d6, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v6),
690 DEFINE_FPU_PSEUDO(d7, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v7),
691 DEFINE_FPU_PSEUDO(d8, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
v8),
692 DEFINE_FPU_PSEUDO(d9, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
v9),
693 DEFINE_FPU_PSEUDO(d10, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
v10),
694 DEFINE_FPU_PSEUDO(d11, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
v11),
695 DEFINE_FPU_PSEUDO(d12, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
v12),
696 DEFINE_FPU_PSEUDO(d13, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
v13),
697 DEFINE_FPU_PSEUDO(d14, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
v14),
698 DEFINE_FPU_PSEUDO(d15, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
v15),
699 DEFINE_FPU_PSEUDO(d16, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v16),
700 DEFINE_FPU_PSEUDO(d17, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v17),
701 DEFINE_FPU_PSEUDO(d18, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v18),
702 DEFINE_FPU_PSEUDO(d19, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v19),
703 DEFINE_FPU_PSEUDO(d20, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v20),
704 DEFINE_FPU_PSEUDO(d21, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v21),
705 DEFINE_FPU_PSEUDO(d22, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v22),
706 DEFINE_FPU_PSEUDO(d23, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v23),
707 DEFINE_FPU_PSEUDO(d24, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v24),
708 DEFINE_FPU_PSEUDO(d25, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v25),
709 DEFINE_FPU_PSEUDO(d26, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v26),
710 DEFINE_FPU_PSEUDO(d27, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v27),
711 DEFINE_FPU_PSEUDO(d28, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v28),
712 DEFINE_FPU_PSEUDO(d29, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v29),
713 DEFINE_FPU_PSEUDO(d30, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v30),
714 DEFINE_FPU_PSEUDO(d31, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v31),
717 DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
718 DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
719 DEFINE_MISC_REGS(far, 8, EXC,
exc_far),
720 DEFINE_MISC_REGS(esr, 4, EXC, exc_esr),
#define DEFINE_DBG(re, y)
#define LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_ARG8
#define LLDB_REGNUM_GENERIC_ARG6
#define LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG7
#define LLDB_INVALID_REGNUM
#define LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_ARG5
Every register is described in detail including its name, alternate name (optional),...