18#include "llvm/Support/CheckedArithmetic.h"
27#define GPR_OFFSET(idx) ((idx)*8)
28#define GPR_OFFSET_NAME(reg) 0
29#define FPU_OFFSET(idx) ((idx)*16)
30#define FPU_OFFSET_NAME(reg) 0
31#define EXC_OFFSET_NAME(reg) 0
32#define DBG_OFFSET_NAME(reg) 0
33#define DBG_OFFSET_NAME(reg) 0
34#define DEFINE_DBG(re, y) \
35 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
36 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
37 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM}, \
38 nullptr, nullptr, nullptr
40#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
44#include "llvm/ADT/STLExtras.h"
45#include "llvm/Support/MathExtras.h"
55 if (reg_num >= std::size(g_register_infos_arm64_le))
57 return g_register_infos_arm64_le[reg_num];
61#define VFPv1 (1u << 1)
62#define VFPv2 (1u << 2)
63#define VFPv3 (1u << 3)
64#define AdvancedSIMD (1u << 4)
66#define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
67#define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
68#define VFPv2v3 (VFPv2 | VFPv3)
70#define UInt(x) ((uint64_t)x)
71#define SInt(x) ((int64_t)x)
74#define integer int64_t
76static inline bool IsZero(uint64_t x) {
return x == 0; }
78static inline uint64_t
NOT(uint64_t x) {
return ~x; }
120 return "Emulate instructions for the ARM64 architecture.";
128 if (arch.
GetTriple().getArch() == llvm::Triple::aarch64 ||
129 arch.
GetTriple().getArch() == llvm::Triple::aarch64_32) {
138 if (arch.
GetTriple().getArch() == llvm::Triple::arm)
140 else if (arch.
GetTriple().getArch() == llvm::Triple::thumb)
146std::optional<RegisterInfo>
188 {0xff000000, 0xd1000000,
No_VFP,
190 "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"},
191 {0xff000000, 0xf1000000,
No_VFP,
193 "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}"},
194 {0xff000000, 0x91000000,
No_VFP,
196 "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"},
197 {0xff000000, 0xb1000000,
No_VFP,
199 "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}"},
201 {0xff000000, 0x51000000,
No_VFP,
203 "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"},
204 {0xff000000, 0x71000000,
No_VFP,
206 "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"},
207 {0xff000000, 0x11000000,
No_VFP,
209 "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"},
210 {0xff000000, 0x31000000,
No_VFP,
212 "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"},
214 {0xffc00000, 0x29000000,
No_VFP,
215 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
216 "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"},
217 {0xffc00000, 0xa9000000,
No_VFP,
218 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
219 "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"},
220 {0xffc00000, 0x2d000000,
No_VFP,
221 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
222 "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]"},
223 {0xffc00000, 0x6d000000,
No_VFP,
224 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
225 "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"},
226 {0xffc00000, 0xad000000,
No_VFP,
227 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
228 "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"},
230 {0xffc00000, 0x29800000,
No_VFP,
231 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
232 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
233 {0xffc00000, 0xa9800000,
No_VFP,
234 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
235 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
236 {0xffc00000, 0x2d800000,
No_VFP,
237 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
238 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"},
239 {0xffc00000, 0x6d800000,
No_VFP,
240 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
241 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
242 {0xffc00000, 0xad800000,
No_VFP,
243 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
244 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
246 {0xffc00000, 0x28800000,
No_VFP,
247 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
248 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
249 {0xffc00000, 0xa8800000,
No_VFP,
250 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
251 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
252 {0xffc00000, 0x2c800000,
No_VFP,
253 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
254 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"},
255 {0xffc00000, 0x6c800000,
No_VFP,
256 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
257 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
258 {0xffc00000, 0xac800000,
No_VFP,
259 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
260 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
262 {0xffc00000, 0x29400000,
No_VFP,
263 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
264 "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"},
265 {0xffc00000, 0xa9400000,
No_VFP,
266 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
267 "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"},
268 {0xffc00000, 0x2d400000,
No_VFP,
269 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
270 "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]"},
271 {0xffc00000, 0x6d400000,
No_VFP,
272 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
273 "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"},
274 {0xffc00000, 0xad400000,
No_VFP,
275 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
276 "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"},
278 {0xffc00000, 0x29c00000,
No_VFP,
279 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
280 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
281 {0xffc00000, 0xa9c00000,
No_VFP,
282 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
283 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
284 {0xffc00000, 0x2dc00000,
No_VFP,
285 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
286 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"},
287 {0xffc00000, 0x6dc00000,
No_VFP,
288 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
289 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
290 {0xffc00000, 0xadc00000,
No_VFP,
291 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
292 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
294 {0xffc00000, 0x28c00000,
No_VFP,
295 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
296 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
297 {0xffc00000, 0xa8c00000,
No_VFP,
298 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
299 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
300 {0xffc00000, 0x2cc00000,
No_VFP,
301 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
302 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"},
303 {0xffc00000, 0x6cc00000,
No_VFP,
304 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
305 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
306 {0xffc00000, 0xacc00000,
No_VFP,
307 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
308 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
310 {0xffe00c00, 0xb8000400,
No_VFP,
311 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
312 "STR <Wt>, [<Xn|SP>], #<simm>"},
313 {0xffe00c00, 0xf8000400,
No_VFP,
314 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
315 "STR <Xt>, [<Xn|SP>], #<simm>"},
316 {0xffe00c00, 0xb8000c00,
No_VFP,
317 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
318 "STR <Wt>, [<Xn|SP>, #<simm>]!"},
319 {0xffe00c00, 0xf8000c00,
No_VFP,
320 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
321 "STR <Xt>, [<Xn|SP>, #<simm>]!"},
322 {0xffc00000, 0xb9000000,
No_VFP,
323 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
324 "STR <Wt>, [<Xn|SP>{, #<pimm>}]"},
325 {0xffc00000, 0xf9000000,
No_VFP,
326 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
327 "STR <Xt>, [<Xn|SP>{, #<pimm>}]"},
329 {0xffe00c00, 0xb8400400,
No_VFP,
330 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
331 "LDR <Wt>, [<Xn|SP>], #<simm>"},
332 {0xffe00c00, 0xf8400400,
No_VFP,
333 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
334 "LDR <Xt>, [<Xn|SP>], #<simm>"},
335 {0xffe00c00, 0xb8400c00,
No_VFP,
336 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
337 "LDR <Wt>, [<Xn|SP>, #<simm>]!"},
338 {0xffe00c00, 0xf8400c00,
No_VFP,
339 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
340 "LDR <Xt>, [<Xn|SP>, #<simm>]!"},
341 {0xffc00000, 0xb9400000,
No_VFP,
342 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
343 "LDR <Wt>, [<Xn|SP>{, #<pimm>}]"},
344 {0xffc00000, 0xf9400000,
No_VFP,
345 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
346 "LDR <Xt>, [<Xn|SP>{, #<pimm>}]"},
353 "CBZ <Wt>, <label>"},
355 "CBNZ <Wt>, <label>"},
357 "TBZ <R><t>, #<imm>, <label>"},
359 "TBNZ <R><t>, #<imm>, <label>"},
362 static const size_t k_num_arm_opcodes = std::size(g_opcodes);
364 for (
size_t i = 0; i < k_num_arm_opcodes; ++i) {
365 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value)
366 return &g_opcodes[i];
372 bool success =
false;
391 if (opcode_data ==
nullptr)
394 const bool auto_advance_pc =
395 evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
397 evaluate_options & eEmulateInstructionOptionIgnoreConditions;
399 bool success =
false;
407 if (auto_advance_pc) {
415 success = (this->*opcode_data->
callback)(opcode);
419 if (auto_advance_pc) {
425 if (new_pc_value == orig_pc_value) {
445 row->GetCFAValue().SetIsRegisterPlusOffset(
gpr_sp_arm64, 0);
476 Hint_Branch(branch_type);
479 _PC = ZeroExtend(target);
485 if target<55> ==
'1' && TCR_EL1.TBI1 ==
'1' then
486 target<63:56> =
'11111111';
487 if target<55> ==
'0' && TCR_EL1.TBI0 ==
'1' then
488 target<63:56> =
'00000000';
490 if TCR_EL2.TBI ==
'1' then
491 target<63:56> =
'00000000';
493 if TCR_EL3.TBI ==
'1' then
494 target<63:56> =
'00000000';
506 }
else if (N == 64) {
562 uint64_t unsigned_sum =
UInt(x) +
UInt(y) +
UInt(carry_in);
563 std::optional<int64_t> signed_sum = llvm::checkedAdd(
SInt(x),
SInt(y));
564 bool overflow = !signed_sum;
566 overflow |= !llvm::checkedAdd(*signed_sum,
SInt(carry_in));
567 uint64_t result = unsigned_sum;
569 result =
Bits64(result, N - 1, 0);
570 proc_state.
N =
Bit64(result, N - 1);
572 proc_state.
C =
UInt(result) != unsigned_sum;
573 proc_state.
V = overflow;
621 bool success =
false;
625 const uint32_t datasize = (sf == 1) ? 64 : 32;
626 boolean sub_op = op == 1;
627 boolean setflags = S == 1;
635 imm =
static_cast<uint64_t
>(imm12) << 12;
643 uint64_t operand2 = imm;
647 operand2 =
NOT(operand2);
656 result =
AddWithCarry(datasize, operand1, operand2, carry_in, proc_state);
666 std::optional<RegisterInfo> reg_info_Rn =
692template <EmulateInstructionARM64::AddrMode a_mode>
708 boolean vector = (V == 1);
710 boolean is_signed =
false;
712 boolean wb_unknown =
false;
713 boolean rt_unknown =
false;
721 scale = 2 +
UInt(opc);
723 scale = (opc & 2) ? 3 : 2;
724 is_signed = (opc & 1) != 0;
729 if (!vector && wback && ((t == n) || (t2 == n))) {
765 idx =
LSL(llvm::SignExtend64<7>(imm7), scale);
767 uint64_t datasize = size * 8;
771 std::optional<RegisterInfo> reg_info_base =
776 std::optional<RegisterInfo> reg_info_Rt;
777 std::optional<RegisterInfo> reg_info_Rt2;
787 if (!reg_info_Rt || !reg_info_Rt2)
790 bool success =
false;
799 wb_address = address + idx;
801 address = wb_address;
825 std::optional<RegisterValue> data_Rt =
ReadRegister(*reg_info_Rt);
829 if (data_Rt->GetAsMemoryData(*reg_info_Rt, buffer, reg_info_Rt->byte_size,
833 if (!
WriteMemory(context_t, address + 0, buffer, reg_info_Rt->byte_size))
836 std::optional<RegisterValue> data_Rt2 =
ReadRegister(*reg_info_Rt2);
840 if (data_Rt2->GetAsMemoryData(*reg_info_Rt2, buffer,
845 if (!
WriteMemory(context_t2, address + size, buffer,
846 reg_info_Rt2->byte_size))
865 memset(buffer,
'U', reg_info_Rt->byte_size);
867 if (!
ReadMemory(context_t, address, buffer, reg_info_Rt->byte_size))
876 if (!vector && is_signed && !data_Rt.
SignExtend(datasize))
883 if (!
ReadMemory(context_t2, address + size, buffer,
884 reg_info_Rt2->byte_size))
894 if (!vector && is_signed && !data_Rt2.
SignExtend(datasize))
919template <EmulateInstructionARM64::AddrMode a_mode>
934 offset = llvm::SignExtend64<9>(
Bits32(opcode, 20, 12));
939 offset = llvm::SignExtend64<9>(
Bits32(opcode, 20, 12));
944 offset =
LSL(
Bits32(opcode, 21, 10), size);
950 if (
Bit32(opc, 1) == 0) {
954 if (size == 2 &&
Bit32(opc, 0) == 1)
959 bool success =
false;
976 std::optional<RegisterInfo> reg_info_base =
981 std::optional<RegisterInfo> reg_info_Rt =
996 postindex ? 0 : offset);
998 std::optional<RegisterValue> data_Rt =
ReadRegister(*reg_info_Rt);
1002 if (data_Rt->GetAsMemoryData(*reg_info_Rt, buffer, reg_info_Rt->byte_size,
1006 if (!
WriteMemory(context, address, buffer, reg_info_Rt->byte_size))
1019 if (!
ReadMemory(context, address, buffer, reg_info_Rt->byte_size))
1054 BranchTo(PC[] + offset, branch_type);
1057 bool success =
false;
1066 int64_t offset = llvm::SignExtend64<28>(
Bits32(opcode, 25, 0) << 2);
1071 switch (branch_type) {
1083 return BranchTo(context, 64, target);
1089 bits(64) offset = SignExtend(imm19:
'00', 64);
1090 bits(4) condition = cond;
1096 bool success =
false;
1103 int64_t offset = llvm::SignExtend64<21>(
Bits32(opcode, 23, 5) << 2);
1109 if (!
BranchTo(context, 64, target))
1118 integer datasize =
if sf ==
'1' then 64
else 32;
1119 boolean iszero = (op ==
'0');
1120 bits(64) offset = SignExtend(imm19:
'00', 64);
1122 bits(datasize) operand1 = X[t];
1123 if IsZero(operand1) == iszero then
1127 bool success =
false;
1130 bool is_zero =
Bit32(opcode, 24) == 0;
1131 int32_t offset = llvm::SignExtend64<21>(
Bits32(opcode, 23, 5) << 2);
1133 const uint64_t operand =
1156 integer datasize =
if b5 ==
'1' then 64
else 32;
1159 bits(64) offset = SignExtend(imm14:
'00', 64);
1162 bool success =
false;
1167 int64_t offset = llvm::SignExtend64<16>(
Bits32(opcode, 18, 5) << 2);
1169 const uint64_t operand =
static llvm::raw_ostream & error(Stream &strm)
EmulateInstructionARM64::ConstraintType ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which)
static uint64_t NOT(uint64_t x)
static uint64_t LSL(uint64_t x, integer shift)
static std::optional< RegisterInfo > LLDBTableGetRegisterInfo(uint32_t reg_num)
static bool IsZero(uint64_t x)
#define LLDB_PLUGIN_DEFINE_ADV(ClassName, PluginName)
bool EmulateLDRSTRImm(const uint32_t opcode)
std::optional< lldb_private::RegisterInfo > GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num) override
static bool SupportsEmulatingInstructionsOfTypeStatic(lldb_private::InstructionType inst_type)
bool ReadInstruction() override
static llvm::StringRef GetPluginNameStatic()
bool EmulateLDPSTP(const uint32_t opcode)
bool EmulateTBZ(const uint32_t opcode)
bool EmulateBcond(const uint32_t opcode)
static Opcode * GetOpcodeForInstruction(const uint32_t opcode)
@ Unpredictable_LDPOVERLAP
@ Unpredictable_WBOVERLAP
ProcState m_opcode_pstate
bool BranchTo(const Context &context, uint32_t N, lldb::addr_t target)
bool EmulateCBZ(const uint32_t opcode)
bool SetTargetTriple(const lldb_private::ArchSpec &arch) override
bool CreateFunctionEntryUnwind(lldb_private::UnwindPlan &unwind_plan) override
bool EvaluateInstruction(uint32_t evaluate_options) override
static llvm::StringRef GetPluginDescriptionStatic()
bool EmulateADDSUBImm(const uint32_t opcode)
bool ConditionHolds(const uint32_t cond)
bool EmulateB(const uint32_t opcode)
ProcState m_emulated_pstate
uint32_t GetFramePointerRegisterNumber() const
static lldb_private::EmulateInstruction * CreateInstance(const lldb_private::ArchSpec &arch, lldb_private::InstructionType inst_type)
static uint64_t AddWithCarry(uint32_t N, uint64_t x, uint64_t y, bool carry_in, EmulateInstructionARM64::ProcState &proc_state)
An architecture specification class.
llvm::Triple & GetTriple()
Architecture triple accessor.
"lldb/Core/EmulateInstruction.h" A class that allows emulation of CPU opcodes.
@ eContextRelativeBranchImmediate
@ eContextSetFramePointer
@ eContextAdjustBaseRegister
@ eContextAdjustStackPointer
@ eContextRestoreStackPointer
@ eContextPushRegisterOnStack
@ eContextPopRegisterOffStack
lldb::ByteOrder GetByteOrder() const
size_t ReadMemory(const Context &context, lldb::addr_t addr, void *dst, size_t dst_len)
std::optional< RegisterValue > ReadRegister(const RegisterInfo ®_info)
bool WriteRegister(const Context &context, const RegisterInfo &ref_info, const RegisterValue ®_value)
bool WriteRegisterUnsigned(const Context &context, const RegisterInfo ®_info, uint64_t reg_value)
bool WriteMemory(const Context &context, lldb::addr_t addr, const void *src, size_t src_len)
uint64_t ReadMemoryUnsigned(const Context &context, lldb::addr_t addr, size_t byte_size, uint64_t fail_value, bool *success_ptr)
uint64_t ReadRegisterUnsigned(const RegisterInfo ®_info, uint64_t fail_value, bool *success_ptr)
static bool RegisterPlugin(llvm::StringRef name, llvm::StringRef description, ABICreateInstance create_callback)
static bool UnregisterPlugin(ABICreateInstance create_callback)
bool SignExtend(uint32_t sign_bitpos)
uint32_t SetFromMemoryData(const RegisterInfo ®_info, const void *src, uint32_t src_len, lldb::ByteOrder src_byte_order, Status &error)
void SetUnwindPlanForSignalTrap(lldb_private::LazyBool is_for_signal_trap)
void SetRegisterKind(lldb::RegisterKind kind)
void SetReturnAddressRegister(uint32_t regnum)
void AppendRow(const RowSP &row_sp)
std::shared_ptr< Row > RowSP
void SetSourcedFromCompiler(lldb_private::LazyBool from_compiler)
void SetSourceName(const char *)
void SetUnwindPlanValidAtAllInstructions(lldb_private::LazyBool valid_at_all_insn)
#define LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_FLAGS
#define LLDB_INVALID_ADDRESS
#define LLDB_INVALID_REGNUM
#define LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_FP
A class that represents a running process on the host machine.
static uint64_t Bits64(const uint64_t bits, const uint32_t msbit, const uint32_t lsbit)
InstructionType
Instruction types.
static uint64_t UnsignedBits(const uint64_t value, const uint64_t msbit, const uint64_t lsbit)
static uint32_t Bits32(const uint32_t bits, const uint32_t msbit, const uint32_t lsbit)
static uint64_t Bit64(const uint64_t bits, const uint32_t bit)
static uint32_t bits(const uint32_t val, const uint32_t msbit, const uint32_t lsbit)
static uint32_t Bit32(const uint32_t bits, const uint32_t bit)
RegisterKind
Register numbering types.
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target
@ eRegisterKindLLDB
lldb's internal register numbers
bool(EmulateInstructionARM64::* callback)(const uint32_t opcode)
void SetRegisterPlusOffset(RegisterInfo base_reg, int64_t signed_offset)
void SetImmediateSigned(int64_t signed_immediate)
void SetRegisterToRegisterPlusOffset(RegisterInfo data_reg, RegisterInfo base_reg, int64_t offset)
void SetAddress(lldb::addr_t address)