59 llvm::ArrayRef<RegData *> subregs,
uint32_t base_size,
62 for (
const RegData *subreg : subregs) {
64 uint32_t base_index = *subreg->base_index;
91 llvm::ArrayRef<RegData *> subregs1,
92 llvm::ArrayRef<RegData *> subregs2,
uint32_t base_size,
94 for (
auto it : llvm::zip(subregs1, subregs2)) {
96 std::tie(regdata1, regdata2) = it;
106 if (regs[base_index1].byte_size != base_size ||
107 regs[base_index2].byte_size != base_size)
122 {base_index1, base_index2},
129 typedef llvm::SmallDenseMap<llvm::StringRef, llvm::SmallVector<RegData, 4>, 64>
134 is64bit ? BaseRegToRegsMap::value_type("r" l "x", \
135 {{GPR32, "e" l "x", std::nullopt}, \
136 {GPR16, l "x", std::nullopt}, \
137 {GPR8h, l "h", std::nullopt}, \
138 {GPR8, l "l", std::nullopt}}) \
139 : BaseRegToRegsMap::value_type("e" l "x", \
140 {{GPR16, l "x", std::nullopt}, \
141 {GPR8h, l "h", std::nullopt}, \
142 {GPR8, l "l", std::nullopt}}) \
147 is64bit ? BaseRegToRegsMap::value_type("r" r16, \
148 {{GPR32, "e" r16, std::nullopt}, \
149 {GPR16, r16, std::nullopt}, \
150 {GPR8, r16 "l", std::nullopt}}) \
151 : BaseRegToRegsMap::value_type( \
153 {{GPR16, r16, std::nullopt}, {GPR8, r16 "l", std::nullopt}}) \
158 BaseRegToRegsMap::value_type("r" #n, {{GPR32, "r" #n "d", std::nullopt}, \
159 {GPR16, "r" #n "w", std::nullopt}, \
160 {GPR8, "r" #n "l", std::nullopt}}) \
164 { BaseRegToRegsMap::value_type("st" #n, {{MM, "mm" #n, std::nullopt}}) }
167 {BaseRegToRegsMap::value_type("ymm" #n "h", \
168 {{YMM_YMMh, "ymm" #n, std::nullopt}})}, \
170 BaseRegToRegsMap::value_type("xmm" #n, \
171 {{YMM_XMM, "ymm" #n, std::nullopt}}) \
194 out.insert(amd64_regs.begin(), amd64_regs.end());
201 std::vector<DynamicRegisterInfo::Register> ®s) {
202 MCBasedABI::AugmentRegisterInfo(regs);
204 ProcessSP process_sp = GetProcessSP();
209 process_sp->GetTarget().GetArchitecture().GetAddressByteSize();
214 llvm::SmallDenseSet<llvm::StringRef, 64> subreg_name_set;
217 std::array<llvm::SmallVector<RegData *, 16>, RegKindCount> subreg_by_kind;
220 for (
const auto &x : base_reg_map) {
221 for (
const auto &subreg : x.second)
222 subreg_name_set.insert(subreg.subreg_name);
226 for (
const auto &x : llvm::enumerate(regs)) {
227 llvm::StringRef reg_name = x.value().name.GetStringRef();
229 if (llvm::is_contained(subreg_name_set, reg_name))
232 auto found = base_reg_map.find(reg_name);
233 if (found == base_reg_map.end())
236 for (
auto &subreg : found->second) {
238 subreg.base_index = x.index();
240 subreg_by_kind[
static_cast<size_t>(subreg.subreg_kind)].push_back(