42 addr_t mask = process_sp->GetCodeAddressMask();
46 mask = process_sp->GetHighmemCodeAddressMask();
59 addr_t mask = process_sp->GetDataAddressMask();
63 mask = process_sp->GetHighmemDataAddressMask();
70std::pair<uint32_t, uint32_t>
87 return llvm::StringSwitch<uint32_t>(name)
105 std::vector<lldb_private::DynamicRegisterInfo::Register> ®s,
106 llvm::ArrayRef<std::optional<uint32_t>> full_reg_indices,
107 uint32_t full_reg_size,
const char *partial_reg_format,
109 for (
auto it : llvm::enumerate(full_reg_indices)) {
110 std::optional<uint32_t> full_reg_index = it.value();
111 if (!full_reg_index || regs[*full_reg_index].byte_size != full_reg_size)
116 llvm::formatv(partial_reg_format, it.index()).str()),
134 std::vector<lldb_private::DynamicRegisterInfo::Register> ®s) {
139 std::array<std::optional<uint32_t>, 32> x_regs;
140 std::array<std::optional<uint32_t>, 32> v_regs;
141 std::array<std::optional<uint32_t>, 32> z_regs;
142 std::optional<uint32_t> z_byte_size;
144 for (
auto it : llvm::enumerate(regs)) {
150 unsigned int reg_num;
151 auto get_reg = [&info, ®_num](
const char *prefix) {
154 return (reg_name.consume_front(prefix) &&
155 llvm::to_integer(reg_name, reg_num, 10) && reg_num < 32) ||
156 (alt_name.consume_front(prefix) &&
157 llvm::to_integer(alt_name, reg_num, 10) && reg_num < 32);
161 x_regs[reg_num] = it.index();
162 else if (get_reg(
"v"))
163 v_regs[reg_num] = it.index();
164 else if (get_reg(
"z")) {
165 z_regs[reg_num] = it.index();
170 else if (get_reg(
"w") || get_reg(
"s") || get_reg(
"d"))
180 auto bool_predicate = [](
const auto ®_num) {
return bool(reg_num); };
181 bool saw_v_regs = llvm::any_of(v_regs, bool_predicate);
182 bool saw_z_regs = llvm::any_of(z_regs, bool_predicate);
190 }
else if (saw_z_regs && z_byte_size) {
217 plan_sp->AppendRow(std::move(row));
218 plan_sp->SetSourceName(
"arm64 at-func-entry default");
220 plan_sp->SetUnwindPlanValidAtAllInstructions(
eLazyBoolNo);
227 const int32_t ptr_size = 8;
234 ptr_size * -2,
true);
236 ptr_size * -1,
true);
239 plan_sp->AppendRow(std::move(row));
240 plan_sp->SetSourceName(
"arm64 default unwind plan");
242 plan_sp->SetUnwindPlanValidAtAllInstructions(
eLazyBoolNo);
static void addPartialRegisters(std::vector< lldb_private::DynamicRegisterInfo::Register > ®s, llvm::ArrayRef< std::optional< uint32_t > > full_reg_indices, uint32_t full_reg_size, const char *partial_reg_format, uint32_t partial_reg_size, lldb::Encoding encoding, lldb::Format format)
constexpr addr_t pac_sign_extension
#define LLDB_PLUGIN_DEFINE(PluginName)
lldb::UnwindPlanSP CreateDefaultUnwindPlan() override
lldb::addr_t FixDataAddress(lldb::addr_t pc) override
lldb::addr_t FixCodeAddress(lldb::addr_t pc) override
Some targets might use bits in a code address to indicate a mode switch.
uint32_t GetGenericNum(llvm::StringRef name) override
Return the generic number of the given register.
virtual lldb::addr_t FixAddress(lldb::addr_t pc, lldb::addr_t mask)
void AugmentRegisterInfo(std::vector< lldb_private::DynamicRegisterInfo::Register > ®s) override
lldb::UnwindPlanSP CreateFunctionEntryUnwindPlan() override
std::pair< uint32_t, uint32_t > GetEHAndDWARFNums(llvm::StringRef name) override
Return eh_frame and dwarf numbers for the given register.
std::string GetMCName(std::string reg) override
For the given (capitalized) lldb register name, return the name of this register in the MCRegisterInf...
lldb::ProcessSP GetProcessSP() const
Request to get a Process shared pointer.
A uniqued constant string class.
void SetCString(const char *cstr)
Set the C string value.
llvm::StringRef GetStringRef() const
Get the string value as a llvm::StringRef.
void AugmentRegisterInfo(std::vector< DynamicRegisterInfo::Register > ®s) override
virtual std::pair< uint32_t, uint32_t > GetEHAndDWARFNums(llvm::StringRef reg)
Return eh_frame and dwarf numbers for the given register.
static void MapRegisterName(std::string ®, llvm::StringRef from_prefix, llvm::StringRef to_prefix)
If the register name is of the form "<from_prefix>[<number>]" then change the name to "<to_prefix>[<n...
void SetIsRegisterPlusOffset(uint32_t reg_num, int32_t offset)
bool SetRegisterLocationToAtCFAPlusOffset(uint32_t reg_num, int32_t offset, bool can_replace)
const FAValue & GetCFAValue() const
bool SetRegisterLocationToRegister(uint32_t reg_num, uint32_t other_reg_num, bool can_replace)
void SetUnspecifiedRegistersAreUndefined(bool unspec_is_undef)
#define LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_ARG8
#define LLDB_INVALID_ADDRESS_MASK
Address Mask Bits not used for addressing are set to 1 in the mask; all mask bits set is an invalid v...
#define LLDB_REGNUM_GENERIC_ARG6
#define LLDB_INVALID_INDEX32
#define LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG7
#define LLDB_REGNUM_GENERIC_FLAGS
#define LLDB_INVALID_REGNUM
#define LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_ARG5
A class that represents a running process on the host machine.
void addSupplementaryRegister(std::vector< DynamicRegisterInfo::Register > ®s, DynamicRegisterInfo::Register new_reg_info)
Format
Display format definitions.
std::shared_ptr< lldb_private::Process > ProcessSP
Encoding
Register encoding definitions.
@ eEncodingVector
vector registers
@ eEncodingUint
unsigned integer
std::shared_ptr< lldb_private::UnwindPlan > UnwindPlanSP
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target