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EmulateInstructionMIPS64.cpp
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1 //===-- EmulateInstructionMIPS64.cpp --------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "EmulateInstructionMIPS64.h"
10 
11 #include <cstdlib>
12 
13 #include "lldb/Core/Address.h"
14 #include "lldb/Core/Opcode.h"
15 #include "lldb/Core/PluginManager.h"
16 #include "lldb/Host/PosixApi.h"
17 #include "lldb/Symbol/UnwindPlan.h"
18 #include "lldb/Utility/ArchSpec.h"
19 #include "lldb/Utility/ConstString.h"
20 #include "lldb/Utility/DataExtractor.h"
21 #include "lldb/Utility/RegisterValue.h"
22 #include "lldb/Utility/Stream.h"
23 #include "llvm-c/Disassembler.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/MC/MCTargetOptions.h"
32 #include "llvm/MC/TargetRegistry.h"
33 #include "llvm/Support/TargetSelect.h"
34 
35 #include "llvm/ADT/STLExtras.h"
36 
37 #include "Plugins/Process/Utility/InstructionUtils.h"
38 #include "Plugins/Process/Utility/RegisterContext_mips.h"
39 
40 using namespace lldb;
41 using namespace lldb_private;
42 
43 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionMIPS64, InstructionMIPS64)
44 
45 #define UInt(x) ((uint64_t)x)
46 #define integer int64_t
47 
48 //
49 // EmulateInstructionMIPS64 implementation
50 //
51 
52 #ifdef __mips__
53 extern "C" {
54 void LLVMInitializeMipsTargetInfo();
55 void LLVMInitializeMipsTarget();
56 void LLVMInitializeMipsAsmPrinter();
57 void LLVMInitializeMipsTargetMC();
58 void LLVMInitializeMipsDisassembler();
59 }
60 #endif
61 
62 EmulateInstructionMIPS64::EmulateInstructionMIPS64(
63  const lldb_private::ArchSpec &arch)
64  : EmulateInstruction(arch) {
65  /* Create instance of llvm::MCDisassembler */
66  std::string Status;
67  llvm::Triple triple = arch.GetTriple();
68  const llvm::Target *target =
69  llvm::TargetRegistry::lookupTarget(triple.getTriple(), Status);
70 
71 /*
72  * If we fail to get the target then we haven't registered it. The
73  * SystemInitializerCommon
74  * does not initialize targets, MCs and disassemblers. However we need the
75  * MCDisassembler
76  * to decode the instructions so that the decoding complexity stays with LLVM.
77  * Initialize the MIPS targets and disassemblers.
78 */
79 #ifdef __mips__
80  if (!target) {
81  LLVMInitializeMipsTargetInfo();
82  LLVMInitializeMipsTarget();
83  LLVMInitializeMipsAsmPrinter();
84  LLVMInitializeMipsTargetMC();
85  LLVMInitializeMipsDisassembler();
86  target = llvm::TargetRegistry::lookupTarget(triple.getTriple(), Status);
87  }
88 #endif
89 
90  assert(target);
91 
92  llvm::StringRef cpu;
93 
94  switch (arch.GetCore()) {
95  case ArchSpec::eCore_mips32:
96  case ArchSpec::eCore_mips32el:
97  cpu = "mips32";
98  break;
99  case ArchSpec::eCore_mips32r2:
100  case ArchSpec::eCore_mips32r2el:
101  cpu = "mips32r2";
102  break;
103  case ArchSpec::eCore_mips32r3:
104  case ArchSpec::eCore_mips32r3el:
105  cpu = "mips32r3";
106  break;
107  case ArchSpec::eCore_mips32r5:
108  case ArchSpec::eCore_mips32r5el:
109  cpu = "mips32r5";
110  break;
111  case ArchSpec::eCore_mips32r6:
112  case ArchSpec::eCore_mips32r6el:
113  cpu = "mips32r6";
114  break;
115  case ArchSpec::eCore_mips64:
116  case ArchSpec::eCore_mips64el:
117  cpu = "mips64";
118  break;
119  case ArchSpec::eCore_mips64r2:
120  case ArchSpec::eCore_mips64r2el:
121  cpu = "mips64r2";
122  break;
123  case ArchSpec::eCore_mips64r3:
124  case ArchSpec::eCore_mips64r3el:
125  cpu = "mips64r3";
126  break;
127  case ArchSpec::eCore_mips64r5:
128  case ArchSpec::eCore_mips64r5el:
129  cpu = "mips64r5";
130  break;
131  case ArchSpec::eCore_mips64r6:
132  case ArchSpec::eCore_mips64r6el:
133  cpu = "mips64r6";
134  break;
135  default:
136  cpu = "generic";
137  break;
138  }
139 
140  std::string features;
141  uint32_t arch_flags = arch.GetFlags();
142  if (arch_flags & ArchSpec::eMIPSAse_msa)
143  features += "+msa,";
144  if (arch_flags & ArchSpec::eMIPSAse_dsp)
145  features += "+dsp,";
146  if (arch_flags & ArchSpec::eMIPSAse_dspr2)
147  features += "+dspr2,";
148  if (arch_flags & ArchSpec::eMIPSAse_mips16)
149  features += "+mips16,";
150  if (arch_flags & ArchSpec::eMIPSAse_micromips)
151  features += "+micromips,";
152 
153  m_reg_info.reset(target->createMCRegInfo(triple.getTriple()));
154  assert(m_reg_info.get());
155 
156  m_insn_info.reset(target->createMCInstrInfo());
157  assert(m_insn_info.get());
158 
159  llvm::MCTargetOptions MCOptions;
160  m_asm_info.reset(
161  target->createMCAsmInfo(*m_reg_info, triple.getTriple(), MCOptions));
162  m_subtype_info.reset(
163  target->createMCSubtargetInfo(triple.getTriple(), cpu, features));
164  assert(m_asm_info.get() && m_subtype_info.get());
165 
166  m_context = std::make_unique<llvm::MCContext>(
167  triple, m_asm_info.get(), m_reg_info.get(), m_subtype_info.get());
168  assert(m_context.get());
169 
170  m_disasm.reset(target->createMCDisassembler(*m_subtype_info, *m_context));
171  assert(m_disasm.get());
172 }
173 
174 void EmulateInstructionMIPS64::Initialize() {
175  PluginManager::RegisterPlugin(GetPluginNameStatic(),
176  GetPluginDescriptionStatic(), CreateInstance);
177 }
178 
179 void EmulateInstructionMIPS64::Terminate() {
180  PluginManager::UnregisterPlugin(CreateInstance);
181 }
182 
183 llvm::StringRef EmulateInstructionMIPS64::GetPluginDescriptionStatic() {
184  return "Emulate instructions for the MIPS64 architecture.";
185 }
186 
187 EmulateInstruction *
188 EmulateInstructionMIPS64::CreateInstance(const ArchSpec &arch,
189  InstructionType inst_type) {
190  if (EmulateInstructionMIPS64::SupportsEmulatingInstructionsOfTypeStatic(
191  inst_type)) {
192  if (arch.GetTriple().getArch() == llvm::Triple::mips64 ||
193  arch.GetTriple().getArch() == llvm::Triple::mips64el) {
194  return new EmulateInstructionMIPS64(arch);
195  }
196  }
197 
198  return nullptr;
199 }
200 
201 bool EmulateInstructionMIPS64::SetTargetTriple(const ArchSpec &arch) {
202  return arch.GetTriple().getArch() == llvm::Triple::mips64 ||
203  arch.GetTriple().getArch() == llvm::Triple::mips64el;
204 }
205 
206 const char *EmulateInstructionMIPS64::GetRegisterName(unsigned reg_num,
207  bool alternate_name) {
208  if (alternate_name) {
209  switch (reg_num) {
210  case dwarf_sp_mips64:
211  return "r29";
212  case dwarf_r30_mips64:
213  return "r30";
214  case dwarf_ra_mips64:
215  return "r31";
216  case dwarf_f0_mips64:
217  return "f0";
218  case dwarf_f1_mips64:
219  return "f1";
220  case dwarf_f2_mips64:
221  return "f2";
222  case dwarf_f3_mips64:
223  return "f3";
224  case dwarf_f4_mips64:
225  return "f4";
226  case dwarf_f5_mips64:
227  return "f5";
228  case dwarf_f6_mips64:
229  return "f6";
230  case dwarf_f7_mips64:
231  return "f7";
232  case dwarf_f8_mips64:
233  return "f8";
234  case dwarf_f9_mips64:
235  return "f9";
236  case dwarf_f10_mips64:
237  return "f10";
238  case dwarf_f11_mips64:
239  return "f11";
240  case dwarf_f12_mips64:
241  return "f12";
242  case dwarf_f13_mips64:
243  return "f13";
244  case dwarf_f14_mips64:
245  return "f14";
246  case dwarf_f15_mips64:
247  return "f15";
248  case dwarf_f16_mips64:
249  return "f16";
250  case dwarf_f17_mips64:
251  return "f17";
252  case dwarf_f18_mips64:
253  return "f18";
254  case dwarf_f19_mips64:
255  return "f19";
256  case dwarf_f20_mips64:
257  return "f20";
258  case dwarf_f21_mips64:
259  return "f21";
260  case dwarf_f22_mips64:
261  return "f22";
262  case dwarf_f23_mips64:
263  return "f23";
264  case dwarf_f24_mips64:
265  return "f24";
266  case dwarf_f25_mips64:
267  return "f25";
268  case dwarf_f26_mips64:
269  return "f26";
270  case dwarf_f27_mips64:
271  return "f27";
272  case dwarf_f28_mips64:
273  return "f28";
274  case dwarf_f29_mips64:
275  return "f29";
276  case dwarf_f30_mips64:
277  return "f30";
278  case dwarf_f31_mips64:
279  return "f31";
280  case dwarf_w0_mips64:
281  return "w0";
282  case dwarf_w1_mips64:
283  return "w1";
284  case dwarf_w2_mips64:
285  return "w2";
286  case dwarf_w3_mips64:
287  return "w3";
288  case dwarf_w4_mips64:
289  return "w4";
290  case dwarf_w5_mips64:
291  return "w5";
292  case dwarf_w6_mips64:
293  return "w6";
294  case dwarf_w7_mips64:
295  return "w7";
296  case dwarf_w8_mips64:
297  return "w8";
298  case dwarf_w9_mips64:
299  return "w9";
300  case dwarf_w10_mips64:
301  return "w10";
302  case dwarf_w11_mips64:
303  return "w11";
304  case dwarf_w12_mips64:
305  return "w12";
306  case dwarf_w13_mips64:
307  return "w13";
308  case dwarf_w14_mips64:
309  return "w14";
310  case dwarf_w15_mips64:
311  return "w15";
312  case dwarf_w16_mips64:
313  return "w16";
314  case dwarf_w17_mips64:
315  return "w17";
316  case dwarf_w18_mips64:
317  return "w18";
318  case dwarf_w19_mips64:
319  return "w19";
320  case dwarf_w20_mips64:
321  return "w20";
322  case dwarf_w21_mips64:
323  return "w21";
324  case dwarf_w22_mips64:
325  return "w22";
326  case dwarf_w23_mips64:
327  return "w23";
328  case dwarf_w24_mips64:
329  return "w24";
330  case dwarf_w25_mips64:
331  return "w25";
332  case dwarf_w26_mips64:
333  return "w26";
334  case dwarf_w27_mips64:
335  return "w27";
336  case dwarf_w28_mips64:
337  return "w28";
338  case dwarf_w29_mips64:
339  return "w29";
340  case dwarf_w30_mips64:
341  return "w30";
342  case dwarf_w31_mips64:
343  return "w31";
344  case dwarf_mir_mips64:
345  return "mir";
346  case dwarf_mcsr_mips64:
347  return "mcsr";
348  case dwarf_config5_mips64:
349  return "config5";
350  default:
351  break;
352  }
353  return nullptr;
354  }
355 
356  switch (reg_num) {
357  case dwarf_zero_mips64:
358  return "r0";
359  case dwarf_r1_mips64:
360  return "r1";
361  case dwarf_r2_mips64:
362  return "r2";
363  case dwarf_r3_mips64:
364  return "r3";
365  case dwarf_r4_mips64:
366  return "r4";
367  case dwarf_r5_mips64:
368  return "r5";
369  case dwarf_r6_mips64:
370  return "r6";
371  case dwarf_r7_mips64:
372  return "r7";
373  case dwarf_r8_mips64:
374  return "r8";
375  case dwarf_r9_mips64:
376  return "r9";
377  case dwarf_r10_mips64:
378  return "r10";
379  case dwarf_r11_mips64:
380  return "r11";
381  case dwarf_r12_mips64:
382  return "r12";
383  case dwarf_r13_mips64:
384  return "r13";
385  case dwarf_r14_mips64:
386  return "r14";
387  case dwarf_r15_mips64:
388  return "r15";
389  case dwarf_r16_mips64:
390  return "r16";
391  case dwarf_r17_mips64:
392  return "r17";
393  case dwarf_r18_mips64:
394  return "r18";
395  case dwarf_r19_mips64:
396  return "r19";
397  case dwarf_r20_mips64:
398  return "r20";
399  case dwarf_r21_mips64:
400  return "r21";
401  case dwarf_r22_mips64:
402  return "r22";
403  case dwarf_r23_mips64:
404  return "r23";
405  case dwarf_r24_mips64:
406  return "r24";
407  case dwarf_r25_mips64:
408  return "r25";
409  case dwarf_r26_mips64:
410  return "r26";
411  case dwarf_r27_mips64:
412  return "r27";
413  case dwarf_gp_mips64:
414  return "gp";
415  case dwarf_sp_mips64:
416  return "sp";
417  case dwarf_r30_mips64:
418  return "fp";
419  case dwarf_ra_mips64:
420  return "ra";
421  case dwarf_sr_mips64:
422  return "sr";
423  case dwarf_lo_mips64:
424  return "lo";
425  case dwarf_hi_mips64:
426  return "hi";
427  case dwarf_bad_mips64:
428  return "bad";
429  case dwarf_cause_mips64:
430  return "cause";
431  case dwarf_pc_mips64:
432  return "pc";
433  case dwarf_f0_mips64:
434  return "f0";
435  case dwarf_f1_mips64:
436  return "f1";
437  case dwarf_f2_mips64:
438  return "f2";
439  case dwarf_f3_mips64:
440  return "f3";
441  case dwarf_f4_mips64:
442  return "f4";
443  case dwarf_f5_mips64:
444  return "f5";
445  case dwarf_f6_mips64:
446  return "f6";
447  case dwarf_f7_mips64:
448  return "f7";
449  case dwarf_f8_mips64:
450  return "f8";
451  case dwarf_f9_mips64:
452  return "f9";
453  case dwarf_f10_mips64:
454  return "f10";
455  case dwarf_f11_mips64:
456  return "f11";
457  case dwarf_f12_mips64:
458  return "f12";
459  case dwarf_f13_mips64:
460  return "f13";
461  case dwarf_f14_mips64:
462  return "f14";
463  case dwarf_f15_mips64:
464  return "f15";
465  case dwarf_f16_mips64:
466  return "f16";
467  case dwarf_f17_mips64:
468  return "f17";
469  case dwarf_f18_mips64:
470  return "f18";
471  case dwarf_f19_mips64:
472  return "f19";
473  case dwarf_f20_mips64:
474  return "f20";
475  case dwarf_f21_mips64:
476  return "f21";
477  case dwarf_f22_mips64:
478  return "f22";
479  case dwarf_f23_mips64:
480  return "f23";
481  case dwarf_f24_mips64:
482  return "f24";
483  case dwarf_f25_mips64:
484  return "f25";
485  case dwarf_f26_mips64:
486  return "f26";
487  case dwarf_f27_mips64:
488  return "f27";
489  case dwarf_f28_mips64:
490  return "f28";
491  case dwarf_f29_mips64:
492  return "f29";
493  case dwarf_f30_mips64:
494  return "f30";
495  case dwarf_f31_mips64:
496  return "f31";
497  case dwarf_fcsr_mips64:
498  return "fcsr";
499  case dwarf_fir_mips64:
500  return "fir";
501  case dwarf_w0_mips64:
502  return "w0";
503  case dwarf_w1_mips64:
504  return "w1";
505  case dwarf_w2_mips64:
506  return "w2";
507  case dwarf_w3_mips64:
508  return "w3";
509  case dwarf_w4_mips64:
510  return "w4";
511  case dwarf_w5_mips64:
512  return "w5";
513  case dwarf_w6_mips64:
514  return "w6";
515  case dwarf_w7_mips64:
516  return "w7";
517  case dwarf_w8_mips64:
518  return "w8";
519  case dwarf_w9_mips64:
520  return "w9";
521  case dwarf_w10_mips64:
522  return "w10";
523  case dwarf_w11_mips64:
524  return "w11";
525  case dwarf_w12_mips64:
526  return "w12";
527  case dwarf_w13_mips64:
528  return "w13";
529  case dwarf_w14_mips64:
530  return "w14";
531  case dwarf_w15_mips64:
532  return "w15";
533  case dwarf_w16_mips64:
534  return "w16";
535  case dwarf_w17_mips64:
536  return "w17";
537  case dwarf_w18_mips64:
538  return "w18";
539  case dwarf_w19_mips64:
540  return "w19";
541  case dwarf_w20_mips64:
542  return "w20";
543  case dwarf_w21_mips64:
544  return "w21";
545  case dwarf_w22_mips64:
546  return "w22";
547  case dwarf_w23_mips64:
548  return "w23";
549  case dwarf_w24_mips64:
550  return "w24";
551  case dwarf_w25_mips64:
552  return "w25";
553  case dwarf_w26_mips64:
554  return "w26";
555  case dwarf_w27_mips64:
556  return "w27";
557  case dwarf_w28_mips64:
558  return "w28";
559  case dwarf_w29_mips64:
560  return "w29";
561  case dwarf_w30_mips64:
562  return "w30";
563  case dwarf_w31_mips64:
564  return "w31";
565  case dwarf_mcsr_mips64:
566  return "mcsr";
567  case dwarf_mir_mips64:
568  return "mir";
569  case dwarf_config5_mips64:
570  return "config5";
571  }
572  return nullptr;
573 }
574 
575 llvm::Optional<RegisterInfo>
576 EmulateInstructionMIPS64::GetRegisterInfo(RegisterKind reg_kind,
577  uint32_t reg_num) {
578  if (reg_kind == eRegisterKindGeneric) {
579  switch (reg_num) {
580  case LLDB_REGNUM_GENERIC_PC:
581  reg_kind = eRegisterKindDWARF;
582  reg_num = dwarf_pc_mips64;
583  break;
584  case LLDB_REGNUM_GENERIC_SP:
585  reg_kind = eRegisterKindDWARF;
586  reg_num = dwarf_sp_mips64;
587  break;
588  case LLDB_REGNUM_GENERIC_FP:
589  reg_kind = eRegisterKindDWARF;
590  reg_num = dwarf_r30_mips64;
591  break;
592  case LLDB_REGNUM_GENERIC_RA:
593  reg_kind = eRegisterKindDWARF;
594  reg_num = dwarf_ra_mips64;
595  break;
596  case LLDB_REGNUM_GENERIC_FLAGS:
597  reg_kind = eRegisterKindDWARF;
598  reg_num = dwarf_sr_mips64;
599  break;
600  default:
601  return {};
602  }
603  }
604 
605  if (reg_kind == eRegisterKindDWARF) {
606  RegisterInfo reg_info;
607  ::memset(&reg_info, 0, sizeof(RegisterInfo));
608  ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
609 
610  if (reg_num == dwarf_sr_mips64 || reg_num == dwarf_fcsr_mips64 ||
611  reg_num == dwarf_fir_mips64 || reg_num == dwarf_mcsr_mips64 ||
612  reg_num == dwarf_mir_mips64 || reg_num == dwarf_config5_mips64) {
613  reg_info.byte_size = 4;
614  reg_info.format = eFormatHex;
615  reg_info.encoding = eEncodingUint;
616  } else if ((int)reg_num >= dwarf_zero_mips64 &&
617  (int)reg_num <= dwarf_f31_mips64) {
618  reg_info.byte_size = 8;
619  reg_info.format = eFormatHex;
620  reg_info.encoding = eEncodingUint;
621  } else if ((int)reg_num >= dwarf_w0_mips64 &&
622  (int)reg_num <= dwarf_w31_mips64) {
623  reg_info.byte_size = 16;
624  reg_info.format = eFormatVectorOfUInt8;
625  reg_info.encoding = eEncodingVector;
626  } else {
627  return {};
628  }
629 
630  reg_info.name = GetRegisterName(reg_num, false);
631  reg_info.alt_name = GetRegisterName(reg_num, true);
632  reg_info.kinds[eRegisterKindDWARF] = reg_num;
633 
634  switch (reg_num) {
635  case dwarf_r30_mips64:
636  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
637  break;
638  case dwarf_ra_mips64:
639  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
640  break;
641  case dwarf_sp_mips64:
642  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
643  break;
644  case dwarf_pc_mips64:
645  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
646  break;
647  case dwarf_sr_mips64:
648  reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
649  break;
650  default:
651  break;
652  }
653  return reg_info;
654  }
655  return {};
656 }
657 
658 EmulateInstructionMIPS64::MipsOpcode *
659 EmulateInstructionMIPS64::GetOpcodeForInstruction(llvm::StringRef op_name) {
660  static EmulateInstructionMIPS64::MipsOpcode g_opcodes[] = {
661  // Prologue/Epilogue instructions
662  {"DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu,
663  "DADDIU rt, rs, immediate"},
664  {"ADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu,
665  "ADDIU rt, rs, immediate"},
666  {"SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt, offset(rs)"},
667  {"LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt, offset(base)"},
668  {"DSUBU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU,
669  "DSUBU rd, rs, rt"},
670  {"SUBU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU,
671  "SUBU rd, rs, rt"},
672  {"DADDU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU,
673  "DADDU rd, rs, rt"},
674  {"ADDU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU,
675  "ADDU rd, rs, rt"},
676  {"LUI", &EmulateInstructionMIPS64::Emulate_LUI, "LUI rt, immediate"},
677 
678  // Load/Store instructions
679  /* Following list of emulated instructions are required by implementation
680  of hardware watchpoint
681  for MIPS in lldb. As we just need the address accessed by instructions,
682  we have generalised
683  all these instructions in 2 functions depending on their addressing
684  modes */
685 
686  {"LB", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
687  "LB rt, offset(base)"},
688  {"LBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
689  "LBE rt, offset(base)"},
690  {"LBU", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
691  "LBU rt, offset(base)"},
692  {"LBUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
693  "LBUE rt, offset(base)"},
694  {"LDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
695  "LDC1 ft, offset(base)"},
696  {"LDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
697  "LDL rt, offset(base)"},
698  {"LDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
699  "LDR rt, offset(base)"},
700  {"LLD", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
701  "LLD rt, offset(base)"},
702  {"LDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
703  "LDC2 rt, offset(base)"},
704  {"LDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
705  "LDXC1 fd, index (base)"},
706  {"LH", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
707  "LH rt, offset(base)"},
708  {"LHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
709  "LHE rt, offset(base)"},
710  {"LHU", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
711  "LHU rt, offset(base)"},
712  {"LHUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
713  "LHUE rt, offset(base)"},
714  {"LL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
715  "LL rt, offset(base)"},
716  {"LLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
717  "LLE rt, offset(base)"},
718  {"LUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
719  "LUXC1 fd, index (base)"},
720  {"LW", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
721  "LW rt, offset(rs)"},
722  {"LWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
723  "LWC1 ft, offset(base)"},
724  {"LWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
725  "LWC2 rt, offset(base)"},
726  {"LWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
727  "LWE rt, offset(base)"},
728  {"LWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
729  "LWL rt, offset(base)"},
730  {"LWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
731  "LWLE rt, offset(base)"},
732  {"LWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
733  "LWR rt, offset(base)"},
734  {"LWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
735  "LWRE rt, offset(base)"},
736  {"LWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
737  "LWXC1 fd, index (base)"},
738 
739  {"SB", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
740  "SB rt, offset(base)"},
741  {"SBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
742  "SBE rt, offset(base)"},
743  {"SC", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
744  "SC rt, offset(base)"},
745  {"SCE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
746  "SCE rt, offset(base)"},
747  {"SCD", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
748  "SCD rt, offset(base)"},
749  {"SDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
750  "SDL rt, offset(base)"},
751  {"SDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
752  "SDR rt, offset(base)"},
753  {"SDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
754  "SDC1 ft, offset(base)"},
755  {"SDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
756  "SDC2 rt, offset(base)"},
757  {"SDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
758  "SDXC1 fs, index (base)"},
759  {"SH", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
760  "SH rt, offset(base)"},
761  {"SHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
762  "SHE rt, offset(base)"},
763  {"SUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
764  "SUXC1 fs, index (base)"},
765  {"SW", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
766  "SW rt, offset(rs)"},
767  {"SWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
768  "SWC1 ft, offset(base)"},
769  {"SWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
770  "SWC2 rt, offset(base)"},
771  {"SWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
772  "SWE rt, offset(base)"},
773  {"SWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
774  "SWL rt, offset(base)"},
775  {"SWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
776  "SWLE rt, offset(base)"},
777  {"SWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
778  "SWR rt, offset(base)"},
779  {"SWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
780  "SWRE rt, offset(base)"},
781  {"SWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
782  "SWXC1 fs, index (base)"},
783 
784  // Branch instructions
785  {"BEQ", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
786  {"BEQ64", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
787  {"BNE", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset"},
788  {"BNE64", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset"},
789  {"BEQL", &EmulateInstructionMIPS64::Emulate_BXX_3ops,
790  "BEQL rs,rt,offset"},
791  {"BNEL", &EmulateInstructionMIPS64::Emulate_BXX_3ops,
792  "BNEL rs,rt,offset"},
793  {"BGEZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
794  "BGEZALL rt,offset"},
795  {"BAL", &EmulateInstructionMIPS64::Emulate_BAL, "BAL offset"},
796  {"BGEZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
797  "BGEZAL rs,offset"},
798  {"BALC", &EmulateInstructionMIPS64::Emulate_BALC, "BALC offset"},
799  {"BC", &EmulateInstructionMIPS64::Emulate_BC, "BC offset"},
800  {"BGEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset"},
801  {"BGEZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset"},
802  {"BLEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
803  "BLEZALC rs,offset"},
804  {"BGEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
805  "BGEZALC rs,offset"},
806  {"BLTZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
807  "BLTZALC rs,offset"},
808  {"BGTZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
809  "BGTZALC rs,offset"},
810  {"BEQZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
811  "BEQZALC rs,offset"},
812  {"BNEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
813  "BNEZALC rs,offset"},
814  {"BEQC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
815  "BEQC rs,rt,offset"},
816  {"BEQC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
817  "BEQC rs,rt,offset"},
818  {"BNEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
819  "BNEC rs,rt,offset"},
820  {"BNEC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
821  "BNEC rs,rt,offset"},
822  {"BLTC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
823  "BLTC rs,rt,offset"},
824  {"BLTC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
825  "BLTC rs,rt,offset"},
826  {"BGEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
827  "BGEC rs,rt,offset"},
828  {"BGEC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
829  "BGEC rs,rt,offset"},
830  {"BLTUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
831  "BLTUC rs,rt,offset"},
832  {"BLTUC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
833  "BLTUC rs,rt,offset"},
834  {"BGEUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
835  "BGEUC rs,rt,offset"},
836  {"BGEUC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
837  "BGEUC rs,rt,offset"},
838  {"BLTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
839  "BLTZC rt,offset"},
840  {"BLTZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
841  "BLTZC rt,offset"},
842  {"BLEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
843  "BLEZC rt,offset"},
844  {"BLEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
845  "BLEZC rt,offset"},
846  {"BGEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
847  "BGEZC rt,offset"},
848  {"BGEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
849  "BGEZC rt,offset"},
850  {"BGTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
851  "BGTZC rt,offset"},
852  {"BGTZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
853  "BGTZC rt,offset"},
854  {"BEQZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
855  "BEQZC rt,offset"},
856  {"BEQZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
857  "BEQZC rt,offset"},
858  {"BNEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
859  "BNEZC rt,offset"},
860  {"BNEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
861  "BNEZC rt,offset"},
862  {"BGEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZL rt,offset"},
863  {"BGTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset"},
864  {"BGTZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset"},
865  {"BGTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZL rt,offset"},
866  {"BLEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset"},
867  {"BLEZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset"},
868  {"BLEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZL rt,offset"},
869  {"BLTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset"},
870  {"BLTZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset"},
871  {"BLTZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
872  "BLTZAL rt,offset"},
873  {"BLTZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
874  "BLTZALL rt,offset"},
875  {"BLTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZL rt,offset"},
876  {"BOVC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
877  "BOVC rs,rt,offset"},
878  {"BNVC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
879  "BNVC rs,rt,offset"},
880  {"J", &EmulateInstructionMIPS64::Emulate_J, "J target"},
881  {"JAL", &EmulateInstructionMIPS64::Emulate_JAL, "JAL target"},
882  {"JALX", &EmulateInstructionMIPS64::Emulate_JAL, "JALX target"},
883  {"JALR", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target"},
884  {"JALR64", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target"},
885  {"JALR_HB", &EmulateInstructionMIPS64::Emulate_JALR, "JALR.HB target"},
886  {"JIALC", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset"},
887  {"JIALC64", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset"},
888  {"JIC", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset"},
889  {"JIC64", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset"},
890  {"JR", &EmulateInstructionMIPS64::Emulate_JR, "JR target"},
891  {"JR64", &EmulateInstructionMIPS64::Emulate_JR, "JR target"},
892  {"JR_HB", &EmulateInstructionMIPS64::Emulate_JR, "JR.HB target"},
893  {"BC1F", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1F cc, offset"},
894  {"BC1T", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1T cc, offset"},
895  {"BC1FL", &EmulateInstructionMIPS64::Emulate_FP_branch,
896  "BC1FL cc, offset"},
897  {"BC1TL", &EmulateInstructionMIPS64::Emulate_FP_branch,
898  "BC1TL cc, offset"},
899  {"BC1EQZ", &EmulateInstructionMIPS64::Emulate_BC1EQZ,
900  "BC1EQZ ft, offset"},
901  {"BC1NEZ", &EmulateInstructionMIPS64::Emulate_BC1NEZ,
902  "BC1NEZ ft, offset"},
903  {"BC1ANY2F", &EmulateInstructionMIPS64::Emulate_3D_branch,
904  "BC1ANY2F cc, offset"},
905  {"BC1ANY2T", &EmulateInstructionMIPS64::Emulate_3D_branch,
906  "BC1ANY2T cc, offset"},
907  {"BC1ANY4F", &EmulateInstructionMIPS64::Emulate_3D_branch,
908  "BC1ANY4F cc, offset"},
909  {"BC1ANY4T", &EmulateInstructionMIPS64::Emulate_3D_branch,
910  "BC1ANY4T cc, offset"},
911  {"BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB, "BNZ.b wt,s16"},
912  {"BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH, "BNZ.h wt,s16"},
913  {"BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW, "BNZ.w wt,s16"},
914  {"BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD, "BNZ.d wt,s16"},
915  {"BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b wt,s16"},
916  {"BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h wt,s16"},
917  {"BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w wt,s16"},
918  {"BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d wt,s16"},
919  {"BNZ_V", &EmulateInstructionMIPS64::Emulate_BNZV, "BNZ.V wt,s16"},
920  {"BZ_V", &EmulateInstructionMIPS64::Emulate_BZV, "BZ.V wt,s16"},
921  };
922 
923  for (MipsOpcode &opcode : g_opcodes) {
924  if (op_name.equals_insensitive(opcode.op_name))
925  return &opcode;
926  }
927  return nullptr;
928 }
929 
930 bool EmulateInstructionMIPS64::ReadInstruction() {
931  bool success = false;
932  m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
933  LLDB_INVALID_ADDRESS, &success);
934  if (success) {
935  Context read_inst_context;
936  read_inst_context.type = eContextReadOpcode;
937  read_inst_context.SetNoArgs();
938  m_opcode.SetOpcode32(
939  ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success),
940  GetByteOrder());
941  }
942  if (!success)
943  m_addr = LLDB_INVALID_ADDRESS;
944  return success;
945 }
946 
947 bool EmulateInstructionMIPS64::EvaluateInstruction(uint32_t evaluate_options) {
948  bool success = false;
949  llvm::MCInst mc_insn;
950  uint64_t insn_size;
951  DataExtractor data;
952 
953  /* Keep the complexity of the decode logic with the llvm::MCDisassembler
954  * class. */
955  if (m_opcode.GetData(data)) {
956  llvm::MCDisassembler::DecodeStatus decode_status;
957  llvm::ArrayRef<uint8_t> raw_insn(data.GetDataStart(), data.GetByteSize());
958  decode_status = m_disasm->getInstruction(mc_insn, insn_size, raw_insn,
959  m_addr, llvm::nulls());
960  if (decode_status != llvm::MCDisassembler::Success)
961  return false;
962  }
963 
964  /*
965  * mc_insn.getOpcode() returns decoded opcode. However to make use
966  * of llvm::Mips::<insn> we would need "MipsGenInstrInfo.inc".
967  */
968  llvm::StringRef op_name = m_insn_info->getName(mc_insn.getOpcode());
969 
970  /*
971  * Decoding has been done already. Just get the call-back function
972  * and emulate the instruction.
973  */
974  MipsOpcode *opcode_data = GetOpcodeForInstruction(op_name);
975 
976  if (opcode_data == nullptr)
977  return false;
978 
979  uint64_t old_pc = 0, new_pc = 0;
980  const bool auto_advance_pc =
981  evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
982 
983  if (auto_advance_pc) {
984  old_pc =
985  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
986  if (!success)
987  return false;
988  }
989 
990  /* emulate instruction */
991  success = (this->*opcode_data->callback)(mc_insn);
992  if (!success)
993  return false;
994 
995  if (auto_advance_pc) {
996  new_pc =
997  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
998  if (!success)
999  return false;
1000 
1001  /* If we haven't changed the PC, change it here */
1002  if (old_pc == new_pc) {
1003  new_pc += 4;
1004  Context context;
1005  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1006  new_pc))
1007  return false;
1008  }
1009  }
1010 
1011  return true;
1012 }
1013 
1014 bool EmulateInstructionMIPS64::CreateFunctionEntryUnwind(
1015  UnwindPlan &unwind_plan) {
1016  unwind_plan.Clear();
1017  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
1018 
1019  UnwindPlan::RowSP row(new UnwindPlan::Row);
1020  const bool can_replace = false;
1021 
1022  // Our previous Call Frame Address is the stack pointer
1023  row->GetCFAValue().SetIsRegisterPlusOffset(dwarf_sp_mips64, 0);
1024 
1025  // Our previous PC is in the RA
1026  row->SetRegisterLocationToRegister(dwarf_pc_mips64, dwarf_ra_mips64,
1027  can_replace);
1028 
1029  unwind_plan.AppendRow(row);
1030 
1031  // All other registers are the same.
1032  unwind_plan.SetSourceName("EmulateInstructionMIPS64");
1033  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1034  unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
1035  unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo);
1036  unwind_plan.SetReturnAddressRegister(dwarf_ra_mips64);
1037 
1038  return true;
1039 }
1040 
1041 bool EmulateInstructionMIPS64::nonvolatile_reg_p(uint64_t regnum) {
1042  switch (regnum) {
1043  case dwarf_r16_mips64:
1044  case dwarf_r17_mips64:
1045  case dwarf_r18_mips64:
1046  case dwarf_r19_mips64:
1047  case dwarf_r20_mips64:
1048  case dwarf_r21_mips64:
1049  case dwarf_r22_mips64:
1050  case dwarf_r23_mips64:
1051  case dwarf_gp_mips64:
1052  case dwarf_sp_mips64:
1053  case dwarf_r30_mips64:
1054  case dwarf_ra_mips64:
1055  return true;
1056  default:
1057  return false;
1058  }
1059  return false;
1060 }
1061 
1062 bool EmulateInstructionMIPS64::Emulate_DADDiu(llvm::MCInst &insn) {
1063  // DADDIU rt, rs, immediate
1064  // GPR[rt] <- GPR[rs] + sign_extend(immediate)
1065 
1066  uint8_t dst, src;
1067  bool success = false;
1068  const uint32_t imm16 = insn.getOperand(2).getImm();
1069  int64_t imm = SignedBits(imm16, 15, 0);
1070 
1071  dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1072  src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1073 
1074  // If immediate is greater than 2^16 - 1 then clang generate LUI,
1075  // (D)ADDIU,(D)SUBU instructions in prolog. Example lui $1, 0x2 daddiu $1,
1076  // $1, -0x5920 dsubu $sp, $sp, $1 In this case, (D)ADDIU dst and src will be
1077  // same and not equal to sp
1078  if (dst == src) {
1079  Context context;
1080 
1081  /* read <src> register */
1082  const uint64_t src_opd_val = ReadRegisterUnsigned(
1083  eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success);
1084  if (!success)
1085  return false;
1086 
1087  /* Check if this is daddiu sp, sp, imm16 */
1088  if (dst == dwarf_sp_mips64) {
1089  /*
1090  * From the MIPS IV spec:
1091  *
1092  * The term “unsigned” in the instruction name is a misnomer; this
1093  * operation is 64-bit modulo arithmetic that does not trap on overflow.
1094  * It is appropriate for arithmetic which is not signed, such as address
1095  * arithmetic, or integer arithmetic environments that ignore overflow,
1096  * such as “C” language arithmetic.
1097  *
1098  * Assume 2's complement and rely on unsigned overflow here.
1099  */
1100  uint64_t result = src_opd_val + imm;
1101  llvm::Optional<RegisterInfo> reg_info_sp =
1102  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64);
1103  if (reg_info_sp)
1104  context.SetRegisterPlusOffset(*reg_info_sp, imm);
1105 
1106  /* We are allocating bytes on stack */
1107  context.type = eContextAdjustStackPointer;
1108 
1109  WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips64,
1110  result);
1111  return true;
1112  }
1113 
1114  imm += src_opd_val;
1115  context.SetImmediateSigned(imm);
1116  context.type = eContextImmediate;
1117 
1118  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF,
1119  dwarf_zero_mips64 + dst, imm))
1120  return false;
1121  }
1122 
1123  return true;
1124 }
1125 
1126 bool EmulateInstructionMIPS64::Emulate_SD(llvm::MCInst &insn) {
1127  uint64_t address;
1128  bool success = false;
1129  uint32_t imm16 = insn.getOperand(2).getImm();
1130  uint64_t imm = SignedBits(imm16, 15, 0);
1131  uint32_t src, base;
1132  Context bad_vaddr_context;
1133 
1134  src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1135  base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1136 
1137  llvm::Optional<RegisterInfo> reg_info_base =
1138  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base);
1139  llvm::Optional<RegisterInfo> reg_info_src =
1140  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src);
1141  if (!reg_info_base || !reg_info_src)
1142  return false;
1143 
1144  /* read SP */
1145  address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips64 + base,
1146  0, &success);
1147  if (!success)
1148  return false;
1149 
1150  /* destination address */
1151  address = address + imm;
1152 
1153  /* We look for sp based non-volatile register stores */
1154  if (nonvolatile_reg_p(src)) {
1155  Context context;
1156  context.type = eContextPushRegisterOnStack;
1157  context.SetRegisterToRegisterPlusOffset(*reg_info_src, *reg_info_base, 0);
1158 
1159  uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
1160  Status error;
1161 
1162  llvm::Optional<RegisterValue> data_src = ReadRegister(*reg_info_base);
1163  if (!data_src)
1164  return false;
1165 
1166  if (data_src->GetAsMemoryData(*reg_info_src, buffer,
1167  reg_info_src->byte_size, eByteOrderLittle,
1168  error) == 0)
1169  return false;
1170 
1171  if (!WriteMemory(context, address, buffer, reg_info_src->byte_size))
1172  return false;
1173  }
1174 
1175  /* Set the bad_vaddr register with base address used in the instruction */
1176  bad_vaddr_context.type = eContextInvalid;
1177  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64,
1178  address);
1179 
1180  return true;
1181 }
1182 
1183 bool EmulateInstructionMIPS64::Emulate_LD(llvm::MCInst &insn) {
1184  bool success = false;
1185  uint32_t src, base;
1186  int64_t imm, address;
1187  Context bad_vaddr_context;
1188 
1189  src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1190  base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1191  imm = insn.getOperand(2).getImm();
1192 
1193  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base))
1194  return false;
1195 
1196  /* read base register */
1197  address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips64 + base,
1198  0, &success);
1199  if (!success)
1200  return false;
1201 
1202  /* destination address */
1203  address = address + imm;
1204 
1205  /* Set the bad_vaddr register with base address used in the instruction */
1206  bad_vaddr_context.type = eContextInvalid;
1207  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64,
1208  address);
1209 
1210  if (nonvolatile_reg_p(src)) {
1211  RegisterValue data_src;
1212  llvm::Optional<RegisterInfo> reg_info_src =
1213  GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src);
1214  if (!reg_info_src)
1215  return false;
1216 
1217  Context context;
1218  context.type = eContextRegisterLoad;
1219 
1220  return WriteRegister(context, *reg_info_src, data_src);
1221  }
1222 
1223  return false;
1224 }
1225 
1226 bool EmulateInstructionMIPS64::Emulate_LUI(llvm::MCInst &insn) {
1227  // LUI rt, immediate
1228  // GPR[rt] <- sign_extend(immediate << 16)
1229 
1230  const uint32_t imm32 = insn.getOperand(1).getImm() << 16;
1231  int64_t imm = SignedBits(imm32, 31, 0);
1232  uint8_t rt;
1233  Context context;
1234 
1235  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1236  context.SetImmediateSigned(imm);
1237  context.type = eContextImmediate;
1238 
1239  return WriteRegisterUnsigned(context, eRegisterKindDWARF,
1240  dwarf_zero_mips64 + rt, imm);
1241 }
1242 
1243 bool EmulateInstructionMIPS64::Emulate_DSUBU_DADDU(llvm::MCInst &insn) {
1244  // DSUBU sp, <src>, <rt>
1245  // DADDU sp, <src>, <rt>
1246  // DADDU dst, sp, <rt>
1247 
1248  bool success = false;
1249  uint64_t result;
1250  uint8_t src, dst, rt;
1251  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1252 
1253  dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1254  src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1255 
1256  /* Check if sp is destination register */
1257  if (dst == dwarf_sp_mips64) {
1258  rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg());
1259 
1260  /* read <src> register */
1261  uint64_t src_opd_val = ReadRegisterUnsigned(
1262  eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success);
1263  if (!success)
1264  return false;
1265 
1266  /* read <rt > register */
1267  uint64_t rt_opd_val = ReadRegisterUnsigned(
1268  eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
1269  if (!success)
1270  return false;
1271 
1272  if (op_name.equals_insensitive("DSUBU") ||
1273  op_name.equals_insensitive("SUBU"))
1274  result = src_opd_val - rt_opd_val;
1275  else
1276  result = src_opd_val + rt_opd_val;
1277 
1278  Context context;
1279  llvm::Optional<RegisterInfo> reg_info_sp =
1280  GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64);
1281  if (reg_info_sp)
1282  context.SetRegisterPlusOffset(*reg_info_sp, rt_opd_val);
1283 
1284  /* We are allocating bytes on stack */
1285  context.type = eContextAdjustStackPointer;
1286 
1287  WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips64, result);
1288 
1289  return true;
1290  } else if (src == dwarf_sp_mips64) {
1291  rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg());
1292 
1293  /* read <src> register */
1294  uint64_t src_opd_val = ReadRegisterUnsigned(
1295  eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success);
1296  if (!success)
1297  return false;
1298 
1299  /* read <rt> register */
1300  uint64_t rt_opd_val = ReadRegisterUnsigned(
1301  eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
1302  if (!success)
1303  return false;
1304 
1305  Context context;
1306 
1307  if (op_name.equals_insensitive("DSUBU") ||
1308  op_name.equals_insensitive("SUBU"))
1309  result = src_opd_val - rt_opd_val;
1310  else
1311  result = src_opd_val + rt_opd_val;
1312 
1313  context.SetImmediateSigned(result);
1314  context.type = eContextImmediate;
1315 
1316  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF,
1317  dwarf_zero_mips64 + dst, result))
1318  return false;
1319  }
1320 
1321  return true;
1322 }
1323 
1324 /*
1325  Emulate below MIPS branch instructions.
1326  BEQ, BNE : Branch on condition
1327  BEQL, BNEL : Branch likely
1328 */
1329 bool EmulateInstructionMIPS64::Emulate_BXX_3ops(llvm::MCInst &insn) {
1330  bool success = false;
1331  uint32_t rs, rt;
1332  int64_t offset, pc, rs_val, rt_val, target = 0;
1333  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1334 
1335  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1336  rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1337  offset = insn.getOperand(2).getImm();
1338 
1339  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1340  if (!success)
1341  return false;
1342 
1343  rs_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1344  dwarf_zero_mips64 + rs, 0, &success);
1345  if (!success)
1346  return false;
1347 
1348  rt_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1349  dwarf_zero_mips64 + rt, 0, &success);
1350  if (!success)
1351  return false;
1352 
1353  if (op_name.equals_insensitive("BEQ") || op_name.equals_insensitive("BEQL") ||
1354  op_name.equals_insensitive("BEQ64")) {
1355  if (rs_val == rt_val)
1356  target = pc + offset;
1357  else
1358  target = pc + 8;
1359  } else if (op_name.equals_insensitive("BNE") ||
1360  op_name.equals_insensitive("BNEL") ||
1361  op_name.equals_insensitive("BNE64")) {
1362  if (rs_val != rt_val)
1363  target = pc + offset;
1364  else
1365  target = pc + 8;
1366  }
1367 
1368  Context context;
1369  context.type = eContextRelativeBranchImmediate;
1370  context.SetImmediate(offset);
1371 
1372  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1373  target);
1374 }
1375 
1376 /*
1377  Emulate below MIPS Non-Compact conditional branch and link instructions.
1378  BLTZAL, BGEZAL :
1379  BLTZALL, BGEZALL : Branch likely
1380 */
1381 bool EmulateInstructionMIPS64::Emulate_Bcond_Link(llvm::MCInst &insn) {
1382  bool success = false;
1383  uint32_t rs;
1384  int64_t offset, pc, target = 0;
1385  int64_t rs_val;
1386  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1387 
1388  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1389  offset = insn.getOperand(1).getImm();
1390 
1391  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1392  if (!success)
1393  return false;
1394 
1395  rs_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1396  dwarf_zero_mips64 + rs, 0, &success);
1397  if (!success)
1398  return false;
1399 
1400  if (op_name.equals_insensitive("BLTZAL") ||
1401  op_name.equals_insensitive("BLTZALL")) {
1402  if (rs_val < 0)
1403  target = pc + offset;
1404  else
1405  target = pc + 8;
1406  } else if (op_name.equals_insensitive("BGEZAL") ||
1407  op_name.equals_insensitive("BGEZALL")) {
1408  if (rs_val >= 0)
1409  target = pc + offset;
1410  else
1411  target = pc + 8;
1412  }
1413 
1414  Context context;
1415 
1416  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1417  target))
1418  return false;
1419 
1420  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips64,
1421  pc + 8))
1422  return false;
1423 
1424  return true;
1425 }
1426 
1427 bool EmulateInstructionMIPS64::Emulate_BAL(llvm::MCInst &insn) {
1428  bool success = false;
1429  int64_t offset, pc, target;
1430 
1431  /*
1432  * BAL offset
1433  * offset = sign_ext (offset << 2)
1434  * RA = PC + 8
1435  * PC = PC + offset
1436  */
1437  offset = insn.getOperand(0).getImm();
1438 
1439  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1440  if (!success)
1441  return false;
1442 
1443  target = pc + offset;
1444 
1445  Context context;
1446 
1447  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1448  target))
1449  return false;
1450 
1451  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips64,
1452  pc + 8))
1453  return false;
1454 
1455  return true;
1456 }
1457 
1458 bool EmulateInstructionMIPS64::Emulate_BALC(llvm::MCInst &insn) {
1459  bool success = false;
1460  int64_t offset, pc, target;
1461 
1462  /*
1463  * BALC offset
1464  * offset = sign_ext (offset << 2)
1465  * RA = PC + 4
1466  * PC = PC + 4 + offset
1467  */
1468  offset = insn.getOperand(0).getImm();
1469 
1470  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1471  if (!success)
1472  return false;
1473 
1474  target = pc + offset;
1475 
1476  Context context;
1477 
1478  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1479  target))
1480  return false;
1481 
1482  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips64,
1483  pc + 4))
1484  return false;
1485 
1486  return true;
1487 }
1488 
1489 /*
1490  Emulate below MIPS conditional branch and link instructions.
1491  BLEZALC, BGEZALC, BLTZALC, BGTZALC, BEQZALC, BNEZALC : Compact branches
1492 */
1493 bool EmulateInstructionMIPS64::Emulate_Bcond_Link_C(llvm::MCInst &insn) {
1494  bool success = false;
1495  uint32_t rs;
1496  int64_t offset, pc, rs_val, target = 0;
1497  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1498 
1499  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1500  offset = insn.getOperand(1).getImm();
1501 
1502  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1503  if (!success)
1504  return false;
1505 
1506  rs_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1507  dwarf_zero_mips64 + rs, 0, &success);
1508  if (!success)
1509  return false;
1510 
1511  if (op_name.equals_insensitive("BLEZALC")) {
1512  if (rs_val <= 0)
1513  target = pc + offset;
1514  else
1515  target = pc + 4;
1516  } else if (op_name.equals_insensitive("BGEZALC")) {
1517  if (rs_val >= 0)
1518  target = pc + offset;
1519  else
1520  target = pc + 4;
1521  } else if (op_name.equals_insensitive("BLTZALC")) {
1522  if (rs_val < 0)
1523  target = pc + offset;
1524  else
1525  target = pc + 4;
1526  } else if (op_name.equals_insensitive("BGTZALC")) {
1527  if (rs_val > 0)
1528  target = pc + offset;
1529  else
1530  target = pc + 4;
1531  } else if (op_name.equals_insensitive("BEQZALC")) {
1532  if (rs_val == 0)
1533  target = pc + offset;
1534  else
1535  target = pc + 4;
1536  } else if (op_name.equals_insensitive("BNEZALC")) {
1537  if (rs_val != 0)
1538  target = pc + offset;
1539  else
1540  target = pc + 4;
1541  }
1542 
1543  Context context;
1544 
1545  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1546  target))
1547  return false;
1548 
1549  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips64,
1550  pc + 4))
1551  return false;
1552 
1553  return true;
1554 }
1555 
1556 /*
1557  Emulate below MIPS branch instructions.
1558  BLTZL, BGEZL, BGTZL, BLEZL : Branch likely
1559  BLTZ, BGEZ, BGTZ, BLEZ : Non-compact branches
1560 */
1561 bool EmulateInstructionMIPS64::Emulate_BXX_2ops(llvm::MCInst &insn) {
1562  bool success = false;
1563  uint32_t rs;
1564  int64_t offset, pc, rs_val, target = 0;
1565  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1566 
1567  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1568  offset = insn.getOperand(1).getImm();
1569 
1570  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1571  if (!success)
1572  return false;
1573 
1574  rs_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1575  dwarf_zero_mips64 + rs, 0, &success);
1576  if (!success)
1577  return false;
1578 
1579  if (op_name.equals_insensitive("BLTZL") ||
1580  op_name.equals_insensitive("BLTZ") ||
1581  op_name.equals_insensitive("BLTZ64")) {
1582  if (rs_val < 0)
1583  target = pc + offset;
1584  else
1585  target = pc + 8;
1586  } else if (op_name.equals_insensitive("BGEZL") ||
1587  op_name.equals_insensitive("BGEZ") ||
1588  op_name.equals_insensitive("BGEZ64")) {
1589  if (rs_val >= 0)
1590  target = pc + offset;
1591  else
1592  target = pc + 8;
1593  } else if (op_name.equals_insensitive("BGTZL") ||
1594  op_name.equals_insensitive("BGTZ") ||
1595  op_name.equals_insensitive("BGTZ64")) {
1596  if (rs_val > 0)
1597  target = pc + offset;
1598  else
1599  target = pc + 8;
1600  } else if (op_name.equals_insensitive("BLEZL") ||
1601  op_name.equals_insensitive("BLEZ") ||
1602  op_name.equals_insensitive("BLEZ64")) {
1603  if (rs_val <= 0)
1604  target = pc + offset;
1605  else
1606  target = pc + 8;
1607  }
1608 
1609  Context context;
1610  context.type = eContextRelativeBranchImmediate;
1611  context.SetImmediate(offset);
1612 
1613  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1614  target);
1615 }
1616 
1617 bool EmulateInstructionMIPS64::Emulate_BC(llvm::MCInst &insn) {
1618  bool success = false;
1619  int64_t offset, pc, target;
1620 
1621  /*
1622  * BC offset
1623  * offset = sign_ext (offset << 2)
1624  * PC = PC + 4 + offset
1625  */
1626  offset = insn.getOperand(0).getImm();
1627 
1628  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1629  if (!success)
1630  return false;
1631 
1632  target = pc + offset;
1633 
1634  Context context;
1635 
1636  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1637  target);
1638 }
1639 
1640 static int IsAdd64bitOverflow(int64_t a, int64_t b) {
1641  int64_t r = (uint64_t)a + (uint64_t)b;
1642  return (a < 0 && b < 0 && r >= 0) || (a >= 0 && b >= 0 && r < 0);
1643 }
1644 
1645 /*
1646  Emulate below MIPS branch instructions.
1647  BEQC, BNEC, BLTC, BGEC, BLTUC, BGEUC, BOVC, BNVC: Compact branch
1648  instructions with no delay slot
1649 */
1650 bool EmulateInstructionMIPS64::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
1651  bool success = false;
1652  uint32_t rs, rt;
1653  int64_t offset, pc, rs_val, rt_val, target = 0;
1654  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1655  uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
1656 
1657  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1658  rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1659  offset = insn.getOperand(2).getImm();
1660 
1661  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1662  if (!success)
1663  return false;
1664 
1665  rs_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1666  dwarf_zero_mips64 + rs, 0, &success);
1667  if (!success)
1668  return false;
1669 
1670  rt_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1671  dwarf_zero_mips64 + rt, 0, &success);
1672  if (!success)
1673  return false;
1674 
1675  if (op_name.equals_insensitive("BEQC") ||
1676  op_name.equals_insensitive("BEQC64")) {
1677  if (rs_val == rt_val)
1678  target = pc + offset;
1679  else
1680  target = pc + 4;
1681  } else if (op_name.equals_insensitive("BNEC") ||
1682  op_name.equals_insensitive("BNEC64")) {
1683  if (rs_val != rt_val)
1684  target = pc + offset;
1685  else
1686  target = pc + 4;
1687  } else if (op_name.equals_insensitive("BLTC") ||
1688  op_name.equals_insensitive("BLTC64")) {
1689  if (rs_val < rt_val)
1690  target = pc + offset;
1691  else
1692  target = pc + 4;
1693  } else if (op_name.equals_insensitive("BGEC64") ||
1694  op_name.equals_insensitive("BGEC")) {
1695  if (rs_val >= rt_val)
1696  target = pc + offset;
1697  else
1698  target = pc + 4;
1699  } else if (op_name.equals_insensitive("BLTUC") ||
1700  op_name.equals_insensitive("BLTUC64")) {
1701  if (rs_val < rt_val)
1702  target = pc + offset;
1703  else
1704  target = pc + 4;
1705  } else if (op_name.equals_insensitive("BGEUC") ||
1706  op_name.equals_insensitive("BGEUC64")) {
1707  if ((uint32_t)rs_val >= (uint32_t)rt_val)
1708  target = pc + offset;
1709  else
1710  target = pc + 4;
1711  } else if (op_name.equals_insensitive("BOVC")) {
1712  if (IsAdd64bitOverflow(rs_val, rt_val))
1713  target = pc + offset;
1714  else
1715  target = pc + 4;
1716  } else if (op_name.equals_insensitive("BNVC")) {
1717  if (!IsAdd64bitOverflow(rs_val, rt_val))
1718  target = pc + offset;
1719  else
1720  target = pc + 4;
1721  }
1722 
1723  Context context;
1724  context.type = eContextRelativeBranchImmediate;
1725  context.SetImmediate(current_inst_size + offset);
1726 
1727  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1728  target);
1729 }
1730 
1731 /*
1732  Emulate below MIPS branch instructions.
1733  BLTZC, BLEZC, BGEZC, BGTZC, BEQZC, BNEZC : Compact Branches
1734 */
1735 bool EmulateInstructionMIPS64::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
1736  bool success = false;
1737  uint32_t rs;
1738  int64_t offset, pc, target = 0;
1739  int64_t rs_val;
1740  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1741  uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
1742 
1743  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1744  offset = insn.getOperand(1).getImm();
1745 
1746  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1747  if (!success)
1748  return false;
1749 
1750  rs_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1751  dwarf_zero_mips64 + rs, 0, &success);
1752  if (!success)
1753  return false;
1754 
1755  if (op_name.equals_insensitive("BLTZC") ||
1756  op_name.equals_insensitive("BLTZC64")) {
1757  if (rs_val < 0)
1758  target = pc + offset;
1759  else
1760  target = pc + 4;
1761  } else if (op_name.equals_insensitive("BLEZC") ||
1762  op_name.equals_insensitive("BLEZC64")) {
1763  if (rs_val <= 0)
1764  target = pc + offset;
1765  else
1766  target = pc + 4;
1767  } else if (op_name.equals_insensitive("BGEZC") ||
1768  op_name.equals_insensitive("BGEZC64")) {
1769  if (rs_val >= 0)
1770  target = pc + offset;
1771  else
1772  target = pc + 4;
1773  } else if (op_name.equals_insensitive("BGTZC") ||
1774  op_name.equals_insensitive("BGTZC64")) {
1775  if (rs_val > 0)
1776  target = pc + offset;
1777  else
1778  target = pc + 4;
1779  } else if (op_name.equals_insensitive("BEQZC") ||
1780  op_name.equals_insensitive("BEQZC64")) {
1781  if (rs_val == 0)
1782  target = pc + offset;
1783  else
1784  target = pc + 4;
1785  } else if (op_name.equals_insensitive("BNEZC") ||
1786  op_name.equals_insensitive("BNEZC64")) {
1787  if (rs_val != 0)
1788  target = pc + offset;
1789  else
1790  target = pc + 4;
1791  }
1792 
1793  Context context;
1794  context.type = eContextRelativeBranchImmediate;
1795  context.SetImmediate(current_inst_size + offset);
1796 
1797  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1798  target);
1799 }
1800 
1801 bool EmulateInstructionMIPS64::Emulate_J(llvm::MCInst &insn) {
1802  bool success = false;
1803  uint64_t offset, pc;
1804 
1805  /*
1806  * J offset
1807  * offset = sign_ext (offset << 2)
1808  * PC = PC[63-28] | offset
1809  */
1810  offset = insn.getOperand(0).getImm();
1811 
1812  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1813  if (!success)
1814  return false;
1815 
1816  /* This is a PC-region branch and not PC-relative */
1817  pc = (pc & 0xFFFFFFFFF0000000ULL) | offset;
1818 
1819  Context context;
1820 
1821  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1822  pc);
1823 }
1824 
1825 bool EmulateInstructionMIPS64::Emulate_JAL(llvm::MCInst &insn) {
1826  bool success = false;
1827  uint64_t offset, target, pc;
1828 
1829  /*
1830  * JAL offset
1831  * offset = sign_ext (offset << 2)
1832  * PC = PC[63-28] | offset
1833  */
1834  offset = insn.getOperand(0).getImm();
1835 
1836  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1837  if (!success)
1838  return false;
1839 
1840  /* This is a PC-region branch and not PC-relative */
1841  target = (pc & 0xFFFFFFFFF0000000ULL) | offset;
1842 
1843  Context context;
1844 
1845  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1846  target))
1847  return false;
1848 
1849  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips64,
1850  pc + 8))
1851  return false;
1852 
1853  return true;
1854 }
1855 
1856 bool EmulateInstructionMIPS64::Emulate_JALR(llvm::MCInst &insn) {
1857  bool success = false;
1858  uint32_t rs, rt;
1859  uint64_t pc, rs_val;
1860 
1861  /*
1862  * JALR rt, rs
1863  * GPR[rt] = PC + 8
1864  * PC = GPR[rs]
1865  */
1866  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1867  rs = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
1868 
1869  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1870  if (!success)
1871  return false;
1872 
1873  rs_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0,
1874  &success);
1875  if (!success)
1876  return false;
1877 
1878  Context context;
1879 
1880  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1881  rs_val))
1882  return false;
1883 
1884  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF,
1885  dwarf_zero_mips64 + rt, pc + 8))
1886  return false;
1887 
1888  return true;
1889 }
1890 
1891 bool EmulateInstructionMIPS64::Emulate_JIALC(llvm::MCInst &insn) {
1892  bool success = false;
1893  uint32_t rt;
1894  int64_t target, offset, pc, rt_val;
1895 
1896  /*
1897  * JIALC rt, offset
1898  * offset = sign_ext (offset)
1899  * PC = GPR[rt] + offset
1900  * RA = PC + 4
1901  */
1902  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1903  offset = insn.getOperand(1).getImm();
1904 
1905  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1906  if (!success)
1907  return false;
1908 
1909  rt_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1910  dwarf_zero_mips64 + rt, 0, &success);
1911  if (!success)
1912  return false;
1913 
1914  target = rt_val + offset;
1915 
1916  Context context;
1917 
1918  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1919  target))
1920  return false;
1921 
1922  if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_ra_mips64,
1923  pc + 4))
1924  return false;
1925 
1926  return true;
1927 }
1928 
1929 bool EmulateInstructionMIPS64::Emulate_JIC(llvm::MCInst &insn) {
1930  bool success = false;
1931  uint32_t rt;
1932  int64_t target, offset, rt_val;
1933 
1934  /*
1935  * JIC rt, offset
1936  * offset = sign_ext (offset)
1937  * PC = GPR[rt] + offset
1938  */
1939  rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1940  offset = insn.getOperand(1).getImm();
1941 
1942  rt_val = (int64_t)ReadRegisterUnsigned(eRegisterKindDWARF,
1943  dwarf_zero_mips64 + rt, 0, &success);
1944  if (!success)
1945  return false;
1946 
1947  target = rt_val + offset;
1948 
1949  Context context;
1950 
1951  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1952  target);
1953 }
1954 
1955 bool EmulateInstructionMIPS64::Emulate_JR(llvm::MCInst &insn) {
1956  bool success = false;
1957  uint32_t rs;
1958  uint64_t rs_val;
1959 
1960  /*
1961  * JR rs
1962  * PC = GPR[rs]
1963  */
1964  rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1965 
1966  rs_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0,
1967  &success);
1968  if (!success)
1969  return false;
1970 
1971  Context context;
1972 
1973  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
1974  rs_val);
1975 }
1976 
1977 /*
1978  Emulate Branch on FP True/False
1979  BC1F, BC1FL : Branch on FP False (L stands for branch likely)
1980  BC1T, BC1TL : Branch on FP True (L stands for branch likely)
1981 */
1982 bool EmulateInstructionMIPS64::Emulate_FP_branch(llvm::MCInst &insn) {
1983  bool success = false;
1984  uint32_t cc, fcsr;
1985  int64_t pc, offset, target = 0;
1986  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
1987 
1988  /*
1989  * BC1F cc, offset
1990  * condition <- (FPConditionCode(cc) == 0)
1991  * if condition then
1992  * offset = sign_ext (offset)
1993  * PC = PC + offset
1994  */
1995  cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
1996  offset = insn.getOperand(1).getImm();
1997 
1998  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
1999  if (!success)
2000  return false;
2001 
2002  fcsr =
2003  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
2004  if (!success)
2005  return false;
2006 
2007  /* fcsr[23], fcsr[25-31] are vaild condition bits */
2008  fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
2009 
2010  if (op_name.equals_insensitive("BC1F") ||
2011  op_name.equals_insensitive("BC1FL")) {
2012  if ((fcsr & (1 << cc)) == 0)
2013  target = pc + offset;
2014  else
2015  target = pc + 8;
2016  } else if (op_name.equals_insensitive("BC1T") ||
2017  op_name.equals_insensitive("BC1TL")) {
2018  if ((fcsr & (1 << cc)) != 0)
2019  target = pc + offset;
2020  else
2021  target = pc + 8;
2022  }
2023 
2024  Context context;
2025 
2026  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
2027  target);
2028 }
2029 
2030 bool EmulateInstructionMIPS64::Emulate_BC1EQZ(llvm::MCInst &insn) {
2031  bool success = false;
2032  uint32_t ft;
2033  uint64_t ft_val;
2034  int64_t target, pc, offset;
2035 
2036  /*
2037  * BC1EQZ ft, offset
2038  * condition <- (FPR[ft].bit0 == 0)
2039  * if condition then
2040  * offset = sign_ext (offset)
2041  * PC = PC + 4 + offset
2042  */
2043  ft = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2044  offset = insn.getOperand(1).getImm();
2045 
2046  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
2047  if (!success)
2048  return false;
2049 
2050  ft_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips64 + ft, 0,
2051  &success);
2052  if (!success)
2053  return false;
2054 
2055  if ((ft_val & 1) == 0)
2056  target = pc + 4 + offset;
2057  else
2058  target = pc + 8;
2059 
2060  Context context;
2061 
2062  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
2063  target);
2064 }
2065 
2066 bool EmulateInstructionMIPS64::Emulate_BC1NEZ(llvm::MCInst &insn) {
2067  bool success = false;
2068  uint32_t ft;
2069  uint64_t ft_val;
2070  int64_t target, pc, offset;
2071 
2072  /*
2073  * BC1NEZ ft, offset
2074  * condition <- (FPR[ft].bit0 != 0)
2075  * if condition then
2076  * offset = sign_ext (offset)
2077  * PC = PC + 4 + offset
2078  */
2079  ft = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2080  offset = insn.getOperand(1).getImm();
2081 
2082  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
2083  if (!success)
2084  return false;
2085 
2086  ft_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips64 + ft, 0,
2087  &success);
2088  if (!success)
2089  return false;
2090 
2091  if ((ft_val & 1) != 0)
2092  target = pc + 4 + offset;
2093  else
2094  target = pc + 8;
2095 
2096  Context context;
2097 
2098  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
2099  target);
2100 }
2101 
2102 /*
2103  Emulate MIPS-3D Branch instructions
2104  BC1ANY2F, BC1ANY2T : Branch on Any of Two Floating Point Condition Codes
2105  False/True
2106  BC1ANY4F, BC1ANY4T : Branch on Any of Four Floating Point Condition Codes
2107  False/True
2108 */
2109 bool EmulateInstructionMIPS64::Emulate_3D_branch(llvm::MCInst &insn) {
2110  bool success = false;
2111  uint32_t cc, fcsr;
2112  int64_t pc, offset, target = 0;
2113  llvm::StringRef op_name = m_insn_info->getName(insn.getOpcode());
2114 
2115  cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2116  offset = insn.getOperand(1).getImm();
2117 
2118  pc = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
2119  if (!success)
2120  return false;
2121 
2122  fcsr = (uint32_t)ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips64,
2123  0, &success);
2124  if (!success)
2125  return false;
2126 
2127  /* fcsr[23], fcsr[25-31] are vaild condition bits */
2128  fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
2129 
2130  if (op_name.equals_insensitive("BC1ANY2F")) {
2131  /* if any one bit is 0 */
2132  if (((fcsr >> cc) & 3) != 3)
2133  target = pc + offset;
2134  else
2135  target = pc + 8;
2136  } else if (op_name.equals_insensitive("BC1ANY2T")) {
2137  /* if any one bit is 1 */
2138  if (((fcsr >> cc) & 3) != 0)
2139  target = pc + offset;
2140  else
2141  target = pc + 8;
2142  } else if (op_name.equals_insensitive("BC1ANY4F")) {
2143  /* if any one bit is 0 */
2144  if (((fcsr >> cc) & 0xf) != 0xf)
2145  target = pc + offset;
2146  else
2147  target = pc + 8;
2148  } else if (op_name.equals_insensitive("BC1ANY4T")) {
2149  /* if any one bit is 1 */
2150  if (((fcsr >> cc) & 0xf) != 0)
2151  target = pc + offset;
2152  else
2153  target = pc + 8;
2154  }
2155 
2156  Context context;
2157 
2158  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
2159  target);
2160 }
2161 
2162 bool EmulateInstructionMIPS64::Emulate_BNZB(llvm::MCInst &insn) {
2163  return Emulate_MSA_Branch_DF(insn, 1, true);
2164 }
2165 
2166 bool EmulateInstructionMIPS64::Emulate_BNZH(llvm::MCInst &insn) {
2167  return Emulate_MSA_Branch_DF(insn, 2, true);
2168 }
2169 
2170 bool EmulateInstructionMIPS64::Emulate_BNZW(llvm::MCInst &insn) {
2171  return Emulate_MSA_Branch_DF(insn, 4, true);
2172 }
2173 
2174 bool EmulateInstructionMIPS64::Emulate_BNZD(llvm::MCInst &insn) {
2175  return Emulate_MSA_Branch_DF(insn, 8, true);
2176 }
2177 
2178 bool EmulateInstructionMIPS64::Emulate_BZB(llvm::MCInst &insn) {
2179  return Emulate_MSA_Branch_DF(insn, 1, false);
2180 }
2181 
2182 bool EmulateInstructionMIPS64::Emulate_BZH(llvm::MCInst &insn) {
2183  return Emulate_MSA_Branch_DF(insn, 2, false);
2184 }
2185 
2186 bool EmulateInstructionMIPS64::Emulate_BZW(llvm::MCInst &insn) {
2187  return Emulate_MSA_Branch_DF(insn, 4, false);
2188 }
2189 
2190 bool EmulateInstructionMIPS64::Emulate_BZD(llvm::MCInst &insn) {
2191  return Emulate_MSA_Branch_DF(insn, 8, false);
2192 }
2193 
2194 bool EmulateInstructionMIPS64::Emulate_MSA_Branch_DF(llvm::MCInst &insn,
2195  int element_byte_size,
2196  bool bnz) {
2197  bool success = false, branch_hit = true;
2198  int64_t target = 0;
2199  RegisterValue reg_value;
2200  const uint8_t *ptr = nullptr;
2201 
2202  uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2203  int64_t offset = insn.getOperand(1).getImm();
2204 
2205  int64_t pc =
2206  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
2207  if (!success)
2208  return false;
2209 
2210  if (ReadRegister(eRegisterKindDWARF, dwarf_w0_mips64 + wt, reg_value))
2211  ptr = (const uint8_t *)reg_value.GetBytes();
2212  else
2213  return false;
2214 
2215  for (int i = 0; i < 16 / element_byte_size; i++) {
2216  switch (element_byte_size) {
2217  case 1:
2218  if ((*ptr == 0 && bnz) || (*ptr != 0 && !bnz))
2219  branch_hit = false;
2220  break;
2221  case 2:
2222  if ((*(const uint16_t *)ptr == 0 && bnz) ||
2223  (*(const uint16_t *)ptr != 0 && !bnz))
2224  branch_hit = false;
2225  break;
2226  case 4:
2227  if ((*(const uint32_t *)ptr == 0 && bnz) ||
2228  (*(const uint32_t *)ptr != 0 && !bnz))
2229  branch_hit = false;
2230  break;
2231  case 8:
2232  if ((*(const uint64_t *)ptr == 0 && bnz) ||
2233  (*(const uint64_t *)ptr != 0 && !bnz))
2234  branch_hit = false;
2235  break;
2236  }
2237  if (!branch_hit)
2238  break;
2239  ptr = ptr + element_byte_size;
2240  }
2241 
2242  if (branch_hit)
2243  target = pc + offset;
2244  else
2245  target = pc + 8;
2246 
2247  Context context;
2248  context.type = eContextRelativeBranchImmediate;
2249 
2250  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
2251  target);
2252 }
2253 
2254 bool EmulateInstructionMIPS64::Emulate_BNZV(llvm::MCInst &insn) {
2255  return Emulate_MSA_Branch_V(insn, true);
2256 }
2257 
2258 bool EmulateInstructionMIPS64::Emulate_BZV(llvm::MCInst &insn) {
2259  return Emulate_MSA_Branch_V(insn, false);
2260 }
2261 
2262 bool EmulateInstructionMIPS64::Emulate_MSA_Branch_V(llvm::MCInst &insn,
2263  bool bnz) {
2264  bool success = false;
2265  int64_t target = 0;
2266  llvm::APInt wr_val = llvm::APInt::getZero(128);
2267  llvm::APInt fail_value = llvm::APInt::getMaxValue(128);
2268  llvm::APInt zero_value = llvm::APInt::getZero(128);
2269  RegisterValue reg_value;
2270 
2271  uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
2272  int64_t offset = insn.getOperand(1).getImm();
2273 
2274  int64_t pc =
2275  ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
2276  if (!success)
2277  return false;
2278 
2279  if (ReadRegister(eRegisterKindDWARF, dwarf_w0_mips64 + wt, reg_value))
2280  wr_val = reg_value.GetAsUInt128(fail_value);
2281  else
2282  return false;
2283 
2284  if ((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) ||
2285  (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz))
2286  target = pc + offset;
2287  else
2288  target = pc + 8;
2289 
2290  Context context;
2291  context.type = eContextRelativeBranchImmediate;
2292 
2293  return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
2294  target);
2295 }
2296 
2297 bool EmulateInstructionMIPS64::Emulate_LDST_Imm(llvm::MCInst &insn) {
2298  bool success = false;
2299  uint32_t base;
2300  int64_t imm, address;
2301  Context bad_vaddr_context;
2302 
2303  uint32_t num_operands = insn.getNumOperands();
2304  base =
2305  m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
2306  imm = insn.getOperand(num_operands - 1).getImm();
2307 
2308  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
2309  return false;
2310 
2311  /* read base register */
2312  address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + base, 0,
2313  &success);
2314  if (!success)
2315  return false;
2316 
2317  /* destination address */
2318  address = address + imm;
2319 
2320  /* Set the bad_vaddr register with base address used in the instruction */
2321  bad_vaddr_context.type = eContextInvalid;
2322  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
2323  address);
2324 
2325  return true;
2326 }
2327 
2328 bool EmulateInstructionMIPS64::Emulate_LDST_Reg(llvm::MCInst &insn) {
2329  bool success = false;
2330  uint32_t base, index;
2331  int64_t address, index_address;
2332  Context bad_vaddr_context;
2333 
2334  uint32_t num_operands = insn.getNumOperands();
2335  base =
2336  m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
2337  index =
2338  m_reg_info->getEncodingValue(insn.getOperand(num_operands - 1).getReg());
2339 
2340  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
2341  return false;
2342 
2343  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + index))
2344  return false;
2345 
2346  /* read base register */
2347  address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + base, 0,
2348  &success);
2349  if (!success)
2350  return false;
2351 
2352  /* read index register */
2353  index_address = ReadRegisterUnsigned(eRegisterKindDWARF,
2354  dwarf_zero_mips + index, 0, &success);
2355  if (!success)
2356  return false;
2357 
2358  /* destination address */
2359  address = address + index_address;
2360 
2361  /* Set the bad_vaddr register with base address used in the instruction */
2362  bad_vaddr_context.type = eContextInvalid;
2363  WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
2364  address);
2365 
2366  return true;
2367 }
dwarf_w24_mips64
@ dwarf_w24_mips64
Definition: RegisterContext_mips.h:230
EmulateInstructionMIPS64::Emulate_3D_branch
bool Emulate_3D_branch(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2109
dwarf_f15_mips64
@ dwarf_f15_mips64
Definition: RegisterContext_mips.h:185
dwarf_w13_mips64
@ dwarf_w13_mips64
Definition: RegisterContext_mips.h:219
dwarf_w29_mips64
@ dwarf_w29_mips64
Definition: RegisterContext_mips.h:235
EmulateInstructionMIPS64::Emulate_Bcond_Link_C
bool Emulate_Bcond_Link_C(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1493
dwarf_w31_mips64
@ dwarf_w31_mips64
Definition: RegisterContext_mips.h:237
dwarf_w8_mips64
@ dwarf_w8_mips64
Definition: RegisterContext_mips.h:214
EmulateInstructionMIPS64::Emulate_BZH
bool Emulate_BZH(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2182
EmulateInstructionMIPS64::Emulate_JALR
bool Emulate_JALR(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1856
dwarf_r18_mips64
@ dwarf_r18_mips64
Definition: RegisterContext_mips.h:150
lldb_private::UnwindPlan::AppendRow
void AppendRow(const RowSP &row_sp)
Definition: UnwindPlan.cpp:362
lldb_private::ArchSpec
Definition: ArchSpec.h:32
dwarf_w10_mips64
@ dwarf_w10_mips64
Definition: RegisterContext_mips.h:216
EmulateInstructionMIPS64::Emulate_BXX_2ops_C
bool Emulate_BXX_2ops_C(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1735
EmulateInstructionMIPS64::Emulate_MSA_Branch_DF
bool Emulate_MSA_Branch_DF(llvm::MCInst &insn, int element_byte_size, bool bnz)
Definition: EmulateInstructionMIPS64.cpp:2194
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:79
dwarf_f5_mips64
@ dwarf_f5_mips64
Definition: RegisterContext_mips.h:175
dwarf_r7_mips64
@ dwarf_r7_mips64
Definition: RegisterContext_mips.h:139
lldb_private::RegisterValue
Definition: RegisterValue.h:28
dwarf_w25_mips64
@ dwarf_w25_mips64
Definition: RegisterContext_mips.h:231
lldb_private::UnwindPlan::SetRegisterKind
void SetRegisterKind(lldb::RegisterKind kind)
Definition: UnwindPlan.h:437
lldb_private::SignedBits
static int64_t SignedBits(const uint64_t value, const uint64_t msbit, const uint64_t lsbit)
Definition: InstructionUtils.h:104
lldb::eRegisterKindDWARF
@ eRegisterKindDWARF
the register numbers seen DWARF
Definition: lldb-enumerations.h:230
EmulateInstructionMIPS64::Emulate_BXX_2ops
bool Emulate_BXX_2ops(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1561
Opcode.h
EmulateInstructionMIPS64::Emulate_DADDiu
bool Emulate_DADDiu(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1062
dwarf_w14_mips64
@ dwarf_w14_mips64
Definition: RegisterContext_mips.h:220
dwarf_r2_mips64
@ dwarf_r2_mips64
Definition: RegisterContext_mips.h:134
EmulateInstructionMIPS64::Emulate_JIC
bool Emulate_JIC(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1929
EmulateInstructionMIPS64::CreateFunctionEntryUnwind
bool CreateFunctionEntryUnwind(lldb_private::UnwindPlan &unwind_plan) override
Definition: EmulateInstructionMIPS64.cpp:1014
dwarf_r21_mips64
@ dwarf_r21_mips64
Definition: RegisterContext_mips.h:153
lldb::eRegisterKindGeneric
@ eRegisterKindGeneric
insn ptr reg, stack ptr reg, etc not specific to any particular target
Definition: lldb-enumerations.h:231
dwarf_f30_mips64
@ dwarf_f30_mips64
Definition: RegisterContext_mips.h:200
EmulateInstructionMIPS64::Emulate_BC1NEZ
bool Emulate_BC1NEZ(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2066
EmulateInstructionMIPS64::Emulate_BNZW
bool Emulate_BNZW(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2170
dwarf_r11_mips64
@ dwarf_r11_mips64
Definition: RegisterContext_mips.h:143
dwarf_f14_mips64
@ dwarf_f14_mips64
Definition: RegisterContext_mips.h:184
dwarf_r8_mips64
@ dwarf_r8_mips64
Definition: RegisterContext_mips.h:140
lldb_private::ArchSpec::GetCore
Core GetCore() const
Definition: ArchSpec.h:442
dwarf_lo_mips64
@ dwarf_lo_mips64
Definition: RegisterContext_mips.h:165
EmulateInstructionMIPS64::nonvolatile_reg_p
bool nonvolatile_reg_p(uint64_t regnum)
Definition: EmulateInstructionMIPS64.cpp:1041
dwarf_w30_mips64
@ dwarf_w30_mips64
Definition: RegisterContext_mips.h:236
lldb_private::UnwindPlan::SetUnwindPlanValidAtAllInstructions
void SetUnwindPlanValidAtAllInstructions(lldb_private::LazyBool valid_at_all_insn)
Definition: UnwindPlan.h:490
dwarf_f7_mips64
@ dwarf_f7_mips64
Definition: RegisterContext_mips.h:177
lldb_private::eLazyBoolYes
@ eLazyBoolYes
Definition: lldb-private-enumerations.h:115
dwarf_r14_mips64
@ dwarf_r14_mips64
Definition: RegisterContext_mips.h:146
lldb_private::EmulateInstruction::Context
Definition: EmulateInstruction.h:184
dwarf_r9_mips64
@ dwarf_r9_mips64
Definition: RegisterContext_mips.h:141
EmulateInstructionMIPS64::Emulate_BNZH
bool Emulate_BNZH(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2166
dwarf_fcsr_mips64
@ dwarf_fcsr_mips64
Definition: RegisterContext_mips.h:202
dwarf_f0_mips64
@ dwarf_f0_mips64
Definition: RegisterContext_mips.h:170
dwarf_f19_mips64
@ dwarf_f19_mips64
Definition: RegisterContext_mips.h:189
EmulateInstructionMIPS64::SetTargetTriple
bool SetTargetTriple(const lldb_private::ArchSpec &arch) override
Definition: EmulateInstructionMIPS64.cpp:201
lldb_private::RegisterValue::GetAsUInt128
llvm::APInt GetAsUInt128(const llvm::APInt &fail_value, bool *success_ptr=nullptr) const
Definition: RegisterValue.cpp:591
dwarf_pc_mips64
@ dwarf_pc_mips64
Definition: RegisterContext_mips.h:169
lldb_private::ArchSpec::GetFlags
uint32_t GetFlags() const
Definition: ArchSpec.h:539
EmulateInstructionMIPS64::Emulate_BXX_3ops_C
bool Emulate_BXX_3ops_C(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1650
dwarf_f6_mips64
@ dwarf_f6_mips64
Definition: RegisterContext_mips.h:176
lldb_private::UnwindPlan::SetUnwindPlanForSignalTrap
void SetUnwindPlanForSignalTrap(lldb_private::LazyBool is_for_signal_trap)
Definition: UnwindPlan.h:502
IsAdd64bitOverflow
static int IsAdd64bitOverflow(int64_t a, int64_t b)
Definition: EmulateInstructionMIPS64.cpp:1640
dwarf_r24_mips64
@ dwarf_r24_mips64
Definition: RegisterContext_mips.h:156
RegisterValue.h
EmulateInstructionMIPS64
Definition: EmulateInstructionMIPS64.h:26
lldb_private::ArchSpec::GetTriple
llvm::Triple & GetTriple()
Architecture triple accessor.
Definition: ArchSpec.h:463
pc
@ pc
Definition: CompactUnwindInfo.cpp:1251
EmulateInstructionMIPS64::Emulate_BNZD
bool Emulate_BNZD(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2174
EmulateInstructionMIPS64::Terminate
static void Terminate()
Definition: EmulateInstructionMIPS64.cpp:179
lldb_private::Opcode::SetOpcode32
void SetOpcode32(uint32_t inst, lldb::ByteOrder order)
Definition: Opcode.h:171
dwarf_r4_mips64
@ dwarf_r4_mips64
Definition: RegisterContext_mips.h:136
lldb_private::UnwindPlan::SetSourceName
void SetSourceName(const char *)
Definition: UnwindPlan.cpp:564
dwarf_r13_mips64
@ dwarf_r13_mips64
Definition: RegisterContext_mips.h:145
dwarf_fir_mips64
@ dwarf_fir_mips64
Definition: RegisterContext_mips.h:203
EmulateInstructionMIPS64::ReadInstruction
bool ReadInstruction() override
Definition: EmulateInstructionMIPS64.cpp:930
LLDB_PLUGIN_DEFINE_ADV
LLDB_PLUGIN_DEFINE_ADV(ObjectContainerUniversalMachO, ObjectContainerMachOArchive) void ObjectContainerUniversalMachO
Definition: ObjectContainerUniversalMachO.cpp:23
EmulateInstructionMIPS64::Emulate_BZV
bool Emulate_BZV(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2258
dwarf_w1_mips64
@ dwarf_w1_mips64
Definition: RegisterContext_mips.h:207
lldb_private::EmulateInstruction::eContextReadOpcode
@ eContextReadOpcode
Definition: EmulateInstruction.h:102
dwarf_w28_mips64
@ dwarf_w28_mips64
Definition: RegisterContext_mips.h:234
dwarf_w7_mips64
@ dwarf_w7_mips64
Definition: RegisterContext_mips.h:213
EmulateInstructionMIPS64::m_disasm
std::unique_ptr< llvm::MCDisassembler > m_disasm
Definition: EmulateInstructionMIPS64.h:172
EmulateInstructionMIPS64::Emulate_FP_branch
bool Emulate_FP_branch(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1982
dwarf_f28_mips64
@ dwarf_f28_mips64
Definition: RegisterContext_mips.h:198
EmulateInstructionMIPS64::m_insn_info
std::unique_ptr< llvm::MCInstrInfo > m_insn_info
Definition: EmulateInstructionMIPS64.h:177
EmulateInstructionMIPS64::Emulate_LDST_Imm
bool Emulate_LDST_Imm(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2297
dwarf_bad_mips64
@ dwarf_bad_mips64
Definition: RegisterContext_mips.h:167
dwarf_r20_mips64
@ dwarf_r20_mips64
Definition: RegisterContext_mips.h:152
LLDB_REGNUM_GENERIC_FLAGS
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:55
EmulateInstructionMIPS64::Emulate_BNZB
bool Emulate_BNZB(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2162
RegisterContext_mips.h
EmulateInstructionMIPS64::CreateInstance
static lldb_private::EmulateInstruction * CreateInstance(const lldb_private::ArchSpec &arch, lldb_private::InstructionType inst_type)
Definition: EmulateInstructionMIPS64.cpp:188
error
static llvm::raw_ostream & error(Stream &strm)
Definition: CommandReturnObject.cpp:17
lldb_private::EmulateInstruction::GetByteOrder
lldb::ByteOrder GetByteOrder() const
Definition: EmulateInstruction.h:433
dwarf_r30_mips64
@ dwarf_r30_mips64
Definition: RegisterContext_mips.h:162
dwarf_w23_mips64
@ dwarf_w23_mips64
Definition: RegisterContext_mips.h:229
lldb_private::EmulateInstruction::eContextImmediate
@ eContextImmediate
Definition: EmulateInstruction.h:106
dwarf_bad_mips
@ dwarf_bad_mips
Definition: RegisterContext_mips.h:55
dwarf_sr_mips64
@ dwarf_sr_mips64
Definition: RegisterContext_mips.h:164
EmulateInstructionMIPS64::Emulate_BZD
bool Emulate_BZD(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2190
EmulateInstructionMIPS64::Emulate_JR
bool Emulate_JR(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1955
EmulateInstructionMIPS64::GetRegisterInfo
llvm::Optional< lldb_private::RegisterInfo > GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num) override
Definition: EmulateInstructionMIPS64.cpp:576
lldb_private::DataExtractor
Definition: DataExtractor.h:48
EmulateInstructionMIPS64::Emulate_JIALC
bool Emulate_JIALC(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1891
lldb_private::UnwindPlan::SetReturnAddressRegister
void SetReturnAddressRegister(uint32_t regnum)
Definition: UnwindPlan.h:439
EmulateInstructionMIPS64::GetPluginNameStatic
static llvm::StringRef GetPluginNameStatic()
Definition: EmulateInstructionMIPS64.h:34
EmulateInstructionMIPS64::Emulate_BC
bool Emulate_BC(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1617
lldb_private::EmulateInstruction::Context::type
ContextType type
Definition: EmulateInstruction.h:185
lldb_private::RegisterValue::GetBytes
const void * GetBytes() const
Definition: RegisterValue.cpp:686
dwarf_w18_mips64
@ dwarf_w18_mips64
Definition: RegisterContext_mips.h:224
dwarf_f20_mips64
@ dwarf_f20_mips64
Definition: RegisterContext_mips.h:190
EmulateInstructionMIPS64::Emulate_BNZV
bool Emulate_BNZV(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2254
EmulateInstructionMIPS64::Emulate_BZW
bool Emulate_BZW(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2186
EmulateInstructionMIPS64::Emulate_J
bool Emulate_J(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1801
EmulateInstructionMIPS64::m_context
std::unique_ptr< llvm::MCContext > m_context
Definition: EmulateInstructionMIPS64.h:176
dwarf_zero_mips
@ dwarf_zero_mips
Definition: RegisterContext_mips.h:20
dwarf_f13_mips64
@ dwarf_f13_mips64
Definition: RegisterContext_mips.h:183
dwarf_cause_mips64
@ dwarf_cause_mips64
Definition: RegisterContext_mips.h:168
lldb_private::DataExtractor::GetDataStart
const uint8_t * GetDataStart() const
Get the data start pointer.
Definition: DataExtractor.h:422
lldb_private::UnwindPlan::SetSourcedFromCompiler
void SetSourcedFromCompiler(lldb_private::LazyBool from_compiler)
Definition: UnwindPlan.h:478
dwarf_f10_mips64
@ dwarf_f10_mips64
Definition: RegisterContext_mips.h:180
lldb::eEncodingUint
@ eEncodingUint
unsigned integer
Definition: lldb-enumerations.h:149
lldb_private::EmulateInstruction::eContextInvalid
@ eContextInvalid
Definition: EmulateInstruction.h:100
dwarf_f9_mips64
@ dwarf_f9_mips64
Definition: RegisterContext_mips.h:179
dwarf_f27_mips64
@ dwarf_f27_mips64
Definition: RegisterContext_mips.h:197
lldb_private::EmulateInstruction::Context::SetRegisterPlusOffset
void SetRegisterPlusOffset(RegisterInfo base_reg, int64_t signed_offset)
Definition: EmulateInstruction.h:249
EmulateInstructionMIPS64::MipsOpcode
Definition: EmulateInstructionMIPS64.h:82
dwarf_f22_mips64
@ dwarf_f22_mips64
Definition: RegisterContext_mips.h:192
dwarf_gp_mips64
@ dwarf_gp_mips64
Definition: RegisterContext_mips.h:160
EmulateInstructionMIPS64::Emulate_MSA_Branch_V
bool Emulate_MSA_Branch_V(llvm::MCInst &insn, bool bnz)
Definition: EmulateInstructionMIPS64.cpp:2262
dwarf_r15_mips64
@ dwarf_r15_mips64
Definition: RegisterContext_mips.h:147
dwarf_w2_mips64
@ dwarf_w2_mips64
Definition: RegisterContext_mips.h:208
lldb_private::EmulateInstruction::Context::SetRegisterToRegisterPlusOffset
void SetRegisterToRegisterPlusOffset(RegisterInfo data_reg, RegisterInfo base_reg, int64_t offset)
Definition: EmulateInstruction.h:262
EmulateInstructionMIPS64::Emulate_LDST_Reg
bool Emulate_LDST_Reg(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2328
EmulateInstructionMIPS64::Emulate_Bcond_Link
bool Emulate_Bcond_Link(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1381
EmulateInstructionMIPS64::Emulate_BC1EQZ
bool Emulate_BC1EQZ(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2030
dwarf_r10_mips64
@ dwarf_r10_mips64
Definition: RegisterContext_mips.h:142
EmulateInstructionMIPS64::EmulateInstructionMIPS64
EmulateInstructionMIPS64(const lldb_private::ArchSpec &arch)
Definition: EmulateInstructionMIPS64.cpp:62
lldb_private::Opcode::GetData
uint32_t GetData(DataExtractor &data) const
Definition: Opcode.cpp:81
EmulateInstructionMIPS64::Emulate_BXX_3ops
bool Emulate_BXX_3ops(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1329
dwarf_w9_mips64
@ dwarf_w9_mips64
Definition: RegisterContext_mips.h:215
EmulateInstructionMIPS64::Emulate_BALC
bool Emulate_BALC(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1458
dwarf_f24_mips64
@ dwarf_f24_mips64
Definition: RegisterContext_mips.h:194
dwarf_w5_mips64
@ dwarf_w5_mips64
Definition: RegisterContext_mips.h:211
dwarf_r19_mips64
@ dwarf_r19_mips64
Definition: RegisterContext_mips.h:151
dwarf_r22_mips64
@ dwarf_r22_mips64
Definition: RegisterContext_mips.h:154
dwarf_f3_mips64
@ dwarf_f3_mips64
Definition: RegisterContext_mips.h:173
string
string(SUBSTRING ${p} 10 -1 pStripped) if($
Definition: Plugins/CMakeLists.txt:40
dwarf_f18_mips64
@ dwarf_f18_mips64
Definition: RegisterContext_mips.h:188
dwarf_mcsr_mips64
@ dwarf_mcsr_mips64
Definition: RegisterContext_mips.h:238
EmulateInstructionMIPS64::GetRegisterName
const char * GetRegisterName(unsigned reg_num, bool alternate_name)
Definition: EmulateInstructionMIPS64.cpp:206
dwarf_f4_mips64
@ dwarf_f4_mips64
Definition: RegisterContext_mips.h:174
dwarf_f23_mips64
@ dwarf_f23_mips64
Definition: RegisterContext_mips.h:193
dwarf_w17_mips64
@ dwarf_w17_mips64
Definition: RegisterContext_mips.h:223
dwarf_r23_mips64
@ dwarf_r23_mips64
Definition: RegisterContext_mips.h:155
Address.h
UnwindPlan.h
EmulateInstructionMIPS64::m_asm_info
std::unique_ptr< llvm::MCAsmInfo > m_asm_info
Definition: EmulateInstructionMIPS64.h:175
InstructionUtils.h
dwarf_f1_mips64
@ dwarf_f1_mips64
Definition: RegisterContext_mips.h:171
EmulateInstructionMIPS64::Initialize
static void Initialize()
Definition: EmulateInstructionMIPS64.cpp:174
lldb::RegisterKind
RegisterKind
Register numbering types.
Definition: lldb-enumerations.h:228
lldb_private::EmulateInstruction::eContextAdjustStackPointer
@ eContextAdjustStackPointer
Definition: EmulateInstruction.h:117
EmulateInstructionMIPS64::Emulate_LUI
bool Emulate_LUI(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1226
dwarf_w4_mips64
@ dwarf_w4_mips64
Definition: RegisterContext_mips.h:210
lldb_private::UnwindPlan::RowSP
std::shared_ptr< Row > RowSP
Definition: UnwindPlan.h:395
dwarf_f8_mips64
@ dwarf_f8_mips64
Definition: RegisterContext_mips.h:178
EmulateInstructionMIPS64::SupportsEmulatingInstructionsOfTypeStatic
static bool SupportsEmulatingInstructionsOfTypeStatic(lldb_private::InstructionType inst_type)
Definition: EmulateInstructionMIPS64.h:42
dwarf_r27_mips64
@ dwarf_r27_mips64
Definition: RegisterContext_mips.h:159
lldb::eEncodingVector
@ eEncodingVector
vector registers
Definition: lldb-enumerations.h:152
dwarf_w22_mips64
@ dwarf_w22_mips64
Definition: RegisterContext_mips.h:228
lldb_private::UnwindPlan::Clear
void Clear()
Definition: UnwindPlan.h:508
lldb_private::Status
Definition: Status.h:44
dwarf_r12_mips64
@ dwarf_r12_mips64
Definition: RegisterContext_mips.h:144
EmulateInstructionMIPS64::EvaluateInstruction
bool EvaluateInstruction(uint32_t evaluate_options) override
Definition: EmulateInstructionMIPS64.cpp:947
lldb_private::EmulateInstruction::ReadRegister
llvm::Optional< RegisterValue > ReadRegister(const RegisterInfo &reg_info)
Definition: EmulateInstruction.cpp:76
lldb_private::EmulateInstruction::Context::SetNoArgs
void SetNoArgs()
Definition: EmulateInstruction.h:328
lldb_private::UnwindPlan::Row
Definition: UnwindPlan.h:55
uint32_t
lldb_private::eLazyBoolNo
@ eLazyBoolNo
Definition: lldb-private-enumerations.h:115
dwarf_f26_mips64
@ dwarf_f26_mips64
Definition: RegisterContext_mips.h:196
lldb_private::EmulateInstruction
Definition: EmulateInstruction.h:93
dwarf_w26_mips64
@ dwarf_w26_mips64
Definition: RegisterContext_mips.h:232
EmulateInstructionMIPS64::Emulate_SD
bool Emulate_SD(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1126
dwarf_mir_mips64
@ dwarf_mir_mips64
Definition: RegisterContext_mips.h:239
dwarf_f25_mips64
@ dwarf_f25_mips64
Definition: RegisterContext_mips.h:195
LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:52
dwarf_sp_mips64
@ dwarf_sp_mips64
Definition: RegisterContext_mips.h:161
dwarf_r16_mips64
@ dwarf_r16_mips64
Definition: RegisterContext_mips.h:148
dwarf_w15_mips64
@ dwarf_w15_mips64
Definition: RegisterContext_mips.h:221
EmulateInstructionMIPS64::Emulate_BZB
bool Emulate_BZB(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:2178
dwarf_f29_mips64
@ dwarf_f29_mips64
Definition: RegisterContext_mips.h:199
EmulateInstructionMIPS64::m_reg_info
std::unique_ptr< llvm::MCRegisterInfo > m_reg_info
Definition: EmulateInstructionMIPS64.h:174
EmulateInstructionMIPS64::GetPluginDescriptionStatic
static llvm::StringRef GetPluginDescriptionStatic()
Definition: EmulateInstructionMIPS64.cpp:183
ArchSpec.h
dwarf_r26_mips64
@ dwarf_r26_mips64
Definition: RegisterContext_mips.h:158
dwarf_f12_mips64
@ dwarf_f12_mips64
Definition: RegisterContext_mips.h:182
EmulateInstructionMIPS64::Emulate_BAL
bool Emulate_BAL(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1427
lldb_private::EmulateInstruction::WriteMemory
bool WriteMemory(const Context &context, lldb::addr_t addr, const void *src, size_t src_len)
Definition: EmulateInstruction.cpp:211
uint16_t
lldb_private::EmulateInstruction::eContextRegisterLoad
@ eContextRegisterLoad
Definition: EmulateInstruction.h:138
dwarf_w21_mips64
@ dwarf_w21_mips64
Definition: RegisterContext_mips.h:227
PluginManager.h
dwarf_r3_mips64
@ dwarf_r3_mips64
Definition: RegisterContext_mips.h:135
LLDB_INVALID_ADDRESS
#define LLDB_INVALID_ADDRESS
Definition: lldb-defines.h:74
dwarf_r6_mips64
@ dwarf_r6_mips64
Definition: RegisterContext_mips.h:138
dwarf_w12_mips64
@ dwarf_w12_mips64
Definition: RegisterContext_mips.h:218
DataExtractor.h
EmulateInstructionMIPS64::MipsOpcode::callback
bool(EmulateInstructionMIPS64::* callback)(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.h:84
lldb_private::InstructionType
InstructionType
Instruction types.
Definition: lldb-private-enumerations.h:118
EmulateInstructionMIPS64::Emulate_DSUBU_DADDU
bool Emulate_DSUBU_DADDU(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1243
dwarf_w6_mips64
@ dwarf_w6_mips64
Definition: RegisterContext_mips.h:212
dwarf_f21_mips64
@ dwarf_f21_mips64
Definition: RegisterContext_mips.h:191
lldb_private
A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
dwarf_zero_mips64
@ dwarf_zero_mips64
Definition: RegisterContext_mips.h:132
lldb::eFormatHex
@ eFormatHex
Definition: lldb-enumerations.h:170
LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:53
EmulateInstructionMIPS64::Emulate_LD
bool Emulate_LD(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1183
EmulateInstructionMIPS64.h
PosixApi.h
dwarf_w16_mips64
@ dwarf_w16_mips64
Definition: RegisterContext_mips.h:222
dwarf_w19_mips64
@ dwarf_w19_mips64
Definition: RegisterContext_mips.h:225
EmulateInstructionMIPS64::GetOpcodeForInstruction
static MipsOpcode * GetOpcodeForInstruction(llvm::StringRef op_name)
Definition: EmulateInstructionMIPS64.cpp:659
dwarf_f11_mips64
@ dwarf_f11_mips64
Definition: RegisterContext_mips.h:181
EmulateInstructionMIPS64::Emulate_JAL
bool Emulate_JAL(llvm::MCInst &insn)
Definition: EmulateInstructionMIPS64.cpp:1825
LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:51
dwarf_f16_mips64
@ dwarf_f16_mips64
Definition: RegisterContext_mips.h:186
ConstString.h
dwarf_r25_mips64
@ dwarf_r25_mips64
Definition: RegisterContext_mips.h:157
lldb_private::EmulateInstruction::ReadMemoryUnsigned
uint64_t ReadMemoryUnsigned(const Context &context, lldb::addr_t addr, size_t byte_size, uint64_t fail_value, bool *success_ptr)
Definition: EmulateInstruction.cpp:173
dwarf_r17_mips64
@ dwarf_r17_mips64
Definition: RegisterContext_mips.h:149
dwarf_f17_mips64
@ dwarf_f17_mips64
Definition: RegisterContext_mips.h:187
Stream.h
dwarf_w11_mips64
@ dwarf_w11_mips64
Definition: RegisterContext_mips.h:217
dwarf_r1_mips64
@ dwarf_r1_mips64
Definition: RegisterContext_mips.h:133
dwarf_w3_mips64
@ dwarf_w3_mips64
Definition: RegisterContext_mips.h:209
dwarf_r5_mips64
@ dwarf_r5_mips64
Definition: RegisterContext_mips.h:137
dwarf_f31_mips64
@ dwarf_f31_mips64
Definition: RegisterContext_mips.h:201
lldb_private::DataExtractor::GetByteSize
uint64_t GetByteSize() const
Get the number of bytes contained in this object.
Definition: DataExtractor.h:270
lldb::eByteOrderLittle
@ eByteOrderLittle
Definition: lldb-enumerations.h:143
lldb_private::EmulateInstruction::Context::SetImmediateSigned
void SetImmediateSigned(int64_t signed_immediate)
Definition: EmulateInstruction.h:302
lldb_private::EmulateInstruction::ReadRegisterUnsigned
uint64_t ReadRegisterUnsigned(const RegisterInfo &reg_info, uint64_t fail_value, bool *success_ptr)
Definition: EmulateInstruction.cpp:112
lldb_private::EmulateInstruction::m_addr
lldb::addr_t m_addr
Definition: EmulateInstruction.h:504
lldb_private::UnwindPlan
Definition: UnwindPlan.h:53
lldb
Definition: SBAddress.h:15
dwarf_w27_mips64
@ dwarf_w27_mips64
Definition: RegisterContext_mips.h:233
lldb_private::EmulateInstruction::eContextPushRegisterOnStack
@ eContextPushRegisterOnStack
Definition: EmulateInstruction.h:110
lldb_private::EmulateInstruction::eContextRelativeBranchImmediate
@ eContextRelativeBranchImmediate
Definition: EmulateInstruction.h:141
lldb_private::EmulateInstruction::WriteRegisterUnsigned
bool WriteRegisterUnsigned(const Context &context, const RegisterInfo &reg_info, uint64_t reg_value)
Definition: EmulateInstruction.cpp:156
dwarf_hi_mips64
@ dwarf_hi_mips64
Definition: RegisterContext_mips.h:166
dwarf_ra_mips64
@ dwarf_ra_mips64
Definition: RegisterContext_mips.h:163
dwarf_f2_mips64
@ dwarf_f2_mips64
Definition: RegisterContext_mips.h:172
lldb_private::EmulateInstruction::WriteRegister
bool WriteRegister(const Context &context, const RegisterInfo &ref_info, const RegisterValue &reg_value)
Definition: EmulateInstruction.cpp:125
lldb::eFormatVectorOfUInt8
@ eFormatVectorOfUInt8
Definition: lldb-enumerations.h:182
lldb_private::EmulateInstruction::Context::SetImmediate
void SetImmediate(uint64_t immediate)
Definition: EmulateInstruction.h:297
dwarf_w0_mips64
@ dwarf_w0_mips64
Definition: RegisterContext_mips.h:206
dwarf_w20_mips64
@ dwarf_w20_mips64
Definition: RegisterContext_mips.h:226
lldb_private::EmulateInstruction::m_opcode
Opcode m_opcode
Definition: EmulateInstruction.h:505
LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:54
EmulateInstructionMIPS64::m_subtype_info
std::unique_ptr< llvm::MCSubtargetInfo > m_subtype_info
Definition: EmulateInstructionMIPS64.h:173
dwarf_config5_mips64
@ dwarf_config5_mips64
Definition: RegisterContext_mips.h:240
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