LLDB  mainline
Macros | Functions
EmulateInstructionARM.cpp File Reference
#include <cstdlib>
#include "EmulateInstructionARM.h"
#include "EmulationStateARM.h"
#include "lldb/Core/Address.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Host/PosixApi.h"
#include "lldb/Interpreter/OptionValueArray.h"
#include "lldb/Interpreter/OptionValueDictionary.h"
#include "lldb/Symbol/UnwindPlan.h"
#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/ConstString.h"
#include "lldb/Utility/Stream.h"
#include "Plugins/Process/Utility/ARMDefines.h"
#include "Plugins/Process/Utility/ARMUtils.h"
#include "Utility/ARM_DWARF_Registers.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/MathExtras.h"
Include dependency graph for EmulateInstructionARM.cpp:

Go to the source code of this file.

Macros

#define APSR_C   Bit32(m_opcode_cpsr, CPSR_C_POS)
 
#define APSR_V   Bit32(m_opcode_cpsr, CPSR_V_POS)
 
#define AlignPC(pc_val)   (pc_val & 0xFFFFFFFC)
 
#define REG_RD   0
 
#define LDM_REGLIST   1
 
#define SP_REG   13
 
#define LR_REG   14
 
#define PC_REG   15
 
#define PC_REGLIST_BIT   0x8000
 
#define ARMv4   (1u << 0)
 
#define ARMv4T   (1u << 1)
 
#define ARMv5T   (1u << 2)
 
#define ARMv5TE   (1u << 3)
 
#define ARMv5TEJ   (1u << 4)
 
#define ARMv6   (1u << 5)
 
#define ARMv6K   (1u << 6)
 
#define ARMv6T2   (1u << 7)
 
#define ARMv7   (1u << 8)
 
#define ARMv7S   (1u << 9)
 
#define ARMv8   (1u << 10)
 
#define ARMvAll   (0xffffffffu)
 
#define ARMV4T_ABOVE
 
#define ARMV5_ABOVE
 
#define ARMV5TE_ABOVE   (ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
 
#define ARMV5J_ABOVE   (ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
 
#define ARMV6_ABOVE   (ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
 
#define ARMV6T2_ABOVE   (ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
 
#define ARMV7_ABOVE   (ARMv7 | ARMv7S | ARMv8)
 
#define No_VFP   0
 
#define VFPv1   (1u << 1)
 
#define VFPv2   (1u << 2)
 
#define VFPv3   (1u << 3)
 
#define AdvancedSIMD   (1u << 4)
 
#define VFPv1_ABOVE   (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
 
#define VFPv2_ABOVE   (VFPv2 | VFPv3 | AdvancedSIMD)
 
#define VFPv2v3   (VFPv2 | VFPv3)
 

Functions

static bool GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo &reg_info)
 
static uint32_t CountITSize (uint32_t ITMask)
 

Macro Definition Documentation

◆ AdvancedSIMD

#define AdvancedSIMD   (1u << 4)

Definition at line 697 of file EmulateInstructionARM.cpp.

◆ AlignPC

#define AlignPC (   pc_val)    (pc_val & 0xFFFFFFFC)

Definition at line 39 of file EmulateInstructionARM.cpp.

◆ APSR_C

#define APSR_C   Bit32(m_opcode_cpsr, CPSR_C_POS)

Definition at line 36 of file EmulateInstructionARM.cpp.

◆ APSR_V

#define APSR_V   Bit32(m_opcode_cpsr, CPSR_V_POS)

Definition at line 37 of file EmulateInstructionARM.cpp.

◆ ARMv4

#define ARMv4   (1u << 0)

Definition at line 666 of file EmulateInstructionARM.cpp.

◆ ARMv4T

#define ARMv4T   (1u << 1)

Definition at line 667 of file EmulateInstructionARM.cpp.

◆ ARMV4T_ABOVE

#define ARMV4T_ABOVE
Value:
ARMv7S | ARMv8)

Definition at line 679 of file EmulateInstructionARM.cpp.

◆ ARMV5_ABOVE

#define ARMV5_ABOVE
Value:
ARMv8)

Definition at line 682 of file EmulateInstructionARM.cpp.

◆ ARMV5J_ABOVE

#define ARMV5J_ABOVE   (ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)

Definition at line 687 of file EmulateInstructionARM.cpp.

◆ ARMv5T

#define ARMv5T   (1u << 2)

Definition at line 668 of file EmulateInstructionARM.cpp.

◆ ARMv5TE

#define ARMv5TE   (1u << 3)

Definition at line 669 of file EmulateInstructionARM.cpp.

◆ ARMV5TE_ABOVE

#define ARMV5TE_ABOVE   (ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)

Definition at line 685 of file EmulateInstructionARM.cpp.

◆ ARMv5TEJ

#define ARMv5TEJ   (1u << 4)

Definition at line 670 of file EmulateInstructionARM.cpp.

◆ ARMv6

#define ARMv6   (1u << 5)

Definition at line 671 of file EmulateInstructionARM.cpp.

◆ ARMV6_ABOVE

#define ARMV6_ABOVE   (ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)

Definition at line 689 of file EmulateInstructionARM.cpp.

◆ ARMv6K

#define ARMv6K   (1u << 6)

Definition at line 672 of file EmulateInstructionARM.cpp.

◆ ARMv6T2

#define ARMv6T2   (1u << 7)

Definition at line 673 of file EmulateInstructionARM.cpp.

◆ ARMV6T2_ABOVE

#define ARMV6T2_ABOVE   (ARMv6T2 | ARMv7 | ARMv7S | ARMv8)

Definition at line 690 of file EmulateInstructionARM.cpp.

◆ ARMv7

#define ARMv7   (1u << 8)

Definition at line 674 of file EmulateInstructionARM.cpp.

◆ ARMV7_ABOVE

#define ARMV7_ABOVE   (ARMv7 | ARMv7S | ARMv8)

Definition at line 691 of file EmulateInstructionARM.cpp.

◆ ARMv7S

#define ARMv7S   (1u << 9)

Definition at line 675 of file EmulateInstructionARM.cpp.

◆ ARMv8

#define ARMv8   (1u << 10)

Definition at line 676 of file EmulateInstructionARM.cpp.

◆ ARMvAll

#define ARMvAll   (0xffffffffu)

Definition at line 677 of file EmulateInstructionARM.cpp.

◆ LDM_REGLIST

#define LDM_REGLIST   1

Definition at line 660 of file EmulateInstructionARM.cpp.

◆ LR_REG

#define LR_REG   14

Definition at line 662 of file EmulateInstructionARM.cpp.

◆ No_VFP

#define No_VFP   0

Definition at line 693 of file EmulateInstructionARM.cpp.

◆ PC_REG

#define PC_REG   15

Definition at line 663 of file EmulateInstructionARM.cpp.

◆ PC_REGLIST_BIT

#define PC_REGLIST_BIT   0x8000

Definition at line 664 of file EmulateInstructionARM.cpp.

◆ REG_RD

#define REG_RD   0

Definition at line 659 of file EmulateInstructionARM.cpp.

◆ SP_REG

#define SP_REG   13

Definition at line 661 of file EmulateInstructionARM.cpp.

◆ VFPv1

#define VFPv1   (1u << 1)

Definition at line 694 of file EmulateInstructionARM.cpp.

◆ VFPv1_ABOVE

#define VFPv1_ABOVE   (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)

Definition at line 699 of file EmulateInstructionARM.cpp.

◆ VFPv2

#define VFPv2   (1u << 2)

Definition at line 695 of file EmulateInstructionARM.cpp.

◆ VFPv2_ABOVE

#define VFPv2_ABOVE   (VFPv2 | VFPv3 | AdvancedSIMD)

Definition at line 700 of file EmulateInstructionARM.cpp.

◆ VFPv2v3

#define VFPv2v3   (VFPv2 | VFPv3)

Definition at line 701 of file EmulateInstructionARM.cpp.

◆ VFPv3

#define VFPv3   (1u << 3)

Definition at line 696 of file EmulateInstructionARM.cpp.

Function Documentation

◆ CountITSize()

static uint32_t CountITSize ( uint32_t  ITMask)
static

Definition at line 604 of file EmulateInstructionARM.cpp.

Referenced by lldb_private::ITSession::InitIT().

◆ GetARMDWARFRegisterInfo()

static bool GetARMDWARFRegisterInfo ( unsigned  reg_num,
RegisterInfo &  reg_info 
)
static

Definition at line 45 of file EmulateInstructionARM.cpp.

References dwarf_cpsr, dwarf_d0, dwarf_d1, dwarf_d10, dwarf_d11, dwarf_d12, dwarf_d13, dwarf_d14, dwarf_d15, dwarf_d16, dwarf_d17, dwarf_d18, dwarf_d19, dwarf_d2, dwarf_d20, dwarf_d21, dwarf_d22, dwarf_d23, dwarf_d24, dwarf_d25, dwarf_d26, dwarf_d27, dwarf_d28, dwarf_d29, dwarf_d3, dwarf_d30, dwarf_d31, dwarf_d4, dwarf_d5, dwarf_d6, dwarf_d7, dwarf_d8, dwarf_d9, dwarf_f0, dwarf_f1, dwarf_f2, dwarf_f3, dwarf_f4, dwarf_f5, dwarf_f6, dwarf_f7, dwarf_lr, dwarf_pc, dwarf_q0, dwarf_q1, dwarf_q10, dwarf_q11, dwarf_q12, dwarf_q13, dwarf_q14, dwarf_q15, dwarf_q2, dwarf_q3, dwarf_q4, dwarf_q5, dwarf_q6, dwarf_q7, dwarf_q8, dwarf_q9, dwarf_r0, dwarf_r1, dwarf_r10, dwarf_r10_fiq, dwarf_r10_usr, dwarf_r11, dwarf_r11_fiq, dwarf_r11_usr, dwarf_r12, dwarf_r12_fiq, dwarf_r12_usr, dwarf_r13_abt, dwarf_r13_fiq, dwarf_r13_irq, dwarf_r13_svc, dwarf_r13_und, dwarf_r13_usr, dwarf_r14_abt, dwarf_r14_fiq, dwarf_r14_irq, dwarf_r14_svc, dwarf_r14_und, dwarf_r14_usr, dwarf_r2, dwarf_r3, dwarf_r4, dwarf_r5, dwarf_r6, dwarf_r7, dwarf_r8, dwarf_r8_fiq, dwarf_r8_usr, dwarf_r9, dwarf_r9_fiq, dwarf_r9_usr, dwarf_s0, dwarf_s1, dwarf_s10, dwarf_s11, dwarf_s12, dwarf_s13, dwarf_s14, dwarf_s15, dwarf_s16, dwarf_s17, dwarf_s18, dwarf_s19, dwarf_s2, dwarf_s20, dwarf_s21, dwarf_s22, dwarf_s23, dwarf_s24, dwarf_s25, dwarf_s26, dwarf_s27, dwarf_s28, dwarf_s29, dwarf_s3, dwarf_s30, dwarf_s31, dwarf_s4, dwarf_s5, dwarf_s6, dwarf_s7, dwarf_s8, dwarf_s9, dwarf_sp, dwarf_spsr, dwarf_spsr_abt, dwarf_spsr_fiq, dwarf_spsr_irq, dwarf_spsr_svc, dwarf_spsr_und, dwarf_wC0, dwarf_wC1, dwarf_wC2, dwarf_wC3, dwarf_wC4, dwarf_wC5, dwarf_wC6, dwarf_wC7, dwarf_wCGR0, dwarf_wCGR1, dwarf_wCGR2, dwarf_wCGR3, dwarf_wCGR4, dwarf_wCGR5, dwarf_wCGR6, dwarf_wCGR7, dwarf_wR0, dwarf_wR1, dwarf_wR10, dwarf_wR11, dwarf_wR12, dwarf_wR13, dwarf_wR14, dwarf_wR15, dwarf_wR2, dwarf_wR3, dwarf_wR4, dwarf_wR5, dwarf_wR6, dwarf_wR7, dwarf_wR8, dwarf_wR9, lldb::eEncodingIEEE754, lldb::eEncodingUint, lldb::eEncodingVector, lldb::eFormatFloat, lldb::eFormatHex, lldb::eFormatVectorOfUInt8, lldb::eRegisterKindDWARF, lldb::eRegisterKindGeneric, LLDB_INVALID_REGNUM, LLDB_REGNUM_GENERIC_FLAGS, LLDB_REGNUM_GENERIC_FP, LLDB_REGNUM_GENERIC_PC, LLDB_REGNUM_GENERIC_RA, and LLDB_REGNUM_GENERIC_SP.

Referenced by lldb_private::EmulateInstructionARM::GetRegisterInfo().

ARMv8
#define ARMv8
Definition: EmulateInstructionARM.cpp:676
ARMv5TE
#define ARMv5TE
Definition: EmulateInstructionARM.cpp:669
ARMv6
#define ARMv6
Definition: EmulateInstructionARM.cpp:671
ARMv7S
#define ARMv7S
Definition: EmulateInstructionARM.cpp:675
ARMv5T
#define ARMv5T
Definition: EmulateInstructionARM.cpp:668
ARMv7
#define ARMv7
Definition: EmulateInstructionARM.cpp:674
ARMv6K
#define ARMv6K
Definition: EmulateInstructionARM.cpp:672
ARMv5TEJ
#define ARMv5TEJ
Definition: EmulateInstructionARM.cpp:670
ARMv4T
#define ARMv4T
Definition: EmulateInstructionARM.cpp:667
ARMv6T2
#define ARMv6T2
Definition: EmulateInstructionARM.cpp:673