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RegisterInfos_arm.h
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1 //===-- RegisterInfos_arm.h -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifdef DECLARE_REGISTER_INFOS_ARM_STRUCT
10 
11 #include <cstddef>
12 
13 #include "lldb/lldb-defines.h"
14 #include "lldb/lldb-enumerations.h"
15 #include "lldb/lldb-private.h"
16 
19 
20 using namespace lldb;
21 using namespace lldb_private;
22 
23 #ifndef GPR_OFFSET
24 #error GPR_OFFSET must be defined before including this header file
25 #endif
26 
27 #ifndef FPU_OFFSET
28 #error FPU_OFFSET must be defined before including this header file
29 #endif
30 
31 #ifndef FPSCR_OFFSET
32 #error FPSCR_OFFSET must be defined before including this header file
33 #endif
34 
35 #ifndef EXC_OFFSET
36 #error EXC_OFFSET_NAME must be defined before including this header file
37 #endif
38 
39 #ifndef DEFINE_DBG
40 #error DEFINE_DBG must be defined before including this header file
41 #endif
42 
43 enum {
44  gpr_r0 = 0,
45  gpr_r1,
46  gpr_r2,
47  gpr_r3,
48  gpr_r4,
49  gpr_r5,
50  gpr_r6,
51  gpr_r7,
52  gpr_r8,
53  gpr_r9,
54  gpr_r10,
55  gpr_r11,
56  gpr_r12,
57  gpr_r13,
58  gpr_sp = gpr_r13,
59  gpr_r14,
60  gpr_lr = gpr_r14,
61  gpr_r15,
62  gpr_pc = gpr_r15,
63  gpr_cpsr,
64 
65  fpu_s0,
66  fpu_s1,
67  fpu_s2,
68  fpu_s3,
69  fpu_s4,
70  fpu_s5,
71  fpu_s6,
72  fpu_s7,
73  fpu_s8,
74  fpu_s9,
75  fpu_s10,
76  fpu_s11,
77  fpu_s12,
78  fpu_s13,
79  fpu_s14,
80  fpu_s15,
81  fpu_s16,
82  fpu_s17,
83  fpu_s18,
84  fpu_s19,
85  fpu_s20,
86  fpu_s21,
87  fpu_s22,
88  fpu_s23,
89  fpu_s24,
90  fpu_s25,
91  fpu_s26,
92  fpu_s27,
93  fpu_s28,
94  fpu_s29,
95  fpu_s30,
96  fpu_s31,
97  fpu_fpscr,
98 
99  fpu_d0,
100  fpu_d1,
101  fpu_d2,
102  fpu_d3,
103  fpu_d4,
104  fpu_d5,
105  fpu_d6,
106  fpu_d7,
107  fpu_d8,
108  fpu_d9,
109  fpu_d10,
110  fpu_d11,
111  fpu_d12,
112  fpu_d13,
113  fpu_d14,
114  fpu_d15,
115  fpu_d16,
116  fpu_d17,
117  fpu_d18,
118  fpu_d19,
119  fpu_d20,
120  fpu_d21,
121  fpu_d22,
122  fpu_d23,
123  fpu_d24,
124  fpu_d25,
125  fpu_d26,
126  fpu_d27,
127  fpu_d28,
128  fpu_d29,
129  fpu_d30,
130  fpu_d31,
131 
132  fpu_q0,
133  fpu_q1,
134  fpu_q2,
135  fpu_q3,
136  fpu_q4,
137  fpu_q5,
138  fpu_q6,
139  fpu_q7,
140  fpu_q8,
141  fpu_q9,
142  fpu_q10,
143  fpu_q11,
144  fpu_q12,
145  fpu_q13,
146  fpu_q14,
147  fpu_q15,
148 
150  exc_fsr,
151  exc_far,
152 
153  dbg_bvr0,
154  dbg_bvr1,
155  dbg_bvr2,
156  dbg_bvr3,
157  dbg_bvr4,
158  dbg_bvr5,
159  dbg_bvr6,
160  dbg_bvr7,
161  dbg_bvr8,
162  dbg_bvr9,
163  dbg_bvr10,
164  dbg_bvr11,
165  dbg_bvr12,
166  dbg_bvr13,
167  dbg_bvr14,
168  dbg_bvr15,
169 
170  dbg_bcr0,
171  dbg_bcr1,
172  dbg_bcr2,
173  dbg_bcr3,
174  dbg_bcr4,
175  dbg_bcr5,
176  dbg_bcr6,
177  dbg_bcr7,
178  dbg_bcr8,
179  dbg_bcr9,
180  dbg_bcr10,
181  dbg_bcr11,
182  dbg_bcr12,
183  dbg_bcr13,
184  dbg_bcr14,
185  dbg_bcr15,
186 
187  dbg_wvr0,
188  dbg_wvr1,
189  dbg_wvr2,
190  dbg_wvr3,
191  dbg_wvr4,
192  dbg_wvr5,
193  dbg_wvr6,
194  dbg_wvr7,
195  dbg_wvr8,
196  dbg_wvr9,
197  dbg_wvr10,
198  dbg_wvr11,
199  dbg_wvr12,
200  dbg_wvr13,
201  dbg_wvr14,
202  dbg_wvr15,
203 
204  dbg_wcr0,
205  dbg_wcr1,
206  dbg_wcr2,
207  dbg_wcr3,
208  dbg_wcr4,
209  dbg_wcr5,
210  dbg_wcr6,
211  dbg_wcr7,
212  dbg_wcr8,
213  dbg_wcr9,
214  dbg_wcr10,
215  dbg_wcr11,
216  dbg_wcr12,
217  dbg_wcr13,
218  dbg_wcr14,
219  dbg_wcr15,
220 
222 };
223 
224 static uint32_t g_s0_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM};
225 static uint32_t g_s1_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM};
226 static uint32_t g_s2_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM};
227 static uint32_t g_s3_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM};
228 static uint32_t g_s4_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM};
229 static uint32_t g_s5_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM};
230 static uint32_t g_s6_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM};
231 static uint32_t g_s7_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM};
232 static uint32_t g_s8_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM};
233 static uint32_t g_s9_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM};
234 static uint32_t g_s10_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM};
235 static uint32_t g_s11_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM};
236 static uint32_t g_s12_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM};
237 static uint32_t g_s13_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM};
238 static uint32_t g_s14_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM};
239 static uint32_t g_s15_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM};
240 static uint32_t g_s16_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM};
241 static uint32_t g_s17_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM};
242 static uint32_t g_s18_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM};
243 static uint32_t g_s19_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM};
244 static uint32_t g_s20_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM};
245 static uint32_t g_s21_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM};
246 static uint32_t g_s22_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM};
247 static uint32_t g_s23_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM};
248 static uint32_t g_s24_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM};
249 static uint32_t g_s25_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM};
250 static uint32_t g_s26_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM};
251 static uint32_t g_s27_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM};
252 static uint32_t g_s28_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
253 static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
254 static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
255 static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
256 
257 static uint32_t g_d0_invalidates[] = {fpu_q0, fpu_s0, fpu_s1,
259 static uint32_t g_d1_invalidates[] = {fpu_q0, fpu_s2, fpu_s3,
261 static uint32_t g_d2_invalidates[] = {fpu_q1, fpu_s4, fpu_s5,
263 static uint32_t g_d3_invalidates[] = {fpu_q1, fpu_s6, fpu_s7,
265 static uint32_t g_d4_invalidates[] = {fpu_q2, fpu_s8, fpu_s9,
267 static uint32_t g_d5_invalidates[] = {fpu_q2, fpu_s10, fpu_s11,
269 static uint32_t g_d6_invalidates[] = {fpu_q3, fpu_s12, fpu_s13,
271 static uint32_t g_d7_invalidates[] = {fpu_q3, fpu_s14, fpu_s15,
273 static uint32_t g_d8_invalidates[] = {fpu_q4, fpu_s16, fpu_s17,
275 static uint32_t g_d9_invalidates[] = {fpu_q4, fpu_s18, fpu_s19,
277 static uint32_t g_d10_invalidates[] = {fpu_q5, fpu_s20, fpu_s21,
279 static uint32_t g_d11_invalidates[] = {fpu_q5, fpu_s22, fpu_s23,
281 static uint32_t g_d12_invalidates[] = {fpu_q6, fpu_s24, fpu_s25,
283 static uint32_t g_d13_invalidates[] = {fpu_q6, fpu_s26, fpu_s27,
285 static uint32_t g_d14_invalidates[] = {fpu_q7, fpu_s28, fpu_s29,
287 static uint32_t g_d15_invalidates[] = {fpu_q7, fpu_s30, fpu_s31,
289 static uint32_t g_d16_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM};
290 static uint32_t g_d17_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM};
291 static uint32_t g_d18_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM};
292 static uint32_t g_d19_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM};
293 static uint32_t g_d20_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM};
294 static uint32_t g_d21_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM};
295 static uint32_t g_d22_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM};
296 static uint32_t g_d23_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM};
297 static uint32_t g_d24_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM};
298 static uint32_t g_d25_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM};
299 static uint32_t g_d26_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM};
300 static uint32_t g_d27_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM};
301 static uint32_t g_d28_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM};
302 static uint32_t g_d29_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM};
303 static uint32_t g_d30_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM};
304 static uint32_t g_d31_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM};
305 
306 static uint32_t g_q0_invalidates[] = {
307  fpu_d0, fpu_d1, fpu_s0, fpu_s1, fpu_s2, fpu_s3, LLDB_INVALID_REGNUM};
308 static uint32_t g_q1_invalidates[] = {
309  fpu_d2, fpu_d3, fpu_s4, fpu_s5, fpu_s6, fpu_s7, LLDB_INVALID_REGNUM};
310 static uint32_t g_q2_invalidates[] = {
311  fpu_d4, fpu_d5, fpu_s8, fpu_s9, fpu_s10, fpu_s11, LLDB_INVALID_REGNUM};
312 static uint32_t g_q3_invalidates[] = {
313  fpu_d6, fpu_d7, fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM};
314 static uint32_t g_q4_invalidates[] = {
315  fpu_d8, fpu_d9, fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM};
316 static uint32_t g_q5_invalidates[] = {
317  fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM};
318 static uint32_t g_q6_invalidates[] = {
319  fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM};
320 static uint32_t g_q7_invalidates[] = {
321  fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM};
322 static uint32_t g_q8_invalidates[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM};
323 static uint32_t g_q9_invalidates[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM};
324 static uint32_t g_q10_invalidates[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM};
325 static uint32_t g_q11_invalidates[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM};
326 static uint32_t g_q12_invalidates[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM};
327 static uint32_t g_q13_invalidates[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM};
328 static uint32_t g_q14_invalidates[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM};
329 static uint32_t g_q15_invalidates[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM};
330 
331 static uint32_t g_q0_contained[] = {fpu_q0, LLDB_INVALID_REGNUM};
332 static uint32_t g_q1_contained[] = {fpu_q1, LLDB_INVALID_REGNUM};
333 static uint32_t g_q2_contained[] = {fpu_q2, LLDB_INVALID_REGNUM};
334 static uint32_t g_q3_contained[] = {fpu_q3, LLDB_INVALID_REGNUM};
335 static uint32_t g_q4_contained[] = {fpu_q4, LLDB_INVALID_REGNUM};
336 static uint32_t g_q5_contained[] = {fpu_q5, LLDB_INVALID_REGNUM};
337 static uint32_t g_q6_contained[] = {fpu_q6, LLDB_INVALID_REGNUM};
338 static uint32_t g_q7_contained[] = {fpu_q7, LLDB_INVALID_REGNUM};
339 static uint32_t g_q8_contained[] = {fpu_q8, LLDB_INVALID_REGNUM};
340 static uint32_t g_q9_contained[] = {fpu_q9, LLDB_INVALID_REGNUM};
341 static uint32_t g_q10_contained[] = {fpu_q10, LLDB_INVALID_REGNUM};
342 static uint32_t g_q11_contained[] = {fpu_q11, LLDB_INVALID_REGNUM};
343 static uint32_t g_q12_contained[] = {fpu_q12, LLDB_INVALID_REGNUM};
344 static uint32_t g_q13_contained[] = {fpu_q13, LLDB_INVALID_REGNUM};
345 static uint32_t g_q14_contained[] = {fpu_q14, LLDB_INVALID_REGNUM};
346 static uint32_t g_q15_contained[] = {fpu_q15, LLDB_INVALID_REGNUM};
347 
348 #define FPU_REG(name, size, offset, qreg) \
349  { \
350  #name, nullptr, size, FPU_OFFSET(offset), eEncodingIEEE754, eFormatFloat, \
351  {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \
352  LLDB_INVALID_REGNUM, fpu_##name }, \
353  g_##qreg##_contained, g_##name##_invalidates, \
354  }
355 
356 #define FPU_QREG(name, offset) \
357  { \
358  #name, nullptr, 16, FPU_OFFSET(offset), eEncodingVector, \
359  eFormatVectorOfUInt8, \
360  {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \
361  LLDB_INVALID_REGNUM, fpu_##name }, \
362  nullptr, g_##name##_invalidates, \
363  }
364 
365 static RegisterInfo g_register_infos_arm[] = {
366  // NAME ALT SZ OFFSET ENCODING FORMAT
367  // EH_FRAME DWARF GENERIC
368  // PROCESS PLUGIN LLDB NATIVE VALUE REGS INVALIDATE REGS
369  // =========== ======= == ============== ================
370  // ==================== =================== ===================
371  // ========================== =================== =============
372  // ============== =================
373  {
374  "r0",
375  nullptr,
376  4,
377  GPR_OFFSET(0),
379  eFormatHex,
381  gpr_r0},
382  nullptr,
383  nullptr,
384  },
385  {
386  "r1",
387  nullptr,
388  4,
389  GPR_OFFSET(1),
391  eFormatHex,
393  gpr_r1},
394  nullptr,
395  nullptr,
396  },
397  {
398  "r2",
399  nullptr,
400  4,
401  GPR_OFFSET(2),
403  eFormatHex,
405  gpr_r2},
406  nullptr,
407  nullptr,
408  },
409  {
410  "r3",
411  nullptr,
412  4,
413  GPR_OFFSET(3),
415  eFormatHex,
417  gpr_r3},
418  nullptr,
419  nullptr,
420  },
421  {
422  "r4",
423  nullptr,
424  4,
425  GPR_OFFSET(4),
427  eFormatHex,
429  gpr_r4},
430  nullptr,
431  nullptr,
432  },
433  {
434  "r5",
435  nullptr,
436  4,
437  GPR_OFFSET(5),
439  eFormatHex,
441  gpr_r5},
442  nullptr,
443  nullptr,
444  },
445  {
446  "r6",
447  nullptr,
448  4,
449  GPR_OFFSET(6),
451  eFormatHex,
453  gpr_r6},
454  nullptr,
455  nullptr,
456  },
457  {
458  "r7",
459  nullptr,
460  4,
461  GPR_OFFSET(7),
463  eFormatHex,
465  gpr_r7},
466  nullptr,
467  nullptr,
468  },
469  {
470  "r8",
471  nullptr,
472  4,
473  GPR_OFFSET(8),
475  eFormatHex,
477  gpr_r8},
478  nullptr,
479  nullptr,
480  },
481  {
482  "r9",
483  nullptr,
484  4,
485  GPR_OFFSET(9),
487  eFormatHex,
489  gpr_r9},
490  nullptr,
491  nullptr,
492  },
493  {
494  "r10",
495  nullptr,
496  4,
497  GPR_OFFSET(10),
499  eFormatHex,
501  gpr_r10},
502  nullptr,
503  nullptr,
504  },
505  {
506  "r11",
507  nullptr,
508  4,
509  GPR_OFFSET(11),
511  eFormatHex,
513  gpr_r11},
514  nullptr,
515  nullptr,
516  },
517  {
518  "r12",
519  nullptr,
520  4,
521  GPR_OFFSET(12),
523  eFormatHex,
525  gpr_r12},
526  nullptr,
527  nullptr,
528  },
529  {
530  "sp",
531  "r13",
532  4,
533  GPR_OFFSET(13),
535  eFormatHex,
537  gpr_sp},
538  nullptr,
539  nullptr,
540  },
541  {
542  "lr",
543  "r14",
544  4,
545  GPR_OFFSET(14),
547  eFormatHex,
549  gpr_lr},
550  nullptr,
551  nullptr,
552  },
553  {
554  "pc",
555  "r15",
556  4,
557  GPR_OFFSET(15),
559  eFormatHex,
561  gpr_pc},
562  nullptr,
563  nullptr,
564  },
565  {
566  "cpsr",
567  "psr",
568  4,
569  GPR_OFFSET(16),
571  eFormatHex,
574  nullptr,
575  nullptr,
576  },
577 
578  FPU_REG(s0, 4, 0, q0),
579  FPU_REG(s1, 4, 1, q0),
580  FPU_REG(s2, 4, 2, q0),
581  FPU_REG(s3, 4, 3, q0),
582  FPU_REG(s4, 4, 4, q1),
583  FPU_REG(s5, 4, 5, q1),
584  FPU_REG(s6, 4, 6, q1),
585  FPU_REG(s7, 4, 7, q1),
586  FPU_REG(s8, 4, 8, q2),
587  FPU_REG(s9, 4, 9, q2),
588  FPU_REG(s10, 4, 10, q2),
589  FPU_REG(s11, 4, 11, q2),
590  FPU_REG(s12, 4, 12, q3),
591  FPU_REG(s13, 4, 13, q3),
592  FPU_REG(s14, 4, 14, q3),
593  FPU_REG(s15, 4, 15, q3),
594  FPU_REG(s16, 4, 16, q4),
595  FPU_REG(s17, 4, 17, q4),
596  FPU_REG(s18, 4, 18, q4),
597  FPU_REG(s19, 4, 19, q4),
598  FPU_REG(s20, 4, 20, q5),
599  FPU_REG(s21, 4, 21, q5),
600  FPU_REG(s22, 4, 22, q5),
601  FPU_REG(s23, 4, 23, q5),
602  FPU_REG(s24, 4, 24, q6),
603  FPU_REG(s25, 4, 25, q6),
604  FPU_REG(s26, 4, 26, q6),
605  FPU_REG(s27, 4, 27, q6),
606  FPU_REG(s28, 4, 28, q7),
607  FPU_REG(s29, 4, 29, q7),
608  FPU_REG(s30, 4, 30, q7),
609  FPU_REG(s31, 4, 31, q7),
610 
611  {
612  "fpscr",
613  nullptr,
614  4,
615  FPSCR_OFFSET,
617  eFormatHex,
620  nullptr,
621  nullptr,
622  },
623 
624  FPU_REG(d0, 8, 0, q0),
625  FPU_REG(d1, 8, 2, q0),
626  FPU_REG(d2, 8, 4, q1),
627  FPU_REG(d3, 8, 6, q1),
628  FPU_REG(d4, 8, 8, q2),
629  FPU_REG(d5, 8, 10, q2),
630  FPU_REG(d6, 8, 12, q3),
631  FPU_REG(d7, 8, 14, q3),
632  FPU_REG(d8, 8, 16, q4),
633  FPU_REG(d9, 8, 18, q4),
634  FPU_REG(d10, 8, 20, q5),
635  FPU_REG(d11, 8, 22, q5),
636  FPU_REG(d12, 8, 24, q6),
637  FPU_REG(d13, 8, 26, q6),
638  FPU_REG(d14, 8, 28, q7),
639  FPU_REG(d15, 8, 30, q7),
640  FPU_REG(d16, 8, 32, q8),
641  FPU_REG(d17, 8, 34, q8),
642  FPU_REG(d18, 8, 36, q9),
643  FPU_REG(d19, 8, 38, q9),
644  FPU_REG(d20, 8, 40, q10),
645  FPU_REG(d21, 8, 42, q10),
646  FPU_REG(d22, 8, 44, q11),
647  FPU_REG(d23, 8, 46, q11),
648  FPU_REG(d24, 8, 48, q12),
649  FPU_REG(d25, 8, 50, q12),
650  FPU_REG(d26, 8, 52, q13),
651  FPU_REG(d27, 8, 54, q13),
652  FPU_REG(d28, 8, 56, q14),
653  FPU_REG(d29, 8, 58, q14),
654  FPU_REG(d30, 8, 60, q15),
655  FPU_REG(d31, 8, 62, q15),
656 
657  FPU_QREG(q0, 0),
658  FPU_QREG(q1, 4),
659  FPU_QREG(q2, 8),
660  FPU_QREG(q3, 12),
661  FPU_QREG(q4, 16),
662  FPU_QREG(q5, 20),
663  FPU_QREG(q6, 24),
664  FPU_QREG(q7, 28),
665  FPU_QREG(q8, 32),
666  FPU_QREG(q9, 36),
667  FPU_QREG(q10, 40),
668  FPU_QREG(q11, 44),
669  FPU_QREG(q12, 48),
670  FPU_QREG(q13, 52),
671  FPU_QREG(q14, 56),
672  FPU_QREG(q15, 60),
673 
674  {
675  "exception",
676  nullptr,
677  4,
678  EXC_OFFSET(0),
680  eFormatHex,
683  nullptr,
684  nullptr,
685  },
686  {
687  "fsr",
688  nullptr,
689  4,
690  EXC_OFFSET(1),
692  eFormatHex,
695  nullptr,
696  nullptr,
697  },
698  {
699  "far",
700  nullptr,
701  4,
702  EXC_OFFSET(2),
704  eFormatHex,
707  nullptr,
708  nullptr,
709  },
710 
711  {DEFINE_DBG(bvr, 0)},
712  {DEFINE_DBG(bvr, 1)},
713  {DEFINE_DBG(bvr, 2)},
714  {DEFINE_DBG(bvr, 3)},
715  {DEFINE_DBG(bvr, 4)},
716  {DEFINE_DBG(bvr, 5)},
717  {DEFINE_DBG(bvr, 6)},
718  {DEFINE_DBG(bvr, 7)},
719  {DEFINE_DBG(bvr, 8)},
720  {DEFINE_DBG(bvr, 9)},
721  {DEFINE_DBG(bvr, 10)},
722  {DEFINE_DBG(bvr, 11)},
723  {DEFINE_DBG(bvr, 12)},
724  {DEFINE_DBG(bvr, 13)},
725  {DEFINE_DBG(bvr, 14)},
726  {DEFINE_DBG(bvr, 15)},
727 
728  {DEFINE_DBG(bcr, 0)},
729  {DEFINE_DBG(bcr, 1)},
730  {DEFINE_DBG(bcr, 2)},
731  {DEFINE_DBG(bcr, 3)},
732  {DEFINE_DBG(bcr, 4)},
733  {DEFINE_DBG(bcr, 5)},
734  {DEFINE_DBG(bcr, 6)},
735  {DEFINE_DBG(bcr, 7)},
736  {DEFINE_DBG(bcr, 8)},
737  {DEFINE_DBG(bcr, 9)},
738  {DEFINE_DBG(bcr, 10)},
739  {DEFINE_DBG(bcr, 11)},
740  {DEFINE_DBG(bcr, 12)},
741  {DEFINE_DBG(bcr, 13)},
742  {DEFINE_DBG(bcr, 14)},
743  {DEFINE_DBG(bcr, 15)},
744 
745  {DEFINE_DBG(wvr, 0)},
746  {DEFINE_DBG(wvr, 1)},
747  {DEFINE_DBG(wvr, 2)},
748  {DEFINE_DBG(wvr, 3)},
749  {DEFINE_DBG(wvr, 4)},
750  {DEFINE_DBG(wvr, 5)},
751  {DEFINE_DBG(wvr, 6)},
752  {DEFINE_DBG(wvr, 7)},
753  {DEFINE_DBG(wvr, 8)},
754  {DEFINE_DBG(wvr, 9)},
755  {DEFINE_DBG(wvr, 10)},
756  {DEFINE_DBG(wvr, 11)},
757  {DEFINE_DBG(wvr, 12)},
758  {DEFINE_DBG(wvr, 13)},
759  {DEFINE_DBG(wvr, 14)},
760  {DEFINE_DBG(wvr, 15)},
761 
762  {DEFINE_DBG(wcr, 0)},
763  {DEFINE_DBG(wcr, 1)},
764  {DEFINE_DBG(wcr, 2)},
765  {DEFINE_DBG(wcr, 3)},
766  {DEFINE_DBG(wcr, 4)},
767  {DEFINE_DBG(wcr, 5)},
768  {DEFINE_DBG(wcr, 6)},
769  {DEFINE_DBG(wcr, 7)},
770  {DEFINE_DBG(wcr, 8)},
771  {DEFINE_DBG(wcr, 9)},
772  {DEFINE_DBG(wcr, 10)},
773  {DEFINE_DBG(wcr, 11)},
774  {DEFINE_DBG(wcr, 12)},
775  {DEFINE_DBG(wcr, 13)},
776  {DEFINE_DBG(wcr, 14)},
777  {DEFINE_DBG(wcr, 15)}};
778 
779 #endif // DECLARE_REGISTER_INFOS_ARM_STRUCT
dbg_bvr7
@ dbg_bvr7
Definition: RegisterContextDarwin_arm.cpp:99
dwarf_r9
@ dwarf_r9
Definition: ABISysV_mips.cpp:48
LLDB_REGNUM_GENERIC_ARG2
#define LLDB_REGNUM_GENERIC_ARG2
Definition: lldb-defines.h:58
fpu_s24
@ fpu_s24
Definition: RegisterContextDarwin_arm.cpp:78
gpr_r7
@ gpr_r7
Definition: RegisterContextDarwin_arm.cpp:40
LLDB_REGNUM_GENERIC_ARG3
#define LLDB_REGNUM_GENERIC_ARG3
Definition: lldb-defines.h:60
dbg_bcr10
@ dbg_bcr10
Definition: RegisterContextDarwin_arm.cpp:119
dbg_wcr14
@ dbg_wcr14
Definition: RegisterContextDarwin_arm.cpp:157
LLDB_REGNUM_GENERIC_ARG1
#define LLDB_REGNUM_GENERIC_ARG1
Definition: lldb-defines.h:56
dbg_bcr0
@ dbg_bcr0
Definition: RegisterContextDarwin_arm.cpp:109
LLDB_INVALID_REGNUM
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:79
fpu_s19
@ fpu_s19
Definition: RegisterContextDarwin_arm.cpp:73
dbg_wcr12
@ dbg_wcr12
Definition: RegisterContextDarwin_arm.cpp:155
dbg_bvr13
@ dbg_bvr13
Definition: RegisterContextDarwin_arm.cpp:105
fpu_s12
@ fpu_s12
Definition: RegisterContextDarwin_arm.cpp:66
dbg_bvr1
@ dbg_bvr1
Definition: RegisterContextDarwin_arm.cpp:93
gpr_r1
@ gpr_r1
Definition: RegisterContextDarwin_arm.cpp:34
fpu_s5
@ fpu_s5
Definition: RegisterContextDarwin_arm.cpp:59
dwarf_sp
@ dwarf_sp
Definition: ARM_DWARF_Registers.h:28
ehframe_r10
@ ehframe_r10
Definition: ARM_ehframe_Registers.h:27
dbg_bcr15
@ dbg_bcr15
Definition: RegisterContextDarwin_arm.cpp:124
fpu_s2
@ fpu_s2
Definition: RegisterContextDarwin_arm.cpp:56
lldb-defines.h
dbg_wcr2
@ dbg_wcr2
Definition: RegisterContextDarwin_arm.cpp:145
fpu_s23
@ fpu_s23
Definition: RegisterContextDarwin_arm.cpp:77
fpu_s17
@ fpu_s17
Definition: RegisterContextDarwin_arm.cpp:71
fpu_s22
@ fpu_s22
Definition: RegisterContextDarwin_arm.cpp:76
dbg_bvr14
@ dbg_bvr14
Definition: RegisterContextDarwin_arm.cpp:106
dbg_wvr13
@ dbg_wvr13
Definition: RegisterContextDarwin_arm.cpp:139
dbg_bvr11
@ dbg_bvr11
Definition: RegisterContextDarwin_arm.cpp:103
dbg_wcr7
@ dbg_wcr7
Definition: RegisterContextDarwin_arm.cpp:150
ehframe_sp
@ ehframe_sp
Definition: ARM_ehframe_Registers.h:30
dbg_bvr12
@ dbg_bvr12
Definition: RegisterContextDarwin_arm.cpp:104
ehframe_r1
@ ehframe_r1
Definition: ARM_ehframe_Registers.h:18
gpr_lr
@ gpr_lr
Definition: RegisterContextDarwin_arm.cpp:49
ehframe_r0
@ ehframe_r0
Definition: ARM_ehframe_Registers.h:17
dbg_wcr6
@ dbg_wcr6
Definition: RegisterContextDarwin_arm.cpp:149
dwarf_cpsr
@ dwarf_cpsr
Definition: ARM_DWARF_Registers.h:31
gpr_cpsr
@ gpr_cpsr
Definition: RegisterContextDarwin_arm.cpp:52
dbg_bvr9
@ dbg_bvr9
Definition: RegisterContextDarwin_arm.cpp:101
dwarf_r12
@ dwarf_r12
Definition: ABISysV_mips.cpp:51
dbg_wvr5
@ dbg_wvr5
Definition: RegisterContextDarwin_arm.cpp:131
dbg_wcr11
@ dbg_wcr11
Definition: RegisterContextDarwin_arm.cpp:154
fpu_s6
@ fpu_s6
Definition: RegisterContextDarwin_arm.cpp:60
dbg_wvr4
@ dbg_wvr4
Definition: RegisterContextDarwin_arm.cpp:130
dbg_wvr7
@ dbg_wvr7
Definition: RegisterContextDarwin_arm.cpp:133
dbg_bvr15
@ dbg_bvr15
Definition: RegisterContextDarwin_arm.cpp:107
dbg_bcr14
@ dbg_bcr14
Definition: RegisterContextDarwin_arm.cpp:123
fpu_s0
@ fpu_s0
Definition: RegisterContextDarwin_arm.cpp:54
dbg_wvr0
@ dbg_wvr0
Definition: RegisterContextDarwin_arm.cpp:126
dbg_wcr3
@ dbg_wcr3
Definition: RegisterContextDarwin_arm.cpp:146
dwarf_r5
@ dwarf_r5
Definition: ABISysV_mips.cpp:44
ehframe_r11
@ ehframe_r11
Definition: ARM_ehframe_Registers.h:28
dbg_bcr7
@ dbg_bcr7
Definition: RegisterContextDarwin_arm.cpp:116
fpu_s26
@ fpu_s26
Definition: RegisterContextDarwin_arm.cpp:80
dwarf_pc
@ dwarf_pc
Definition: ABISysV_mips.cpp:76
LLDB_REGNUM_GENERIC_FLAGS
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:55
dbg_bcr3
@ dbg_bcr3
Definition: RegisterContextDarwin_arm.cpp:112
dwarf_r4
@ dwarf_r4
Definition: ABISysV_mips.cpp:43
ARM_ehframe_Registers.h
gpr_r4
@ gpr_r4
Definition: RegisterContextDarwin_arm.cpp:37
ehframe_r3
@ ehframe_r3
Definition: ARM_ehframe_Registers.h:20
dbg_wcr10
@ dbg_wcr10
Definition: RegisterContextDarwin_arm.cpp:153
dbg_bcr13
@ dbg_bcr13
Definition: RegisterContextDarwin_arm.cpp:122
dbg_bcr2
@ dbg_bcr2
Definition: RegisterContextDarwin_arm.cpp:111
gpr_r6
@ gpr_r6
Definition: RegisterContextDarwin_arm.cpp:39
fpu_s3
@ fpu_s3
Definition: RegisterContextDarwin_arm.cpp:57
fpu_s10
@ fpu_s10
Definition: RegisterContextDarwin_arm.cpp:64
ehframe_r12
@ ehframe_r12
Definition: ARM_ehframe_Registers.h:29
dbg_wvr15
@ dbg_wvr15
Definition: RegisterContextDarwin_arm.cpp:141
fpu_s29
@ fpu_s29
Definition: RegisterContextDarwin_arm.cpp:83
dwarf_r2
@ dwarf_r2
Definition: ABISysV_mips.cpp:41
gpr_sp
@ gpr_sp
Definition: RegisterContextDarwin_arm.cpp:47
gpr_r12
@ gpr_r12
Definition: RegisterContextDarwin_arm.cpp:45
dwarf_r7
@ dwarf_r7
Definition: ABISysV_mips.cpp:46
lldb::eEncodingUint
@ eEncodingUint
unsigned integer
Definition: lldb-enumerations.h:148
dwarf_r1
@ dwarf_r1
Definition: ABISysV_mips.cpp:40
fpu_s31
@ fpu_s31
Definition: RegisterContextDarwin_arm.cpp:85
ehframe_r9
@ ehframe_r9
Definition: ARM_ehframe_Registers.h:26
lldb-enumerations.h
dbg_wvr10
@ dbg_wvr10
Definition: RegisterContextDarwin_arm.cpp:136
fpu_s15
@ fpu_s15
Definition: RegisterContextDarwin_arm.cpp:69
fpu_s18
@ fpu_s18
Definition: RegisterContextDarwin_arm.cpp:72
FPSCR_OFFSET
#define FPSCR_OFFSET
Definition: RegisterInfoPOSIX_arm.cpp:24
dbg_wvr8
@ dbg_wvr8
Definition: RegisterContextDarwin_arm.cpp:134
dbg_wcr5
@ dbg_wcr5
Definition: RegisterContextDarwin_arm.cpp:148
exc_far
@ exc_far
Definition: RegisterContextDarwin_arm.cpp:90
gpr_r14
@ gpr_r14
Definition: RegisterContextDarwin_arm.cpp:48
dbg_wcr8
@ dbg_wcr8
Definition: RegisterContextDarwin_arm.cpp:151
fpu_s20
@ fpu_s20
Definition: RegisterContextDarwin_arm.cpp:74
fpu_s16
@ fpu_s16
Definition: RegisterContextDarwin_arm.cpp:70
gpr_r11
@ gpr_r11
Definition: RegisterContextDarwin_arm.cpp:44
ehframe_cpsr
@ ehframe_cpsr
Definition: ARM_ehframe_Registers.h:33
dbg_bvr2
@ dbg_bvr2
Definition: RegisterContextDarwin_arm.cpp:94
dwarf_r10
@ dwarf_r10
Definition: ABISysV_mips.cpp:49
gpr_r3
@ gpr_r3
Definition: RegisterContextDarwin_arm.cpp:36
dwarf_lr
@ dwarf_lr
Definition: ABISysV_ppc.cpp:106
fpu_s7
@ fpu_s7
Definition: RegisterContextDarwin_arm.cpp:61
gpr_r13
@ gpr_r13
Definition: RegisterContextDarwin_arm.cpp:46
ehframe_r6
@ ehframe_r6
Definition: ARM_ehframe_Registers.h:23
dbg_wvr6
@ dbg_wvr6
Definition: RegisterContextDarwin_arm.cpp:132
dbg_bvr10
@ dbg_bvr10
Definition: RegisterContextDarwin_arm.cpp:102
ARM_DWARF_Registers.h
lldb-private.h
fpu_s25
@ fpu_s25
Definition: RegisterContextDarwin_arm.cpp:79
dwarf_r0
@ dwarf_r0
Definition: ABISysV_mips.cpp:39
dbg_wvr1
@ dbg_wvr1
Definition: RegisterContextDarwin_arm.cpp:127
fpu_s13
@ fpu_s13
Definition: RegisterContextDarwin_arm.cpp:67
DEFINE_DBG
#define DEFINE_DBG(re, y)
Definition: EmulateInstructionARM64.cpp:34
gpr_r0
@ gpr_r0
Definition: RegisterContextDarwin_arm.cpp:33
dbg_wcr13
@ dbg_wcr13
Definition: RegisterContextDarwin_arm.cpp:156
ehframe_r4
@ ehframe_r4
Definition: ARM_ehframe_Registers.h:21
fpu_s4
@ fpu_s4
Definition: RegisterContextDarwin_arm.cpp:58
EXC_OFFSET
#define EXC_OFFSET(idx)
Definition: RegisterContextDarwin_arm.cpp:165
uint32_t
dbg_bcr11
@ dbg_bcr11
Definition: RegisterContextDarwin_arm.cpp:120
dbg_bvr0
@ dbg_bvr0
Definition: RegisterContextDarwin_arm.cpp:92
LLDB_REGNUM_GENERIC_SP
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:52
dbg_wvr12
@ dbg_wvr12
Definition: RegisterContextDarwin_arm.cpp:138
dwarf_r8
@ dwarf_r8
Definition: ABISysV_mips.cpp:47
gpr_r2
@ gpr_r2
Definition: RegisterContextDarwin_arm.cpp:35
gpr_r8
@ gpr_r8
Definition: RegisterContextDarwin_arm.cpp:41
fpu_s9
@ fpu_s9
Definition: RegisterContextDarwin_arm.cpp:63
dbg_bcr8
@ dbg_bcr8
Definition: RegisterContextDarwin_arm.cpp:117
dwarf_r11
@ dwarf_r11
Definition: ABISysV_mips.cpp:50
fpu_s11
@ fpu_s11
Definition: RegisterContextDarwin_arm.cpp:65
gpr_r9
@ gpr_r9
Definition: RegisterContextDarwin_arm.cpp:42
fpu_s21
@ fpu_s21
Definition: RegisterContextDarwin_arm.cpp:75
dbg_bvr4
@ dbg_bvr4
Definition: RegisterContextDarwin_arm.cpp:96
ehframe_r7
@ ehframe_r7
Definition: ARM_ehframe_Registers.h:24
dbg_bvr3
@ dbg_bvr3
Definition: RegisterContextDarwin_arm.cpp:95
exc_fsr
@ exc_fsr
Definition: RegisterContextDarwin_arm.cpp:89
dbg_wcr9
@ dbg_wcr9
Definition: RegisterContextDarwin_arm.cpp:152
gpr_r5
@ gpr_r5
Definition: RegisterContextDarwin_arm.cpp:38
dbg_bcr1
@ dbg_bcr1
Definition: RegisterContextDarwin_arm.cpp:110
dbg_wvr14
@ dbg_wvr14
Definition: RegisterContextDarwin_arm.cpp:140
dbg_bvr6
@ dbg_bvr6
Definition: RegisterContextDarwin_arm.cpp:98
dbg_wcr0
@ dbg_wcr0
Definition: RegisterContextDarwin_arm.cpp:143
ehframe_r8
@ ehframe_r8
Definition: ARM_ehframe_Registers.h:25
dbg_bcr6
@ dbg_bcr6
Definition: RegisterContextDarwin_arm.cpp:115
ehframe_r5
@ ehframe_r5
Definition: ARM_ehframe_Registers.h:22
LLDB_REGNUM_GENERIC_ARG4
#define LLDB_REGNUM_GENERIC_ARG4
Definition: lldb-defines.h:62
lldb_private
A class that represents a running process on the host machine.
Definition: SBCommandInterpreterRunOptions.h:16
ehframe_r2
@ ehframe_r2
Definition: ARM_ehframe_Registers.h:19
lldb::eFormatHex
@ eFormatHex
Definition: lldb-enumerations.h:169
LLDB_REGNUM_GENERIC_FP
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:53
fpu_s30
@ fpu_s30
Definition: RegisterContextDarwin_arm.cpp:84
k_num_registers
@ k_num_registers
Definition: RegisterContextDarwin_arm.cpp:160
dbg_bvr8
@ dbg_bvr8
Definition: RegisterContextDarwin_arm.cpp:100
ehframe_pc
@ ehframe_pc
Definition: ARM_ehframe_Registers.h:32
dbg_bcr9
@ dbg_bcr9
Definition: RegisterContextDarwin_arm.cpp:118
dwarf_r3
@ dwarf_r3
Definition: ABISysV_mips.cpp:42
LLDB_REGNUM_GENERIC_PC
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:51
fpu_s1
@ fpu_s1
Definition: RegisterContextDarwin_arm.cpp:55
dbg_wcr1
@ dbg_wcr1
Definition: RegisterContextDarwin_arm.cpp:144
dbg_wvr9
@ dbg_wvr9
Definition: RegisterContextDarwin_arm.cpp:135
dbg_bcr12
@ dbg_bcr12
Definition: RegisterContextDarwin_arm.cpp:121
gpr_r10
@ gpr_r10
Definition: RegisterContextDarwin_arm.cpp:43
dbg_wcr15
@ dbg_wcr15
Definition: RegisterContextDarwin_arm.cpp:158
dbg_wcr4
@ dbg_wcr4
Definition: RegisterContextDarwin_arm.cpp:147
dbg_wvr2
@ dbg_wvr2
Definition: RegisterContextDarwin_arm.cpp:128
dwarf_r6
@ dwarf_r6
Definition: ABISysV_mips.cpp:45
fpu_s14
@ fpu_s14
Definition: RegisterContextDarwin_arm.cpp:68
GPR_OFFSET
#define GPR_OFFSET(idx)
Definition: EmulateInstructionARM64.cpp:27
dbg_bcr4
@ dbg_bcr4
Definition: RegisterContextDarwin_arm.cpp:113
dbg_bcr5
@ dbg_bcr5
Definition: RegisterContextDarwin_arm.cpp:114
dbg_bvr5
@ dbg_bvr5
Definition: RegisterContextDarwin_arm.cpp:97
lldb
Definition: SBAddress.h:15
fpu_s28
@ fpu_s28
Definition: RegisterContextDarwin_arm.cpp:82
gpr_pc
@ gpr_pc
Definition: RegisterContextDarwin_arm.cpp:51
fpu_s8
@ fpu_s8
Definition: RegisterContextDarwin_arm.cpp:62
fpu_fpscr
@ fpu_fpscr
Definition: RegisterContextDarwin_arm.cpp:86
gpr_r15
@ gpr_r15
Definition: RegisterContextDarwin_arm.cpp:50
ehframe_lr
@ ehframe_lr
Definition: ARM_ehframe_Registers.h:31
dbg_wvr3
@ dbg_wvr3
Definition: RegisterContextDarwin_arm.cpp:129
dbg_wvr11
@ dbg_wvr11
Definition: RegisterContextDarwin_arm.cpp:137
LLDB_REGNUM_GENERIC_RA
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:54
fpu_s27
@ fpu_s27
Definition: RegisterContextDarwin_arm.cpp:81
exc_exception
@ exc_exception
Definition: RegisterContextDarwin_arm.cpp:88