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RegisterInfos_arm.h
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1 //===-- RegisterInfos_arm.h -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifdef DECLARE_REGISTER_INFOS_ARM_STRUCT
10 
11 #include <stddef.h>
12 
13 #include "lldb/lldb-defines.h"
14 #include "lldb/lldb-enumerations.h"
15 #include "lldb/lldb-private.h"
16 
19 
20 using namespace lldb;
21 using namespace lldb_private;
22 
23 #ifndef GPR_OFFSET
24 #error GPR_OFFSET must be defined before including this header file
25 #endif
26 
27 #ifndef FPU_OFFSET
28 #error FPU_OFFSET must be defined before including this header file
29 #endif
30 
31 #ifndef FPSCR_OFFSET
32 #error FPSCR_OFFSET must be defined before including this header file
33 #endif
34 
35 #ifndef EXC_OFFSET
36 #error EXC_OFFSET_NAME must be defined before including this header file
37 #endif
38 
39 #ifndef DEFINE_DBG
40 #error DEFINE_DBG must be defined before including this header file
41 #endif
42 
43 enum {
44  gpr_r0 = 0,
45  gpr_r1,
46  gpr_r2,
47  gpr_r3,
48  gpr_r4,
49  gpr_r5,
50  gpr_r6,
51  gpr_r7,
52  gpr_r8,
53  gpr_r9,
54  gpr_r10,
55  gpr_r11,
56  gpr_r12,
57  gpr_r13,
58  gpr_sp = gpr_r13,
59  gpr_r14,
60  gpr_lr = gpr_r14,
61  gpr_r15,
62  gpr_pc = gpr_r15,
63  gpr_cpsr,
64 
65  fpu_s0,
66  fpu_s1,
67  fpu_s2,
68  fpu_s3,
69  fpu_s4,
70  fpu_s5,
71  fpu_s6,
72  fpu_s7,
73  fpu_s8,
74  fpu_s9,
75  fpu_s10,
76  fpu_s11,
77  fpu_s12,
78  fpu_s13,
79  fpu_s14,
80  fpu_s15,
81  fpu_s16,
82  fpu_s17,
83  fpu_s18,
84  fpu_s19,
85  fpu_s20,
86  fpu_s21,
87  fpu_s22,
88  fpu_s23,
89  fpu_s24,
90  fpu_s25,
91  fpu_s26,
92  fpu_s27,
93  fpu_s28,
94  fpu_s29,
95  fpu_s30,
96  fpu_s31,
97  fpu_fpscr,
98 
99  fpu_d0,
100  fpu_d1,
101  fpu_d2,
102  fpu_d3,
103  fpu_d4,
104  fpu_d5,
105  fpu_d6,
106  fpu_d7,
107  fpu_d8,
108  fpu_d9,
109  fpu_d10,
110  fpu_d11,
111  fpu_d12,
112  fpu_d13,
113  fpu_d14,
114  fpu_d15,
115  fpu_d16,
116  fpu_d17,
117  fpu_d18,
118  fpu_d19,
119  fpu_d20,
120  fpu_d21,
121  fpu_d22,
122  fpu_d23,
123  fpu_d24,
124  fpu_d25,
125  fpu_d26,
126  fpu_d27,
127  fpu_d28,
128  fpu_d29,
129  fpu_d30,
130  fpu_d31,
131 
132  fpu_q0,
133  fpu_q1,
134  fpu_q2,
135  fpu_q3,
136  fpu_q4,
137  fpu_q5,
138  fpu_q6,
139  fpu_q7,
140  fpu_q8,
141  fpu_q9,
142  fpu_q10,
143  fpu_q11,
144  fpu_q12,
145  fpu_q13,
146  fpu_q14,
147  fpu_q15,
148 
150  exc_fsr,
151  exc_far,
152 
153  dbg_bvr0,
154  dbg_bvr1,
155  dbg_bvr2,
156  dbg_bvr3,
157  dbg_bvr4,
158  dbg_bvr5,
159  dbg_bvr6,
160  dbg_bvr7,
161  dbg_bvr8,
162  dbg_bvr9,
163  dbg_bvr10,
164  dbg_bvr11,
165  dbg_bvr12,
166  dbg_bvr13,
167  dbg_bvr14,
168  dbg_bvr15,
169 
170  dbg_bcr0,
171  dbg_bcr1,
172  dbg_bcr2,
173  dbg_bcr3,
174  dbg_bcr4,
175  dbg_bcr5,
176  dbg_bcr6,
177  dbg_bcr7,
178  dbg_bcr8,
179  dbg_bcr9,
180  dbg_bcr10,
181  dbg_bcr11,
182  dbg_bcr12,
183  dbg_bcr13,
184  dbg_bcr14,
185  dbg_bcr15,
186 
187  dbg_wvr0,
188  dbg_wvr1,
189  dbg_wvr2,
190  dbg_wvr3,
191  dbg_wvr4,
192  dbg_wvr5,
193  dbg_wvr6,
194  dbg_wvr7,
195  dbg_wvr8,
196  dbg_wvr9,
197  dbg_wvr10,
198  dbg_wvr11,
199  dbg_wvr12,
200  dbg_wvr13,
201  dbg_wvr14,
202  dbg_wvr15,
203 
204  dbg_wcr0,
205  dbg_wcr1,
206  dbg_wcr2,
207  dbg_wcr3,
208  dbg_wcr4,
209  dbg_wcr5,
210  dbg_wcr6,
211  dbg_wcr7,
212  dbg_wcr8,
213  dbg_wcr9,
214  dbg_wcr10,
215  dbg_wcr11,
216  dbg_wcr12,
217  dbg_wcr13,
218  dbg_wcr14,
219  dbg_wcr15,
220 
222 };
223 
224 static uint32_t g_s0_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM};
225 static uint32_t g_s1_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM};
226 static uint32_t g_s2_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM};
227 static uint32_t g_s3_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM};
228 static uint32_t g_s4_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM};
229 static uint32_t g_s5_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM};
230 static uint32_t g_s6_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM};
231 static uint32_t g_s7_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM};
232 static uint32_t g_s8_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM};
233 static uint32_t g_s9_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM};
234 static uint32_t g_s10_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM};
235 static uint32_t g_s11_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM};
236 static uint32_t g_s12_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM};
237 static uint32_t g_s13_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM};
238 static uint32_t g_s14_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM};
239 static uint32_t g_s15_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM};
240 static uint32_t g_s16_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM};
241 static uint32_t g_s17_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM};
242 static uint32_t g_s18_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM};
243 static uint32_t g_s19_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM};
244 static uint32_t g_s20_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM};
245 static uint32_t g_s21_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM};
246 static uint32_t g_s22_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM};
247 static uint32_t g_s23_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM};
248 static uint32_t g_s24_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM};
249 static uint32_t g_s25_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM};
250 static uint32_t g_s26_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM};
251 static uint32_t g_s27_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM};
252 static uint32_t g_s28_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
253 static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
254 static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
255 static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
256 
257 static uint32_t g_d0_contains[] = {fpu_s0, fpu_s1, LLDB_INVALID_REGNUM};
258 static uint32_t g_d1_contains[] = {fpu_s2, fpu_s3, LLDB_INVALID_REGNUM};
259 static uint32_t g_d2_contains[] = {fpu_s4, fpu_s5, LLDB_INVALID_REGNUM};
260 static uint32_t g_d3_contains[] = {fpu_s6, fpu_s7, LLDB_INVALID_REGNUM};
261 static uint32_t g_d4_contains[] = {fpu_s8, fpu_s9, LLDB_INVALID_REGNUM};
262 static uint32_t g_d5_contains[] = {fpu_s10, fpu_s11, LLDB_INVALID_REGNUM};
263 static uint32_t g_d6_contains[] = {fpu_s12, fpu_s13, LLDB_INVALID_REGNUM};
264 static uint32_t g_d7_contains[] = {fpu_s14, fpu_s15, LLDB_INVALID_REGNUM};
265 static uint32_t g_d8_contains[] = {fpu_s16, fpu_s17, LLDB_INVALID_REGNUM};
266 static uint32_t g_d9_contains[] = {fpu_s18, fpu_s19, LLDB_INVALID_REGNUM};
267 static uint32_t g_d10_contains[] = {fpu_s20, fpu_s21, LLDB_INVALID_REGNUM};
268 static uint32_t g_d11_contains[] = {fpu_s22, fpu_s23, LLDB_INVALID_REGNUM};
269 static uint32_t g_d12_contains[] = {fpu_s24, fpu_s25, LLDB_INVALID_REGNUM};
270 static uint32_t g_d13_contains[] = {fpu_s26, fpu_s27, LLDB_INVALID_REGNUM};
271 static uint32_t g_d14_contains[] = {fpu_s28, fpu_s29, LLDB_INVALID_REGNUM};
272 static uint32_t g_d15_contains[] = {fpu_s30, fpu_s31, LLDB_INVALID_REGNUM};
273 
274 static uint32_t g_d0_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM};
275 static uint32_t g_d1_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM};
276 static uint32_t g_d2_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM};
277 static uint32_t g_d3_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM};
278 static uint32_t g_d4_invalidates[] = {fpu_q2, LLDB_INVALID_REGNUM};
279 static uint32_t g_d5_invalidates[] = {fpu_q2, LLDB_INVALID_REGNUM};
280 static uint32_t g_d6_invalidates[] = {fpu_q3, LLDB_INVALID_REGNUM};
281 static uint32_t g_d7_invalidates[] = {fpu_q3, LLDB_INVALID_REGNUM};
282 static uint32_t g_d8_invalidates[] = {fpu_q4, LLDB_INVALID_REGNUM};
283 static uint32_t g_d9_invalidates[] = {fpu_q4, LLDB_INVALID_REGNUM};
284 static uint32_t g_d10_invalidates[] = {fpu_q5, LLDB_INVALID_REGNUM};
285 static uint32_t g_d11_invalidates[] = {fpu_q5, LLDB_INVALID_REGNUM};
286 static uint32_t g_d12_invalidates[] = {fpu_q6, LLDB_INVALID_REGNUM};
287 static uint32_t g_d13_invalidates[] = {fpu_q6, LLDB_INVALID_REGNUM};
288 static uint32_t g_d14_invalidates[] = {fpu_q7, LLDB_INVALID_REGNUM};
289 static uint32_t g_d15_invalidates[] = {fpu_q7, LLDB_INVALID_REGNUM};
290 static uint32_t g_d16_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM};
291 static uint32_t g_d17_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM};
292 static uint32_t g_d18_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM};
293 static uint32_t g_d19_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM};
294 static uint32_t g_d20_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM};
295 static uint32_t g_d21_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM};
296 static uint32_t g_d22_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM};
297 static uint32_t g_d23_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM};
298 static uint32_t g_d24_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM};
299 static uint32_t g_d25_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM};
300 static uint32_t g_d26_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM};
301 static uint32_t g_d27_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM};
302 static uint32_t g_d28_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM};
303 static uint32_t g_d29_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM};
304 static uint32_t g_d30_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM};
305 static uint32_t g_d31_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM};
306 
307 static uint32_t g_q0_contains[] = {
308  fpu_d0, fpu_d1, fpu_s0, fpu_s1, fpu_s2, fpu_s3, LLDB_INVALID_REGNUM};
309 static uint32_t g_q1_contains[] = {
310  fpu_d2, fpu_d3, fpu_s4, fpu_s5, fpu_s6, fpu_s7, LLDB_INVALID_REGNUM};
311 static uint32_t g_q2_contains[] = {
312  fpu_d4, fpu_d5, fpu_s8, fpu_s9, fpu_s10, fpu_s11, LLDB_INVALID_REGNUM};
313 static uint32_t g_q3_contains[] = {
314  fpu_d6, fpu_d7, fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM};
315 static uint32_t g_q4_contains[] = {
316  fpu_d8, fpu_d9, fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM};
317 static uint32_t g_q5_contains[] = {
318  fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM};
319 static uint32_t g_q6_contains[] = {
320  fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM};
321 static uint32_t g_q7_contains[] = {
322  fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM};
323 static uint32_t g_q8_contains[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM};
324 static uint32_t g_q9_contains[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM};
325 static uint32_t g_q10_contains[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM};
326 static uint32_t g_q11_contains[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM};
327 static uint32_t g_q12_contains[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM};
328 static uint32_t g_q13_contains[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM};
329 static uint32_t g_q14_contains[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM};
330 static uint32_t g_q15_contains[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM};
331 
332 static RegisterInfo g_register_infos_arm[] = {
333  // NAME ALT SZ OFFSET ENCODING FORMAT
334  // EH_FRAME DWARF GENERIC
335  // PROCESS PLUGIN LLDB NATIVE VALUE REGS INVALIDATE REGS
336  // =========== ======= == ============== ================
337  // ==================== =================== ===================
338  // ========================== =================== =============
339  // ============== =================
340  {"r0",
341  nullptr,
342  4,
343  GPR_OFFSET(0),
345  eFormatHex,
347  gpr_r0},
348  nullptr,
349  nullptr,
350  nullptr,
351  0},
352  {"r1",
353  nullptr,
354  4,
355  GPR_OFFSET(1),
357  eFormatHex,
359  gpr_r1},
360  nullptr,
361  nullptr,
362  nullptr,
363  0},
364  {"r2",
365  nullptr,
366  4,
367  GPR_OFFSET(2),
369  eFormatHex,
371  gpr_r2},
372  nullptr,
373  nullptr,
374  nullptr,
375  0},
376  {"r3",
377  nullptr,
378  4,
379  GPR_OFFSET(3),
381  eFormatHex,
383  gpr_r3},
384  nullptr,
385  nullptr,
386  nullptr,
387  0},
388  {"r4",
389  nullptr,
390  4,
391  GPR_OFFSET(4),
393  eFormatHex,
395  nullptr,
396  nullptr,
397  nullptr,
398  0},
399  {"r5",
400  nullptr,
401  4,
402  GPR_OFFSET(5),
404  eFormatHex,
406  nullptr,
407  nullptr,
408  nullptr,
409  0},
410  {"r6",
411  nullptr,
412  4,
413  GPR_OFFSET(6),
415  eFormatHex,
417  nullptr,
418  nullptr,
419  nullptr,
420  0},
421  {"r7",
422  nullptr,
423  4,
424  GPR_OFFSET(7),
426  eFormatHex,
428  nullptr,
429  nullptr,
430  nullptr,
431  0},
432  {"r8",
433  nullptr,
434  4,
435  GPR_OFFSET(8),
437  eFormatHex,
439  nullptr,
440  nullptr,
441  nullptr,
442  0},
443  {"r9",
444  nullptr,
445  4,
446  GPR_OFFSET(9),
448  eFormatHex,
450  nullptr,
451  nullptr,
452  nullptr,
453  0},
454  {"r10",
455  nullptr,
456  4,
457  GPR_OFFSET(10),
459  eFormatHex,
461  gpr_r10},
462  nullptr,
463  nullptr,
464  nullptr,
465  0},
466  {"r11",
467  nullptr,
468  4,
469  GPR_OFFSET(11),
471  eFormatHex,
473  gpr_r11},
474  nullptr,
475  nullptr,
476  nullptr,
477  0},
478  {"r12",
479  nullptr,
480  4,
481  GPR_OFFSET(12),
483  eFormatHex,
485  gpr_r12},
486  nullptr,
487  nullptr,
488  nullptr,
489  0},
490  {"sp",
491  "r13",
492  4,
493  GPR_OFFSET(13),
495  eFormatHex,
497  gpr_sp},
498  nullptr,
499  nullptr,
500  nullptr,
501  0},
502  {"lr",
503  "r14",
504  4,
505  GPR_OFFSET(14),
507  eFormatHex,
509  gpr_lr},
510  nullptr,
511  nullptr,
512  nullptr,
513  0},
514  {"pc",
515  "r15",
516  4,
517  GPR_OFFSET(15),
519  eFormatHex,
521  gpr_pc},
522  nullptr,
523  nullptr,
524  nullptr,
525  0},
526  {"cpsr",
527  "psr",
528  4,
529  GPR_OFFSET(16),
531  eFormatHex,
533  gpr_cpsr},
534  nullptr,
535  nullptr,
536  nullptr,
537  0},
538 
539  {"s0",
540  nullptr,
541  4,
542  FPU_OFFSET(0),
544  eFormatFloat,
546  fpu_s0},
547  nullptr,
548  g_s0_invalidates,
549  nullptr,
550  0},
551  {"s1",
552  nullptr,
553  4,
554  FPU_OFFSET(1),
556  eFormatFloat,
558  fpu_s1},
559  nullptr,
560  g_s1_invalidates,
561  nullptr,
562  0},
563  {"s2",
564  nullptr,
565  4,
566  FPU_OFFSET(2),
568  eFormatFloat,
570  fpu_s2},
571  nullptr,
572  g_s2_invalidates,
573  nullptr,
574  0},
575  {"s3",
576  nullptr,
577  4,
578  FPU_OFFSET(3),
580  eFormatFloat,
582  fpu_s3},
583  nullptr,
584  g_s3_invalidates,
585  nullptr,
586  0},
587  {"s4",
588  nullptr,
589  4,
590  FPU_OFFSET(4),
592  eFormatFloat,
594  fpu_s4},
595  nullptr,
596  g_s4_invalidates,
597  nullptr,
598  0},
599  {"s5",
600  nullptr,
601  4,
602  FPU_OFFSET(5),
604  eFormatFloat,
606  fpu_s5},
607  nullptr,
608  g_s5_invalidates,
609  nullptr,
610  0},
611  {"s6",
612  nullptr,
613  4,
614  FPU_OFFSET(6),
616  eFormatFloat,
618  fpu_s6},
619  nullptr,
620  g_s6_invalidates,
621  nullptr,
622  0},
623  {"s7",
624  nullptr,
625  4,
626  FPU_OFFSET(7),
628  eFormatFloat,
630  fpu_s7},
631  nullptr,
632  g_s7_invalidates,
633  nullptr,
634  0},
635  {"s8",
636  nullptr,
637  4,
638  FPU_OFFSET(8),
640  eFormatFloat,
642  fpu_s8},
643  nullptr,
644  g_s8_invalidates,
645  nullptr,
646  0},
647  {"s9",
648  nullptr,
649  4,
650  FPU_OFFSET(9),
652  eFormatFloat,
654  fpu_s9},
655  nullptr,
656  g_s9_invalidates,
657  nullptr,
658  0},
659  {"s10",
660  nullptr,
661  4,
662  FPU_OFFSET(10),
664  eFormatFloat,
666  fpu_s10},
667  nullptr,
668  g_s10_invalidates,
669  nullptr,
670  0},
671  {"s11",
672  nullptr,
673  4,
674  FPU_OFFSET(11),
676  eFormatFloat,
678  fpu_s11},
679  nullptr,
680  g_s11_invalidates,
681  nullptr,
682  0},
683  {"s12",
684  nullptr,
685  4,
686  FPU_OFFSET(12),
688  eFormatFloat,
690  fpu_s12},
691  nullptr,
692  g_s12_invalidates,
693  nullptr,
694  0},
695  {"s13",
696  nullptr,
697  4,
698  FPU_OFFSET(13),
700  eFormatFloat,
702  fpu_s13},
703  nullptr,
704  g_s13_invalidates,
705  nullptr,
706  0},
707  {"s14",
708  nullptr,
709  4,
710  FPU_OFFSET(14),
712  eFormatFloat,
714  fpu_s14},
715  nullptr,
716  g_s14_invalidates,
717  nullptr,
718  0},
719  {"s15",
720  nullptr,
721  4,
722  FPU_OFFSET(15),
724  eFormatFloat,
726  fpu_s15},
727  nullptr,
728  g_s15_invalidates,
729  nullptr,
730  0},
731  {"s16",
732  nullptr,
733  4,
734  FPU_OFFSET(16),
736  eFormatFloat,
738  fpu_s16},
739  nullptr,
740  g_s16_invalidates,
741  nullptr,
742  0},
743  {"s17",
744  nullptr,
745  4,
746  FPU_OFFSET(17),
748  eFormatFloat,
750  fpu_s17},
751  nullptr,
752  g_s17_invalidates,
753  nullptr,
754  0},
755  {"s18",
756  nullptr,
757  4,
758  FPU_OFFSET(18),
760  eFormatFloat,
762  fpu_s18},
763  nullptr,
764  g_s18_invalidates,
765  nullptr,
766  0},
767  {"s19",
768  nullptr,
769  4,
770  FPU_OFFSET(19),
772  eFormatFloat,
774  fpu_s19},
775  nullptr,
776  g_s19_invalidates,
777  nullptr,
778  0},
779  {"s20",
780  nullptr,
781  4,
782  FPU_OFFSET(20),
784  eFormatFloat,
786  fpu_s20},
787  nullptr,
788  g_s20_invalidates,
789  nullptr,
790  0},
791  {"s21",
792  nullptr,
793  4,
794  FPU_OFFSET(21),
796  eFormatFloat,
798  fpu_s21},
799  nullptr,
800  g_s21_invalidates,
801  nullptr,
802  0},
803  {"s22",
804  nullptr,
805  4,
806  FPU_OFFSET(22),
808  eFormatFloat,
810  fpu_s22},
811  nullptr,
812  g_s22_invalidates,
813  nullptr,
814  0},
815  {"s23",
816  nullptr,
817  4,
818  FPU_OFFSET(23),
820  eFormatFloat,
822  fpu_s23},
823  nullptr,
824  g_s23_invalidates,
825  nullptr,
826  0},
827  {"s24",
828  nullptr,
829  4,
830  FPU_OFFSET(24),
832  eFormatFloat,
834  fpu_s24},
835  nullptr,
836  g_s24_invalidates,
837  nullptr,
838  0},
839  {"s25",
840  nullptr,
841  4,
842  FPU_OFFSET(25),
844  eFormatFloat,
846  fpu_s25},
847  nullptr,
848  g_s25_invalidates,
849  nullptr,
850  0},
851  {"s26",
852  nullptr,
853  4,
854  FPU_OFFSET(26),
856  eFormatFloat,
858  fpu_s26},
859  nullptr,
860  g_s26_invalidates,
861  nullptr,
862  0},
863  {"s27",
864  nullptr,
865  4,
866  FPU_OFFSET(27),
868  eFormatFloat,
870  fpu_s27},
871  nullptr,
872  g_s27_invalidates,
873  nullptr,
874  0},
875  {"s28",
876  nullptr,
877  4,
878  FPU_OFFSET(28),
880  eFormatFloat,
882  fpu_s28},
883  nullptr,
884  g_s28_invalidates,
885  nullptr,
886  0},
887  {"s29",
888  nullptr,
889  4,
890  FPU_OFFSET(29),
892  eFormatFloat,
894  fpu_s29},
895  nullptr,
896  g_s29_invalidates,
897  nullptr,
898  0},
899  {"s30",
900  nullptr,
901  4,
902  FPU_OFFSET(30),
904  eFormatFloat,
906  fpu_s30},
907  nullptr,
908  g_s30_invalidates,
909  nullptr,
910  0},
911  {"s31",
912  nullptr,
913  4,
914  FPU_OFFSET(31),
916  eFormatFloat,
918  fpu_s31},
919  nullptr,
920  g_s31_invalidates,
921  nullptr,
922  0},
923  {"fpscr",
924  nullptr,
925  4,
926  FPSCR_OFFSET,
928  eFormatHex,
931  nullptr,
932  nullptr,
933  nullptr,
934  0},
935 
936  {"d0",
937  nullptr,
938  8,
939  FPU_OFFSET(0),
941  eFormatFloat,
943  fpu_d0},
944  g_d0_contains,
945  g_d0_invalidates,
946  nullptr,
947  0},
948  {"d1",
949  nullptr,
950  8,
951  FPU_OFFSET(2),
953  eFormatFloat,
955  fpu_d1},
956  g_d1_contains,
957  g_d1_invalidates,
958  nullptr,
959  0},
960  {"d2",
961  nullptr,
962  8,
963  FPU_OFFSET(4),
965  eFormatFloat,
967  fpu_d2},
968  g_d2_contains,
969  g_d2_invalidates,
970  nullptr,
971  0},
972  {"d3",
973  nullptr,
974  8,
975  FPU_OFFSET(6),
977  eFormatFloat,
979  fpu_d3},
980  g_d3_contains,
981  g_d3_invalidates,
982  nullptr,
983  0},
984  {"d4",
985  nullptr,
986  8,
987  FPU_OFFSET(8),
989  eFormatFloat,
991  fpu_d4},
992  g_d4_contains,
993  g_d4_invalidates,
994  nullptr,
995  0},
996  {"d5",
997  nullptr,
998  8,
999  FPU_OFFSET(10),
1001  eFormatFloat,
1003  fpu_d5},
1004  g_d5_contains,
1005  g_d5_invalidates,
1006  nullptr,
1007  0},
1008  {"d6",
1009  nullptr,
1010  8,
1011  FPU_OFFSET(12),
1013  eFormatFloat,
1015  fpu_d6},
1016  g_d6_contains,
1017  g_d6_invalidates,
1018  nullptr,
1019  0},
1020  {"d7",
1021  nullptr,
1022  8,
1023  FPU_OFFSET(14),
1025  eFormatFloat,
1027  fpu_d7},
1028  g_d7_contains,
1029  g_d7_invalidates,
1030  nullptr,
1031  0},
1032  {"d8",
1033  nullptr,
1034  8,
1035  FPU_OFFSET(16),
1037  eFormatFloat,
1039  fpu_d8},
1040  g_d8_contains,
1041  g_d8_invalidates,
1042  nullptr,
1043  0},
1044  {"d9",
1045  nullptr,
1046  8,
1047  FPU_OFFSET(18),
1049  eFormatFloat,
1051  fpu_d9},
1052  g_d9_contains,
1053  g_d9_invalidates,
1054  nullptr,
1055  0},
1056  {"d10",
1057  nullptr,
1058  8,
1059  FPU_OFFSET(20),
1061  eFormatFloat,
1063  fpu_d10},
1064  g_d10_contains,
1065  g_d10_invalidates,
1066  nullptr,
1067  0},
1068  {"d11",
1069  nullptr,
1070  8,
1071  FPU_OFFSET(22),
1073  eFormatFloat,
1075  fpu_d11},
1076  g_d11_contains,
1077  g_d11_invalidates,
1078  nullptr,
1079  0},
1080  {"d12",
1081  nullptr,
1082  8,
1083  FPU_OFFSET(24),
1085  eFormatFloat,
1087  fpu_d12},
1088  g_d12_contains,
1089  g_d12_invalidates,
1090  nullptr,
1091  0},
1092  {"d13",
1093  nullptr,
1094  8,
1095  FPU_OFFSET(26),
1097  eFormatFloat,
1099  fpu_d13},
1100  g_d13_contains,
1101  g_d13_invalidates,
1102  nullptr,
1103  0},
1104  {"d14",
1105  nullptr,
1106  8,
1107  FPU_OFFSET(28),
1109  eFormatFloat,
1111  fpu_d14},
1112  g_d14_contains,
1113  g_d14_invalidates,
1114  nullptr,
1115  0},
1116  {"d15",
1117  nullptr,
1118  8,
1119  FPU_OFFSET(30),
1121  eFormatFloat,
1123  fpu_d15},
1124  g_d15_contains,
1125  g_d15_invalidates,
1126  nullptr,
1127  0},
1128  {"d16",
1129  nullptr,
1130  8,
1131  FPU_OFFSET(32),
1133  eFormatFloat,
1135  fpu_d16},
1136  nullptr,
1137  g_d16_invalidates,
1138  nullptr,
1139  0},
1140  {"d17",
1141  nullptr,
1142  8,
1143  FPU_OFFSET(34),
1145  eFormatFloat,
1147  fpu_d17},
1148  nullptr,
1149  g_d17_invalidates,
1150  nullptr,
1151  0},
1152  {"d18",
1153  nullptr,
1154  8,
1155  FPU_OFFSET(36),
1157  eFormatFloat,
1159  fpu_d18},
1160  nullptr,
1161  g_d18_invalidates,
1162  nullptr,
1163  0},
1164  {"d19",
1165  nullptr,
1166  8,
1167  FPU_OFFSET(38),
1169  eFormatFloat,
1171  fpu_d19},
1172  nullptr,
1173  g_d19_invalidates,
1174  nullptr,
1175  0},
1176  {"d20",
1177  nullptr,
1178  8,
1179  FPU_OFFSET(40),
1181  eFormatFloat,
1183  fpu_d20},
1184  nullptr,
1185  g_d20_invalidates,
1186  nullptr,
1187  0},
1188  {"d21",
1189  nullptr,
1190  8,
1191  FPU_OFFSET(42),
1193  eFormatFloat,
1195  fpu_d21},
1196  nullptr,
1197  g_d21_invalidates,
1198  nullptr,
1199  0},
1200  {"d22",
1201  nullptr,
1202  8,
1203  FPU_OFFSET(44),
1205  eFormatFloat,
1207  fpu_d22},
1208  nullptr,
1209  g_d22_invalidates,
1210  nullptr,
1211  0},
1212  {"d23",
1213  nullptr,
1214  8,
1215  FPU_OFFSET(46),
1217  eFormatFloat,
1219  fpu_d23},
1220  nullptr,
1221  g_d23_invalidates,
1222  nullptr,
1223  0},
1224  {"d24",
1225  nullptr,
1226  8,
1227  FPU_OFFSET(48),
1229  eFormatFloat,
1231  fpu_d24},
1232  nullptr,
1233  g_d24_invalidates,
1234  nullptr,
1235  0},
1236  {"d25",
1237  nullptr,
1238  8,
1239  FPU_OFFSET(50),
1241  eFormatFloat,
1243  fpu_d25},
1244  nullptr,
1245  g_d25_invalidates,
1246  nullptr,
1247  0},
1248  {"d26",
1249  nullptr,
1250  8,
1251  FPU_OFFSET(52),
1253  eFormatFloat,
1255  fpu_d26},
1256  nullptr,
1257  g_d26_invalidates,
1258  nullptr,
1259  0},
1260  {"d27",
1261  nullptr,
1262  8,
1263  FPU_OFFSET(54),
1265  eFormatFloat,
1267  fpu_d27},
1268  nullptr,
1269  g_d27_invalidates,
1270  nullptr,
1271  0},
1272  {"d28",
1273  nullptr,
1274  8,
1275  FPU_OFFSET(56),
1277  eFormatFloat,
1279  fpu_d28},
1280  nullptr,
1281  g_d28_invalidates,
1282  nullptr,
1283  0},
1284  {"d29",
1285  nullptr,
1286  8,
1287  FPU_OFFSET(58),
1289  eFormatFloat,
1291  fpu_d29},
1292  nullptr,
1293  g_d29_invalidates,
1294  nullptr,
1295  0},
1296  {"d30",
1297  nullptr,
1298  8,
1299  FPU_OFFSET(60),
1301  eFormatFloat,
1303  fpu_d30},
1304  nullptr,
1305  g_d30_invalidates,
1306  nullptr,
1307  0},
1308  {"d31",
1309  nullptr,
1310  8,
1311  FPU_OFFSET(62),
1313  eFormatFloat,
1315  fpu_d31},
1316  nullptr,
1317  g_d31_invalidates,
1318  nullptr,
1319  0},
1320 
1321  {"q0",
1322  nullptr,
1323  16,
1324  FPU_OFFSET(0),
1328  fpu_q0},
1329  g_q0_contains,
1330  nullptr,
1331  nullptr,
1332  0},
1333  {"q1",
1334  nullptr,
1335  16,
1336  FPU_OFFSET(4),
1340  fpu_q1},
1341  g_q1_contains,
1342  nullptr,
1343  nullptr,
1344  0},
1345  {"q2",
1346  nullptr,
1347  16,
1348  FPU_OFFSET(8),
1352  fpu_q2},
1353  g_q2_contains,
1354  nullptr,
1355  nullptr,
1356  0},
1357  {"q3",
1358  nullptr,
1359  16,
1360  FPU_OFFSET(12),
1364  fpu_q3},
1365  g_q3_contains,
1366  nullptr,
1367  nullptr,
1368  0},
1369  {"q4",
1370  nullptr,
1371  16,
1372  FPU_OFFSET(16),
1376  fpu_q4},
1377  g_q4_contains,
1378  nullptr,
1379  nullptr,
1380  0},
1381  {"q5",
1382  nullptr,
1383  16,
1384  FPU_OFFSET(20),
1388  fpu_q5},
1389  g_q5_contains,
1390  nullptr,
1391  nullptr,
1392  0},
1393  {"q6",
1394  nullptr,
1395  16,
1396  FPU_OFFSET(24),
1400  fpu_q6},
1401  g_q6_contains,
1402  nullptr,
1403  nullptr,
1404  0},
1405  {"q7",
1406  nullptr,
1407  16,
1408  FPU_OFFSET(28),
1412  fpu_q7},
1413  g_q7_contains,
1414  nullptr,
1415  nullptr,
1416  0},
1417  {"q8",
1418  nullptr,
1419  16,
1420  FPU_OFFSET(32),
1424  fpu_q8},
1425  g_q8_contains,
1426  nullptr,
1427  nullptr,
1428  0},
1429  {"q9",
1430  nullptr,
1431  16,
1432  FPU_OFFSET(36),
1436  fpu_q9},
1437  g_q9_contains,
1438  nullptr,
1439  nullptr,
1440  0},
1441  {"q10",
1442  nullptr,
1443  16,
1444  FPU_OFFSET(40),
1448  fpu_q10},
1449  g_q10_contains,
1450  nullptr,
1451  nullptr,
1452  0},
1453  {"q11",
1454  nullptr,
1455  16,
1456  FPU_OFFSET(44),
1460  fpu_q11},
1461  g_q11_contains,
1462  nullptr,
1463  nullptr,
1464  0},
1465  {"q12",
1466  nullptr,
1467  16,
1468  FPU_OFFSET(48),
1472  fpu_q12},
1473  g_q12_contains,
1474  nullptr,
1475  nullptr,
1476  0},
1477  {"q13",
1478  nullptr,
1479  16,
1480  FPU_OFFSET(52),
1484  fpu_q13},
1485  g_q13_contains,
1486  nullptr,
1487  nullptr,
1488  0},
1489  {"q14",
1490  nullptr,
1491  16,
1492  FPU_OFFSET(56),
1496  fpu_q14},
1497  g_q14_contains,
1498  nullptr,
1499  nullptr,
1500  0},
1501  {"q15",
1502  nullptr,
1503  16,
1504  FPU_OFFSET(60),
1508  fpu_q15},
1509  g_q15_contains,
1510  nullptr,
1511  nullptr,
1512  0},
1513 
1514  {"exception",
1515  nullptr,
1516  4,
1517  EXC_OFFSET(0),
1518  eEncodingUint,
1519  eFormatHex,
1522  nullptr,
1523  nullptr,
1524  nullptr,
1525  0},
1526  {"fsr",
1527  nullptr,
1528  4,
1529  EXC_OFFSET(1),
1530  eEncodingUint,
1531  eFormatHex,
1534  nullptr,
1535  nullptr,
1536  nullptr,
1537  0},
1538  {"far",
1539  nullptr,
1540  4,
1541  EXC_OFFSET(2),
1542  eEncodingUint,
1543  eFormatHex,
1546  nullptr,
1547  nullptr,
1548  nullptr,
1549  0},
1550 
1551  {DEFINE_DBG(bvr, 0)},
1552  {DEFINE_DBG(bvr, 1)},
1553  {DEFINE_DBG(bvr, 2)},
1554  {DEFINE_DBG(bvr, 3)},
1555  {DEFINE_DBG(bvr, 4)},
1556  {DEFINE_DBG(bvr, 5)},
1557  {DEFINE_DBG(bvr, 6)},
1558  {DEFINE_DBG(bvr, 7)},
1559  {DEFINE_DBG(bvr, 8)},
1560  {DEFINE_DBG(bvr, 9)},
1561  {DEFINE_DBG(bvr, 10)},
1562  {DEFINE_DBG(bvr, 11)},
1563  {DEFINE_DBG(bvr, 12)},
1564  {DEFINE_DBG(bvr, 13)},
1565  {DEFINE_DBG(bvr, 14)},
1566  {DEFINE_DBG(bvr, 15)},
1567 
1568  {DEFINE_DBG(bcr, 0)},
1569  {DEFINE_DBG(bcr, 1)},
1570  {DEFINE_DBG(bcr, 2)},
1571  {DEFINE_DBG(bcr, 3)},
1572  {DEFINE_DBG(bcr, 4)},
1573  {DEFINE_DBG(bcr, 5)},
1574  {DEFINE_DBG(bcr, 6)},
1575  {DEFINE_DBG(bcr, 7)},
1576  {DEFINE_DBG(bcr, 8)},
1577  {DEFINE_DBG(bcr, 9)},
1578  {DEFINE_DBG(bcr, 10)},
1579  {DEFINE_DBG(bcr, 11)},
1580  {DEFINE_DBG(bcr, 12)},
1581  {DEFINE_DBG(bcr, 13)},
1582  {DEFINE_DBG(bcr, 14)},
1583  {DEFINE_DBG(bcr, 15)},
1584 
1585  {DEFINE_DBG(wvr, 0)},
1586  {DEFINE_DBG(wvr, 1)},
1587  {DEFINE_DBG(wvr, 2)},
1588  {DEFINE_DBG(wvr, 3)},
1589  {DEFINE_DBG(wvr, 4)},
1590  {DEFINE_DBG(wvr, 5)},
1591  {DEFINE_DBG(wvr, 6)},
1592  {DEFINE_DBG(wvr, 7)},
1593  {DEFINE_DBG(wvr, 8)},
1594  {DEFINE_DBG(wvr, 9)},
1595  {DEFINE_DBG(wvr, 10)},
1596  {DEFINE_DBG(wvr, 11)},
1597  {DEFINE_DBG(wvr, 12)},
1598  {DEFINE_DBG(wvr, 13)},
1599  {DEFINE_DBG(wvr, 14)},
1600  {DEFINE_DBG(wvr, 15)},
1601 
1602  {DEFINE_DBG(wcr, 0)},
1603  {DEFINE_DBG(wcr, 1)},
1604  {DEFINE_DBG(wcr, 2)},
1605  {DEFINE_DBG(wcr, 3)},
1606  {DEFINE_DBG(wcr, 4)},
1607  {DEFINE_DBG(wcr, 5)},
1608  {DEFINE_DBG(wcr, 6)},
1609  {DEFINE_DBG(wcr, 7)},
1610  {DEFINE_DBG(wcr, 8)},
1611  {DEFINE_DBG(wcr, 9)},
1612  {DEFINE_DBG(wcr, 10)},
1613  {DEFINE_DBG(wcr, 11)},
1614  {DEFINE_DBG(wcr, 12)},
1615  {DEFINE_DBG(wcr, 13)},
1616  {DEFINE_DBG(wcr, 14)},
1617  {DEFINE_DBG(wcr, 15)}};
1618 
1619 #endif // DECLARE_REGISTER_INFOS_ARM_STRUCT
#define LLDB_REGNUM_GENERIC_PC
Definition: lldb-defines.h:63
Enumerations for broadcasting.
Definition: SBLaunchInfo.h:14
#define GPR_OFFSET(idx)
#define LLDB_REGNUM_GENERIC_RA
Definition: lldb-defines.h:66
#define LLDB_REGNUM_GENERIC_ARG4
Definition: lldb-defines.h:74
#define LLDB_REGNUM_GENERIC_ARG2
Definition: lldb-defines.h:70
#define LLDB_REGNUM_GENERIC_SP
Definition: lldb-defines.h:64
#define LLDB_REGNUM_GENERIC_ARG1
Definition: lldb-defines.h:68
#define FPSCR_OFFSET
#define LLDB_REGNUM_GENERIC_FP
Definition: lldb-defines.h:65
#define LLDB_REGNUM_GENERIC_FLAGS
Definition: lldb-defines.h:67
#define DEFINE_DBG(re, y)
#define LLDB_REGNUM_GENERIC_ARG3
Definition: lldb-defines.h:72
Definition: SBAddress.h:15
#define FPU_OFFSET(idx)
#define EXC_OFFSET(idx)
#define LLDB_INVALID_REGNUM
Definition: lldb-defines.h:90